src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/u_debug.h"
  29 #include "intel/blorp/blorp.h"
  30 #include "intel/dev/gen_debug.h"
  31 #include "intel/compiler/brw_compiler.h"
  32 #include "iris_batch.h"
  33 #include "iris_binder.h"
  34 #include "iris_fence.h"
  35 #include "iris_resource.h"
  36 #include "iris_screen.h"
  37
  38 struct iris_bo;
  39 struct iris_context;
  40 struct blorp_batch;
  41 struct blorp_params;
  42
  43 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
  44 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  45 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
  46 #define IRIS_MAX_ABOS 16
  47 #define IRIS_MAX_SSBOS 16
  48 #define IRIS_MAX_VIEWPORTS 16
  49 #define IRIS_MAX_CLIP_PLANES 8
  50
  51 enum iris_param_domain {
  52    BRW_PARAM_DOMAIN_BUILTIN = 0,
  53    BRW_PARAM_DOMAIN_IMAGE,
  54 };
  55
  56 #define BRW_PARAM(domain, val)   (BRW_PARAM_DOMAIN_##domain << 24 | (val))
  57 #define BRW_PARAM_DOMAIN(param)  ((uint32_t)(param) >> 24)
  58 #define BRW_PARAM_VALUE(param)   ((uint32_t)(param) & 0x00ffffff)
  59 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
  60 #define BRW_PARAM_IMAGE_IDX(value)   (BRW_PARAM_VALUE(value) >> 8)
  61 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
  62
  63 /**
  64  * Dirty flags.  When state changes, we flag some combination of these
  65  * to indicate that particular GPU commands need to be re-emitted.
  66  *
  67  * Each bit typically corresponds to a single 3DSTATE_* command packet, but
  68  * in rare cases they map to a group of related packets that need to be
  69  * emitted together.
  70  *
  71  * See iris_upload_render_state().
  72  */
  73 #define IRIS_DIRTY_COLOR_CALC_STATE         (1ull <<  0)
  74 #define IRIS_DIRTY_POLYGON_STIPPLE          (1ull <<  1)
  75 #define IRIS_DIRTY_SCISSOR_RECT             (1ull <<  2)
  76 #define IRIS_DIRTY_WM_DEPTH_STENCIL         (1ull <<  3)
  77 #define IRIS_DIRTY_CC_VIEWPORT              (1ull <<  4)
  78 #define IRIS_DIRTY_SF_CL_VIEWPORT           (1ull <<  5)
  79 #define IRIS_DIRTY_PS_BLEND                 (1ull <<  6)
  80 #define IRIS_DIRTY_BLEND_STATE              (1ull <<  7)
  81 #define IRIS_DIRTY_RASTER                   (1ull <<  8)
  82 #define IRIS_DIRTY_CLIP                     (1ull <<  9)
  83 #define IRIS_DIRTY_SBE                      (1ull << 10)
  84 #define IRIS_DIRTY_LINE_STIPPLE             (1ull << 11)
  85 #define IRIS_DIRTY_VERTEX_ELEMENTS          (1ull << 12)
  86 #define IRIS_DIRTY_MULTISAMPLE              (1ull << 13)
  87 #define IRIS_DIRTY_VERTEX_BUFFERS           (1ull << 14)
  88 #define IRIS_DIRTY_SAMPLE_MASK              (1ull << 15)
  89 #define IRIS_DIRTY_SAMPLER_STATES_VS        (1ull << 16)
  90 #define IRIS_DIRTY_SAMPLER_STATES_TCS       (1ull << 17)
  91 #define IRIS_DIRTY_SAMPLER_STATES_TES       (1ull << 18)
  92 #define IRIS_DIRTY_SAMPLER_STATES_GS        (1ull << 19)
  93 #define IRIS_DIRTY_SAMPLER_STATES_PS        (1ull << 20)
  94 #define IRIS_DIRTY_SAMPLER_STATES_CS        (1ull << 21)
  95 #define IRIS_DIRTY_UNCOMPILED_VS            (1ull << 22)
  96 #define IRIS_DIRTY_UNCOMPILED_TCS           (1ull << 23)
  97 #define IRIS_DIRTY_UNCOMPILED_TES           (1ull << 24)
  98 #define IRIS_DIRTY_UNCOMPILED_GS            (1ull << 25)
  99 #define IRIS_DIRTY_UNCOMPILED_FS            (1ull << 26)
 100 #define IRIS_DIRTY_UNCOMPILED_CS            (1ull << 27)
 101 #define IRIS_DIRTY_VS                       (1ull << 28)
 102 #define IRIS_DIRTY_TCS                      (1ull << 29)
 103 #define IRIS_DIRTY_TES                      (1ull << 30)
 104 #define IRIS_DIRTY_GS                       (1ull << 31)
 105 #define IRIS_DIRTY_FS                       (1ull << 32)
 106 #define IRIS_DIRTY_CS                       (1ull << 33)
 107 #define IRIS_DIRTY_URB                      (1ull << 34)
 108 #define IRIS_DIRTY_CONSTANTS_VS             (1ull << 35)
 109 #define IRIS_DIRTY_CONSTANTS_TCS            (1ull << 36)
 110 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
 111 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
 112 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
 113 #define IRIS_DIRTY_CONSTANTS_CS             (1ull << 40)
 114 #define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 41)
 115 #define IRIS_DIRTY_WM                       (1ull << 42)
 116 #define IRIS_DIRTY_BINDINGS_VS              (1ull << 43)
 117 #define IRIS_DIRTY_BINDINGS_TCS             (1ull << 44)
 118 #define IRIS_DIRTY_BINDINGS_TES             (1ull << 45)
 119 #define IRIS_DIRTY_BINDINGS_GS              (1ull << 46)
 120 #define IRIS_DIRTY_BINDINGS_FS              (1ull << 47)
 121 #define IRIS_DIRTY_BINDINGS_CS              (1ull << 48)
 122 #define IRIS_DIRTY_SO_BUFFERS               (1ull << 49)
 123 #define IRIS_DIRTY_SO_DECL_LIST             (1ull << 50)
 124 #define IRIS_DIRTY_STREAMOUT                (1ull << 51)
 125 #define IRIS_DIRTY_VF_SGVS                  (1ull << 52)
 126 #define IRIS_DIRTY_VF                       (1ull << 53)
 127 #define IRIS_DIRTY_VF_TOPOLOGY              (1ull << 54)
 128 #define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES  (1ull << 55)
 129 #define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 56)
 130 #define IRIS_DIRTY_VF_STATISTICS            (1ull << 57)
 131
 132 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
 133                                     IRIS_DIRTY_SAMPLER_STATES_CS | \
 134                                     IRIS_DIRTY_UNCOMPILED_CS | \
 135                                     IRIS_DIRTY_CONSTANTS_CS | \
 136                                     IRIS_DIRTY_BINDINGS_CS | \
 137                                     IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
 138
 139 #define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
 140
 141 #define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS  | \
 142                                  IRIS_DIRTY_BINDINGS_TCS | \
 143                                  IRIS_DIRTY_BINDINGS_TES | \
 144                                  IRIS_DIRTY_BINDINGS_GS  | \
 145                                  IRIS_DIRTY_BINDINGS_FS  | \
 146                                  IRIS_DIRTY_BINDINGS_CS)
 147
 148 /**
 149  * Non-orthogonal state (NOS) dependency flags.
 150  *
 151  * Shader programs may depend on non-orthogonal state.  These flags are
 152  * used to indicate that a shader's key depends on the state provided by
 153  * a certain Gallium CSO.  Changing any CSOs marked as a dependency will
 154  * cause the driver to re-compute the shader key, possibly triggering a
 155  * shader recompile.
 156  */
 157 enum iris_nos_dep {
 158    IRIS_NOS_FRAMEBUFFER,
 159    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 160    IRIS_NOS_RASTERIZER,
 161    IRIS_NOS_BLEND,
 162    IRIS_NOS_LAST_VUE_MAP,
 163
 164    IRIS_NOS_COUNT,
 165 };
 166
 167 struct iris_depth_stencil_alpha_state;
 168
 169 /**
 170  * Cache IDs for the in-memory program cache (ice->shaders.cache).
 171  */
 172 enum iris_program_cache_id {
 173    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 174    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 175    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 176    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 177    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 178    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 179    IRIS_CACHE_BLORP,
 180 };
 181
 182 /** @{
 183  *
 184  * Defines for PIPE_CONTROL operations, which trigger cache flushes,
 185  * synchronization, pipelined memory writes, and so on.
 186  *
 187  * The bits here are not the actual hardware values.  The actual fields
 188  * move between various generations, so we just have flags for each
 189  * potential operation, and use genxml to encode the actual packet.
 190  */
 191 enum pipe_control_flags
 192 {
 193    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 194    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 195    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 196    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 197    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 198    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 199    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 200    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 201    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 202    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 203    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 204    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 205    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 206    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 207    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 208    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 209    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 210    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 211    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 212    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 213    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 214    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 215    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 216    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 217 };
 218
 219 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 220    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 221     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 222     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 223
 224 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 225    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 226     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 227     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 228     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 229     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 230
 231 enum iris_predicate_state {
 232    /* The first two states are used if we can determine whether to draw
 233     * without having to look at the values in the query object buffer. This
 234     * will happen if there is no conditional render in progress, if the query
 235     * object is already completed or if something else has already added
 236     * samples to the preliminary result.
 237     */
 238    IRIS_PREDICATE_STATE_RENDER,
 239    IRIS_PREDICATE_STATE_DONT_RENDER,
 240
 241    /* In this case whether to draw or not depends on the result of an
 242     * MI_PREDICATE command so the predicate enable bit needs to be checked.
 243     */
 244    IRIS_PREDICATE_STATE_USE_BIT,
 245 };
 246
 247 /** @} */
 248
 249 /**
 250  * A compiled shader variant, containing a pointer to the GPU assembly,
 251  * as well as program data and other packets needed by state upload.
 252  *
 253  * There can be several iris_compiled_shader variants per API-level shader
 254  * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
 255  */
 256 struct iris_compiled_shader {
 257    /** Reference to the uploaded assembly. */
 258    struct iris_state_ref assembly;
 259
 260    /** Pointer to the assembly in the BO's map. */
 261    void *map;
 262
 263    /** The program data (owned by the program cache hash table) */
 264    struct brw_stage_prog_data *prog_data;
 265
 266    /** A list of system values to be uploaded as uniforms. */
 267    enum brw_param_builtin *system_values;
 268    unsigned num_system_values;
 269
 270    /** Number of constbufs expected by the shader. */
 271    unsigned num_cbufs;
 272
 273    /**
 274     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 275     * (the VUE-based information for transform feedback outputs).
 276     */
 277    uint32_t *streamout;
 278
 279    /**
 280     * Shader packets and other data derived from prog_data.  These must be
 281     * completely determined from prog_data.
 282     */
 283    uint8_t derived_data[0];
 284 };
 285
 286 /**
 287  * API context state that is replicated per shader stage.
 288  */
 289 struct iris_shader_state {
 290    /** Uniform Buffers */
 291    struct pipe_shader_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 292    struct iris_state_ref constbuf_surf_state[PIPE_MAX_CONSTANT_BUFFERS];
 293
 294    struct pipe_constant_buffer cbuf0;
 295    bool cbuf0_needs_upload;
 296
 297    /** Shader Storage Buffers */
 298    struct pipe_shader_buffer ssbo[PIPE_MAX_SHADER_BUFFERS];
 299    struct iris_state_ref ssbo_surf_state[PIPE_MAX_SHADER_BUFFERS];
 300
 301    /** Shader Storage Images (image load store) */
 302    struct iris_image_view image[PIPE_MAX_SHADER_IMAGES];
 303
 304    struct iris_state_ref sampler_table;
 305    struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
 306    struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
 307
 308    /** Bitfield of which constant buffers are bound (non-null). */
 309    uint32_t bound_cbufs;
 310
 311    /** Bitfield of which image views are bound (non-null). */
 312    uint32_t bound_image_views;
 313
 314    /** Bitfield of which sampler views are bound (non-null). */
 315    uint32_t bound_sampler_views;
 316
 317    /** Bitfield of which shader storage buffers are bound (non-null). */
 318    uint32_t bound_ssbos;
 319
 320    /** Bitfield of which shader storage buffers are writable. */
 321    uint32_t writable_ssbos;
 322 };
 323
 324 /**
 325  * Gallium CSO for stream output (transform feedback) targets.
 326  */
 327 struct iris_stream_output_target {
 328    struct pipe_stream_output_target base;
 329
 330    /** Storage holding the offset where we're writing in the buffer */
 331    struct iris_state_ref offset;
 332
 333    /** Stride (dwords-per-vertex) during this transform feedback operation */
 334    uint16_t stride;
 335 };
 336
 337 /**
 338  * Virtual table for generation-specific (genxml) function calls.
 339  */
 340 struct iris_vtable {
 341    void (*destroy_state)(struct iris_context *ice);
 342    void (*init_render_context)(struct iris_screen *screen,
 343                                struct iris_batch *batch,
 344                                struct iris_vtable *vtbl,
 345                                struct pipe_debug_callback *dbg);
 346    void (*init_compute_context)(struct iris_screen *screen,
 347                                 struct iris_batch *batch,
 348                                 struct iris_vtable *vtbl,
 349                                 struct pipe_debug_callback *dbg);
 350    void (*upload_render_state)(struct iris_context *ice,
 351                                struct iris_batch *batch,
 352                                const struct pipe_draw_info *draw);
 353    void (*update_surface_base_address)(struct iris_batch *batch,
 354                                        struct iris_binder *binder);
 355    void (*upload_compute_state)(struct iris_context *ice,
 356                                 struct iris_batch *batch,
 357                                 const struct pipe_grid_info *grid);
 358    void (*rebind_buffer)(struct iris_context *ice,
 359                          struct iris_resource *res,
 360                          uint64_t old_address);
 361    void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst,
 362                                uint32_t src);
 363    void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst,
 364                                uint32_t src);
 365    void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
 366                                uint32_t val);
 367    void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
 368                                uint64_t val);
 369    void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg,
 370                                struct iris_bo *bo, uint32_t offset);
 371    void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg,
 372                                struct iris_bo *bo, uint32_t offset);
 373    void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg,
 374                                 struct iris_bo *bo, uint32_t offset,
 375                                 bool predicated);
 376    void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg,
 377                                 struct iris_bo *bo, uint32_t offset,
 378                                 bool predicated);
 379    void (*store_data_imm32)(struct iris_batch *batch,
 380                             struct iris_bo *bo, uint32_t offset,
 381                             uint32_t value);
 382    void (*store_data_imm64)(struct iris_batch *batch,
 383                             struct iris_bo *bo, uint32_t offset,
 384                             uint64_t value);
 385    void (*copy_mem_mem)(struct iris_batch *batch,
 386                         struct iris_bo *dst_bo, uint32_t dst_offset,
 387                         struct iris_bo *src_bo, uint32_t src_offset,
 388                         unsigned bytes);
 389    void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
 390                                  struct iris_bo *bo, uint32_t offset,
 391                                  uint64_t imm);
 392
 393    unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
 394    void (*store_derived_program_state)(struct iris_context *ice,
 395                                        enum iris_program_cache_id cache_id,
 396                                        struct iris_compiled_shader *shader);
 397    uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
 398                                     const struct brw_vue_map *vue_map);
 399    void (*populate_vs_key)(const struct iris_context *ice,
 400                            const struct shader_info *info,
 401                            struct brw_vs_prog_key *key);
 402    void (*populate_tcs_key)(const struct iris_context *ice,
 403                             struct brw_tcs_prog_key *key);
 404    void (*populate_tes_key)(const struct iris_context *ice,
 405                             struct brw_tes_prog_key *key);
 406    void (*populate_gs_key)(const struct iris_context *ice,
 407                            struct brw_gs_prog_key *key);
 408    void (*populate_fs_key)(const struct iris_context *ice,
 409                            struct brw_wm_prog_key *key);
 410    void (*populate_cs_key)(const struct iris_context *ice,
 411                            struct brw_cs_prog_key *key);
 412    uint32_t (*mocs)(const struct iris_bo *bo);
 413 };
 414
 415 /**
 416  * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
 417  *
 418  * See iris_border_color.c for more information.
 419  */
 420 struct iris_border_color_pool {
 421    struct iris_bo *bo;
 422    void *map;
 423    unsigned insert_point;
 424
 425    /** Map from border colors to offsets in the buffer. */
 426    struct hash_table *ht;
 427 };
 428
 429 /**
 430  * The API context (derived from pipe_context).
 431  *
 432  * Most driver state is tracked here.
 433  */
 434 struct iris_context {
 435    struct pipe_context ctx;
 436
 437    /** A debug callback for KHR_debug output. */
 438    struct pipe_debug_callback dbg;
 439
 440    /** Slab allocator for iris_transfer_map objects. */
 441    struct slab_child_pool transfer_pool;
 442
 443    struct iris_vtable vtbl;
 444
 445    struct blorp_context blorp;
 446
 447    struct iris_batch batches[IRIS_BATCH_COUNT];
 448
 449    struct u_upload_mgr *query_buffer_uploader;
 450
 451    struct {
 452       struct {
 453          /**
 454           * Either the value of BaseVertex for indexed draw calls or the value
 455           * of the argument <first> for non-indexed draw calls.
 456           */
 457          int firstvertex;
 458          int baseinstance;
 459       } params;
 460
 461       /**
 462        * Resource and offset that stores draw_parameters from the indirect
 463        * buffer or to the buffer that stures the previous values for non
 464        * indirect draws.
 465        */
 466       struct pipe_resource *draw_params_res;
 467       uint32_t draw_params_offset;
 468
 469       struct {
 470          /**
 471           * The value of DrawID. This always comes in from it's own vertex
 472           * buffer since it's not part of the indirect draw parameters.
 473           */
 474          int drawid;
 475
 476          /**
 477           * Stores if an indexed or non-indexed draw (~0/0). Useful to
 478           * calculate BaseVertex as an AND of firstvertex and is_indexed_draw.
 479           */
 480          int is_indexed_draw;
 481       } derived_params;
 482
 483       /**
 484        * Resource and offset used for GL_ARB_shader_draw_parameters which
 485        * contains parameters that are not present in the indirect buffer as
 486        * drawid and is_indexed_draw. They will go in their own vertex element.
 487        */
 488       struct pipe_resource *derived_draw_params_res;
 489       uint32_t derived_draw_params_offset;
 490
 491       bool is_indirect;
 492    } draw;
 493
 494    struct {
 495       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 496       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 497       struct brw_vue_map *last_vue_map;
 498
 499       struct u_upload_mgr *uploader;
 500       struct hash_table *cache;
 501
 502       unsigned urb_size;
 503
 504       /* Track last VS URB entry size */
 505       unsigned last_vs_entry_size;
 506
 507       /**
 508        * Scratch buffers for various sizes and stages.
 509        *
 510        * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
 511        * and shader stage.
 512        */
 513       struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
 514    } shaders;
 515
 516    struct {
 517       struct iris_query *query;
 518       bool condition;
 519    } condition;
 520
 521    struct {
 522       uint64_t dirty;
 523       uint64_t dirty_for_nos[IRIS_NOS_COUNT];
 524
 525       unsigned num_viewports;
 526       unsigned sample_mask;
 527       struct iris_blend_state *cso_blend;
 528       struct iris_rasterizer_state *cso_rast;
 529       struct iris_depth_stencil_alpha_state *cso_zsa;
 530       struct iris_vertex_element_state *cso_vertex_elements;
 531       struct pipe_blend_color blend_color;
 532       struct pipe_poly_stipple poly_stipple;
 533       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 534       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 535       struct pipe_stencil_ref stencil_ref;
 536       struct pipe_framebuffer_state framebuffer;
 537       struct pipe_clip_state clip_planes;
 538
 539       float default_outer_level[4];
 540       float default_inner_level[2];
 541
 542       /** Bitfield of which vertex buffers are bound (non-null). */
 543       uint64_t bound_vertex_buffers;
 544
 545       bool object_preemption; /**< Object level preemption enabled. */
 546
 547       bool primitive_restart;
 548       unsigned cut_index;
 549       enum pipe_prim_type prim_mode:8;
 550       uint8_t vertices_per_patch;
 551
 552       /** The last compute grid size */
 553       uint32_t last_grid[3];
 554       /** Reference to the BO containing the compute grid size */
 555       struct iris_state_ref grid_size;
 556       /** Reference to the SURFACE_STATE for the compute grid resource */
 557       struct iris_state_ref grid_surf_state;
 558
 559       /**
 560        * Array of aux usages for drawing, altered to account for any
 561        * self-dependencies from resources bound for sampling and rendering.
 562        */
 563       enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS];
 564
 565       /** Bitfield of whether color blending is enabled for RT[i] */
 566       uint8_t blend_enables;
 567
 568       /** Are depth writes enabled?  (Depth buffer may or may not exist.) */
 569       bool depth_writes_enabled;
 570
 571       /** Are stencil writes enabled?  (Stencil buffer may or may not exist.) */
 572       bool stencil_writes_enabled;
 573
 574       /** GenX-specific current state */
 575       struct iris_genx_state *genx;
 576
 577       struct iris_shader_state shaders[MESA_SHADER_STAGES];
 578
 579       /** Do vertex shader uses shader draw parameters ? */
 580       bool vs_uses_draw_params;
 581       bool vs_uses_derived_draw_params;
 582       bool vs_needs_sgvs_element;
 583
 584       /** Do vertex shader uses edge flag ? */
 585       bool vs_needs_edge_flag;
 586
 587       /** Do any samplers need border color?  One bit per shader stage. */
 588       uint8_t need_border_colors;
 589
 590       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 591       bool streamout_active;
 592
 593       bool statistics_counters_enabled;
 594
 595       /** Current conditional rendering mode */
 596       enum iris_predicate_state predicate;
 597
 598       /**
 599        * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the
 600        * render context that needs to be uploaded to the compute context.
 601        */
 602       struct iris_bo *compute_predicate;
 603
 604       /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
 605       bool prims_generated_query_active;
 606
 607       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 608       uint32_t *streamout;
 609
 610       /** Current strides for each streamout buffer */
 611       uint16_t *streamout_strides;
 612
 613       /** The SURFACE_STATE for a 1x1x1 null surface. */
 614       struct iris_state_ref unbound_tex;
 615
 616       /** The SURFACE_STATE for a framebuffer-sized null surface. */
 617       struct iris_state_ref null_fb;
 618
 619       struct u_upload_mgr *surface_uploader;
 620       // XXX: may want a separate uploader for "hey I made a CSO!" vs
 621       // "I'm streaming this out at draw time and never want it again!"
 622       struct u_upload_mgr *dynamic_uploader;
 623
 624       struct iris_binder binder;
 625
 626       struct iris_border_color_pool border_color_pool;
 627
 628       /** The high 16-bits of the last VBO/index buffer addresses */
 629       uint16_t last_vbo_high_bits[33];
 630       uint16_t last_index_bo_high_bits;
 631
 632       /**
 633        * Resources containing streamed state which our render context
 634        * currently points to.  Used to re-add these to the validation
 635        * list when we start a new batch and haven't resubmitted commands.
 636        */
 637       struct {
 638          struct pipe_resource *cc_vp;
 639          struct pipe_resource *sf_cl_vp;
 640          struct pipe_resource *color_calc;
 641          struct pipe_resource *scissor;
 642          struct pipe_resource *blend;
 643          struct pipe_resource *index_buffer;
 644       } last_res;
 645    } state;
 646 };
 647
 648 #define perf_debug(dbg, ...) do {                      \
 649    if (INTEL_DEBUG & DEBUG_PERF)                       \
 650       dbg_printf(__VA_ARGS__);                         \
 651    if (unlikely(dbg))                                  \
 652       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 653 } while(0)
 654
 655 double get_time(void);
 656
 657 struct pipe_context *
 658 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 659
 660 void iris_init_blit_functions(struct pipe_context *ctx);
 661 void iris_init_clear_functions(struct pipe_context *ctx);
 662 void iris_init_program_functions(struct pipe_context *ctx);
 663 void iris_init_resource_functions(struct pipe_context *ctx);
 664 void iris_init_query_functions(struct pipe_context *ctx);
 665 void iris_update_compiled_shaders(struct iris_context *ice);
 666 void iris_update_compiled_compute_shader(struct iris_context *ice);
 667 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
 668                                     uint32_t *dst);
 669
 670
 671 /* iris_blit.c */
 672 void iris_blorp_surf_for_resource(struct iris_vtable *vtbl,
 673                                   struct blorp_surf *surf,
 674                                   struct pipe_resource *p_res,
 675                                   enum isl_aux_usage aux_usage,
 676                                   unsigned level,
 677                                   bool is_render_target);
 678 void iris_copy_region(struct blorp_context *blorp,
 679                       struct iris_batch *batch,
 680                       struct pipe_resource *dst,
 681                       unsigned dst_level,
 682                       unsigned dstx, unsigned dsty, unsigned dstz,
 683                       struct pipe_resource *src,
 684                       unsigned src_level,
 685                       const struct pipe_box *src_box);
 686
 687 /* iris_draw.c */
 688
 689 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 690 void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
 691
 692 /* iris_pipe_control.c */
 693
 694 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 695                                   uint32_t flags);
 696 void iris_emit_pipe_control_write(struct iris_batch *batch, uint32_t flags,
 697                                   struct iris_bo *bo, uint32_t offset,
 698                                   uint64_t imm);
 699 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 700                                 uint32_t flags);
 701
 702 void iris_init_flush_functions(struct pipe_context *ctx);
 703
 704 /* iris_blorp.c */
 705 void gen8_init_blorp(struct iris_context *ice);
 706 void gen9_init_blorp(struct iris_context *ice);
 707 void gen10_init_blorp(struct iris_context *ice);
 708 void gen11_init_blorp(struct iris_context *ice);
 709
 710 /* iris_border_color.c */
 711
 712 void iris_init_border_color_pool(struct iris_context *ice);
 713 void iris_destroy_border_color_pool(struct iris_context *ice);
 714 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 715 uint32_t iris_upload_border_color(struct iris_context *ice,
 716                                   union pipe_color_union *color);
 717
 718 /* iris_state.c */
 719 void gen8_init_state(struct iris_context *ice);
 720 void gen9_init_state(struct iris_context *ice);
 721 void gen10_init_state(struct iris_context *ice);
 722 void gen11_init_state(struct iris_context *ice);
 723 void gen8_emit_urb_setup(struct iris_context *ice,
 724                           struct iris_batch *batch,
 725                           const unsigned size[4],
 726                           bool tess_present, bool gs_present);
 727 void gen9_emit_urb_setup(struct iris_context *ice,
 728                           struct iris_batch *batch,
 729                           const unsigned size[4],
 730                           bool tess_present, bool gs_present);
 731 void gen10_emit_urb_setup(struct iris_context *ice,
 732                           struct iris_batch *batch,
 733                           const unsigned size[4],
 734                           bool tess_present, bool gs_present);
 735 void gen11_emit_urb_setup(struct iris_context *ice,
 736                           struct iris_batch *batch,
 737                           const unsigned size[4],
 738                           bool tess_present, bool gs_present);
 739
 740 /* iris_program.c */
 741 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
 742                                                gl_shader_stage stage);
 743 struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
 744                                        unsigned per_thread_scratch,
 745                                        gl_shader_stage stage);
 746
 747 /* iris_program_cache.c */
 748
 749 void iris_init_program_cache(struct iris_context *ice);
 750 void iris_destroy_program_cache(struct iris_context *ice);
 751 void iris_print_program_cache(struct iris_context *ice);
 752 struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice,
 753                                                      enum iris_program_cache_id,
 754                                                      uint32_t key_size,
 755                                                      const void *key);
 756 struct iris_compiled_shader *iris_upload_shader(struct iris_context *ice,
 757                                                 enum iris_program_cache_id,
 758                                                 uint32_t key_size,
 759                                                 const void *key,
 760                                                 const void *assembly,
 761                                                 struct brw_stage_prog_data *,
 762                                                 uint32_t *streamout,
 763                                                 enum brw_param_builtin *sysv,
 764                                                 unsigned num_system_values,
 765                                                 unsigned num_cbufs);
 766 const void *iris_find_previous_compile(const struct iris_context *ice,
 767                                        enum iris_program_cache_id cache_id,
 768                                        unsigned program_string_id);
 769 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 770                               const void *key,
 771                               uint32_t key_size,
 772                               uint32_t *kernel_out,
 773                               void *prog_data_out);
 774 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
 775                               const void *key, uint32_t key_size,
 776                               const void *kernel, uint32_t kernel_size,
 777                               const struct brw_stage_prog_data *prog_data,
 778                               uint32_t prog_data_size,
 779                               uint32_t *kernel_out,
 780                               void *prog_data_out);
 781
 782 /* iris_query.c */
 783
 784 void iris_math_div32_gpr0(struct iris_context *ice,
 785                           struct iris_batch *batch,
 786                           uint32_t D);
 787 void iris_math_add32_gpr0(struct iris_context *ice,
 788                           struct iris_batch *batch,
 789                           uint32_t x);
 790
 791 uint64_t iris_timebase_scale(const struct gen_device_info *devinfo,
 792                              uint64_t gpu_timestamp);
 793 void iris_resolve_conditional_render(struct iris_context *ice);
 794
 795 /* iris_resolve.c */
 796
 797 void iris_predraw_resolve_inputs(struct iris_context *ice,
 798                                  struct iris_batch *batch,
 799                                  bool *draw_aux_buffer_disabled,
 800                                  gl_shader_stage stage,
 801                                  bool consider_framebuffer);
 802 void iris_predraw_resolve_framebuffer(struct iris_context *ice,
 803                                       struct iris_batch *batch,
 804                                       bool *draw_aux_buffer_disabled);
 805 void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
 806                                            struct iris_batch *batch);
 807 void iris_cache_sets_clear(struct iris_batch *batch);
 808 void iris_flush_depth_and_render_caches(struct iris_batch *batch);
 809 void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
 810 void iris_cache_flush_for_render(struct iris_batch *batch,
 811                                  struct iris_bo *bo,
 812                                  enum isl_format format,
 813                                  enum isl_aux_usage aux_usage);
 814 void iris_render_cache_add_bo(struct iris_batch *batch,
 815                               struct iris_bo *bo,
 816                               enum isl_format format,
 817                               enum isl_aux_usage aux_usage);
 818 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 819 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 820
 821 /* iris_state.c */
 822 void gen9_iris_enable_obj_preemption(struct iris_context *ice, struct iris_batch *batch, bool enable);
 823 void gen10_iris_enable_obj_preemption(struct iris_context *ice, struct iris_batch *batch, bool enable);
 824 #endif