src/gallium/drivers/iris/iris_context.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef IRIS_CONTEXT_H
  24 #define IRIS_CONTEXT_H
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_state.h"
  28 #include "util/slab.h"
  29 #include "util/u_debug.h"
  30 #include "intel/blorp/blorp.h"
  31 #include "intel/dev/gen_debug.h"
  32 #include "intel/common/gen_l3_config.h"
  33 #include "intel/compiler/brw_compiler.h"
  34 #include "iris_batch.h"
  35 #include "iris_binder.h"
  36 #include "iris_fence.h"
  37 #include "iris_resource.h"
  38 #include "iris_screen.h"
  39
  40 struct iris_bo;
  41 struct iris_context;
  42 struct blorp_batch;
  43 struct blorp_params;
  44
  45 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
  46 #define IRIS_MAX_TEXTURE_SAMPLERS 32
  47 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
  48 #define IRIS_MAX_ABOS 16
  49 #define IRIS_MAX_SSBOS 16
  50 #define IRIS_MAX_VIEWPORTS 16
  51 #define IRIS_MAX_CLIP_PLANES 8
  52 #define IRIS_MAX_GLOBAL_BINDINGS 32
  53
  54 enum iris_param_domain {
  55    BRW_PARAM_DOMAIN_BUILTIN = 0,
  56    BRW_PARAM_DOMAIN_IMAGE,
  57 };
  58
  59 enum iris_shader_reloc {
  60    IRIS_SHADER_RELOC_CONST_DATA_ADDR_LOW,
  61    IRIS_SHADER_RELOC_CONST_DATA_ADDR_HIGH,
  62 };
  63
  64 enum {
  65    DRI_CONF_BO_REUSE_DISABLED,
  66    DRI_CONF_BO_REUSE_ALL
  67 };
  68
  69 #define BRW_PARAM(domain, val)   (BRW_PARAM_DOMAIN_##domain << 24 | (val))
  70 #define BRW_PARAM_DOMAIN(param)  ((uint32_t)(param) >> 24)
  71 #define BRW_PARAM_VALUE(param)   ((uint32_t)(param) & 0x00ffffff)
  72 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
  73 #define BRW_PARAM_IMAGE_IDX(value)   (BRW_PARAM_VALUE(value) >> 8)
  74 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
  75
  76 /**
  77  * Dirty flags.  When state changes, we flag some combination of these
  78  * to indicate that particular GPU commands need to be re-emitted.
  79  *
  80  * Each bit typically corresponds to a single 3DSTATE_* command packet, but
  81  * in rare cases they map to a group of related packets that need to be
  82  * emitted together.
  83  *
  84  * See iris_upload_render_state().
  85  */
  86 #define IRIS_DIRTY_COLOR_CALC_STATE               (1ull <<  0)
  87 #define IRIS_DIRTY_POLYGON_STIPPLE                (1ull <<  1)
  88 #define IRIS_DIRTY_SCISSOR_RECT                   (1ull <<  2)
  89 #define IRIS_DIRTY_WM_DEPTH_STENCIL               (1ull <<  3)
  90 #define IRIS_DIRTY_CC_VIEWPORT                    (1ull <<  4)
  91 #define IRIS_DIRTY_SF_CL_VIEWPORT                 (1ull <<  5)
  92 #define IRIS_DIRTY_PS_BLEND                       (1ull <<  6)
  93 #define IRIS_DIRTY_BLEND_STATE                    (1ull <<  7)
  94 #define IRIS_DIRTY_RASTER                         (1ull <<  8)
  95 #define IRIS_DIRTY_CLIP                           (1ull <<  9)
  96 #define IRIS_DIRTY_SBE                            (1ull << 10)
  97 #define IRIS_DIRTY_LINE_STIPPLE                   (1ull << 11)
  98 #define IRIS_DIRTY_VERTEX_ELEMENTS                (1ull << 12)
  99 #define IRIS_DIRTY_MULTISAMPLE                    (1ull << 13)
 100 #define IRIS_DIRTY_VERTEX_BUFFERS                 (1ull << 14)
 101 #define IRIS_DIRTY_SAMPLE_MASK                    (1ull << 15)
 102 #define IRIS_DIRTY_URB                            (1ull << 16)
 103 #define IRIS_DIRTY_DEPTH_BUFFER                   (1ull << 17)
 104 #define IRIS_DIRTY_WM                             (1ull << 18)
 105 #define IRIS_DIRTY_SO_BUFFERS                     (1ull << 19)
 106 #define IRIS_DIRTY_SO_DECL_LIST                   (1ull << 20)
 107 #define IRIS_DIRTY_STREAMOUT                      (1ull << 21)
 108 #define IRIS_DIRTY_VF_SGVS                        (1ull << 22)
 109 #define IRIS_DIRTY_VF                             (1ull << 23)
 110 #define IRIS_DIRTY_VF_TOPOLOGY                    (1ull << 24)
 111 #define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES    (1ull << 25)
 112 #define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES   (1ull << 26)
 113 #define IRIS_DIRTY_VF_STATISTICS                  (1ull << 27)
 114 #define IRIS_DIRTY_PMA_FIX                        (1ull << 28)
 115 #define IRIS_DIRTY_DEPTH_BOUNDS                   (1ull << 29)
 116 #define IRIS_DIRTY_RENDER_BUFFER                  (1ull << 30)
 117 #define IRIS_DIRTY_STENCIL_REF                    (1ull << 31)
 118
 119 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
 120
 121 #define IRIS_ALL_DIRTY_FOR_RENDER (~IRIS_ALL_DIRTY_FOR_COMPUTE)
 122
 123 /**
 124  * Per-stage dirty flags.  When state changes, we flag some combination of
 125  * these to indicate that particular GPU commands need to be re-emitted.
 126  * Unlike the IRIS_DIRTY_* flags these are shader stage-specific and can be
 127  * indexed by shifting the mask by the shader stage index.
 128  *
 129  * See iris_upload_render_state().
 130  */
 131 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_VS        (1ull << 0)
 132 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_TCS       (1ull << 1)
 133 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_TES       (1ull << 2)
 134 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_GS        (1ull << 3)
 135 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_PS        (1ull << 4)
 136 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_CS        (1ull << 5)
 137 #define IRIS_STAGE_DIRTY_UNCOMPILED_VS            (1ull << 6)
 138 #define IRIS_STAGE_DIRTY_UNCOMPILED_TCS           (1ull << 7)
 139 #define IRIS_STAGE_DIRTY_UNCOMPILED_TES           (1ull << 8)
 140 #define IRIS_STAGE_DIRTY_UNCOMPILED_GS            (1ull << 9)
 141 #define IRIS_STAGE_DIRTY_UNCOMPILED_FS            (1ull << 10)
 142 #define IRIS_STAGE_DIRTY_UNCOMPILED_CS            (1ull << 11)
 143 #define IRIS_STAGE_DIRTY_VS                       (1ull << 12)
 144 #define IRIS_STAGE_DIRTY_TCS                      (1ull << 13)
 145 #define IRIS_STAGE_DIRTY_TES                      (1ull << 14)
 146 #define IRIS_STAGE_DIRTY_GS                       (1ull << 15)
 147 #define IRIS_STAGE_DIRTY_FS                       (1ull << 16)
 148 #define IRIS_STAGE_DIRTY_CS                       (1ull << 17)
 149 #define IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS      18
 150 #define IRIS_STAGE_DIRTY_CONSTANTS_VS             (1ull << 18)
 151 #define IRIS_STAGE_DIRTY_CONSTANTS_TCS            (1ull << 19)
 152 #define IRIS_STAGE_DIRTY_CONSTANTS_TES            (1ull << 20)
 153 #define IRIS_STAGE_DIRTY_CONSTANTS_GS             (1ull << 21)
 154 #define IRIS_STAGE_DIRTY_CONSTANTS_FS             (1ull << 22)
 155 #define IRIS_STAGE_DIRTY_CONSTANTS_CS             (1ull << 23)
 156 #define IRIS_STAGE_DIRTY_BINDINGS_VS              (1ull << 24)
 157 #define IRIS_STAGE_DIRTY_BINDINGS_TCS             (1ull << 25)
 158 #define IRIS_STAGE_DIRTY_BINDINGS_TES             (1ull << 26)
 159 #define IRIS_STAGE_DIRTY_BINDINGS_GS              (1ull << 27)
 160 #define IRIS_STAGE_DIRTY_BINDINGS_FS              (1ull << 28)
 161 #define IRIS_STAGE_DIRTY_BINDINGS_CS              (1ull << 29)
 162
 163 #define IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE (IRIS_STAGE_DIRTY_CS | \
 164                                           IRIS_STAGE_DIRTY_SAMPLER_STATES_CS | \
 165                                           IRIS_STAGE_DIRTY_UNCOMPILED_CS |    \
 166                                           IRIS_STAGE_DIRTY_CONSTANTS_CS |     \
 167                                           IRIS_STAGE_DIRTY_BINDINGS_CS)
 168
 169 #define IRIS_ALL_STAGE_DIRTY_FOR_RENDER (~IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE)
 170
 171 #define IRIS_ALL_STAGE_DIRTY_BINDINGS (IRIS_STAGE_DIRTY_BINDINGS_VS  | \
 172                                        IRIS_STAGE_DIRTY_BINDINGS_TCS | \
 173                                        IRIS_STAGE_DIRTY_BINDINGS_TES | \
 174                                        IRIS_STAGE_DIRTY_BINDINGS_GS  | \
 175                                        IRIS_STAGE_DIRTY_BINDINGS_FS  | \
 176                                        IRIS_STAGE_DIRTY_BINDINGS_CS)
 177
 178 /**
 179  * Non-orthogonal state (NOS) dependency flags.
 180  *
 181  * Shader programs may depend on non-orthogonal state.  These flags are
 182  * used to indicate that a shader's key depends on the state provided by
 183  * a certain Gallium CSO.  Changing any CSOs marked as a dependency will
 184  * cause the driver to re-compute the shader key, possibly triggering a
 185  * shader recompile.
 186  */
 187 enum iris_nos_dep {
 188    IRIS_NOS_FRAMEBUFFER,
 189    IRIS_NOS_DEPTH_STENCIL_ALPHA,
 190    IRIS_NOS_RASTERIZER,
 191    IRIS_NOS_BLEND,
 192    IRIS_NOS_LAST_VUE_MAP,
 193
 194    IRIS_NOS_COUNT,
 195 };
 196
 197 /** @{
 198  *
 199  * Program cache keys for state based recompiles.
 200  */
 201
 202 struct iris_base_prog_key {
 203    unsigned program_string_id;
 204 };
 205
 206 struct iris_vue_prog_key {
 207    struct iris_base_prog_key base;
 208
 209    unsigned nr_userclip_plane_consts:4;
 210 };
 211
 212 struct iris_vs_prog_key {
 213    struct iris_vue_prog_key vue;
 214 };
 215
 216 struct iris_tcs_prog_key {
 217    struct iris_vue_prog_key vue;
 218
 219    uint16_t tes_primitive_mode;
 220
 221    uint8_t input_vertices;
 222
 223    bool quads_workaround;
 224
 225    /** A bitfield of per-patch outputs written. */
 226    uint32_t patch_outputs_written;
 227
 228    /** A bitfield of per-vertex outputs written. */
 229    uint64_t outputs_written;
 230 };
 231
 232 struct iris_tes_prog_key {
 233    struct iris_vue_prog_key vue;
 234
 235    /** A bitfield of per-patch inputs read. */
 236    uint32_t patch_inputs_read;
 237
 238    /** A bitfield of per-vertex inputs read. */
 239    uint64_t inputs_read;
 240 };
 241
 242 struct iris_gs_prog_key {
 243    struct iris_vue_prog_key vue;
 244 };
 245
 246 struct iris_fs_prog_key {
 247    struct iris_base_prog_key base;
 248
 249    unsigned nr_color_regions:5;
 250    bool flat_shade:1;
 251    bool alpha_test_replicate_alpha:1;
 252    bool alpha_to_coverage:1;
 253    bool clamp_fragment_color:1;
 254    bool persample_interp:1;
 255    bool multisample_fbo:1;
 256    bool force_dual_color_blend:1;
 257    bool coherent_fb_fetch:1;
 258
 259    uint8_t color_outputs_valid;
 260    uint64_t input_slots_valid;
 261 };
 262
 263 struct iris_cs_prog_key {
 264    struct iris_base_prog_key base;
 265 };
 266
 267 /** @} */
 268
 269 struct iris_depth_stencil_alpha_state;
 270
 271 /**
 272  * Cache IDs for the in-memory program cache (ice->shaders.cache).
 273  */
 274 enum iris_program_cache_id {
 275    IRIS_CACHE_VS  = MESA_SHADER_VERTEX,
 276    IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL,
 277    IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL,
 278    IRIS_CACHE_GS  = MESA_SHADER_GEOMETRY,
 279    IRIS_CACHE_FS  = MESA_SHADER_FRAGMENT,
 280    IRIS_CACHE_CS  = MESA_SHADER_COMPUTE,
 281    IRIS_CACHE_BLORP,
 282 };
 283
 284 /** @{
 285  *
 286  * Defines for PIPE_CONTROL operations, which trigger cache flushes,
 287  * synchronization, pipelined memory writes, and so on.
 288  *
 289  * The bits here are not the actual hardware values.  The actual fields
 290  * move between various generations, so we just have flags for each
 291  * potential operation, and use genxml to encode the actual packet.
 292  */
 293 enum pipe_control_flags
 294 {
 295    PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
 296    PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
 297    PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
 298    PIPE_CONTROL_CS_STALL                        = (1 << 4),
 299    PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
 300    PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
 301    PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
 302    PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
 303    PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
 304    PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
 305    PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
 306    PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
 307    PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
 308    PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
 309    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
 310    PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
 311    PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
 312    PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
 313    PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
 314    PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
 315    PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
 316    PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
 317    PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
 318    PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
 319    PIPE_CONTROL_TILE_CACHE_FLUSH                = (1 << 25),
 320    PIPE_CONTROL_FLUSH_HDC                       = (1 << 26),
 321 };
 322
 323 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
 324    (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
 325     PIPE_CONTROL_DATA_CACHE_FLUSH |   \
 326     PIPE_CONTROL_RENDER_TARGET_FLUSH)
 327
 328 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
 329    (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
 330     PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
 331     PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
 332     PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
 333     PIPE_CONTROL_INSTRUCTION_INVALIDATE)
 334
 335 enum iris_predicate_state {
 336    /* The first two states are used if we can determine whether to draw
 337     * without having to look at the values in the query object buffer. This
 338     * will happen if there is no conditional render in progress, if the query
 339     * object is already completed or if something else has already added
 340     * samples to the preliminary result.
 341     */
 342    IRIS_PREDICATE_STATE_RENDER,
 343    IRIS_PREDICATE_STATE_DONT_RENDER,
 344
 345    /* In this case whether to draw or not depends on the result of an
 346     * MI_PREDICATE command so the predicate enable bit needs to be checked.
 347     */
 348    IRIS_PREDICATE_STATE_USE_BIT,
 349 };
 350
 351 /** @} */
 352
 353 /**
 354  * An uncompiled, API-facing shader.  This is the Gallium CSO for shaders.
 355  * It primarily contains the NIR for the shader.
 356  *
 357  * Each API-facing shader can be compiled into multiple shader variants,
 358  * based on non-orthogonal state dependencies, recorded in the shader key.
 359  *
 360  * See iris_compiled_shader, which represents a compiled shader variant.
 361  */
 362 struct iris_uncompiled_shader {
 363    struct nir_shader *nir;
 364
 365    struct pipe_stream_output_info stream_output;
 366
 367    /* A SHA1 of the serialized NIR for the disk cache. */
 368    unsigned char nir_sha1[20];
 369
 370    unsigned program_id;
 371
 372    /** Bitfield of (1 << IRIS_NOS_*) flags. */
 373    unsigned nos;
 374
 375    /** Have any shader variants been compiled yet? */
 376    bool compiled_once;
 377
 378    /** Should we use ALT mode for math?  Useful for ARB programs. */
 379    bool use_alt_mode;
 380
 381    bool needs_edge_flag;
 382
 383    /* Whether shader uses atomic operations. */
 384    bool uses_atomic_load_store;
 385
 386    /** Size (in bytes) of the kernel input data */
 387    unsigned kernel_input_size;
 388 };
 389
 390 enum iris_surface_group {
 391    IRIS_SURFACE_GROUP_RENDER_TARGET,
 392    IRIS_SURFACE_GROUP_RENDER_TARGET_READ,
 393    IRIS_SURFACE_GROUP_CS_WORK_GROUPS,
 394    IRIS_SURFACE_GROUP_TEXTURE,
 395    IRIS_SURFACE_GROUP_IMAGE,
 396    IRIS_SURFACE_GROUP_UBO,
 397    IRIS_SURFACE_GROUP_SSBO,
 398
 399    IRIS_SURFACE_GROUP_COUNT,
 400 };
 401
 402 enum {
 403    /* Invalid value for a binding table index. */
 404    IRIS_SURFACE_NOT_USED = 0xa0a0a0a0,
 405 };
 406
 407 struct iris_binding_table {
 408    uint32_t size_bytes;
 409
 410    /** Number of surfaces in each group, before compacting. */
 411    uint32_t sizes[IRIS_SURFACE_GROUP_COUNT];
 412
 413    /** Initial offset of each group. */
 414    uint32_t offsets[IRIS_SURFACE_GROUP_COUNT];
 415
 416    /** Mask of surfaces used in each group. */
 417    uint64_t used_mask[IRIS_SURFACE_GROUP_COUNT];
 418 };
 419
 420 /**
 421  * A compiled shader variant, containing a pointer to the GPU assembly,
 422  * as well as program data and other packets needed by state upload.
 423  *
 424  * There can be several iris_compiled_shader variants per API-level shader
 425  * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key).
 426  */
 427 struct iris_compiled_shader {
 428    struct list_head link;
 429
 430    /** Reference to the uploaded assembly. */
 431    struct iris_state_ref assembly;
 432
 433    /** Pointer to the assembly in the BO's map. */
 434    void *map;
 435
 436    /** The program data (owned by the program cache hash table) */
 437    struct brw_stage_prog_data *prog_data;
 438
 439    /** A list of system values to be uploaded as uniforms. */
 440    enum brw_param_builtin *system_values;
 441    unsigned num_system_values;
 442
 443    /** Size (in bytes) of the kernel input data */
 444    unsigned kernel_input_size;
 445
 446    /** Number of constbufs expected by the shader. */
 447    unsigned num_cbufs;
 448
 449    /**
 450     * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
 451     * (the VUE-based information for transform feedback outputs).
 452     */
 453    uint32_t *streamout;
 454
 455    struct iris_binding_table bt;
 456
 457    /**
 458     * Shader packets and other data derived from prog_data.  These must be
 459     * completely determined from prog_data.
 460     */
 461    uint8_t derived_data[0];
 462 };
 463
 464 /**
 465  * API context state that is replicated per shader stage.
 466  */
 467 struct iris_shader_state {
 468    /** Uniform Buffers */
 469    struct pipe_shader_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
 470    struct iris_state_ref constbuf_surf_state[PIPE_MAX_CONSTANT_BUFFERS];
 471
 472    bool sysvals_need_upload;
 473
 474    /** Shader Storage Buffers */
 475    struct pipe_shader_buffer ssbo[PIPE_MAX_SHADER_BUFFERS];
 476    struct iris_state_ref ssbo_surf_state[PIPE_MAX_SHADER_BUFFERS];
 477
 478    /** Shader Storage Images (image load store) */
 479    struct iris_image_view image[PIPE_MAX_SHADER_IMAGES];
 480
 481    struct iris_state_ref sampler_table;
 482    struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
 483    struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
 484
 485    /** Bitfield of which constant buffers are bound (non-null). */
 486    uint32_t bound_cbufs;
 487
 488    /** Bitfield of which image views are bound (non-null). */
 489    uint32_t bound_image_views;
 490
 491    /** Bitfield of which sampler views are bound (non-null). */
 492    uint32_t bound_sampler_views;
 493
 494    /** Bitfield of which shader storage buffers are bound (non-null). */
 495    uint32_t bound_ssbos;
 496
 497    /** Bitfield of which shader storage buffers are writable. */
 498    uint32_t writable_ssbos;
 499 };
 500
 501 /**
 502  * Gallium CSO for stream output (transform feedback) targets.
 503  */
 504 struct iris_stream_output_target {
 505    struct pipe_stream_output_target base;
 506
 507    /** Storage holding the offset where we're writing in the buffer */
 508    struct iris_state_ref offset;
 509
 510    /** Stride (bytes-per-vertex) during this transform feedback operation */
 511    uint16_t stride;
 512
 513    /** Has 3DSTATE_SO_BUFFER actually been emitted, zeroing the offsets? */
 514    bool zeroed;
 515 };
 516
 517 /**
 518  * A pool containing SAMPLER_BORDER_COLOR_STATE entries.
 519  *
 520  * See iris_border_color.c for more information.
 521  */
 522 struct iris_border_color_pool {
 523    struct iris_bo *bo;
 524    void *map;
 525    unsigned insert_point;
 526
 527    /** Map from border colors to offsets in the buffer. */
 528    struct hash_table *ht;
 529 };
 530
 531 /**
 532  * The API context (derived from pipe_context).
 533  *
 534  * Most driver state is tracked here.
 535  */
 536 struct iris_context {
 537    struct pipe_context ctx;
 538
 539    /** A debug callback for KHR_debug output. */
 540    struct pipe_debug_callback dbg;
 541
 542    /** A device reset status callback for notifying that the GPU is hosed. */
 543    struct pipe_device_reset_callback reset;
 544
 545    /** Slab allocator for iris_transfer_map objects. */
 546    struct slab_child_pool transfer_pool;
 547
 548    struct blorp_context blorp;
 549
 550    struct iris_batch batches[IRIS_BATCH_COUNT];
 551
 552    struct u_upload_mgr *query_buffer_uploader;
 553
 554    struct {
 555       struct {
 556          /**
 557           * Either the value of BaseVertex for indexed draw calls or the value
 558           * of the argument <first> for non-indexed draw calls.
 559           */
 560          int firstvertex;
 561          int baseinstance;
 562       } params;
 563
 564       /**
 565        * Are the above values the ones stored in the draw_params buffer?
 566        * If so, we can compare them against new values to see if anything
 567        * changed.  If not, we need to assume they changed.
 568        */
 569       bool params_valid;
 570
 571       /**
 572        * Resource and offset that stores draw_parameters from the indirect
 573        * buffer or to the buffer that stures the previous values for non
 574        * indirect draws.
 575        */
 576       struct iris_state_ref draw_params;
 577
 578       struct {
 579          /**
 580           * The value of DrawID. This always comes in from it's own vertex
 581           * buffer since it's not part of the indirect draw parameters.
 582           */
 583          int drawid;
 584
 585          /**
 586           * Stores if an indexed or non-indexed draw (~0/0). Useful to
 587           * calculate BaseVertex as an AND of firstvertex and is_indexed_draw.
 588           */
 589          int is_indexed_draw;
 590       } derived_params;
 591
 592       /**
 593        * Resource and offset used for GL_ARB_shader_draw_parameters which
 594        * contains parameters that are not present in the indirect buffer as
 595        * drawid and is_indexed_draw. They will go in their own vertex element.
 596        */
 597       struct iris_state_ref derived_draw_params;
 598    } draw;
 599
 600    struct {
 601       struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
 602       struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
 603       struct brw_vue_map *last_vue_map;
 604
 605       /** List of shader variants whose deletion has been deferred for now */
 606       struct list_head deleted_variants[MESA_SHADER_STAGES];
 607
 608       struct u_upload_mgr *uploader;
 609       struct hash_table *cache;
 610
 611       /** Is a GS or TES outputting points or lines? */
 612       bool output_topology_is_points_or_lines;
 613
 614       /**
 615        * Scratch buffers for various sizes and stages.
 616        *
 617        * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
 618        * and shader stage.
 619        */
 620       struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
 621    } shaders;
 622
 623    struct {
 624       struct iris_query *query;
 625       bool condition;
 626    } condition;
 627
 628    struct gen_perf_context *perf_ctx;
 629
 630    /** Frame number for debug prints */
 631    uint32_t frame;
 632
 633    struct {
 634       uint64_t dirty;
 635       uint64_t stage_dirty;
 636       uint64_t stage_dirty_for_nos[IRIS_NOS_COUNT];
 637
 638       unsigned num_viewports;
 639       unsigned sample_mask;
 640       struct iris_blend_state *cso_blend;
 641       struct iris_rasterizer_state *cso_rast;
 642       struct iris_depth_stencil_alpha_state *cso_zsa;
 643       struct iris_vertex_element_state *cso_vertex_elements;
 644       struct pipe_blend_color blend_color;
 645       struct pipe_poly_stipple poly_stipple;
 646       struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS];
 647       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
 648       struct pipe_stencil_ref stencil_ref;
 649       struct pipe_framebuffer_state framebuffer;
 650       struct pipe_clip_state clip_planes;
 651
 652       float default_outer_level[4];
 653       float default_inner_level[2];
 654
 655       /** Bitfield of which vertex buffers are bound (non-null). */
 656       uint64_t bound_vertex_buffers;
 657
 658       bool primitive_restart;
 659       unsigned cut_index;
 660       enum pipe_prim_type prim_mode:8;
 661       bool prim_is_points_or_lines;
 662       uint8_t vertices_per_patch;
 663
 664       bool window_space_position;
 665
 666       /** The last compute group size */
 667       uint32_t last_block[3];
 668
 669       /** The last compute grid size */
 670       uint32_t last_grid[3];
 671       /** Reference to the BO containing the compute grid size */
 672       struct iris_state_ref grid_size;
 673       /** Reference to the SURFACE_STATE for the compute grid resource */
 674       struct iris_state_ref grid_surf_state;
 675
 676       /**
 677        * Array of aux usages for drawing, altered to account for any
 678        * self-dependencies from resources bound for sampling and rendering.
 679        */
 680       enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS];
 681
 682       enum gen_urb_deref_block_size urb_deref_block_size;
 683
 684       /** Are depth writes enabled?  (Depth buffer may or may not exist.) */
 685       bool depth_writes_enabled;
 686
 687       /** Are stencil writes enabled?  (Stencil buffer may or may not exist.) */
 688       bool stencil_writes_enabled;
 689
 690       /** GenX-specific current state */
 691       struct iris_genx_state *genx;
 692
 693       struct iris_shader_state shaders[MESA_SHADER_STAGES];
 694
 695       /** Do vertex shader uses shader draw parameters ? */
 696       bool vs_uses_draw_params;
 697       bool vs_uses_derived_draw_params;
 698       bool vs_needs_sgvs_element;
 699
 700       /** Do vertex shader uses edge flag ? */
 701       bool vs_needs_edge_flag;
 702
 703       /** Do any samplers need border color?  One bit per shader stage. */
 704       uint8_t need_border_colors;
 705
 706       /** Global resource bindings */
 707       struct pipe_resource *global_bindings[IRIS_MAX_GLOBAL_BINDINGS];
 708
 709       struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
 710       bool streamout_active;
 711
 712       bool statistics_counters_enabled;
 713
 714       /** Current conditional rendering mode */
 715       enum iris_predicate_state predicate;
 716
 717       /**
 718        * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the
 719        * render context that needs to be uploaded to the compute context.
 720        */
 721       struct iris_bo *compute_predicate;
 722
 723       /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
 724       bool prims_generated_query_active;
 725
 726       /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
 727       uint32_t *streamout;
 728
 729       /** The SURFACE_STATE for a 1x1x1 null surface. */
 730       struct iris_state_ref unbound_tex;
 731
 732       /** The SURFACE_STATE for a framebuffer-sized null surface. */
 733       struct iris_state_ref null_fb;
 734
 735       struct u_upload_mgr *surface_uploader;
 736       struct u_upload_mgr *dynamic_uploader;
 737
 738       struct iris_binder binder;
 739
 740       struct iris_border_color_pool border_color_pool;
 741
 742       /** The high 16-bits of the last VBO/index buffer addresses */
 743       uint16_t last_vbo_high_bits[33];
 744       uint16_t last_index_bo_high_bits;
 745
 746       /**
 747        * Resources containing streamed state which our render context
 748        * currently points to.  Used to re-add these to the validation
 749        * list when we start a new batch and haven't resubmitted commands.
 750        */
 751       struct {
 752          struct pipe_resource *cc_vp;
 753          struct pipe_resource *sf_cl_vp;
 754          struct pipe_resource *color_calc;
 755          struct pipe_resource *scissor;
 756          struct pipe_resource *blend;
 757          struct pipe_resource *index_buffer;
 758          struct pipe_resource *cs_thread_ids;
 759          struct pipe_resource *cs_desc;
 760       } last_res;
 761
 762       /** Records the size of variable-length state for INTEL_DEBUG=bat */
 763       struct hash_table_u64 *sizes;
 764
 765       /** Last rendering scale argument provided to genX(emit_hashing_mode). */
 766       unsigned current_hash_scale;
 767    } state;
 768 };
 769
 770 #define perf_debug(dbg, ...) do {                      \
 771    if (INTEL_DEBUG & DEBUG_PERF)                       \
 772       dbg_printf(__VA_ARGS__);                         \
 773    if (unlikely(dbg))                                  \
 774       pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
 775 } while(0)
 776
 777 double get_time(void);
 778
 779 struct pipe_context *
 780 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 781
 782 void iris_lost_context_state(struct iris_batch *batch);
 783
 784 void iris_init_blit_functions(struct pipe_context *ctx);
 785 void iris_init_clear_functions(struct pipe_context *ctx);
 786 void iris_init_program_functions(struct pipe_context *ctx);
 787 void iris_init_resource_functions(struct pipe_context *ctx);
 788 void iris_init_perfquery_functions(struct pipe_context *ctx);
 789 void iris_update_compiled_shaders(struct iris_context *ice);
 790 void iris_update_compiled_compute_shader(struct iris_context *ice);
 791 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
 792                                     unsigned threads,
 793                                     uint32_t *dst);
 794
 795
 796 /* iris_blit.c */
 797 void iris_blorp_surf_for_resource(struct isl_device *isl_dev,
 798                                   struct blorp_surf *surf,
 799                                   struct pipe_resource *p_res,
 800                                   enum isl_aux_usage aux_usage,
 801                                   unsigned level,
 802                                   bool is_render_target);
 803 void iris_copy_region(struct blorp_context *blorp,
 804                       struct iris_batch *batch,
 805                       struct pipe_resource *dst,
 806                       unsigned dst_level,
 807                       unsigned dstx, unsigned dsty, unsigned dstz,
 808                       struct pipe_resource *src,
 809                       unsigned src_level,
 810                       const struct pipe_box *src_box);
 811
 812 /* iris_draw.c */
 813
 814 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 815 void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
 816
 817 /* iris_pipe_control.c */
 818
 819 void iris_emit_pipe_control_flush(struct iris_batch *batch,
 820                                   const char *reason, uint32_t flags);
 821 void iris_emit_pipe_control_write(struct iris_batch *batch,
 822                                   const char *reason, uint32_t flags,
 823                                   struct iris_bo *bo, uint32_t offset,
 824                                   uint64_t imm);
 825 void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
 826                                 const char *reason, uint32_t flags);
 827 void iris_emit_buffer_barrier_for(struct iris_batch *batch,
 828                                   struct iris_bo *bo,
 829                                   enum iris_domain access);
 830 void iris_flush_all_caches(struct iris_batch *batch);
 831
 832 #define iris_handle_always_flush_cache(batch) \
 833    if (unlikely(batch->screen->driconf.always_flush_cache)) \
 834       iris_flush_all_caches(batch);
 835
 836 void iris_init_flush_functions(struct pipe_context *ctx);
 837
 838 /* iris_border_color.c */
 839
 840 void iris_init_border_color_pool(struct iris_context *ice);
 841 void iris_destroy_border_color_pool(struct iris_context *ice);
 842 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
 843 uint32_t iris_upload_border_color(struct iris_context *ice,
 844                                   union pipe_color_union *color);
 845
 846 /* iris_program.c */
 847 void iris_upload_ubo_ssbo_surf_state(struct iris_context *ice,
 848                                      struct pipe_shader_buffer *buf,
 849                                      struct iris_state_ref *surf_state,
 850                                      bool ssbo);
 851 const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
 852                                                gl_shader_stage stage);
 853 struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
 854                                        unsigned per_thread_scratch,
 855                                        gl_shader_stage stage);
 856 uint32_t iris_group_index_to_bti(const struct iris_binding_table *bt,
 857                                  enum iris_surface_group group,
 858                                  uint32_t index);
 859 uint32_t iris_bti_to_group_index(const struct iris_binding_table *bt,
 860                                  enum iris_surface_group group,
 861                                  uint32_t bti);
 862
 863 /* iris_disk_cache.c */
 864
 865 void iris_disk_cache_store(struct disk_cache *cache,
 866                            const struct iris_uncompiled_shader *ish,
 867                            const struct iris_compiled_shader *shader,
 868                            const void *prog_key,
 869                            uint32_t prog_key_size);
 870 struct iris_compiled_shader *
 871 iris_disk_cache_retrieve(struct iris_context *ice,
 872                          const struct iris_uncompiled_shader *ish,
 873                          const void *prog_key,
 874                          uint32_t prog_key_size);
 875
 876 /* iris_program_cache.c */
 877
 878 void iris_init_program_cache(struct iris_context *ice);
 879 void iris_destroy_program_cache(struct iris_context *ice);
 880 void iris_print_program_cache(struct iris_context *ice);
 881 struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice,
 882                                                      enum iris_program_cache_id,
 883                                                      uint32_t key_size,
 884                                                      const void *key);
 885 struct iris_compiled_shader *iris_upload_shader(struct iris_context *ice,
 886                                                 enum iris_program_cache_id,
 887                                                 uint32_t key_size,
 888                                                 const void *key,
 889                                                 const void *assembly,
 890                                                 struct brw_stage_prog_data *,
 891                                                 uint32_t *streamout,
 892                                                 enum brw_param_builtin *sysv,
 893                                                 unsigned num_system_values,
 894                                                 unsigned kernel_input_size,
 895                                                 unsigned num_cbufs,
 896                                                 const struct iris_binding_table *bt);
 897 const void *iris_find_previous_compile(const struct iris_context *ice,
 898                                        enum iris_program_cache_id cache_id,
 899                                        unsigned program_string_id);
 900 void iris_delete_shader_variants(struct iris_context *ice,
 901                                  struct iris_uncompiled_shader *ish);
 902 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch,
 903                               const void *key,
 904                               uint32_t key_size,
 905                               uint32_t *kernel_out,
 906                               void *prog_data_out);
 907 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch, uint32_t stage,
 908                               const void *key, uint32_t key_size,
 909                               const void *kernel, uint32_t kernel_size,
 910                               const struct brw_stage_prog_data *prog_data,
 911                               uint32_t prog_data_size,
 912                               uint32_t *kernel_out,
 913                               void *prog_data_out);
 914
 915 /* iris_resolve.c */
 916
 917 void iris_predraw_resolve_inputs(struct iris_context *ice,
 918                                  struct iris_batch *batch,
 919                                  bool *draw_aux_buffer_disabled,
 920                                  gl_shader_stage stage,
 921                                  bool consider_framebuffer);
 922 void iris_predraw_resolve_framebuffer(struct iris_context *ice,
 923                                       struct iris_batch *batch,
 924                                       bool *draw_aux_buffer_disabled);
 925 void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
 926                                            struct iris_batch *batch);
 927 void iris_cache_flush_for_render(struct iris_batch *batch,
 928                                  struct iris_bo *bo,
 929                                  enum isl_format format,
 930                                  enum isl_aux_usage aux_usage);
 931 int iris_get_driver_query_info(struct pipe_screen *pscreen, unsigned index,
 932                                struct pipe_driver_query_info *info);
 933 int iris_get_driver_query_group_info(struct pipe_screen *pscreen,
 934                                      unsigned index,
 935                                      struct pipe_driver_query_group_info *info);
 936
 937 /* iris_state.c */
 938 void gen9_toggle_preemption(struct iris_context *ice,
 939                             struct iris_batch *batch,
 940                             const struct pipe_draw_info *draw);
 941
 942
 943
 944 #ifdef genX
 945 #  include "iris_genx_protos.h"
 946 #else
 947 #  define genX(x) gen4_##x
 948 #  include "iris_genx_protos.h"
 949 #  undef genX
 950 #  define genX(x) gen5_##x
 951 #  include "iris_genx_protos.h"
 952 #  undef genX
 953 #  define genX(x) gen6_##x
 954 #  include "iris_genx_protos.h"
 955 #  undef genX
 956 #  define genX(x) gen7_##x
 957 #  include "iris_genx_protos.h"
 958 #  undef genX
 959 #  define genX(x) gen75_##x
 960 #  include "iris_genx_protos.h"
 961 #  undef genX
 962 #  define genX(x) gen8_##x
 963 #  include "iris_genx_protos.h"
 964 #  undef genX
 965 #  define genX(x) gen9_##x
 966 #  include "iris_genx_protos.h"
 967 #  undef genX
 968 #  define genX(x) gen10_##x
 969 #  include "iris_genx_protos.h"
 970 #  undef genX
 971 #  define genX(x) gen11_##x
 972 #  include "iris_genx_protos.h"
 973 #  undef genX
 974 #  define genX(x) gen12_##x
 975 #  include "iris_genx_protos.h"
 976 #  undef genX
 977 #endif
 978
 979 #endif