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iris: disable 6x MSAA support
[mesa.git] / src / gallium / drivers / iris / iris_formats.c
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "util/bitscan.h"
25 #include "util/macros.h"
26 #include "util/u_format.h"
27
28 #include "iris_resource.h"
29 #include "iris_screen.h"
30
31 enum isl_format
32 iris_isl_format_for_pipe_format(enum pipe_format pf)
33 {
34 static const enum isl_format table[PIPE_FORMAT_COUNT] = {
35 [0 ... PIPE_FORMAT_COUNT-1] = ISL_FORMAT_UNSUPPORTED,
36
37 [PIPE_FORMAT_B8G8R8A8_UNORM] = ISL_FORMAT_B8G8R8A8_UNORM,
38 [PIPE_FORMAT_B8G8R8X8_UNORM] = ISL_FORMAT_B8G8R8X8_UNORM,
39 //[PIPE_FORMAT_A8R8G8B8_UNORM] = ISL_FORMAT_A8R8G8B8_UNORM,
40 //[PIPE_FORMAT_X8R8G8B8_UNORM] = ISL_FORMAT_X8R8G8B8_UNORM,
41 [PIPE_FORMAT_B5G5R5A1_UNORM] = ISL_FORMAT_B5G5R5A1_UNORM,
42 [PIPE_FORMAT_B4G4R4A4_UNORM] = ISL_FORMAT_B4G4R4A4_UNORM,
43 [PIPE_FORMAT_B5G6R5_UNORM] = ISL_FORMAT_B5G6R5_UNORM,
44 [PIPE_FORMAT_R10G10B10A2_UNORM] = ISL_FORMAT_R10G10B10A2_UNORM,
45 //[PIPE_FORMAT_L8_UNORM] = ISL_FORMAT_L8_UNORM,
46 //[PIPE_FORMAT_A8_UNORM] = ISL_FORMAT_A8_UNORM,
47 //[PIPE_FORMAT_I8_UNORM] = ISL_FORMAT_I8_UNORM,
48 //[PIPE_FORMAT_L8A8_UNORM] = ISL_FORMAT_L8A8_UNORM,
49 //[PIPE_FORMAT_L16_UNORM] = ISL_FORMAT_L16_UNORM,
50 //[PIPE_FORMAT_UYVY] = ISL_FORMAT_UYVY,
51 //[PIPE_FORMAT_YUYV] = ISL_FORMAT_YUYV,
52 [PIPE_FORMAT_Z16_UNORM] = ISL_FORMAT_R16_UNORM,
53 [PIPE_FORMAT_Z32_UNORM] = ISL_FORMAT_R32_UNORM,
54 [PIPE_FORMAT_Z32_FLOAT] = ISL_FORMAT_R32_FLOAT,
55 /* XXX: separate stencil */
56 [PIPE_FORMAT_Z24_UNORM_S8_UINT] = ISL_FORMAT_R24_UNORM_X8_TYPELESS,
57 //[PIPE_FORMAT_S8_UINT_Z24_UNORM] = ISL_FORMAT_S8_UINT_Z24_UNORM,
58 //[PIPE_FORMAT_Z24X8_UNORM] = ISL_FORMAT_R24_UNORM_X8_TYPELESS,
59 [PIPE_FORMAT_X8Z24_UNORM] = ISL_FORMAT_R24_UNORM_X8_TYPELESS,
60 [PIPE_FORMAT_S8_UINT] = ISL_FORMAT_R8_UINT,
61 [PIPE_FORMAT_R64_FLOAT] = ISL_FORMAT_R64_FLOAT,
62 [PIPE_FORMAT_R64G64_FLOAT] = ISL_FORMAT_R64G64_FLOAT,
63 [PIPE_FORMAT_R64G64B64_FLOAT] = ISL_FORMAT_R64G64B64_FLOAT,
64 [PIPE_FORMAT_R64G64B64A64_FLOAT] = ISL_FORMAT_R64G64B64A64_FLOAT,
65 [PIPE_FORMAT_R32_FLOAT] = ISL_FORMAT_R32_FLOAT,
66 [PIPE_FORMAT_R32G32_FLOAT] = ISL_FORMAT_R32G32_FLOAT,
67 [PIPE_FORMAT_R32G32B32_FLOAT] = ISL_FORMAT_R32G32B32_FLOAT,
68 [PIPE_FORMAT_R32G32B32A32_FLOAT] = ISL_FORMAT_R32G32B32A32_FLOAT,
69 [PIPE_FORMAT_R32_UNORM] = ISL_FORMAT_R32_UNORM,
70 [PIPE_FORMAT_R32G32_UNORM] = ISL_FORMAT_R32G32_UNORM,
71 [PIPE_FORMAT_R32G32B32_UNORM] = ISL_FORMAT_R32G32B32_UNORM,
72 [PIPE_FORMAT_R32G32B32A32_UNORM] = ISL_FORMAT_R32G32B32A32_UNORM,
73 [PIPE_FORMAT_R32_USCALED] = ISL_FORMAT_R32_USCALED,
74 [PIPE_FORMAT_R32G32_USCALED] = ISL_FORMAT_R32G32_USCALED,
75 [PIPE_FORMAT_R32G32B32_USCALED] = ISL_FORMAT_R32G32B32_USCALED,
76 [PIPE_FORMAT_R32G32B32A32_USCALED] = ISL_FORMAT_R32G32B32A32_USCALED,
77 [PIPE_FORMAT_R32_SNORM] = ISL_FORMAT_R32_SNORM,
78 [PIPE_FORMAT_R32G32_SNORM] = ISL_FORMAT_R32G32_SNORM,
79 [PIPE_FORMAT_R32G32B32_SNORM] = ISL_FORMAT_R32G32B32_SNORM,
80 [PIPE_FORMAT_R32G32B32A32_SNORM] = ISL_FORMAT_R32G32B32A32_SNORM,
81 [PIPE_FORMAT_R32_SSCALED] = ISL_FORMAT_R32_SSCALED,
82 [PIPE_FORMAT_R32G32_SSCALED] = ISL_FORMAT_R32G32_SSCALED,
83 [PIPE_FORMAT_R32G32B32_SSCALED] = ISL_FORMAT_R32G32B32_SSCALED,
84 [PIPE_FORMAT_R32G32B32A32_SSCALED] = ISL_FORMAT_R32G32B32A32_SSCALED,
85 [PIPE_FORMAT_R16_UNORM] = ISL_FORMAT_R16_UNORM,
86 [PIPE_FORMAT_R16G16_UNORM] = ISL_FORMAT_R16G16_UNORM,
87 [PIPE_FORMAT_R16G16B16_UNORM] = ISL_FORMAT_R16G16B16_UNORM,
88 [PIPE_FORMAT_R16G16B16A16_UNORM] = ISL_FORMAT_R16G16B16A16_UNORM,
89 [PIPE_FORMAT_R16_USCALED] = ISL_FORMAT_R16_USCALED,
90 [PIPE_FORMAT_R16G16_USCALED] = ISL_FORMAT_R16G16_USCALED,
91 [PIPE_FORMAT_R16G16B16_USCALED] = ISL_FORMAT_R16G16B16_USCALED,
92 [PIPE_FORMAT_R16G16B16A16_USCALED] = ISL_FORMAT_R16G16B16A16_USCALED,
93 [PIPE_FORMAT_R16_SNORM] = ISL_FORMAT_R16_SNORM,
94 [PIPE_FORMAT_R16G16_SNORM] = ISL_FORMAT_R16G16_SNORM,
95 [PIPE_FORMAT_R16G16B16_SNORM] = ISL_FORMAT_R16G16B16_SNORM,
96 [PIPE_FORMAT_R16G16B16A16_SNORM] = ISL_FORMAT_R16G16B16A16_SNORM,
97 [PIPE_FORMAT_R16_SSCALED] = ISL_FORMAT_R16_SSCALED,
98 [PIPE_FORMAT_R16G16_SSCALED] = ISL_FORMAT_R16G16_SSCALED,
99 [PIPE_FORMAT_R16G16B16_SSCALED] = ISL_FORMAT_R16G16B16_SSCALED,
100 [PIPE_FORMAT_R16G16B16A16_SSCALED] = ISL_FORMAT_R16G16B16A16_SSCALED,
101 [PIPE_FORMAT_R8_UNORM] = ISL_FORMAT_R8_UNORM,
102 [PIPE_FORMAT_R8G8_UNORM] = ISL_FORMAT_R8G8_UNORM,
103 [PIPE_FORMAT_R8G8B8_UNORM] = ISL_FORMAT_R8G8B8_UNORM,
104 [PIPE_FORMAT_R8G8B8A8_UNORM] = ISL_FORMAT_R8G8B8A8_UNORM,
105 //[PIPE_FORMAT_X8B8G8R8_UNORM] = ISL_FORMAT_X8B8G8R8_UNORM,
106 [PIPE_FORMAT_R8_USCALED] = ISL_FORMAT_R8_USCALED,
107 [PIPE_FORMAT_R8G8_USCALED] = ISL_FORMAT_R8G8_USCALED,
108 [PIPE_FORMAT_R8G8B8_USCALED] = ISL_FORMAT_R8G8B8_USCALED,
109 [PIPE_FORMAT_R8G8B8A8_USCALED] = ISL_FORMAT_R8G8B8A8_USCALED,
110 [PIPE_FORMAT_R8_SNORM] = ISL_FORMAT_R8_SNORM,
111 [PIPE_FORMAT_R8G8_SNORM] = ISL_FORMAT_R8G8_SNORM,
112 [PIPE_FORMAT_R8G8B8_SNORM] = ISL_FORMAT_R8G8B8_SNORM,
113 [PIPE_FORMAT_R8G8B8A8_SNORM] = ISL_FORMAT_R8G8B8A8_SNORM,
114 [PIPE_FORMAT_R8_SSCALED] = ISL_FORMAT_R8_SSCALED,
115 [PIPE_FORMAT_R8G8_SSCALED] = ISL_FORMAT_R8G8_SSCALED,
116 [PIPE_FORMAT_R8G8B8_SSCALED] = ISL_FORMAT_R8G8B8_SSCALED,
117 [PIPE_FORMAT_R8G8B8A8_SSCALED] = ISL_FORMAT_R8G8B8A8_SSCALED,
118 [PIPE_FORMAT_R32_FIXED] = ISL_FORMAT_R32_SFIXED,
119 [PIPE_FORMAT_R32G32_FIXED] = ISL_FORMAT_R32G32_SFIXED,
120 [PIPE_FORMAT_R32G32B32_FIXED] = ISL_FORMAT_R32G32B32_SFIXED,
121 [PIPE_FORMAT_R32G32B32A32_FIXED] = ISL_FORMAT_R32G32B32A32_SFIXED,
122 [PIPE_FORMAT_R16_FLOAT] = ISL_FORMAT_R16_FLOAT,
123 [PIPE_FORMAT_R16G16_FLOAT] = ISL_FORMAT_R16G16_FLOAT,
124 [PIPE_FORMAT_R16G16B16_FLOAT] = ISL_FORMAT_R16G16B16_FLOAT,
125 [PIPE_FORMAT_R16G16B16A16_FLOAT] = ISL_FORMAT_R16G16B16A16_FLOAT,
126
127 //[PIPE_FORMAT_L8_SRGB] = ISL_FORMAT_L8_UNORM_SRGB,
128 //[PIPE_FORMAT_L8A8_SRGB] = ISL_FORMAT_L8A8_UNORM_SRGB,
129 [PIPE_FORMAT_R8G8B8_SRGB] = ISL_FORMAT_R8G8B8_UNORM_SRGB,
130 //[PIPE_FORMAT_A8B8G8R8_SRGB] = ISL_FORMAT_A8B8G8R8_UNORM_SRGB,
131 //[PIPE_FORMAT_X8B8G8R8_SRGB] = ISL_FORMAT_X8B8G8R8_UNORM_SRGB,
132 [PIPE_FORMAT_B8G8R8A8_SRGB] = ISL_FORMAT_B8G8R8A8_UNORM_SRGB,
133 [PIPE_FORMAT_B8G8R8X8_SRGB] = ISL_FORMAT_B8G8R8X8_UNORM_SRGB,
134 //[PIPE_FORMAT_A8R8G8B8_SRGB] = ISL_FORMAT_A8R8G8B8_UNORM_SRGB,
135 //[PIPE_FORMAT_X8R8G8B8_SRGB] = ISL_FORMAT_X8R8G8B8_UNORM_SRGB,
136 [PIPE_FORMAT_R8G8B8A8_SRGB] = ISL_FORMAT_R8G8B8A8_UNORM_SRGB,
137
138 [PIPE_FORMAT_DXT1_RGB] = ISL_FORMAT_BC1_UNORM,
139 [PIPE_FORMAT_DXT1_RGBA] = ISL_FORMAT_BC1_UNORM,
140 [PIPE_FORMAT_DXT3_RGBA] = ISL_FORMAT_BC2_UNORM,
141 [PIPE_FORMAT_DXT5_RGBA] = ISL_FORMAT_BC3_UNORM,
142
143 [PIPE_FORMAT_DXT1_SRGB] = ISL_FORMAT_BC1_UNORM_SRGB,
144 [PIPE_FORMAT_DXT1_SRGBA] = ISL_FORMAT_BC1_UNORM_SRGB,
145 [PIPE_FORMAT_DXT3_SRGBA] = ISL_FORMAT_BC2_UNORM_SRGB,
146 [PIPE_FORMAT_DXT5_SRGBA] = ISL_FORMAT_BC3_UNORM_SRGB,
147
148 [PIPE_FORMAT_RGTC1_UNORM] = ISL_FORMAT_BC4_UNORM,
149 [PIPE_FORMAT_RGTC1_SNORM] = ISL_FORMAT_BC4_SNORM,
150 [PIPE_FORMAT_RGTC2_UNORM] = ISL_FORMAT_BC5_UNORM,
151 [PIPE_FORMAT_RGTC2_SNORM] = ISL_FORMAT_BC5_SNORM,
152
153 //[PIPE_FORMAT_R8G8_B8G8_UNORM] = ISL_FORMAT_R8G8_B8G8_UNORM,
154 //[PIPE_FORMAT_G8R8_G8B8_UNORM] = ISL_FORMAT_G8R8_G8B8_UNORM,
155
156 //[PIPE_FORMAT_R8SG8SB8UX8U_NORM] = ISL_FORMAT_R8SG8SB8UX8U_NORM,
157 //[PIPE_FORMAT_R5SG5SB6U_NORM] = ISL_FORMAT_R5SG5SB6U_NORM,
158
159 //[PIPE_FORMAT_A8B8G8R8_UNORM] = ISL_FORMAT_A8B8G8R8_UNORM,
160 [PIPE_FORMAT_B5G5R5X1_UNORM] = ISL_FORMAT_B5G5R5X1_UNORM,
161 [PIPE_FORMAT_R10G10B10A2_USCALED] = ISL_FORMAT_R10G10B10A2_USCALED,
162 [PIPE_FORMAT_R11G11B10_FLOAT] = ISL_FORMAT_R11G11B10_FLOAT,
163 [PIPE_FORMAT_R9G9B9E5_FLOAT] = ISL_FORMAT_R9G9B9E5_SHAREDEXP,
164 [PIPE_FORMAT_Z32_FLOAT_S8X24_UINT] = ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS,
165 [PIPE_FORMAT_R1_UNORM] = ISL_FORMAT_R1_UNORM,
166 [PIPE_FORMAT_R10G10B10X2_USCALED] = ISL_FORMAT_R10G10B10X2_USCALED,
167 //[PIPE_FORMAT_R10G10B10X2_SNORM] = ISL_FORMAT_R10G10B10X2_SNORM,
168 //[PIPE_FORMAT_L4A4_UNORM] = ISL_FORMAT_R4G4_UNORM,
169 [PIPE_FORMAT_B10G10R10A2_UNORM] = ISL_FORMAT_B10G10R10A2_UNORM,
170 //[PIPE_FORMAT_R10SG10SB10SA2U_NORM] = ISL_FORMAT_R10SG10SB10SA2U_NORM,
171 //[PIPE_FORMAT_R8G8Bx_SNORM] = ISL_FORMAT_R8G8Bx_SNORM,
172 [PIPE_FORMAT_R8G8B8X8_UNORM] = ISL_FORMAT_R8G8B8X8_UNORM,
173 //[PIPE_FORMAT_B4G4R4X4_UNORM] = ISL_FORMAT_B4G4R4X4_UNORM,
174
175 /* some stencil samplers formats */
176 //[PIPE_FORMAT_X24S8_UINT] = ISL_FORMAT_X24S8_UINT,
177 //[PIPE_FORMAT_S8X24_UINT] = ISL_FORMAT_S8X24_UINT,
178 //[PIPE_FORMAT_X32_S8X24_UINT] = ISL_FORMAT_X32_S8X24_UINT,
179
180 //[PIPE_FORMAT_B2G3R3_UNORM] = ISL_FORMAT_B2G3R3_UNORM,
181 //[PIPE_FORMAT_L16A16_UNORM] = ISL_FORMAT_R16G16_UNORM,
182 //[PIPE_FORMAT_A16_UNORM] = ISL_FORMAT_R16_UNORM,
183 //[PIPE_FORMAT_I16_UNORM] = ISL_FORMAT_R16_UNORM,
184
185 //[PIPE_FORMAT_LATC1_UNORM] = ISL_FORMAT_LATC1_UNORM,
186 //[PIPE_FORMAT_LATC1_SNORM] = ISL_FORMAT_LATC1_SNORM,
187 //[PIPE_FORMAT_LATC2_UNORM] = ISL_FORMAT_LATC2_UNORM,
188 //[PIPE_FORMAT_LATC2_SNORM] = ISL_FORMAT_LATC2_SNORM,
189
190 //[PIPE_FORMAT_A8_SNORM] = ISL_FORMAT_R8_SNORM,
191 //[PIPE_FORMAT_L8_SNORM] = ISL_FORMAT_R8_SNORM,
192 //[PIPE_FORMAT_L8A8_SNORM] = ISL_FORMAT_R8G8_SNORM,
193 //[PIPE_FORMAT_I8_SNORM] = ISL_FORMAT_R8_SNORM,
194 //[PIPE_FORMAT_A16_SNORM] = ISL_FORMAT_R16_SNORM,
195 //[PIPE_FORMAT_L16_SNORM] = ISL_FORMAT_R16_SNORM,
196 //[PIPE_FORMAT_L16A16_SNORM] = ISL_FORMAT_R16G16_SNORM,
197 //[PIPE_FORMAT_I16_SNORM] = ISL_FORMAT_R16_SNORM,
198
199 //[PIPE_FORMAT_A16_FLOAT] = ISL_FORMAT_R16_FLOAT,
200 //[PIPE_FORMAT_L16_FLOAT] = ISL_FORMAT_R16_FLOAT,
201 //[PIPE_FORMAT_L16A16_FLOAT] = ISL_FORMAT_R16G16_FLOAT,
202 //[PIPE_FORMAT_I16_FLOAT] = ISL_FORMAT_R16_FLOAT,
203 //[PIPE_FORMAT_A32_FLOAT] = ISL_FORMAT_R32_FLOAT,
204 //[PIPE_FORMAT_L32_FLOAT] = ISL_FORMAT_R32_FLOAT,
205 //[PIPE_FORMAT_L32A32_FLOAT] = ISL_FORMAT_R32G32_FLOAT,
206 //[PIPE_FORMAT_I32_FLOAT] = ISL_FORMAT_R32_FLOAT,
207
208 //[PIPE_FORMAT_YV12] = ISL_FORMAT_YV12,
209 //[PIPE_FORMAT_YV16] = ISL_FORMAT_YV16,
210 //[PIPE_FORMAT_IYUV] = ISL_FORMAT_IYUV,
211 //[PIPE_FORMAT_NV12] = ISL_FORMAT_NV12,
212 //[PIPE_FORMAT_NV21] = ISL_FORMAT_NV21,
213
214 //[PIPE_FORMAT_A4R4_UNORM] = ISL_FORMAT_A4R4_UNORM,
215 //[PIPE_FORMAT_R4A4_UNORM] = ISL_FORMAT_R4A4_UNORM,
216 //[PIPE_FORMAT_R8A8_UNORM] = ISL_FORMAT_R8A8_UNORM,
217 //[PIPE_FORMAT_A8R8_UNORM] = ISL_FORMAT_A8R8_UNORM,
218
219 [PIPE_FORMAT_R10G10B10A2_SSCALED] = ISL_FORMAT_R10G10B10A2_SSCALED,
220 [PIPE_FORMAT_R10G10B10A2_SNORM] = ISL_FORMAT_R10G10B10A2_SNORM,
221
222 [PIPE_FORMAT_B10G10R10A2_USCALED] = ISL_FORMAT_B10G10R10A2_USCALED,
223 [PIPE_FORMAT_B10G10R10A2_SSCALED] = ISL_FORMAT_B10G10R10A2_SSCALED,
224 [PIPE_FORMAT_B10G10R10A2_SNORM] = ISL_FORMAT_B10G10R10A2_SNORM,
225
226 [PIPE_FORMAT_R8_UINT] = ISL_FORMAT_R8_UINT,
227 [PIPE_FORMAT_R8G8_UINT] = ISL_FORMAT_R8G8_UINT,
228 [PIPE_FORMAT_R8G8B8_UINT] = ISL_FORMAT_R8G8B8_UINT,
229 [PIPE_FORMAT_R8G8B8A8_UINT] = ISL_FORMAT_R8G8B8A8_UINT,
230
231 [PIPE_FORMAT_R8_SINT] = ISL_FORMAT_R8_SINT,
232 [PIPE_FORMAT_R8G8_SINT] = ISL_FORMAT_R8G8_SINT,
233 [PIPE_FORMAT_R8G8B8_SINT] = ISL_FORMAT_R8G8B8_SINT,
234 [PIPE_FORMAT_R8G8B8A8_SINT] = ISL_FORMAT_R8G8B8A8_SINT,
235
236 [PIPE_FORMAT_R16_UINT] = ISL_FORMAT_R16_UINT,
237 [PIPE_FORMAT_R16G16_UINT] = ISL_FORMAT_R16G16_UINT,
238 [PIPE_FORMAT_R16G16B16_UINT] = ISL_FORMAT_R16G16B16_UINT,
239 [PIPE_FORMAT_R16G16B16A16_UINT] = ISL_FORMAT_R16G16B16A16_UINT,
240
241 [PIPE_FORMAT_R16_SINT] = ISL_FORMAT_R16_SINT,
242 [PIPE_FORMAT_R16G16_SINT] = ISL_FORMAT_R16G16_SINT,
243 [PIPE_FORMAT_R16G16B16_SINT] = ISL_FORMAT_R16G16B16_SINT,
244 [PIPE_FORMAT_R16G16B16A16_SINT] = ISL_FORMAT_R16G16B16A16_SINT,
245
246 [PIPE_FORMAT_R32_UINT] = ISL_FORMAT_R32_UINT,
247 [PIPE_FORMAT_R32G32_UINT] = ISL_FORMAT_R32G32_UINT,
248 [PIPE_FORMAT_R32G32B32_UINT] = ISL_FORMAT_R32G32B32_UINT,
249 [PIPE_FORMAT_R32G32B32A32_UINT] = ISL_FORMAT_R32G32B32A32_UINT,
250
251 [PIPE_FORMAT_R32_SINT] = ISL_FORMAT_R32_SINT,
252 [PIPE_FORMAT_R32G32_SINT] = ISL_FORMAT_R32G32_SINT,
253 [PIPE_FORMAT_R32G32B32_SINT] = ISL_FORMAT_R32G32B32_SINT,
254 [PIPE_FORMAT_R32G32B32A32_SINT] = ISL_FORMAT_R32G32B32A32_SINT,
255
256 /*
257 [PIPE_FORMAT_A8_UINT] = ISL_FORMAT_R8_UINT,
258 [PIPE_FORMAT_I8_UINT] = ISL_FORMAT_R8_UINT,
259 [PIPE_FORMAT_L8_UINT] = ISL_FORMAT_R8_UINT,
260 [PIPE_FORMAT_L8A8_UINT] = ISL_FORMAT_R8G8_UINT,
261
262 [PIPE_FORMAT_A8_SINT] = ISL_FORMAT_R8_SINT,
263 [PIPE_FORMAT_I8_SINT] = ISL_FORMAT_R8_SINT,
264 [PIPE_FORMAT_L8_SINT] = ISL_FORMAT_R8_SINT,
265 [PIPE_FORMAT_L8A8_SINT] = ISL_FORMAT_R8G8_SINT,
266
267 [PIPE_FORMAT_A16_UINT] = ISL_FORMAT_R16_UINT,
268 [PIPE_FORMAT_I16_UINT] = ISL_FORMAT_R16_UINT,
269 [PIPE_FORMAT_L16_UINT] = ISL_FORMAT_R16_UINT,
270 [PIPE_FORMAT_L16A16_UINT] = ISL_FORMAT_R16G16_UINT,
271
272 [PIPE_FORMAT_A16_SINT] = ISL_FORMAT_R16_SINT,
273 [PIPE_FORMAT_I16_SINT] = ISL_FORMAT_R16_SINT,
274 [PIPE_FORMAT_L16_SINT] = ISL_FORMAT_R16_SINT,
275 [PIPE_FORMAT_L16A16_SINT] = ISL_FORMAT_R16G16_SINT,
276
277 [PIPE_FORMAT_A32_UINT] = ISL_FORMAT_R32_UINT,
278 [PIPE_FORMAT_I32_UINT] = ISL_FORMAT_R32_UINT,
279 [PIPE_FORMAT_L32_UINT] = ISL_FORMAT_R32_UINT,
280 [PIPE_FORMAT_L32A32_UINT] = ISL_FORMAT_R32G32_UINT,
281
282 [PIPE_FORMAT_A32_SINT] = ISL_FORMAT_R32_SINT,
283 [PIPE_FORMAT_I32_SINT] = ISL_FORMAT_R32_SINT,
284 [PIPE_FORMAT_L32_SINT] = ISL_FORMAT_R32_SINT,
285 [PIPE_FORMAT_L32A32_SINT] = ISL_FORMAT_R32G32_SINT,
286 */
287
288 [PIPE_FORMAT_B10G10R10A2_UINT] = ISL_FORMAT_B10G10R10A2_UINT,
289
290 [PIPE_FORMAT_ETC1_RGB8] = ISL_FORMAT_ETC1_RGB8,
291
292 //[PIPE_FORMAT_R8G8_R8B8_UNORM] = ISL_FORMAT_R8G8_R8B8_UNORM,
293 //[PIPE_FORMAT_G8R8_B8R8_UNORM] = ISL_FORMAT_G8R8_B8R8_UNORM,
294
295 //[PIPE_FORMAT_R8G8B8X8_SNORM] = ISL_FORMAT_R8G8B8X8_SNORM,
296 [PIPE_FORMAT_R8G8B8X8_SRGB] = ISL_FORMAT_R8G8B8X8_UNORM_SRGB,
297 //[PIPE_FORMAT_R8G8B8X8_UINT] = ISL_FORMAT_R8G8B8X8_UINT,
298 //[PIPE_FORMAT_R8G8B8X8_SINT] = ISL_FORMAT_R8G8B8X8_SINT,
299 [PIPE_FORMAT_B10G10R10X2_UNORM] = ISL_FORMAT_B10G10R10X2_UNORM,
300 [PIPE_FORMAT_R16G16B16X16_UNORM] = ISL_FORMAT_R16G16B16X16_UNORM,
301 //[PIPE_FORMAT_R16G16B16X16_SNORM] = ISL_FORMAT_R16G16B16X16_SNORM,
302 [PIPE_FORMAT_R16G16B16X16_FLOAT] = ISL_FORMAT_R16G16B16X16_FLOAT,
303 //[PIPE_FORMAT_R16G16B16X16_UINT] = ISL_FORMAT_R16G16B16X16_UINT,
304 //[PIPE_FORMAT_R16G16B16X16_SINT] = ISL_FORMAT_R16G16B16X16_SINT,
305 [PIPE_FORMAT_R32G32B32X32_FLOAT] = ISL_FORMAT_R32G32B32X32_FLOAT,
306 //[PIPE_FORMAT_R32G32B32X32_UINT] = ISL_FORMAT_R32G32B32X32_UINT,
307 //[PIPE_FORMAT_R32G32B32X32_SINT] = ISL_FORMAT_R32G32B32X32_SINT,
308
309 //[PIPE_FORMAT_R8A8_SNORM] = ISL_FORMAT_R8A8_SNORM,
310 //[PIPE_FORMAT_R16A16_UNORM] = ISL_FORMAT_R16A16_UNORM,
311 //[PIPE_FORMAT_R16A16_SNORM] = ISL_FORMAT_R16A16_SNORM,
312 //[PIPE_FORMAT_R16A16_FLOAT] = ISL_FORMAT_R16A16_FLOAT,
313 //[PIPE_FORMAT_R32A32_FLOAT] = ISL_FORMAT_R32A32_FLOAT,
314 //[PIPE_FORMAT_R8A8_UINT] = ISL_FORMAT_R8A8_UINT,
315 //[PIPE_FORMAT_R8A8_SINT] = ISL_FORMAT_R8A8_SINT,
316 //[PIPE_FORMAT_R16A16_UINT] = ISL_FORMAT_R16A16_UINT,
317 //[PIPE_FORMAT_R16A16_SINT] = ISL_FORMAT_R16A16_SINT,
318 //[PIPE_FORMAT_R32A32_UINT] = ISL_FORMAT_R32A32_UINT,
319 //[PIPE_FORMAT_R32A32_SINT] = ISL_FORMAT_R32A32_SINT,
320 [PIPE_FORMAT_R10G10B10A2_UINT] = ISL_FORMAT_R10G10B10A2_UINT,
321
322 [PIPE_FORMAT_B5G6R5_SRGB] = ISL_FORMAT_B5G6R5_UNORM_SRGB,
323
324 [PIPE_FORMAT_BPTC_RGBA_UNORM] = ISL_FORMAT_BC7_UNORM,
325 [PIPE_FORMAT_BPTC_SRGBA] = ISL_FORMAT_BC7_UNORM_SRGB,
326 [PIPE_FORMAT_BPTC_RGB_FLOAT] = ISL_FORMAT_BC6H_SF16,
327 [PIPE_FORMAT_BPTC_RGB_UFLOAT] = ISL_FORMAT_BC6H_UF16,
328
329 //[PIPE_FORMAT_A8L8_UNORM] = ISL_FORMAT_A8L8_UNORM,
330 //[PIPE_FORMAT_A8L8_SNORM] = ISL_FORMAT_A8L8_SNORM,
331 //[PIPE_FORMAT_A8L8_SRGB] = ISL_FORMAT_A8L8_SRGB,
332 //[PIPE_FORMAT_A16L16_UNORM] = ISL_FORMAT_A16L16_UNORM,
333
334 //[PIPE_FORMAT_G8R8_UNORM] = ISL_FORMAT_G8R8_UNORM,
335 //[PIPE_FORMAT_G8R8_SNORM] = ISL_FORMAT_G8R8_SNORM,
336 //[PIPE_FORMAT_G16R16_UNORM] = ISL_FORMAT_G16R16_UNORM,
337 //[PIPE_FORMAT_G16R16_SNORM] = ISL_FORMAT_G16R16_SNORM,
338
339 //[PIPE_FORMAT_A8B8G8R8_SNORM] = ISL_FORMAT_A8B8G8R8_SNORM,
340 //[PIPE_FORMAT_X8B8G8R8_SNORM] = ISL_FORMAT_X8B8G8R8_SNORM,
341
342 [PIPE_FORMAT_ETC2_RGB8] = ISL_FORMAT_ETC2_RGB8,
343 [PIPE_FORMAT_ETC2_SRGB8] = ISL_FORMAT_ETC2_SRGB8,
344 [PIPE_FORMAT_ETC2_RGB8A1] = ISL_FORMAT_ETC2_RGB8_PTA,
345 [PIPE_FORMAT_ETC2_SRGB8A1] = ISL_FORMAT_ETC2_SRGB8_PTA,
346 [PIPE_FORMAT_ETC2_RGBA8] = ISL_FORMAT_ETC2_EAC_RGBA8,
347 [PIPE_FORMAT_ETC2_SRGBA8] = ISL_FORMAT_ETC2_EAC_SRGB8_A8,
348 [PIPE_FORMAT_ETC2_R11_UNORM] = ISL_FORMAT_EAC_R11,
349 [PIPE_FORMAT_ETC2_R11_SNORM] = ISL_FORMAT_EAC_SIGNED_R11,
350 [PIPE_FORMAT_ETC2_RG11_UNORM] = ISL_FORMAT_EAC_RG11,
351 [PIPE_FORMAT_ETC2_RG11_SNORM] = ISL_FORMAT_EAC_SIGNED_RG11,
352
353
354 [PIPE_FORMAT_ASTC_4x4] = ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16,
355 [PIPE_FORMAT_ASTC_5x4] = ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16,
356 [PIPE_FORMAT_ASTC_5x5] = ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16,
357 [PIPE_FORMAT_ASTC_6x5] = ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16,
358 [PIPE_FORMAT_ASTC_6x6] = ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16,
359 [PIPE_FORMAT_ASTC_8x5] = ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16,
360 [PIPE_FORMAT_ASTC_8x6] = ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16,
361 [PIPE_FORMAT_ASTC_8x8] = ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16,
362 [PIPE_FORMAT_ASTC_10x5] = ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16,
363 [PIPE_FORMAT_ASTC_10x6] = ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16,
364 [PIPE_FORMAT_ASTC_10x8] = ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16,
365 [PIPE_FORMAT_ASTC_10x10] = ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16,
366 [PIPE_FORMAT_ASTC_12x10] = ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16,
367 [PIPE_FORMAT_ASTC_12x12] = ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16,
368
369 [PIPE_FORMAT_ASTC_4x4_SRGB] = ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB,
370 [PIPE_FORMAT_ASTC_5x4_SRGB] = ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB,
371 [PIPE_FORMAT_ASTC_5x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB,
372 [PIPE_FORMAT_ASTC_6x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB,
373 [PIPE_FORMAT_ASTC_6x6_SRGB] = ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB,
374 [PIPE_FORMAT_ASTC_8x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB,
375 [PIPE_FORMAT_ASTC_8x6_SRGB] = ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB,
376 [PIPE_FORMAT_ASTC_8x8_SRGB] = ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB,
377 [PIPE_FORMAT_ASTC_10x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB,
378 [PIPE_FORMAT_ASTC_10x6_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB,
379 [PIPE_FORMAT_ASTC_10x8_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB,
380 [PIPE_FORMAT_ASTC_10x10_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB,
381 [PIPE_FORMAT_ASTC_12x10_SRGB] = ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB,
382 [PIPE_FORMAT_ASTC_12x12_SRGB] = ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB,
383
384 //[PIPE_FORMAT_P016] = ISL_FORMAT_P016,
385
386 //[PIPE_FORMAT_R10G10B10X2_UNORM] = ISL_FORMAT_R10G10B10X2_UNORM,
387 [PIPE_FORMAT_A1B5G5R5_UNORM] = ISL_FORMAT_A1B5G5R5_UNORM,
388 //[PIPE_FORMAT_X1B5G5R5_UNORM] = ISL_FORMAT_X1B5G5R5_UNORM,
389 };
390 assert(pf < PIPE_FORMAT_COUNT);
391 return table[pf];
392 }
393
394 boolean
395 iris_is_format_supported(struct pipe_screen *pscreen,
396 enum pipe_format pformat,
397 enum pipe_texture_target target,
398 unsigned sample_count,
399 unsigned storage_sample_count,
400 unsigned usage)
401 {
402 struct iris_screen *screen = (struct iris_screen *) pscreen;
403 const struct gen_device_info *devinfo = &screen->devinfo;
404
405 // XXX: msaa max
406 if (sample_count > 16 || !util_is_power_of_two_or_zero(sample_count))
407 return false;
408
409 if (pformat == PIPE_FORMAT_NONE)
410 return true;
411
412 enum isl_format format = iris_isl_format_for_pipe_format(pformat);
413
414 if (format == ISL_FORMAT_UNSUPPORTED)
415 return false;
416
417 bool supported = true;
418
419 if (sample_count > 1)
420 supported &= isl_format_supports_multisampling(devinfo, format);
421
422 if (usage & PIPE_BIND_DEPTH_STENCIL) {
423 supported &= format == ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS ||
424 format == ISL_FORMAT_R32_FLOAT ||
425 format == ISL_FORMAT_R24_UNORM_X8_TYPELESS ||
426 format == ISL_FORMAT_R16_UNORM;
427 }
428
429 if (usage & PIPE_BIND_RENDER_TARGET)
430 supported &= isl_format_supports_rendering(devinfo, format);
431
432 if (usage & PIPE_BIND_SHADER_IMAGE) {
433 // XXX: allow untyped reads
434 supported &= isl_format_supports_typed_reads(devinfo, format) &&
435 isl_format_supports_typed_writes(devinfo, format);
436 }
437
438 if (usage & PIPE_BIND_SAMPLER_VIEW)
439 supported &= isl_format_supports_sampling(devinfo, format);
440
441 if (usage & PIPE_BIND_VERTEX_BUFFER)
442 supported &= isl_format_supports_vertex_fetch(devinfo, format);
443
444 if (usage & PIPE_BIND_INDEX_BUFFER) {
445 supported &= format == ISL_FORMAT_R8_UINT ||
446 format == ISL_FORMAT_R16_UINT ||
447 format == ISL_FORMAT_R32_UINT;
448 }
449
450 if (usage & PIPE_BIND_CONSTANT_BUFFER) {
451 // XXX:
452 }
453
454 if (usage & PIPE_BIND_STREAM_OUTPUT) {
455 // XXX:
456 }
457
458 if (usage & PIPE_BIND_CURSOR) {
459 // XXX:
460 }
461
462 if (usage & PIPE_BIND_CUSTOM) {
463 // XXX:
464 }
465
466 if (usage & PIPE_BIND_SHADER_BUFFER) {
467 // XXX:
468 }
469
470 if (usage & PIPE_BIND_COMPUTE_RESOURCE) {
471 // XXX:
472 }
473
474 if (usage & PIPE_BIND_COMMAND_ARGS_BUFFER) {
475 // XXX:
476 }
477
478 if (usage & PIPE_BIND_QUERY_BUFFER) {
479 // XXX:
480 }
481
482 return supported;
483 }
484