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iris: enable a few more formats
[mesa.git] / src / gallium / drivers / iris / iris_formats.c
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "util/u_format.h"
25 #include "util/macros.h"
26
27 #include "iris_resource.h"
28 #include "iris_screen.h"
29
30 enum isl_format
31 iris_isl_format_for_pipe_format(enum pipe_format pf)
32 {
33 static const enum isl_format table[PIPE_FORMAT_COUNT] = {
34 [0 ... PIPE_FORMAT_COUNT-1] = ISL_FORMAT_UNSUPPORTED,
35
36 [PIPE_FORMAT_B8G8R8A8_UNORM] = ISL_FORMAT_B8G8R8A8_UNORM,
37 [PIPE_FORMAT_B8G8R8X8_UNORM] = ISL_FORMAT_B8G8R8X8_UNORM,
38 //[PIPE_FORMAT_A8R8G8B8_UNORM] = ISL_FORMAT_A8R8G8B8_UNORM,
39 //[PIPE_FORMAT_X8R8G8B8_UNORM] = ISL_FORMAT_X8R8G8B8_UNORM,
40 [PIPE_FORMAT_B5G5R5A1_UNORM] = ISL_FORMAT_B5G5R5A1_UNORM,
41 [PIPE_FORMAT_B4G4R4A4_UNORM] = ISL_FORMAT_B4G4R4A4_UNORM,
42 [PIPE_FORMAT_B5G6R5_UNORM] = ISL_FORMAT_B5G6R5_UNORM,
43 [PIPE_FORMAT_R10G10B10A2_UNORM] = ISL_FORMAT_R10G10B10A2_UNORM,
44 [PIPE_FORMAT_L8_UNORM] = ISL_FORMAT_L8_UNORM,
45 [PIPE_FORMAT_A8_UNORM] = ISL_FORMAT_A8_UNORM,
46 [PIPE_FORMAT_I8_UNORM] = ISL_FORMAT_I8_UNORM,
47 [PIPE_FORMAT_L8A8_UNORM] = ISL_FORMAT_L8A8_UNORM,
48 [PIPE_FORMAT_L16_UNORM] = ISL_FORMAT_L16_UNORM,
49 //[PIPE_FORMAT_UYVY] = ISL_FORMAT_UYVY,
50 //[PIPE_FORMAT_YUYV] = ISL_FORMAT_YUYV,
51 [PIPE_FORMAT_Z16_UNORM] = ISL_FORMAT_R16_UNORM,
52 [PIPE_FORMAT_Z32_UNORM] = ISL_FORMAT_R32_UNORM,
53 [PIPE_FORMAT_Z32_FLOAT] = ISL_FORMAT_R32_FLOAT,
54 //[PIPE_FORMAT_Z24_UNORM_S8_UINT] = ISL_FORMAT_R24_UNORM_S8_UINT,
55 //[PIPE_FORMAT_S8_UINT_Z24_UNORM] = ISL_FORMAT_S8_UINT_Z24_UNORM,
56 [PIPE_FORMAT_Z24X8_UNORM] = ISL_FORMAT_R24_UNORM_X8_TYPELESS,
57 //[PIPE_FORMAT_X8Z24_UNORM] = ISL_FORMAT_R24_UNORM_X8_TYPELESS,
58 [PIPE_FORMAT_S8_UINT] = ISL_FORMAT_R8_UINT,
59 [PIPE_FORMAT_R64_FLOAT] = ISL_FORMAT_R64_FLOAT,
60 [PIPE_FORMAT_R64G64_FLOAT] = ISL_FORMAT_R64G64_FLOAT,
61 [PIPE_FORMAT_R64G64B64_FLOAT] = ISL_FORMAT_R64G64B64_FLOAT,
62 [PIPE_FORMAT_R64G64B64A64_FLOAT] = ISL_FORMAT_R64G64B64A64_FLOAT,
63 [PIPE_FORMAT_R32_FLOAT] = ISL_FORMAT_R32_FLOAT,
64 [PIPE_FORMAT_R32G32_FLOAT] = ISL_FORMAT_R32G32_FLOAT,
65 [PIPE_FORMAT_R32G32B32_FLOAT] = ISL_FORMAT_R32G32B32_FLOAT,
66 [PIPE_FORMAT_R32G32B32A32_FLOAT] = ISL_FORMAT_R32G32B32A32_FLOAT,
67 [PIPE_FORMAT_R32_UNORM] = ISL_FORMAT_R32_UNORM,
68 [PIPE_FORMAT_R32G32_UNORM] = ISL_FORMAT_R32G32_UNORM,
69 [PIPE_FORMAT_R32G32B32_UNORM] = ISL_FORMAT_R32G32B32_UNORM,
70 [PIPE_FORMAT_R32G32B32A32_UNORM] = ISL_FORMAT_R32G32B32A32_UNORM,
71 [PIPE_FORMAT_R32_USCALED] = ISL_FORMAT_R32_USCALED,
72 [PIPE_FORMAT_R32G32_USCALED] = ISL_FORMAT_R32G32_USCALED,
73 [PIPE_FORMAT_R32G32B32_USCALED] = ISL_FORMAT_R32G32B32_USCALED,
74 [PIPE_FORMAT_R32G32B32A32_USCALED] = ISL_FORMAT_R32G32B32A32_USCALED,
75 [PIPE_FORMAT_R32_SNORM] = ISL_FORMAT_R32_SNORM,
76 [PIPE_FORMAT_R32G32_SNORM] = ISL_FORMAT_R32G32_SNORM,
77 [PIPE_FORMAT_R32G32B32_SNORM] = ISL_FORMAT_R32G32B32_SNORM,
78 [PIPE_FORMAT_R32G32B32A32_SNORM] = ISL_FORMAT_R32G32B32A32_SNORM,
79 [PIPE_FORMAT_R32_SSCALED] = ISL_FORMAT_R32_SSCALED,
80 [PIPE_FORMAT_R32G32_SSCALED] = ISL_FORMAT_R32G32_SSCALED,
81 [PIPE_FORMAT_R32G32B32_SSCALED] = ISL_FORMAT_R32G32B32_SSCALED,
82 [PIPE_FORMAT_R32G32B32A32_SSCALED] = ISL_FORMAT_R32G32B32A32_SSCALED,
83 [PIPE_FORMAT_R16_UNORM] = ISL_FORMAT_R16_UNORM,
84 [PIPE_FORMAT_R16G16_UNORM] = ISL_FORMAT_R16G16_UNORM,
85 [PIPE_FORMAT_R16G16B16_UNORM] = ISL_FORMAT_R16G16B16_UNORM,
86 [PIPE_FORMAT_R16G16B16A16_UNORM] = ISL_FORMAT_R16G16B16A16_UNORM,
87 [PIPE_FORMAT_R16_USCALED] = ISL_FORMAT_R16_USCALED,
88 [PIPE_FORMAT_R16G16_USCALED] = ISL_FORMAT_R16G16_USCALED,
89 [PIPE_FORMAT_R16G16B16_USCALED] = ISL_FORMAT_R16G16B16_USCALED,
90 [PIPE_FORMAT_R16G16B16A16_USCALED] = ISL_FORMAT_R16G16B16A16_USCALED,
91 [PIPE_FORMAT_R16_SNORM] = ISL_FORMAT_R16_SNORM,
92 [PIPE_FORMAT_R16G16_SNORM] = ISL_FORMAT_R16G16_SNORM,
93 [PIPE_FORMAT_R16G16B16_SNORM] = ISL_FORMAT_R16G16B16_SNORM,
94 [PIPE_FORMAT_R16G16B16A16_SNORM] = ISL_FORMAT_R16G16B16A16_SNORM,
95 [PIPE_FORMAT_R16_SSCALED] = ISL_FORMAT_R16_SSCALED,
96 [PIPE_FORMAT_R16G16_SSCALED] = ISL_FORMAT_R16G16_SSCALED,
97 [PIPE_FORMAT_R16G16B16_SSCALED] = ISL_FORMAT_R16G16B16_SSCALED,
98 [PIPE_FORMAT_R16G16B16A16_SSCALED] = ISL_FORMAT_R16G16B16A16_SSCALED,
99 [PIPE_FORMAT_R8_UNORM] = ISL_FORMAT_R8_UNORM,
100 [PIPE_FORMAT_R8G8_UNORM] = ISL_FORMAT_R8G8_UNORM,
101 [PIPE_FORMAT_R8G8B8_UNORM] = ISL_FORMAT_R8G8B8_UNORM,
102 [PIPE_FORMAT_R8G8B8A8_UNORM] = ISL_FORMAT_R8G8B8A8_UNORM,
103 //[PIPE_FORMAT_X8B8G8R8_UNORM] = ISL_FORMAT_X8B8G8R8_UNORM,
104 [PIPE_FORMAT_R8_USCALED] = ISL_FORMAT_R8_USCALED,
105 [PIPE_FORMAT_R8G8_USCALED] = ISL_FORMAT_R8G8_USCALED,
106 [PIPE_FORMAT_R8G8B8_USCALED] = ISL_FORMAT_R8G8B8_USCALED,
107 [PIPE_FORMAT_R8G8B8A8_USCALED] = ISL_FORMAT_R8G8B8A8_USCALED,
108 [PIPE_FORMAT_R8_SNORM] = ISL_FORMAT_R8_SNORM,
109 [PIPE_FORMAT_R8G8_SNORM] = ISL_FORMAT_R8G8_SNORM,
110 [PIPE_FORMAT_R8G8B8_SNORM] = ISL_FORMAT_R8G8B8_SNORM,
111 [PIPE_FORMAT_R8G8B8A8_SNORM] = ISL_FORMAT_R8G8B8A8_SNORM,
112 [PIPE_FORMAT_R8_SSCALED] = ISL_FORMAT_R8_SSCALED,
113 [PIPE_FORMAT_R8G8_SSCALED] = ISL_FORMAT_R8G8_SSCALED,
114 [PIPE_FORMAT_R8G8B8_SSCALED] = ISL_FORMAT_R8G8B8_SSCALED,
115 [PIPE_FORMAT_R8G8B8A8_SSCALED] = ISL_FORMAT_R8G8B8A8_SSCALED,
116 [PIPE_FORMAT_R32_FIXED] = ISL_FORMAT_R32_SFIXED,
117 [PIPE_FORMAT_R32G32_FIXED] = ISL_FORMAT_R32G32_SFIXED,
118 [PIPE_FORMAT_R32G32B32_FIXED] = ISL_FORMAT_R32G32B32_SFIXED,
119 [PIPE_FORMAT_R32G32B32A32_FIXED] = ISL_FORMAT_R32G32B32A32_SFIXED,
120 [PIPE_FORMAT_R16_FLOAT] = ISL_FORMAT_R16_FLOAT,
121 [PIPE_FORMAT_R16G16_FLOAT] = ISL_FORMAT_R16G16_FLOAT,
122 [PIPE_FORMAT_R16G16B16_FLOAT] = ISL_FORMAT_R16G16B16_FLOAT,
123 [PIPE_FORMAT_R16G16B16A16_FLOAT] = ISL_FORMAT_R16G16B16A16_FLOAT,
124
125 [PIPE_FORMAT_L8_SRGB] = ISL_FORMAT_L8_UNORM_SRGB,
126 [PIPE_FORMAT_L8A8_SRGB] = ISL_FORMAT_L8A8_UNORM_SRGB,
127 [PIPE_FORMAT_R8G8B8_SRGB] = ISL_FORMAT_R8G8B8_UNORM_SRGB,
128 //[PIPE_FORMAT_A8B8G8R8_SRGB] = ISL_FORMAT_A8B8G8R8_UNORM_SRGB,
129 //[PIPE_FORMAT_X8B8G8R8_SRGB] = ISL_FORMAT_X8B8G8R8_UNORM_SRGB,
130 [PIPE_FORMAT_B8G8R8A8_SRGB] = ISL_FORMAT_B8G8R8A8_UNORM_SRGB,
131 [PIPE_FORMAT_B8G8R8X8_SRGB] = ISL_FORMAT_B8G8R8X8_UNORM_SRGB,
132 //[PIPE_FORMAT_A8R8G8B8_SRGB] = ISL_FORMAT_A8R8G8B8_UNORM_SRGB,
133 //[PIPE_FORMAT_X8R8G8B8_SRGB] = ISL_FORMAT_X8R8G8B8_UNORM_SRGB,
134 [PIPE_FORMAT_R8G8B8A8_SRGB] = ISL_FORMAT_R8G8B8A8_UNORM_SRGB,
135
136 [PIPE_FORMAT_DXT1_RGB] = ISL_FORMAT_BC1_UNORM,
137 [PIPE_FORMAT_DXT1_RGBA] = ISL_FORMAT_BC1_UNORM,
138 [PIPE_FORMAT_DXT3_RGBA] = ISL_FORMAT_BC2_UNORM,
139 [PIPE_FORMAT_DXT5_RGBA] = ISL_FORMAT_BC3_UNORM,
140
141 [PIPE_FORMAT_DXT1_SRGB] = ISL_FORMAT_BC1_UNORM_SRGB,
142 [PIPE_FORMAT_DXT1_SRGBA] = ISL_FORMAT_BC1_UNORM_SRGB,
143 [PIPE_FORMAT_DXT3_SRGBA] = ISL_FORMAT_BC2_UNORM_SRGB,
144 [PIPE_FORMAT_DXT5_SRGBA] = ISL_FORMAT_BC3_UNORM_SRGB,
145
146 [PIPE_FORMAT_RGTC1_UNORM] = ISL_FORMAT_BC4_UNORM,
147 [PIPE_FORMAT_RGTC1_SNORM] = ISL_FORMAT_BC4_SNORM,
148 [PIPE_FORMAT_RGTC2_UNORM] = ISL_FORMAT_BC5_UNORM,
149 [PIPE_FORMAT_RGTC2_SNORM] = ISL_FORMAT_BC5_SNORM,
150
151 //[PIPE_FORMAT_R8G8_B8G8_UNORM] = ISL_FORMAT_R8G8_B8G8_UNORM,
152 //[PIPE_FORMAT_G8R8_G8B8_UNORM] = ISL_FORMAT_G8R8_G8B8_UNORM,
153
154 //[PIPE_FORMAT_R8SG8SB8UX8U_NORM] = ISL_FORMAT_R8SG8SB8UX8U_NORM,
155 //[PIPE_FORMAT_R5SG5SB6U_NORM] = ISL_FORMAT_R5SG5SB6U_NORM,
156
157 //[PIPE_FORMAT_A8B8G8R8_UNORM] = ISL_FORMAT_A8B8G8R8_UNORM,
158 [PIPE_FORMAT_B5G5R5X1_UNORM] = ISL_FORMAT_B5G5R5X1_UNORM,
159 [PIPE_FORMAT_R10G10B10A2_USCALED] = ISL_FORMAT_R10G10B10A2_USCALED,
160 [PIPE_FORMAT_R11G11B10_FLOAT] = ISL_FORMAT_R11G11B10_FLOAT,
161 [PIPE_FORMAT_R9G9B9E5_FLOAT] = ISL_FORMAT_R9G9B9E5_SHAREDEXP,
162 //[PIPE_FORMAT_Z32_FLOAT_S8X24_UINT] = ISL_FORMAT_R32_FLOAT_S8X24_UINT,
163 [PIPE_FORMAT_R1_UNORM] = ISL_FORMAT_R1_UNORM,
164 [PIPE_FORMAT_R10G10B10X2_USCALED] = ISL_FORMAT_R10G10B10X2_USCALED,
165 //[PIPE_FORMAT_R10G10B10X2_SNORM] = ISL_FORMAT_R10G10B10X2_SNORM,
166 //[PIPE_FORMAT_L4A4_UNORM] = ISL_FORMAT_R4G4_UNORM,
167 [PIPE_FORMAT_B10G10R10A2_UNORM] = ISL_FORMAT_B10G10R10A2_UNORM,
168 //[PIPE_FORMAT_R10SG10SB10SA2U_NORM] = ISL_FORMAT_R10SG10SB10SA2U_NORM,
169 //[PIPE_FORMAT_R8G8Bx_SNORM] = ISL_FORMAT_R8G8Bx_SNORM,
170 [PIPE_FORMAT_R8G8B8X8_UNORM] = ISL_FORMAT_R8G8B8X8_UNORM,
171 //[PIPE_FORMAT_B4G4R4X4_UNORM] = ISL_FORMAT_B4G4R4X4_UNORM,
172
173 /* some stencil samplers formats */
174 //[PIPE_FORMAT_X24S8_UINT] = ISL_FORMAT_X24S8_UINT,
175 //[PIPE_FORMAT_S8X24_UINT] = ISL_FORMAT_S8X24_UINT,
176 //[PIPE_FORMAT_X32_S8X24_UINT] = ISL_FORMAT_X32_S8X24_UINT,
177
178 //[PIPE_FORMAT_B2G3R3_UNORM] = ISL_FORMAT_B2G3R3_UNORM,
179 [PIPE_FORMAT_L16A16_UNORM] = ISL_FORMAT_R16G16_UNORM,
180 [PIPE_FORMAT_A16_UNORM] = ISL_FORMAT_R16_UNORM,
181 [PIPE_FORMAT_I16_UNORM] = ISL_FORMAT_R16_UNORM,
182
183 //[PIPE_FORMAT_LATC1_UNORM] = ISL_FORMAT_LATC1_UNORM,
184 //[PIPE_FORMAT_LATC1_SNORM] = ISL_FORMAT_LATC1_SNORM,
185 //[PIPE_FORMAT_LATC2_UNORM] = ISL_FORMAT_LATC2_UNORM,
186 //[PIPE_FORMAT_LATC2_SNORM] = ISL_FORMAT_LATC2_SNORM,
187
188 [PIPE_FORMAT_A8_SNORM] = ISL_FORMAT_R8_SNORM,
189 [PIPE_FORMAT_L8_SNORM] = ISL_FORMAT_R8_SNORM,
190 [PIPE_FORMAT_L8A8_SNORM] = ISL_FORMAT_R8G8_SNORM,
191 [PIPE_FORMAT_I8_SNORM] = ISL_FORMAT_R8_SNORM,
192 [PIPE_FORMAT_A16_SNORM] = ISL_FORMAT_R16_SNORM,
193 [PIPE_FORMAT_L16_SNORM] = ISL_FORMAT_R16_SNORM,
194 [PIPE_FORMAT_L16A16_SNORM] = ISL_FORMAT_R16G16_SNORM,
195 [PIPE_FORMAT_I16_SNORM] = ISL_FORMAT_R16_SNORM,
196
197 [PIPE_FORMAT_A16_FLOAT] = ISL_FORMAT_R16_FLOAT,
198 [PIPE_FORMAT_L16_FLOAT] = ISL_FORMAT_R16_FLOAT,
199 [PIPE_FORMAT_L16A16_FLOAT] = ISL_FORMAT_R16G16_FLOAT,
200 [PIPE_FORMAT_I16_FLOAT] = ISL_FORMAT_R16_FLOAT,
201 [PIPE_FORMAT_A32_FLOAT] = ISL_FORMAT_R32_FLOAT,
202 [PIPE_FORMAT_L32_FLOAT] = ISL_FORMAT_R32_FLOAT,
203 [PIPE_FORMAT_L32A32_FLOAT] = ISL_FORMAT_R32G32_FLOAT,
204 [PIPE_FORMAT_I32_FLOAT] = ISL_FORMAT_R32_FLOAT,
205
206 //[PIPE_FORMAT_YV12] = ISL_FORMAT_YV12,
207 //[PIPE_FORMAT_YV16] = ISL_FORMAT_YV16,
208 //[PIPE_FORMAT_IYUV] = ISL_FORMAT_IYUV,
209 //[PIPE_FORMAT_NV12] = ISL_FORMAT_NV12,
210 //[PIPE_FORMAT_NV21] = ISL_FORMAT_NV21,
211
212 //[PIPE_FORMAT_A4R4_UNORM] = ISL_FORMAT_A4R4_UNORM,
213 //[PIPE_FORMAT_R4A4_UNORM] = ISL_FORMAT_R4A4_UNORM,
214 //[PIPE_FORMAT_R8A8_UNORM] = ISL_FORMAT_R8A8_UNORM,
215 //[PIPE_FORMAT_A8R8_UNORM] = ISL_FORMAT_A8R8_UNORM,
216
217 [PIPE_FORMAT_R10G10B10A2_SSCALED] = ISL_FORMAT_R10G10B10A2_SSCALED,
218 [PIPE_FORMAT_R10G10B10A2_SNORM] = ISL_FORMAT_R10G10B10A2_SNORM,
219
220 [PIPE_FORMAT_B10G10R10A2_USCALED] = ISL_FORMAT_B10G10R10A2_USCALED,
221 [PIPE_FORMAT_B10G10R10A2_SSCALED] = ISL_FORMAT_B10G10R10A2_SSCALED,
222 [PIPE_FORMAT_B10G10R10A2_SNORM] = ISL_FORMAT_B10G10R10A2_SNORM,
223
224 [PIPE_FORMAT_R8_UINT] = ISL_FORMAT_R8_UINT,
225 [PIPE_FORMAT_R8G8_UINT] = ISL_FORMAT_R8G8_UINT,
226 [PIPE_FORMAT_R8G8B8_UINT] = ISL_FORMAT_R8G8B8_UINT,
227 [PIPE_FORMAT_R8G8B8A8_UINT] = ISL_FORMAT_R8G8B8A8_UINT,
228
229 [PIPE_FORMAT_R8_SINT] = ISL_FORMAT_R8_SINT,
230 [PIPE_FORMAT_R8G8_SINT] = ISL_FORMAT_R8G8_SINT,
231 [PIPE_FORMAT_R8G8B8_SINT] = ISL_FORMAT_R8G8B8_SINT,
232 [PIPE_FORMAT_R8G8B8A8_SINT] = ISL_FORMAT_R8G8B8A8_SINT,
233
234 [PIPE_FORMAT_R16_UINT] = ISL_FORMAT_R16_UINT,
235 [PIPE_FORMAT_R16G16_UINT] = ISL_FORMAT_R16G16_UINT,
236 [PIPE_FORMAT_R16G16B16_UINT] = ISL_FORMAT_R16G16B16_UINT,
237 [PIPE_FORMAT_R16G16B16A16_UINT] = ISL_FORMAT_R16G16B16A16_UINT,
238
239 [PIPE_FORMAT_R16_SINT] = ISL_FORMAT_R16_SINT,
240 [PIPE_FORMAT_R16G16_SINT] = ISL_FORMAT_R16G16_SINT,
241 [PIPE_FORMAT_R16G16B16_SINT] = ISL_FORMAT_R16G16B16_SINT,
242 [PIPE_FORMAT_R16G16B16A16_SINT] = ISL_FORMAT_R16G16B16A16_SINT,
243
244 [PIPE_FORMAT_R32_UINT] = ISL_FORMAT_R32_UINT,
245 [PIPE_FORMAT_R32G32_UINT] = ISL_FORMAT_R32G32_UINT,
246 [PIPE_FORMAT_R32G32B32_UINT] = ISL_FORMAT_R32G32B32_UINT,
247 [PIPE_FORMAT_R32G32B32A32_UINT] = ISL_FORMAT_R32G32B32A32_UINT,
248
249 [PIPE_FORMAT_R32_SINT] = ISL_FORMAT_R32_SINT,
250 [PIPE_FORMAT_R32G32_SINT] = ISL_FORMAT_R32G32_SINT,
251 [PIPE_FORMAT_R32G32B32_SINT] = ISL_FORMAT_R32G32B32_SINT,
252 [PIPE_FORMAT_R32G32B32A32_SINT] = ISL_FORMAT_R32G32B32A32_SINT,
253
254 [PIPE_FORMAT_A8_UINT] = ISL_FORMAT_R8_UINT,
255 [PIPE_FORMAT_I8_UINT] = ISL_FORMAT_R8_UINT,
256 [PIPE_FORMAT_L8_UINT] = ISL_FORMAT_R8_UINT,
257 [PIPE_FORMAT_L8A8_UINT] = ISL_FORMAT_R8G8_UINT,
258
259 [PIPE_FORMAT_A8_SINT] = ISL_FORMAT_R8_SINT,
260 [PIPE_FORMAT_I8_SINT] = ISL_FORMAT_R8_SINT,
261 [PIPE_FORMAT_L8_SINT] = ISL_FORMAT_R8_SINT,
262 [PIPE_FORMAT_L8A8_SINT] = ISL_FORMAT_R8G8_SINT,
263
264 [PIPE_FORMAT_A16_UINT] = ISL_FORMAT_R16_UINT,
265 [PIPE_FORMAT_I16_UINT] = ISL_FORMAT_R16_UINT,
266 [PIPE_FORMAT_L16_UINT] = ISL_FORMAT_R16_UINT,
267 [PIPE_FORMAT_L16A16_UINT] = ISL_FORMAT_R16G16_UINT,
268
269 [PIPE_FORMAT_A16_SINT] = ISL_FORMAT_R16_SINT,
270 [PIPE_FORMAT_I16_SINT] = ISL_FORMAT_R16_SINT,
271 [PIPE_FORMAT_L16_SINT] = ISL_FORMAT_R16_SINT,
272 [PIPE_FORMAT_L16A16_SINT] = ISL_FORMAT_R16G16_SINT,
273
274 [PIPE_FORMAT_A32_UINT] = ISL_FORMAT_R32_UINT,
275 [PIPE_FORMAT_I32_UINT] = ISL_FORMAT_R32_UINT,
276 [PIPE_FORMAT_L32_UINT] = ISL_FORMAT_R32_UINT,
277 [PIPE_FORMAT_L32A32_UINT] = ISL_FORMAT_R32G32_UINT,
278
279 [PIPE_FORMAT_A32_SINT] = ISL_FORMAT_R32_SINT,
280 [PIPE_FORMAT_I32_SINT] = ISL_FORMAT_R32_SINT,
281 [PIPE_FORMAT_L32_SINT] = ISL_FORMAT_R32_SINT,
282 [PIPE_FORMAT_L32A32_SINT] = ISL_FORMAT_R32G32_SINT,
283
284 [PIPE_FORMAT_B10G10R10A2_UINT] = ISL_FORMAT_B10G10R10A2_UINT,
285
286 [PIPE_FORMAT_ETC1_RGB8] = ISL_FORMAT_ETC1_RGB8,
287
288 //[PIPE_FORMAT_R8G8_R8B8_UNORM] = ISL_FORMAT_R8G8_R8B8_UNORM,
289 //[PIPE_FORMAT_G8R8_B8R8_UNORM] = ISL_FORMAT_G8R8_B8R8_UNORM,
290
291 //[PIPE_FORMAT_R8G8B8X8_SNORM] = ISL_FORMAT_R8G8B8X8_SNORM,
292 [PIPE_FORMAT_R8G8B8X8_SRGB] = ISL_FORMAT_R8G8B8X8_UNORM_SRGB,
293 //[PIPE_FORMAT_R8G8B8X8_UINT] = ISL_FORMAT_R8G8B8X8_UINT,
294 //[PIPE_FORMAT_R8G8B8X8_SINT] = ISL_FORMAT_R8G8B8X8_SINT,
295 [PIPE_FORMAT_B10G10R10X2_UNORM] = ISL_FORMAT_B10G10R10X2_UNORM,
296 [PIPE_FORMAT_R16G16B16X16_UNORM] = ISL_FORMAT_R16G16B16X16_UNORM,
297 //[PIPE_FORMAT_R16G16B16X16_SNORM] = ISL_FORMAT_R16G16B16X16_SNORM,
298 [PIPE_FORMAT_R16G16B16X16_FLOAT] = ISL_FORMAT_R16G16B16X16_FLOAT,
299 //[PIPE_FORMAT_R16G16B16X16_UINT] = ISL_FORMAT_R16G16B16X16_UINT,
300 //[PIPE_FORMAT_R16G16B16X16_SINT] = ISL_FORMAT_R16G16B16X16_SINT,
301 [PIPE_FORMAT_R32G32B32X32_FLOAT] = ISL_FORMAT_R32G32B32X32_FLOAT,
302 //[PIPE_FORMAT_R32G32B32X32_UINT] = ISL_FORMAT_R32G32B32X32_UINT,
303 //[PIPE_FORMAT_R32G32B32X32_SINT] = ISL_FORMAT_R32G32B32X32_SINT,
304
305 //[PIPE_FORMAT_R8A8_SNORM] = ISL_FORMAT_R8A8_SNORM,
306 //[PIPE_FORMAT_R16A16_UNORM] = ISL_FORMAT_R16A16_UNORM,
307 //[PIPE_FORMAT_R16A16_SNORM] = ISL_FORMAT_R16A16_SNORM,
308 //[PIPE_FORMAT_R16A16_FLOAT] = ISL_FORMAT_R16A16_FLOAT,
309 //[PIPE_FORMAT_R32A32_FLOAT] = ISL_FORMAT_R32A32_FLOAT,
310 //[PIPE_FORMAT_R8A8_UINT] = ISL_FORMAT_R8A8_UINT,
311 //[PIPE_FORMAT_R8A8_SINT] = ISL_FORMAT_R8A8_SINT,
312 //[PIPE_FORMAT_R16A16_UINT] = ISL_FORMAT_R16A16_UINT,
313 //[PIPE_FORMAT_R16A16_SINT] = ISL_FORMAT_R16A16_SINT,
314 //[PIPE_FORMAT_R32A32_UINT] = ISL_FORMAT_R32A32_UINT,
315 //[PIPE_FORMAT_R32A32_SINT] = ISL_FORMAT_R32A32_SINT,
316 [PIPE_FORMAT_R10G10B10A2_UINT] = ISL_FORMAT_R10G10B10A2_UINT,
317
318 [PIPE_FORMAT_B5G6R5_SRGB] = ISL_FORMAT_B5G6R5_UNORM_SRGB,
319
320 [PIPE_FORMAT_BPTC_RGBA_UNORM] = ISL_FORMAT_BC7_UNORM,
321 [PIPE_FORMAT_BPTC_SRGBA] = ISL_FORMAT_BC7_UNORM_SRGB,
322 [PIPE_FORMAT_BPTC_RGB_FLOAT] = ISL_FORMAT_BC6H_SF16,
323 [PIPE_FORMAT_BPTC_RGB_UFLOAT] = ISL_FORMAT_BC6H_UF16,
324
325 //[PIPE_FORMAT_A8L8_UNORM] = ISL_FORMAT_A8L8_UNORM,
326 //[PIPE_FORMAT_A8L8_SNORM] = ISL_FORMAT_A8L8_SNORM,
327 //[PIPE_FORMAT_A8L8_SRGB] = ISL_FORMAT_A8L8_SRGB,
328 //[PIPE_FORMAT_A16L16_UNORM] = ISL_FORMAT_A16L16_UNORM,
329
330 //[PIPE_FORMAT_G8R8_UNORM] = ISL_FORMAT_G8R8_UNORM,
331 //[PIPE_FORMAT_G8R8_SNORM] = ISL_FORMAT_G8R8_SNORM,
332 //[PIPE_FORMAT_G16R16_UNORM] = ISL_FORMAT_G16R16_UNORM,
333 //[PIPE_FORMAT_G16R16_SNORM] = ISL_FORMAT_G16R16_SNORM,
334
335 //[PIPE_FORMAT_A8B8G8R8_SNORM] = ISL_FORMAT_A8B8G8R8_SNORM,
336 //[PIPE_FORMAT_X8B8G8R8_SNORM] = ISL_FORMAT_X8B8G8R8_SNORM,
337
338 [PIPE_FORMAT_ETC2_RGB8] = ISL_FORMAT_ETC2_RGB8,
339 [PIPE_FORMAT_ETC2_SRGB8] = ISL_FORMAT_ETC2_SRGB8,
340 [PIPE_FORMAT_ETC2_RGB8A1] = ISL_FORMAT_ETC2_RGB8_PTA,
341 [PIPE_FORMAT_ETC2_SRGB8A1] = ISL_FORMAT_ETC2_SRGB8_PTA,
342 [PIPE_FORMAT_ETC2_RGBA8] = ISL_FORMAT_ETC2_EAC_RGBA8,
343 [PIPE_FORMAT_ETC2_SRGBA8] = ISL_FORMAT_ETC2_EAC_SRGB8_A8,
344 [PIPE_FORMAT_ETC2_R11_UNORM] = ISL_FORMAT_EAC_R11,
345 [PIPE_FORMAT_ETC2_R11_SNORM] = ISL_FORMAT_EAC_SIGNED_R11,
346 [PIPE_FORMAT_ETC2_RG11_UNORM] = ISL_FORMAT_EAC_RG11,
347 [PIPE_FORMAT_ETC2_RG11_SNORM] = ISL_FORMAT_EAC_SIGNED_RG11,
348
349
350 [PIPE_FORMAT_ASTC_4x4] = ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16,
351 [PIPE_FORMAT_ASTC_5x4] = ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16,
352 [PIPE_FORMAT_ASTC_5x5] = ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16,
353 [PIPE_FORMAT_ASTC_6x5] = ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16,
354 [PIPE_FORMAT_ASTC_6x6] = ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16,
355 [PIPE_FORMAT_ASTC_8x5] = ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16,
356 [PIPE_FORMAT_ASTC_8x6] = ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16,
357 [PIPE_FORMAT_ASTC_8x8] = ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16,
358 [PIPE_FORMAT_ASTC_10x5] = ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16,
359 [PIPE_FORMAT_ASTC_10x6] = ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16,
360 [PIPE_FORMAT_ASTC_10x8] = ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16,
361 [PIPE_FORMAT_ASTC_10x10] = ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16,
362 [PIPE_FORMAT_ASTC_12x10] = ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16,
363 [PIPE_FORMAT_ASTC_12x12] = ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16,
364
365 [PIPE_FORMAT_ASTC_4x4_SRGB] = ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB,
366 [PIPE_FORMAT_ASTC_5x4_SRGB] = ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB,
367 [PIPE_FORMAT_ASTC_5x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB,
368 [PIPE_FORMAT_ASTC_6x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB,
369 [PIPE_FORMAT_ASTC_6x6_SRGB] = ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB,
370 [PIPE_FORMAT_ASTC_8x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB,
371 [PIPE_FORMAT_ASTC_8x6_SRGB] = ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB,
372 [PIPE_FORMAT_ASTC_8x8_SRGB] = ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB,
373 [PIPE_FORMAT_ASTC_10x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB,
374 [PIPE_FORMAT_ASTC_10x6_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB,
375 [PIPE_FORMAT_ASTC_10x8_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB,
376 [PIPE_FORMAT_ASTC_10x10_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB,
377 [PIPE_FORMAT_ASTC_12x10_SRGB] = ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB,
378 [PIPE_FORMAT_ASTC_12x12_SRGB] = ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB,
379
380 //[PIPE_FORMAT_P016] = ISL_FORMAT_P016,
381
382 //[PIPE_FORMAT_R10G10B10X2_UNORM] = ISL_FORMAT_R10G10B10X2_UNORM,
383 [PIPE_FORMAT_A1B5G5R5_UNORM] = ISL_FORMAT_A1B5G5R5_UNORM,
384 //[PIPE_FORMAT_X1B5G5R5_UNORM] = ISL_FORMAT_X1B5G5R5_UNORM,
385 };
386 assert(pf < PIPE_FORMAT_COUNT);
387 return table[pf];
388 }
389
390 boolean
391 iris_is_format_supported(struct pipe_screen *pscreen,
392 enum pipe_format pformat,
393 enum pipe_texture_target target,
394 unsigned sample_count,
395 unsigned storage_sample_count,
396 unsigned usage)
397 {
398 struct iris_screen *screen = (struct iris_screen *) pscreen;
399 const struct gen_device_info *devinfo = &screen->devinfo;
400
401 // XXX: msaa max
402 if (sample_count > 1)
403 return false;
404
405 bool supported = true;
406
407 enum isl_format format = iris_isl_format_for_pipe_format(pformat);
408
409 if (sample_count > 1)
410 supported &= isl_format_supports_multisampling(devinfo, format);
411
412 if (usage & PIPE_BIND_DEPTH_STENCIL) {
413 supported &= format == ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS ||
414 format == ISL_FORMAT_R32_FLOAT ||
415 format == ISL_FORMAT_R24_UNORM_X8_TYPELESS ||
416 format == ISL_FORMAT_R16_UNORM;
417 }
418
419 if (usage & PIPE_BIND_RENDER_TARGET)
420 supported &= isl_format_supports_rendering(devinfo, format);
421
422 if (usage & PIPE_BIND_SHADER_IMAGE) {
423 // XXX: allow untyped reads
424 supported &= isl_format_supports_typed_reads(devinfo, format) &&
425 isl_format_supports_typed_writes(devinfo, format);
426 }
427
428 if (usage & PIPE_BIND_SAMPLER_VIEW)
429 supported &= isl_format_supports_sampling(devinfo, format);
430
431 if (usage & PIPE_BIND_VERTEX_BUFFER)
432 supported &= isl_format_supports_vertex_fetch(devinfo, format);
433
434 if (usage & PIPE_BIND_INDEX_BUFFER) {
435 supported &= format == ISL_FORMAT_R8_UINT ||
436 format == ISL_FORMAT_R16_UINT ||
437 format == ISL_FORMAT_R32_UINT;
438 }
439
440 if (usage & PIPE_BIND_CONSTANT_BUFFER) {
441 // XXX:
442 }
443
444 if (usage & PIPE_BIND_STREAM_OUTPUT) {
445 // XXX:
446 }
447
448 if (usage & PIPE_BIND_CURSOR) {
449 // XXX:
450 }
451
452 if (usage & PIPE_BIND_CUSTOM) {
453 // XXX:
454 }
455
456 if (usage & PIPE_BIND_SHADER_BUFFER) {
457 // XXX:
458 }
459
460 if (usage & PIPE_BIND_COMPUTE_RESOURCE) {
461 // XXX:
462 }
463
464 if (usage & PIPE_BIND_COMMAND_ARGS_BUFFER) {
465 // XXX:
466 }
467
468 if (usage & PIPE_BIND_QUERY_BUFFER) {
469 // XXX:
470 }
471
472 return true;
473 }
474