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iris: rework format translation apis
[mesa.git] / src / gallium / drivers / iris / iris_formats.c
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 /**
24 * @file iris_formats.c
25 *
26 * Converts Gallium formats (PIPE_FORMAT_*) to hardware ones (ISL_FORMAT_*).
27 * Provides information about which formats support what features.
28 */
29
30 #include "util/bitscan.h"
31 #include "util/macros.h"
32 #include "util/u_format.h"
33
34 #include "iris_resource.h"
35 #include "iris_screen.h"
36
37 static enum isl_format
38 iris_isl_format_for_pipe_format(enum pipe_format pf)
39 {
40 static const enum isl_format table[PIPE_FORMAT_COUNT] = {
41 [0 ... PIPE_FORMAT_COUNT-1] = ISL_FORMAT_UNSUPPORTED,
42
43 [PIPE_FORMAT_B8G8R8A8_UNORM] = ISL_FORMAT_B8G8R8A8_UNORM,
44 [PIPE_FORMAT_B8G8R8X8_UNORM] = ISL_FORMAT_B8G8R8X8_UNORM,
45 //[PIPE_FORMAT_A8R8G8B8_UNORM] = ISL_FORMAT_A8R8G8B8_UNORM,
46 //[PIPE_FORMAT_X8R8G8B8_UNORM] = ISL_FORMAT_X8R8G8B8_UNORM,
47 [PIPE_FORMAT_B5G5R5A1_UNORM] = ISL_FORMAT_B5G5R5A1_UNORM,
48 [PIPE_FORMAT_B4G4R4A4_UNORM] = ISL_FORMAT_B4G4R4A4_UNORM,
49 [PIPE_FORMAT_B5G6R5_UNORM] = ISL_FORMAT_B5G6R5_UNORM,
50 [PIPE_FORMAT_R10G10B10A2_UNORM] = ISL_FORMAT_R10G10B10A2_UNORM,
51 //[PIPE_FORMAT_L8_UNORM] = ISL_FORMAT_L8_UNORM,
52 //[PIPE_FORMAT_A8_UNORM] = ISL_FORMAT_A8_UNORM,
53 //[PIPE_FORMAT_I8_UNORM] = ISL_FORMAT_I8_UNORM,
54 //[PIPE_FORMAT_L8A8_UNORM] = ISL_FORMAT_L8A8_UNORM,
55 //[PIPE_FORMAT_L16_UNORM] = ISL_FORMAT_L16_UNORM,
56 //[PIPE_FORMAT_UYVY] = ISL_FORMAT_UYVY,
57 //[PIPE_FORMAT_YUYV] = ISL_FORMAT_YUYV,
58
59 [PIPE_FORMAT_Z16_UNORM] = ISL_FORMAT_R16_UNORM,
60 [PIPE_FORMAT_Z32_UNORM] = ISL_FORMAT_R32_UNORM,
61 [PIPE_FORMAT_Z32_FLOAT] = ISL_FORMAT_R32_FLOAT,
62
63 /* We translate the combined depth/stencil formats to depth only here */
64 [PIPE_FORMAT_Z24_UNORM_S8_UINT] = ISL_FORMAT_R24_UNORM_X8_TYPELESS,
65 [PIPE_FORMAT_Z24X8_UNORM] = ISL_FORMAT_R24_UNORM_X8_TYPELESS,
66 [PIPE_FORMAT_Z32_FLOAT_S8X24_UINT] = ISL_FORMAT_R32_FLOAT,
67
68 [PIPE_FORMAT_S8_UINT] = ISL_FORMAT_R8_UINT,
69 [PIPE_FORMAT_X24S8_UINT] = ISL_FORMAT_R8_UINT,
70
71 [PIPE_FORMAT_R64_FLOAT] = ISL_FORMAT_R64_FLOAT,
72 [PIPE_FORMAT_R64G64_FLOAT] = ISL_FORMAT_R64G64_FLOAT,
73 [PIPE_FORMAT_R64G64B64_FLOAT] = ISL_FORMAT_R64G64B64_FLOAT,
74 [PIPE_FORMAT_R64G64B64A64_FLOAT] = ISL_FORMAT_R64G64B64A64_FLOAT,
75 [PIPE_FORMAT_R32_FLOAT] = ISL_FORMAT_R32_FLOAT,
76 [PIPE_FORMAT_R32G32_FLOAT] = ISL_FORMAT_R32G32_FLOAT,
77 [PIPE_FORMAT_R32G32B32_FLOAT] = ISL_FORMAT_R32G32B32_FLOAT,
78 [PIPE_FORMAT_R32G32B32A32_FLOAT] = ISL_FORMAT_R32G32B32A32_FLOAT,
79 [PIPE_FORMAT_R32_UNORM] = ISL_FORMAT_R32_UNORM,
80 [PIPE_FORMAT_R32G32_UNORM] = ISL_FORMAT_R32G32_UNORM,
81 [PIPE_FORMAT_R32G32B32_UNORM] = ISL_FORMAT_R32G32B32_UNORM,
82 [PIPE_FORMAT_R32G32B32A32_UNORM] = ISL_FORMAT_R32G32B32A32_UNORM,
83 [PIPE_FORMAT_R32_USCALED] = ISL_FORMAT_R32_USCALED,
84 [PIPE_FORMAT_R32G32_USCALED] = ISL_FORMAT_R32G32_USCALED,
85 [PIPE_FORMAT_R32G32B32_USCALED] = ISL_FORMAT_R32G32B32_USCALED,
86 [PIPE_FORMAT_R32G32B32A32_USCALED] = ISL_FORMAT_R32G32B32A32_USCALED,
87 [PIPE_FORMAT_R32_SNORM] = ISL_FORMAT_R32_SNORM,
88 [PIPE_FORMAT_R32G32_SNORM] = ISL_FORMAT_R32G32_SNORM,
89 [PIPE_FORMAT_R32G32B32_SNORM] = ISL_FORMAT_R32G32B32_SNORM,
90 [PIPE_FORMAT_R32G32B32A32_SNORM] = ISL_FORMAT_R32G32B32A32_SNORM,
91 [PIPE_FORMAT_R32_SSCALED] = ISL_FORMAT_R32_SSCALED,
92 [PIPE_FORMAT_R32G32_SSCALED] = ISL_FORMAT_R32G32_SSCALED,
93 [PIPE_FORMAT_R32G32B32_SSCALED] = ISL_FORMAT_R32G32B32_SSCALED,
94 [PIPE_FORMAT_R32G32B32A32_SSCALED] = ISL_FORMAT_R32G32B32A32_SSCALED,
95 [PIPE_FORMAT_R16_UNORM] = ISL_FORMAT_R16_UNORM,
96 [PIPE_FORMAT_R16G16_UNORM] = ISL_FORMAT_R16G16_UNORM,
97 [PIPE_FORMAT_R16G16B16_UNORM] = ISL_FORMAT_R16G16B16_UNORM,
98 [PIPE_FORMAT_R16G16B16A16_UNORM] = ISL_FORMAT_R16G16B16A16_UNORM,
99 [PIPE_FORMAT_R16_USCALED] = ISL_FORMAT_R16_USCALED,
100 [PIPE_FORMAT_R16G16_USCALED] = ISL_FORMAT_R16G16_USCALED,
101 [PIPE_FORMAT_R16G16B16_USCALED] = ISL_FORMAT_R16G16B16_USCALED,
102 [PIPE_FORMAT_R16G16B16A16_USCALED] = ISL_FORMAT_R16G16B16A16_USCALED,
103 [PIPE_FORMAT_R16_SNORM] = ISL_FORMAT_R16_SNORM,
104 [PIPE_FORMAT_R16G16_SNORM] = ISL_FORMAT_R16G16_SNORM,
105 [PIPE_FORMAT_R16G16B16_SNORM] = ISL_FORMAT_R16G16B16_SNORM,
106 [PIPE_FORMAT_R16G16B16A16_SNORM] = ISL_FORMAT_R16G16B16A16_SNORM,
107 [PIPE_FORMAT_R16_SSCALED] = ISL_FORMAT_R16_SSCALED,
108 [PIPE_FORMAT_R16G16_SSCALED] = ISL_FORMAT_R16G16_SSCALED,
109 [PIPE_FORMAT_R16G16B16_SSCALED] = ISL_FORMAT_R16G16B16_SSCALED,
110 [PIPE_FORMAT_R16G16B16A16_SSCALED] = ISL_FORMAT_R16G16B16A16_SSCALED,
111 [PIPE_FORMAT_R8_UNORM] = ISL_FORMAT_R8_UNORM,
112 [PIPE_FORMAT_R8G8_UNORM] = ISL_FORMAT_R8G8_UNORM,
113 [PIPE_FORMAT_R8G8B8_UNORM] = ISL_FORMAT_R8G8B8_UNORM,
114 [PIPE_FORMAT_R8G8B8A8_UNORM] = ISL_FORMAT_R8G8B8A8_UNORM,
115 //[PIPE_FORMAT_X8B8G8R8_UNORM] = ISL_FORMAT_X8B8G8R8_UNORM,
116 [PIPE_FORMAT_R8_USCALED] = ISL_FORMAT_R8_USCALED,
117 [PIPE_FORMAT_R8G8_USCALED] = ISL_FORMAT_R8G8_USCALED,
118 [PIPE_FORMAT_R8G8B8_USCALED] = ISL_FORMAT_R8G8B8_USCALED,
119 [PIPE_FORMAT_R8G8B8A8_USCALED] = ISL_FORMAT_R8G8B8A8_USCALED,
120 [PIPE_FORMAT_R8_SNORM] = ISL_FORMAT_R8_SNORM,
121 [PIPE_FORMAT_R8G8_SNORM] = ISL_FORMAT_R8G8_SNORM,
122 [PIPE_FORMAT_R8G8B8_SNORM] = ISL_FORMAT_R8G8B8_SNORM,
123 [PIPE_FORMAT_R8G8B8A8_SNORM] = ISL_FORMAT_R8G8B8A8_SNORM,
124 [PIPE_FORMAT_R8_SSCALED] = ISL_FORMAT_R8_SSCALED,
125 [PIPE_FORMAT_R8G8_SSCALED] = ISL_FORMAT_R8G8_SSCALED,
126 [PIPE_FORMAT_R8G8B8_SSCALED] = ISL_FORMAT_R8G8B8_SSCALED,
127 [PIPE_FORMAT_R8G8B8A8_SSCALED] = ISL_FORMAT_R8G8B8A8_SSCALED,
128 [PIPE_FORMAT_R32_FIXED] = ISL_FORMAT_R32_SFIXED,
129 [PIPE_FORMAT_R32G32_FIXED] = ISL_FORMAT_R32G32_SFIXED,
130 [PIPE_FORMAT_R32G32B32_FIXED] = ISL_FORMAT_R32G32B32_SFIXED,
131 [PIPE_FORMAT_R32G32B32A32_FIXED] = ISL_FORMAT_R32G32B32A32_SFIXED,
132 [PIPE_FORMAT_R16_FLOAT] = ISL_FORMAT_R16_FLOAT,
133 [PIPE_FORMAT_R16G16_FLOAT] = ISL_FORMAT_R16G16_FLOAT,
134 [PIPE_FORMAT_R16G16B16_FLOAT] = ISL_FORMAT_R16G16B16_FLOAT,
135 [PIPE_FORMAT_R16G16B16A16_FLOAT] = ISL_FORMAT_R16G16B16A16_FLOAT,
136
137 //[PIPE_FORMAT_L8_SRGB] = ISL_FORMAT_L8_UNORM_SRGB,
138 //[PIPE_FORMAT_L8A8_SRGB] = ISL_FORMAT_L8A8_UNORM_SRGB,
139 [PIPE_FORMAT_R8G8B8_SRGB] = ISL_FORMAT_R8G8B8_UNORM_SRGB,
140 //[PIPE_FORMAT_A8B8G8R8_SRGB] = ISL_FORMAT_A8B8G8R8_UNORM_SRGB,
141 //[PIPE_FORMAT_X8B8G8R8_SRGB] = ISL_FORMAT_X8B8G8R8_UNORM_SRGB,
142 [PIPE_FORMAT_B8G8R8A8_SRGB] = ISL_FORMAT_B8G8R8A8_UNORM_SRGB,
143 [PIPE_FORMAT_B8G8R8X8_SRGB] = ISL_FORMAT_B8G8R8X8_UNORM_SRGB,
144 //[PIPE_FORMAT_A8R8G8B8_SRGB] = ISL_FORMAT_A8R8G8B8_UNORM_SRGB,
145 //[PIPE_FORMAT_X8R8G8B8_SRGB] = ISL_FORMAT_X8R8G8B8_UNORM_SRGB,
146 [PIPE_FORMAT_R8G8B8A8_SRGB] = ISL_FORMAT_R8G8B8A8_UNORM_SRGB,
147
148 [PIPE_FORMAT_DXT1_RGB] = ISL_FORMAT_BC1_UNORM,
149 [PIPE_FORMAT_DXT1_RGBA] = ISL_FORMAT_BC1_UNORM,
150 [PIPE_FORMAT_DXT3_RGBA] = ISL_FORMAT_BC2_UNORM,
151 [PIPE_FORMAT_DXT5_RGBA] = ISL_FORMAT_BC3_UNORM,
152
153 [PIPE_FORMAT_DXT1_SRGB] = ISL_FORMAT_BC1_UNORM_SRGB,
154 [PIPE_FORMAT_DXT1_SRGBA] = ISL_FORMAT_BC1_UNORM_SRGB,
155 [PIPE_FORMAT_DXT3_SRGBA] = ISL_FORMAT_BC2_UNORM_SRGB,
156 [PIPE_FORMAT_DXT5_SRGBA] = ISL_FORMAT_BC3_UNORM_SRGB,
157
158 [PIPE_FORMAT_RGTC1_UNORM] = ISL_FORMAT_BC4_UNORM,
159 [PIPE_FORMAT_RGTC1_SNORM] = ISL_FORMAT_BC4_SNORM,
160 [PIPE_FORMAT_RGTC2_UNORM] = ISL_FORMAT_BC5_UNORM,
161 [PIPE_FORMAT_RGTC2_SNORM] = ISL_FORMAT_BC5_SNORM,
162
163 //[PIPE_FORMAT_R8G8_B8G8_UNORM] = ISL_FORMAT_R8G8_B8G8_UNORM,
164 //[PIPE_FORMAT_G8R8_G8B8_UNORM] = ISL_FORMAT_G8R8_G8B8_UNORM,
165
166 //[PIPE_FORMAT_R8SG8SB8UX8U_NORM] = ISL_FORMAT_R8SG8SB8UX8U_NORM,
167 //[PIPE_FORMAT_R5SG5SB6U_NORM] = ISL_FORMAT_R5SG5SB6U_NORM,
168
169 //[PIPE_FORMAT_A8B8G8R8_UNORM] = ISL_FORMAT_A8B8G8R8_UNORM,
170 [PIPE_FORMAT_B5G5R5X1_UNORM] = ISL_FORMAT_B5G5R5X1_UNORM,
171 [PIPE_FORMAT_R10G10B10A2_USCALED] = ISL_FORMAT_R10G10B10A2_USCALED,
172 [PIPE_FORMAT_R11G11B10_FLOAT] = ISL_FORMAT_R11G11B10_FLOAT,
173 [PIPE_FORMAT_R9G9B9E5_FLOAT] = ISL_FORMAT_R9G9B9E5_SHAREDEXP,
174 [PIPE_FORMAT_R1_UNORM] = ISL_FORMAT_R1_UNORM,
175 [PIPE_FORMAT_R10G10B10X2_USCALED] = ISL_FORMAT_R10G10B10X2_USCALED,
176 //[PIPE_FORMAT_R10G10B10X2_SNORM] = ISL_FORMAT_R10G10B10X2_SNORM,
177 //[PIPE_FORMAT_L4A4_UNORM] = ISL_FORMAT_R4G4_UNORM,
178 [PIPE_FORMAT_B10G10R10A2_UNORM] = ISL_FORMAT_B10G10R10A2_UNORM,
179 //[PIPE_FORMAT_R10SG10SB10SA2U_NORM] = ISL_FORMAT_R10SG10SB10SA2U_NORM,
180 //[PIPE_FORMAT_R8G8Bx_SNORM] = ISL_FORMAT_R8G8Bx_SNORM,
181 [PIPE_FORMAT_R8G8B8X8_UNORM] = ISL_FORMAT_R8G8B8X8_UNORM,
182 //[PIPE_FORMAT_B4G4R4X4_UNORM] = ISL_FORMAT_B4G4R4X4_UNORM,
183
184 /* some stencil samplers formats */
185 //[PIPE_FORMAT_X24S8_UINT] = ISL_FORMAT_X24S8_UINT,
186 //[PIPE_FORMAT_S8X24_UINT] = ISL_FORMAT_S8X24_UINT,
187 //[PIPE_FORMAT_X32_S8X24_UINT] = ISL_FORMAT_X32_S8X24_UINT,
188
189 //[PIPE_FORMAT_B2G3R3_UNORM] = ISL_FORMAT_B2G3R3_UNORM,
190 //[PIPE_FORMAT_L16A16_UNORM] = ISL_FORMAT_R16G16_UNORM,
191 //[PIPE_FORMAT_A16_UNORM] = ISL_FORMAT_R16_UNORM,
192 //[PIPE_FORMAT_I16_UNORM] = ISL_FORMAT_R16_UNORM,
193
194 //[PIPE_FORMAT_LATC1_UNORM] = ISL_FORMAT_LATC1_UNORM,
195 //[PIPE_FORMAT_LATC1_SNORM] = ISL_FORMAT_LATC1_SNORM,
196 //[PIPE_FORMAT_LATC2_UNORM] = ISL_FORMAT_LATC2_UNORM,
197 //[PIPE_FORMAT_LATC2_SNORM] = ISL_FORMAT_LATC2_SNORM,
198
199 //[PIPE_FORMAT_A8_SNORM] = ISL_FORMAT_R8_SNORM,
200 //[PIPE_FORMAT_L8_SNORM] = ISL_FORMAT_R8_SNORM,
201 //[PIPE_FORMAT_L8A8_SNORM] = ISL_FORMAT_R8G8_SNORM,
202 //[PIPE_FORMAT_I8_SNORM] = ISL_FORMAT_R8_SNORM,
203 //[PIPE_FORMAT_A16_SNORM] = ISL_FORMAT_R16_SNORM,
204 //[PIPE_FORMAT_L16_SNORM] = ISL_FORMAT_R16_SNORM,
205 //[PIPE_FORMAT_L16A16_SNORM] = ISL_FORMAT_R16G16_SNORM,
206 //[PIPE_FORMAT_I16_SNORM] = ISL_FORMAT_R16_SNORM,
207
208 //[PIPE_FORMAT_A16_FLOAT] = ISL_FORMAT_R16_FLOAT,
209 //[PIPE_FORMAT_L16_FLOAT] = ISL_FORMAT_R16_FLOAT,
210 //[PIPE_FORMAT_L16A16_FLOAT] = ISL_FORMAT_R16G16_FLOAT,
211 //[PIPE_FORMAT_I16_FLOAT] = ISL_FORMAT_R16_FLOAT,
212 //[PIPE_FORMAT_A32_FLOAT] = ISL_FORMAT_R32_FLOAT,
213 //[PIPE_FORMAT_L32_FLOAT] = ISL_FORMAT_R32_FLOAT,
214 //[PIPE_FORMAT_L32A32_FLOAT] = ISL_FORMAT_R32G32_FLOAT,
215 //[PIPE_FORMAT_I32_FLOAT] = ISL_FORMAT_R32_FLOAT,
216
217 //[PIPE_FORMAT_YV12] = ISL_FORMAT_YV12,
218 //[PIPE_FORMAT_YV16] = ISL_FORMAT_YV16,
219 //[PIPE_FORMAT_IYUV] = ISL_FORMAT_IYUV,
220 //[PIPE_FORMAT_NV12] = ISL_FORMAT_NV12,
221 //[PIPE_FORMAT_NV21] = ISL_FORMAT_NV21,
222
223 //[PIPE_FORMAT_A4R4_UNORM] = ISL_FORMAT_A4R4_UNORM,
224 //[PIPE_FORMAT_R4A4_UNORM] = ISL_FORMAT_R4A4_UNORM,
225 //[PIPE_FORMAT_R8A8_UNORM] = ISL_FORMAT_R8A8_UNORM,
226 //[PIPE_FORMAT_A8R8_UNORM] = ISL_FORMAT_A8R8_UNORM,
227
228 [PIPE_FORMAT_R10G10B10A2_SSCALED] = ISL_FORMAT_R10G10B10A2_SSCALED,
229 [PIPE_FORMAT_R10G10B10A2_SNORM] = ISL_FORMAT_R10G10B10A2_SNORM,
230
231 [PIPE_FORMAT_B10G10R10A2_USCALED] = ISL_FORMAT_B10G10R10A2_USCALED,
232 [PIPE_FORMAT_B10G10R10A2_SSCALED] = ISL_FORMAT_B10G10R10A2_SSCALED,
233 [PIPE_FORMAT_B10G10R10A2_SNORM] = ISL_FORMAT_B10G10R10A2_SNORM,
234
235 [PIPE_FORMAT_R8_UINT] = ISL_FORMAT_R8_UINT,
236 [PIPE_FORMAT_R8G8_UINT] = ISL_FORMAT_R8G8_UINT,
237 [PIPE_FORMAT_R8G8B8_UINT] = ISL_FORMAT_R8G8B8_UINT,
238 [PIPE_FORMAT_R8G8B8A8_UINT] = ISL_FORMAT_R8G8B8A8_UINT,
239
240 [PIPE_FORMAT_R8_SINT] = ISL_FORMAT_R8_SINT,
241 [PIPE_FORMAT_R8G8_SINT] = ISL_FORMAT_R8G8_SINT,
242 [PIPE_FORMAT_R8G8B8_SINT] = ISL_FORMAT_R8G8B8_SINT,
243 [PIPE_FORMAT_R8G8B8A8_SINT] = ISL_FORMAT_R8G8B8A8_SINT,
244
245 [PIPE_FORMAT_R16_UINT] = ISL_FORMAT_R16_UINT,
246 [PIPE_FORMAT_R16G16_UINT] = ISL_FORMAT_R16G16_UINT,
247 [PIPE_FORMAT_R16G16B16_UINT] = ISL_FORMAT_R16G16B16_UINT,
248 [PIPE_FORMAT_R16G16B16A16_UINT] = ISL_FORMAT_R16G16B16A16_UINT,
249
250 [PIPE_FORMAT_R16_SINT] = ISL_FORMAT_R16_SINT,
251 [PIPE_FORMAT_R16G16_SINT] = ISL_FORMAT_R16G16_SINT,
252 [PIPE_FORMAT_R16G16B16_SINT] = ISL_FORMAT_R16G16B16_SINT,
253 [PIPE_FORMAT_R16G16B16A16_SINT] = ISL_FORMAT_R16G16B16A16_SINT,
254
255 [PIPE_FORMAT_R32_UINT] = ISL_FORMAT_R32_UINT,
256 [PIPE_FORMAT_R32G32_UINT] = ISL_FORMAT_R32G32_UINT,
257 [PIPE_FORMAT_R32G32B32_UINT] = ISL_FORMAT_R32G32B32_UINT,
258 [PIPE_FORMAT_R32G32B32A32_UINT] = ISL_FORMAT_R32G32B32A32_UINT,
259
260 [PIPE_FORMAT_R32_SINT] = ISL_FORMAT_R32_SINT,
261 [PIPE_FORMAT_R32G32_SINT] = ISL_FORMAT_R32G32_SINT,
262 [PIPE_FORMAT_R32G32B32_SINT] = ISL_FORMAT_R32G32B32_SINT,
263 [PIPE_FORMAT_R32G32B32A32_SINT] = ISL_FORMAT_R32G32B32A32_SINT,
264
265 /*
266 [PIPE_FORMAT_A8_UINT] = ISL_FORMAT_R8_UINT,
267 [PIPE_FORMAT_I8_UINT] = ISL_FORMAT_R8_UINT,
268 [PIPE_FORMAT_L8_UINT] = ISL_FORMAT_R8_UINT,
269 [PIPE_FORMAT_L8A8_UINT] = ISL_FORMAT_R8G8_UINT,
270
271 [PIPE_FORMAT_A8_SINT] = ISL_FORMAT_R8_SINT,
272 [PIPE_FORMAT_I8_SINT] = ISL_FORMAT_R8_SINT,
273 [PIPE_FORMAT_L8_SINT] = ISL_FORMAT_R8_SINT,
274 [PIPE_FORMAT_L8A8_SINT] = ISL_FORMAT_R8G8_SINT,
275
276 [PIPE_FORMAT_A16_UINT] = ISL_FORMAT_R16_UINT,
277 [PIPE_FORMAT_I16_UINT] = ISL_FORMAT_R16_UINT,
278 [PIPE_FORMAT_L16_UINT] = ISL_FORMAT_R16_UINT,
279 [PIPE_FORMAT_L16A16_UINT] = ISL_FORMAT_R16G16_UINT,
280
281 [PIPE_FORMAT_A16_SINT] = ISL_FORMAT_R16_SINT,
282 [PIPE_FORMAT_I16_SINT] = ISL_FORMAT_R16_SINT,
283 [PIPE_FORMAT_L16_SINT] = ISL_FORMAT_R16_SINT,
284 [PIPE_FORMAT_L16A16_SINT] = ISL_FORMAT_R16G16_SINT,
285
286 [PIPE_FORMAT_A32_UINT] = ISL_FORMAT_R32_UINT,
287 [PIPE_FORMAT_I32_UINT] = ISL_FORMAT_R32_UINT,
288 [PIPE_FORMAT_L32_UINT] = ISL_FORMAT_R32_UINT,
289 [PIPE_FORMAT_L32A32_UINT] = ISL_FORMAT_R32G32_UINT,
290
291 [PIPE_FORMAT_A32_SINT] = ISL_FORMAT_R32_SINT,
292 [PIPE_FORMAT_I32_SINT] = ISL_FORMAT_R32_SINT,
293 [PIPE_FORMAT_L32_SINT] = ISL_FORMAT_R32_SINT,
294 [PIPE_FORMAT_L32A32_SINT] = ISL_FORMAT_R32G32_SINT,
295 */
296
297 [PIPE_FORMAT_B10G10R10A2_UINT] = ISL_FORMAT_B10G10R10A2_UINT,
298
299 [PIPE_FORMAT_ETC1_RGB8] = ISL_FORMAT_ETC1_RGB8,
300
301 //[PIPE_FORMAT_R8G8_R8B8_UNORM] = ISL_FORMAT_R8G8_R8B8_UNORM,
302 //[PIPE_FORMAT_G8R8_B8R8_UNORM] = ISL_FORMAT_G8R8_B8R8_UNORM,
303
304 //[PIPE_FORMAT_R8G8B8X8_SNORM] = ISL_FORMAT_R8G8B8X8_SNORM,
305 [PIPE_FORMAT_R8G8B8X8_SRGB] = ISL_FORMAT_R8G8B8X8_UNORM_SRGB,
306 //[PIPE_FORMAT_R8G8B8X8_UINT] = ISL_FORMAT_R8G8B8X8_UINT,
307 //[PIPE_FORMAT_R8G8B8X8_SINT] = ISL_FORMAT_R8G8B8X8_SINT,
308 [PIPE_FORMAT_B10G10R10X2_UNORM] = ISL_FORMAT_B10G10R10X2_UNORM,
309 [PIPE_FORMAT_R16G16B16X16_UNORM] = ISL_FORMAT_R16G16B16X16_UNORM,
310 //[PIPE_FORMAT_R16G16B16X16_SNORM] = ISL_FORMAT_R16G16B16X16_SNORM,
311 [PIPE_FORMAT_R16G16B16X16_FLOAT] = ISL_FORMAT_R16G16B16X16_FLOAT,
312 //[PIPE_FORMAT_R16G16B16X16_UINT] = ISL_FORMAT_R16G16B16X16_UINT,
313 //[PIPE_FORMAT_R16G16B16X16_SINT] = ISL_FORMAT_R16G16B16X16_SINT,
314 [PIPE_FORMAT_R32G32B32X32_FLOAT] = ISL_FORMAT_R32G32B32X32_FLOAT,
315 //[PIPE_FORMAT_R32G32B32X32_UINT] = ISL_FORMAT_R32G32B32X32_UINT,
316 //[PIPE_FORMAT_R32G32B32X32_SINT] = ISL_FORMAT_R32G32B32X32_SINT,
317
318 //[PIPE_FORMAT_R8A8_SNORM] = ISL_FORMAT_R8A8_SNORM,
319 //[PIPE_FORMAT_R16A16_UNORM] = ISL_FORMAT_R16A16_UNORM,
320 //[PIPE_FORMAT_R16A16_SNORM] = ISL_FORMAT_R16A16_SNORM,
321 //[PIPE_FORMAT_R16A16_FLOAT] = ISL_FORMAT_R16A16_FLOAT,
322 //[PIPE_FORMAT_R32A32_FLOAT] = ISL_FORMAT_R32A32_FLOAT,
323 //[PIPE_FORMAT_R8A8_UINT] = ISL_FORMAT_R8A8_UINT,
324 //[PIPE_FORMAT_R8A8_SINT] = ISL_FORMAT_R8A8_SINT,
325 //[PIPE_FORMAT_R16A16_UINT] = ISL_FORMAT_R16A16_UINT,
326 //[PIPE_FORMAT_R16A16_SINT] = ISL_FORMAT_R16A16_SINT,
327 //[PIPE_FORMAT_R32A32_UINT] = ISL_FORMAT_R32A32_UINT,
328 //[PIPE_FORMAT_R32A32_SINT] = ISL_FORMAT_R32A32_SINT,
329 [PIPE_FORMAT_R10G10B10A2_UINT] = ISL_FORMAT_R10G10B10A2_UINT,
330
331 [PIPE_FORMAT_B5G6R5_SRGB] = ISL_FORMAT_B5G6R5_UNORM_SRGB,
332
333 [PIPE_FORMAT_BPTC_RGBA_UNORM] = ISL_FORMAT_BC7_UNORM,
334 [PIPE_FORMAT_BPTC_SRGBA] = ISL_FORMAT_BC7_UNORM_SRGB,
335 [PIPE_FORMAT_BPTC_RGB_FLOAT] = ISL_FORMAT_BC6H_SF16,
336 [PIPE_FORMAT_BPTC_RGB_UFLOAT] = ISL_FORMAT_BC6H_UF16,
337
338 //[PIPE_FORMAT_A8L8_UNORM] = ISL_FORMAT_A8L8_UNORM,
339 //[PIPE_FORMAT_A8L8_SNORM] = ISL_FORMAT_A8L8_SNORM,
340 //[PIPE_FORMAT_A8L8_SRGB] = ISL_FORMAT_A8L8_SRGB,
341 //[PIPE_FORMAT_A16L16_UNORM] = ISL_FORMAT_A16L16_UNORM,
342
343 //[PIPE_FORMAT_G8R8_UNORM] = ISL_FORMAT_G8R8_UNORM,
344 //[PIPE_FORMAT_G8R8_SNORM] = ISL_FORMAT_G8R8_SNORM,
345 //[PIPE_FORMAT_G16R16_UNORM] = ISL_FORMAT_G16R16_UNORM,
346 //[PIPE_FORMAT_G16R16_SNORM] = ISL_FORMAT_G16R16_SNORM,
347
348 //[PIPE_FORMAT_A8B8G8R8_SNORM] = ISL_FORMAT_A8B8G8R8_SNORM,
349 //[PIPE_FORMAT_X8B8G8R8_SNORM] = ISL_FORMAT_X8B8G8R8_SNORM,
350
351 [PIPE_FORMAT_ETC2_RGB8] = ISL_FORMAT_ETC2_RGB8,
352 [PIPE_FORMAT_ETC2_SRGB8] = ISL_FORMAT_ETC2_SRGB8,
353 [PIPE_FORMAT_ETC2_RGB8A1] = ISL_FORMAT_ETC2_RGB8_PTA,
354 [PIPE_FORMAT_ETC2_SRGB8A1] = ISL_FORMAT_ETC2_SRGB8_PTA,
355 [PIPE_FORMAT_ETC2_RGBA8] = ISL_FORMAT_ETC2_EAC_RGBA8,
356 [PIPE_FORMAT_ETC2_SRGBA8] = ISL_FORMAT_ETC2_EAC_SRGB8_A8,
357 [PIPE_FORMAT_ETC2_R11_UNORM] = ISL_FORMAT_EAC_R11,
358 [PIPE_FORMAT_ETC2_R11_SNORM] = ISL_FORMAT_EAC_SIGNED_R11,
359 [PIPE_FORMAT_ETC2_RG11_UNORM] = ISL_FORMAT_EAC_RG11,
360 [PIPE_FORMAT_ETC2_RG11_SNORM] = ISL_FORMAT_EAC_SIGNED_RG11,
361
362
363 [PIPE_FORMAT_ASTC_4x4] = ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16,
364 [PIPE_FORMAT_ASTC_5x4] = ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16,
365 [PIPE_FORMAT_ASTC_5x5] = ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16,
366 [PIPE_FORMAT_ASTC_6x5] = ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16,
367 [PIPE_FORMAT_ASTC_6x6] = ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16,
368 [PIPE_FORMAT_ASTC_8x5] = ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16,
369 [PIPE_FORMAT_ASTC_8x6] = ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16,
370 [PIPE_FORMAT_ASTC_8x8] = ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16,
371 [PIPE_FORMAT_ASTC_10x5] = ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16,
372 [PIPE_FORMAT_ASTC_10x6] = ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16,
373 [PIPE_FORMAT_ASTC_10x8] = ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16,
374 [PIPE_FORMAT_ASTC_10x10] = ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16,
375 [PIPE_FORMAT_ASTC_12x10] = ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16,
376 [PIPE_FORMAT_ASTC_12x12] = ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16,
377
378 [PIPE_FORMAT_ASTC_4x4_SRGB] = ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB,
379 [PIPE_FORMAT_ASTC_5x4_SRGB] = ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB,
380 [PIPE_FORMAT_ASTC_5x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB,
381 [PIPE_FORMAT_ASTC_6x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB,
382 [PIPE_FORMAT_ASTC_6x6_SRGB] = ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB,
383 [PIPE_FORMAT_ASTC_8x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB,
384 [PIPE_FORMAT_ASTC_8x6_SRGB] = ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB,
385 [PIPE_FORMAT_ASTC_8x8_SRGB] = ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB,
386 [PIPE_FORMAT_ASTC_10x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB,
387 [PIPE_FORMAT_ASTC_10x6_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB,
388 [PIPE_FORMAT_ASTC_10x8_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB,
389 [PIPE_FORMAT_ASTC_10x10_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB,
390 [PIPE_FORMAT_ASTC_12x10_SRGB] = ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB,
391 [PIPE_FORMAT_ASTC_12x12_SRGB] = ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB,
392
393 //[PIPE_FORMAT_P016] = ISL_FORMAT_P016,
394
395 //[PIPE_FORMAT_R10G10B10X2_UNORM] = ISL_FORMAT_R10G10B10X2_UNORM,
396 [PIPE_FORMAT_A1B5G5R5_UNORM] = ISL_FORMAT_A1B5G5R5_UNORM,
397 //[PIPE_FORMAT_X1B5G5R5_UNORM] = ISL_FORMAT_X1B5G5R5_UNORM,
398 };
399 assert(pf < PIPE_FORMAT_COUNT);
400 return table[pf];
401 }
402
403 struct iris_format_info
404 iris_format_for_usage(const struct gen_device_info *devinfo,
405 enum pipe_format pformat,
406 isl_surf_usage_flags_t usage)
407 {
408 struct isl_swizzle swizzle = ISL_SWIZZLE_IDENTITY;
409
410 enum isl_format format = iris_isl_format_for_pipe_format(pformat);
411
412 /* Convert RGBX into RGBA for rendering or typed image access. */
413 if (isl_format_is_rgbx(format) &&
414 (((usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
415 !isl_format_supports_rendering(devinfo, format)) ||
416 ((usage & ISL_SURF_USAGE_STORAGE_BIT) &&
417 !(isl_format_supports_typed_writes(devinfo, format) &&
418 isl_format_supports_typed_reads(devinfo, format))))) {
419 format = isl_format_rgbx_to_rgba(format);
420 }
421
422 return (struct iris_format_info) { .fmt = format, .swizzle = swizzle };
423 }
424
425 /**
426 * The pscreen->is_format_supported() driver hook.
427 *
428 * Returns true if the given format is supported for the given usage
429 * (PIPE_BIND_*) and sample count.
430 */
431 boolean
432 iris_is_format_supported(struct pipe_screen *pscreen,
433 enum pipe_format pformat,
434 enum pipe_texture_target target,
435 unsigned sample_count,
436 unsigned storage_sample_count,
437 unsigned usage)
438 {
439 struct iris_screen *screen = (struct iris_screen *) pscreen;
440 const struct gen_device_info *devinfo = &screen->devinfo;
441
442 // XXX: msaa max
443 if (sample_count > 16 || !util_is_power_of_two_or_zero(sample_count))
444 return false;
445
446 if (pformat == PIPE_FORMAT_NONE)
447 return true;
448
449 enum isl_format format = iris_isl_format_for_pipe_format(pformat);
450
451 if (format == ISL_FORMAT_UNSUPPORTED)
452 return false;
453
454 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
455 const bool is_integer = isl_format_has_int_channel(format);
456 bool supported = true;
457
458 if (sample_count > 1)
459 supported &= isl_format_supports_multisampling(devinfo, format);
460
461 if (usage & PIPE_BIND_DEPTH_STENCIL) {
462 supported &= format == ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS ||
463 format == ISL_FORMAT_R32_FLOAT ||
464 format == ISL_FORMAT_R24_UNORM_X8_TYPELESS ||
465 format == ISL_FORMAT_R16_UNORM ||
466 format == ISL_FORMAT_R8_UINT;
467 }
468
469 if (usage & PIPE_BIND_RENDER_TARGET) {
470 supported &= isl_format_supports_rendering(devinfo, format);
471 if (!is_integer)
472 supported &= isl_format_supports_alpha_blending(devinfo, format);
473 }
474
475 if (usage & PIPE_BIND_SHADER_IMAGE) {
476 // XXX: allow untyped reads
477 supported &= isl_format_supports_typed_reads(devinfo, format) &&
478 isl_format_supports_typed_writes(devinfo, format);
479 }
480
481 if (usage & PIPE_BIND_SAMPLER_VIEW) {
482 supported &= isl_format_supports_sampling(devinfo, format);
483 if (!is_integer)
484 supported &= isl_format_supports_filtering(devinfo, format);
485
486 /* Don't advertise 3-component RGB formats. This ensures that they
487 * are renderable from an API perspective since the state tracker will
488 * fall back to RGBA or RGBX, which are renderable. We want to render
489 * internally for copies and blits, even if the application doesn't.
490 *
491 * We do need to advertise 32-bit RGB for texture buffers though.
492 */
493 supported &= fmtl->bpb != 24 && fmtl->bpb != 48 &&
494 (fmtl->bpb != 96 || target == PIPE_BUFFER);
495 }
496
497 if (usage & PIPE_BIND_VERTEX_BUFFER)
498 supported &= isl_format_supports_vertex_fetch(devinfo, format);
499
500 if (usage & PIPE_BIND_INDEX_BUFFER) {
501 supported &= format == ISL_FORMAT_R8_UINT ||
502 format == ISL_FORMAT_R16_UINT ||
503 format == ISL_FORMAT_R32_UINT;
504 }
505
506 if (usage & PIPE_BIND_CONSTANT_BUFFER) {
507 // XXX:
508 }
509
510 if (usage & PIPE_BIND_STREAM_OUTPUT) {
511 // XXX:
512 }
513
514 if (usage & PIPE_BIND_CURSOR) {
515 // XXX:
516 }
517
518 if (usage & PIPE_BIND_CUSTOM) {
519 // XXX:
520 }
521
522 if (usage & PIPE_BIND_SHADER_BUFFER) {
523 // XXX:
524 }
525
526 if (usage & PIPE_BIND_COMPUTE_RESOURCE) {
527 // XXX:
528 }
529
530 if (usage & PIPE_BIND_COMMAND_ARGS_BUFFER) {
531 // XXX:
532 }
533
534 if (usage & PIPE_BIND_QUERY_BUFFER) {
535 // XXX:
536 }
537
538 return supported;
539 }
540