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iris: disallow RGB32 formats too
[mesa.git] / src / gallium / drivers / iris / iris_formats.c
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file iris_formats.c
26 *
27 * Converts Gallium formats (PIPE_FORMAT_*) to hardware ones (ISL_FORMAT_*).
28 * Provides information about which formats support what features.
29 */
30
31 #include "util/bitscan.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34
35 #include "iris_resource.h"
36 #include "iris_screen.h"
37
38 enum isl_format
39 iris_isl_format_for_pipe_format(enum pipe_format pf)
40 {
41 static const enum isl_format table[PIPE_FORMAT_COUNT] = {
42 [0 ... PIPE_FORMAT_COUNT-1] = ISL_FORMAT_UNSUPPORTED,
43
44 [PIPE_FORMAT_B8G8R8A8_UNORM] = ISL_FORMAT_B8G8R8A8_UNORM,
45 [PIPE_FORMAT_B8G8R8X8_UNORM] = ISL_FORMAT_B8G8R8X8_UNORM,
46 //[PIPE_FORMAT_A8R8G8B8_UNORM] = ISL_FORMAT_A8R8G8B8_UNORM,
47 //[PIPE_FORMAT_X8R8G8B8_UNORM] = ISL_FORMAT_X8R8G8B8_UNORM,
48 [PIPE_FORMAT_B5G5R5A1_UNORM] = ISL_FORMAT_B5G5R5A1_UNORM,
49 [PIPE_FORMAT_B4G4R4A4_UNORM] = ISL_FORMAT_B4G4R4A4_UNORM,
50 [PIPE_FORMAT_B5G6R5_UNORM] = ISL_FORMAT_B5G6R5_UNORM,
51 [PIPE_FORMAT_R10G10B10A2_UNORM] = ISL_FORMAT_R10G10B10A2_UNORM,
52 //[PIPE_FORMAT_L8_UNORM] = ISL_FORMAT_L8_UNORM,
53 //[PIPE_FORMAT_A8_UNORM] = ISL_FORMAT_A8_UNORM,
54 //[PIPE_FORMAT_I8_UNORM] = ISL_FORMAT_I8_UNORM,
55 //[PIPE_FORMAT_L8A8_UNORM] = ISL_FORMAT_L8A8_UNORM,
56 //[PIPE_FORMAT_L16_UNORM] = ISL_FORMAT_L16_UNORM,
57 //[PIPE_FORMAT_UYVY] = ISL_FORMAT_UYVY,
58 //[PIPE_FORMAT_YUYV] = ISL_FORMAT_YUYV,
59 [PIPE_FORMAT_Z16_UNORM] = ISL_FORMAT_R16_UNORM,
60 [PIPE_FORMAT_Z32_UNORM] = ISL_FORMAT_R32_UNORM,
61 [PIPE_FORMAT_Z32_FLOAT] = ISL_FORMAT_R32_FLOAT,
62 /* XXX: separate stencil */
63 [PIPE_FORMAT_Z24_UNORM_S8_UINT] = ISL_FORMAT_R24_UNORM_X8_TYPELESS,
64 //[PIPE_FORMAT_S8_UINT_Z24_UNORM] = ISL_FORMAT_S8_UINT_Z24_UNORM,
65 [PIPE_FORMAT_Z24X8_UNORM] = ISL_FORMAT_R24_UNORM_X8_TYPELESS,
66 //[PIPE_FORMAT_X8Z24_UNORM] = ISL_FORMAT_R24_UNORM_X8_TYPELESS,
67 [PIPE_FORMAT_S8_UINT] = ISL_FORMAT_R8_UINT,
68 [PIPE_FORMAT_R64_FLOAT] = ISL_FORMAT_R64_FLOAT,
69 [PIPE_FORMAT_R64G64_FLOAT] = ISL_FORMAT_R64G64_FLOAT,
70 [PIPE_FORMAT_R64G64B64_FLOAT] = ISL_FORMAT_R64G64B64_FLOAT,
71 [PIPE_FORMAT_R64G64B64A64_FLOAT] = ISL_FORMAT_R64G64B64A64_FLOAT,
72 [PIPE_FORMAT_R32_FLOAT] = ISL_FORMAT_R32_FLOAT,
73 [PIPE_FORMAT_R32G32_FLOAT] = ISL_FORMAT_R32G32_FLOAT,
74 [PIPE_FORMAT_R32G32B32_FLOAT] = ISL_FORMAT_R32G32B32_FLOAT,
75 [PIPE_FORMAT_R32G32B32A32_FLOAT] = ISL_FORMAT_R32G32B32A32_FLOAT,
76 [PIPE_FORMAT_R32_UNORM] = ISL_FORMAT_R32_UNORM,
77 [PIPE_FORMAT_R32G32_UNORM] = ISL_FORMAT_R32G32_UNORM,
78 [PIPE_FORMAT_R32G32B32_UNORM] = ISL_FORMAT_R32G32B32_UNORM,
79 [PIPE_FORMAT_R32G32B32A32_UNORM] = ISL_FORMAT_R32G32B32A32_UNORM,
80 [PIPE_FORMAT_R32_USCALED] = ISL_FORMAT_R32_USCALED,
81 [PIPE_FORMAT_R32G32_USCALED] = ISL_FORMAT_R32G32_USCALED,
82 [PIPE_FORMAT_R32G32B32_USCALED] = ISL_FORMAT_R32G32B32_USCALED,
83 [PIPE_FORMAT_R32G32B32A32_USCALED] = ISL_FORMAT_R32G32B32A32_USCALED,
84 [PIPE_FORMAT_R32_SNORM] = ISL_FORMAT_R32_SNORM,
85 [PIPE_FORMAT_R32G32_SNORM] = ISL_FORMAT_R32G32_SNORM,
86 [PIPE_FORMAT_R32G32B32_SNORM] = ISL_FORMAT_R32G32B32_SNORM,
87 [PIPE_FORMAT_R32G32B32A32_SNORM] = ISL_FORMAT_R32G32B32A32_SNORM,
88 [PIPE_FORMAT_R32_SSCALED] = ISL_FORMAT_R32_SSCALED,
89 [PIPE_FORMAT_R32G32_SSCALED] = ISL_FORMAT_R32G32_SSCALED,
90 [PIPE_FORMAT_R32G32B32_SSCALED] = ISL_FORMAT_R32G32B32_SSCALED,
91 [PIPE_FORMAT_R32G32B32A32_SSCALED] = ISL_FORMAT_R32G32B32A32_SSCALED,
92 [PIPE_FORMAT_R16_UNORM] = ISL_FORMAT_R16_UNORM,
93 [PIPE_FORMAT_R16G16_UNORM] = ISL_FORMAT_R16G16_UNORM,
94 [PIPE_FORMAT_R16G16B16_UNORM] = ISL_FORMAT_R16G16B16_UNORM,
95 [PIPE_FORMAT_R16G16B16A16_UNORM] = ISL_FORMAT_R16G16B16A16_UNORM,
96 [PIPE_FORMAT_R16_USCALED] = ISL_FORMAT_R16_USCALED,
97 [PIPE_FORMAT_R16G16_USCALED] = ISL_FORMAT_R16G16_USCALED,
98 [PIPE_FORMAT_R16G16B16_USCALED] = ISL_FORMAT_R16G16B16_USCALED,
99 [PIPE_FORMAT_R16G16B16A16_USCALED] = ISL_FORMAT_R16G16B16A16_USCALED,
100 [PIPE_FORMAT_R16_SNORM] = ISL_FORMAT_R16_SNORM,
101 [PIPE_FORMAT_R16G16_SNORM] = ISL_FORMAT_R16G16_SNORM,
102 [PIPE_FORMAT_R16G16B16_SNORM] = ISL_FORMAT_R16G16B16_SNORM,
103 [PIPE_FORMAT_R16G16B16A16_SNORM] = ISL_FORMAT_R16G16B16A16_SNORM,
104 [PIPE_FORMAT_R16_SSCALED] = ISL_FORMAT_R16_SSCALED,
105 [PIPE_FORMAT_R16G16_SSCALED] = ISL_FORMAT_R16G16_SSCALED,
106 [PIPE_FORMAT_R16G16B16_SSCALED] = ISL_FORMAT_R16G16B16_SSCALED,
107 [PIPE_FORMAT_R16G16B16A16_SSCALED] = ISL_FORMAT_R16G16B16A16_SSCALED,
108 [PIPE_FORMAT_R8_UNORM] = ISL_FORMAT_R8_UNORM,
109 [PIPE_FORMAT_R8G8_UNORM] = ISL_FORMAT_R8G8_UNORM,
110 [PIPE_FORMAT_R8G8B8_UNORM] = ISL_FORMAT_R8G8B8_UNORM,
111 [PIPE_FORMAT_R8G8B8A8_UNORM] = ISL_FORMAT_R8G8B8A8_UNORM,
112 //[PIPE_FORMAT_X8B8G8R8_UNORM] = ISL_FORMAT_X8B8G8R8_UNORM,
113 [PIPE_FORMAT_R8_USCALED] = ISL_FORMAT_R8_USCALED,
114 [PIPE_FORMAT_R8G8_USCALED] = ISL_FORMAT_R8G8_USCALED,
115 [PIPE_FORMAT_R8G8B8_USCALED] = ISL_FORMAT_R8G8B8_USCALED,
116 [PIPE_FORMAT_R8G8B8A8_USCALED] = ISL_FORMAT_R8G8B8A8_USCALED,
117 [PIPE_FORMAT_R8_SNORM] = ISL_FORMAT_R8_SNORM,
118 [PIPE_FORMAT_R8G8_SNORM] = ISL_FORMAT_R8G8_SNORM,
119 [PIPE_FORMAT_R8G8B8_SNORM] = ISL_FORMAT_R8G8B8_SNORM,
120 [PIPE_FORMAT_R8G8B8A8_SNORM] = ISL_FORMAT_R8G8B8A8_SNORM,
121 [PIPE_FORMAT_R8_SSCALED] = ISL_FORMAT_R8_SSCALED,
122 [PIPE_FORMAT_R8G8_SSCALED] = ISL_FORMAT_R8G8_SSCALED,
123 [PIPE_FORMAT_R8G8B8_SSCALED] = ISL_FORMAT_R8G8B8_SSCALED,
124 [PIPE_FORMAT_R8G8B8A8_SSCALED] = ISL_FORMAT_R8G8B8A8_SSCALED,
125 [PIPE_FORMAT_R32_FIXED] = ISL_FORMAT_R32_SFIXED,
126 [PIPE_FORMAT_R32G32_FIXED] = ISL_FORMAT_R32G32_SFIXED,
127 [PIPE_FORMAT_R32G32B32_FIXED] = ISL_FORMAT_R32G32B32_SFIXED,
128 [PIPE_FORMAT_R32G32B32A32_FIXED] = ISL_FORMAT_R32G32B32A32_SFIXED,
129 [PIPE_FORMAT_R16_FLOAT] = ISL_FORMAT_R16_FLOAT,
130 [PIPE_FORMAT_R16G16_FLOAT] = ISL_FORMAT_R16G16_FLOAT,
131 [PIPE_FORMAT_R16G16B16_FLOAT] = ISL_FORMAT_R16G16B16_FLOAT,
132 [PIPE_FORMAT_R16G16B16A16_FLOAT] = ISL_FORMAT_R16G16B16A16_FLOAT,
133
134 //[PIPE_FORMAT_L8_SRGB] = ISL_FORMAT_L8_UNORM_SRGB,
135 //[PIPE_FORMAT_L8A8_SRGB] = ISL_FORMAT_L8A8_UNORM_SRGB,
136 [PIPE_FORMAT_R8G8B8_SRGB] = ISL_FORMAT_R8G8B8_UNORM_SRGB,
137 //[PIPE_FORMAT_A8B8G8R8_SRGB] = ISL_FORMAT_A8B8G8R8_UNORM_SRGB,
138 //[PIPE_FORMAT_X8B8G8R8_SRGB] = ISL_FORMAT_X8B8G8R8_UNORM_SRGB,
139 [PIPE_FORMAT_B8G8R8A8_SRGB] = ISL_FORMAT_B8G8R8A8_UNORM_SRGB,
140 [PIPE_FORMAT_B8G8R8X8_SRGB] = ISL_FORMAT_B8G8R8X8_UNORM_SRGB,
141 //[PIPE_FORMAT_A8R8G8B8_SRGB] = ISL_FORMAT_A8R8G8B8_UNORM_SRGB,
142 //[PIPE_FORMAT_X8R8G8B8_SRGB] = ISL_FORMAT_X8R8G8B8_UNORM_SRGB,
143 [PIPE_FORMAT_R8G8B8A8_SRGB] = ISL_FORMAT_R8G8B8A8_UNORM_SRGB,
144
145 [PIPE_FORMAT_DXT1_RGB] = ISL_FORMAT_BC1_UNORM,
146 [PIPE_FORMAT_DXT1_RGBA] = ISL_FORMAT_BC1_UNORM,
147 [PIPE_FORMAT_DXT3_RGBA] = ISL_FORMAT_BC2_UNORM,
148 [PIPE_FORMAT_DXT5_RGBA] = ISL_FORMAT_BC3_UNORM,
149
150 [PIPE_FORMAT_DXT1_SRGB] = ISL_FORMAT_BC1_UNORM_SRGB,
151 [PIPE_FORMAT_DXT1_SRGBA] = ISL_FORMAT_BC1_UNORM_SRGB,
152 [PIPE_FORMAT_DXT3_SRGBA] = ISL_FORMAT_BC2_UNORM_SRGB,
153 [PIPE_FORMAT_DXT5_SRGBA] = ISL_FORMAT_BC3_UNORM_SRGB,
154
155 [PIPE_FORMAT_RGTC1_UNORM] = ISL_FORMAT_BC4_UNORM,
156 [PIPE_FORMAT_RGTC1_SNORM] = ISL_FORMAT_BC4_SNORM,
157 [PIPE_FORMAT_RGTC2_UNORM] = ISL_FORMAT_BC5_UNORM,
158 [PIPE_FORMAT_RGTC2_SNORM] = ISL_FORMAT_BC5_SNORM,
159
160 //[PIPE_FORMAT_R8G8_B8G8_UNORM] = ISL_FORMAT_R8G8_B8G8_UNORM,
161 //[PIPE_FORMAT_G8R8_G8B8_UNORM] = ISL_FORMAT_G8R8_G8B8_UNORM,
162
163 //[PIPE_FORMAT_R8SG8SB8UX8U_NORM] = ISL_FORMAT_R8SG8SB8UX8U_NORM,
164 //[PIPE_FORMAT_R5SG5SB6U_NORM] = ISL_FORMAT_R5SG5SB6U_NORM,
165
166 //[PIPE_FORMAT_A8B8G8R8_UNORM] = ISL_FORMAT_A8B8G8R8_UNORM,
167 [PIPE_FORMAT_B5G5R5X1_UNORM] = ISL_FORMAT_B5G5R5X1_UNORM,
168 [PIPE_FORMAT_R10G10B10A2_USCALED] = ISL_FORMAT_R10G10B10A2_USCALED,
169 [PIPE_FORMAT_R11G11B10_FLOAT] = ISL_FORMAT_R11G11B10_FLOAT,
170 [PIPE_FORMAT_R9G9B9E5_FLOAT] = ISL_FORMAT_R9G9B9E5_SHAREDEXP,
171 [PIPE_FORMAT_Z32_FLOAT_S8X24_UINT] = ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS,
172 [PIPE_FORMAT_R1_UNORM] = ISL_FORMAT_R1_UNORM,
173 [PIPE_FORMAT_R10G10B10X2_USCALED] = ISL_FORMAT_R10G10B10X2_USCALED,
174 //[PIPE_FORMAT_R10G10B10X2_SNORM] = ISL_FORMAT_R10G10B10X2_SNORM,
175 //[PIPE_FORMAT_L4A4_UNORM] = ISL_FORMAT_R4G4_UNORM,
176 [PIPE_FORMAT_B10G10R10A2_UNORM] = ISL_FORMAT_B10G10R10A2_UNORM,
177 //[PIPE_FORMAT_R10SG10SB10SA2U_NORM] = ISL_FORMAT_R10SG10SB10SA2U_NORM,
178 //[PIPE_FORMAT_R8G8Bx_SNORM] = ISL_FORMAT_R8G8Bx_SNORM,
179 [PIPE_FORMAT_R8G8B8X8_UNORM] = ISL_FORMAT_R8G8B8X8_UNORM,
180 //[PIPE_FORMAT_B4G4R4X4_UNORM] = ISL_FORMAT_B4G4R4X4_UNORM,
181
182 /* some stencil samplers formats */
183 //[PIPE_FORMAT_X24S8_UINT] = ISL_FORMAT_X24S8_UINT,
184 //[PIPE_FORMAT_S8X24_UINT] = ISL_FORMAT_S8X24_UINT,
185 //[PIPE_FORMAT_X32_S8X24_UINT] = ISL_FORMAT_X32_S8X24_UINT,
186
187 //[PIPE_FORMAT_B2G3R3_UNORM] = ISL_FORMAT_B2G3R3_UNORM,
188 //[PIPE_FORMAT_L16A16_UNORM] = ISL_FORMAT_R16G16_UNORM,
189 //[PIPE_FORMAT_A16_UNORM] = ISL_FORMAT_R16_UNORM,
190 //[PIPE_FORMAT_I16_UNORM] = ISL_FORMAT_R16_UNORM,
191
192 //[PIPE_FORMAT_LATC1_UNORM] = ISL_FORMAT_LATC1_UNORM,
193 //[PIPE_FORMAT_LATC1_SNORM] = ISL_FORMAT_LATC1_SNORM,
194 //[PIPE_FORMAT_LATC2_UNORM] = ISL_FORMAT_LATC2_UNORM,
195 //[PIPE_FORMAT_LATC2_SNORM] = ISL_FORMAT_LATC2_SNORM,
196
197 //[PIPE_FORMAT_A8_SNORM] = ISL_FORMAT_R8_SNORM,
198 //[PIPE_FORMAT_L8_SNORM] = ISL_FORMAT_R8_SNORM,
199 //[PIPE_FORMAT_L8A8_SNORM] = ISL_FORMAT_R8G8_SNORM,
200 //[PIPE_FORMAT_I8_SNORM] = ISL_FORMAT_R8_SNORM,
201 //[PIPE_FORMAT_A16_SNORM] = ISL_FORMAT_R16_SNORM,
202 //[PIPE_FORMAT_L16_SNORM] = ISL_FORMAT_R16_SNORM,
203 //[PIPE_FORMAT_L16A16_SNORM] = ISL_FORMAT_R16G16_SNORM,
204 //[PIPE_FORMAT_I16_SNORM] = ISL_FORMAT_R16_SNORM,
205
206 //[PIPE_FORMAT_A16_FLOAT] = ISL_FORMAT_R16_FLOAT,
207 //[PIPE_FORMAT_L16_FLOAT] = ISL_FORMAT_R16_FLOAT,
208 //[PIPE_FORMAT_L16A16_FLOAT] = ISL_FORMAT_R16G16_FLOAT,
209 //[PIPE_FORMAT_I16_FLOAT] = ISL_FORMAT_R16_FLOAT,
210 //[PIPE_FORMAT_A32_FLOAT] = ISL_FORMAT_R32_FLOAT,
211 //[PIPE_FORMAT_L32_FLOAT] = ISL_FORMAT_R32_FLOAT,
212 //[PIPE_FORMAT_L32A32_FLOAT] = ISL_FORMAT_R32G32_FLOAT,
213 //[PIPE_FORMAT_I32_FLOAT] = ISL_FORMAT_R32_FLOAT,
214
215 //[PIPE_FORMAT_YV12] = ISL_FORMAT_YV12,
216 //[PIPE_FORMAT_YV16] = ISL_FORMAT_YV16,
217 //[PIPE_FORMAT_IYUV] = ISL_FORMAT_IYUV,
218 //[PIPE_FORMAT_NV12] = ISL_FORMAT_NV12,
219 //[PIPE_FORMAT_NV21] = ISL_FORMAT_NV21,
220
221 //[PIPE_FORMAT_A4R4_UNORM] = ISL_FORMAT_A4R4_UNORM,
222 //[PIPE_FORMAT_R4A4_UNORM] = ISL_FORMAT_R4A4_UNORM,
223 //[PIPE_FORMAT_R8A8_UNORM] = ISL_FORMAT_R8A8_UNORM,
224 //[PIPE_FORMAT_A8R8_UNORM] = ISL_FORMAT_A8R8_UNORM,
225
226 [PIPE_FORMAT_R10G10B10A2_SSCALED] = ISL_FORMAT_R10G10B10A2_SSCALED,
227 [PIPE_FORMAT_R10G10B10A2_SNORM] = ISL_FORMAT_R10G10B10A2_SNORM,
228
229 [PIPE_FORMAT_B10G10R10A2_USCALED] = ISL_FORMAT_B10G10R10A2_USCALED,
230 [PIPE_FORMAT_B10G10R10A2_SSCALED] = ISL_FORMAT_B10G10R10A2_SSCALED,
231 [PIPE_FORMAT_B10G10R10A2_SNORM] = ISL_FORMAT_B10G10R10A2_SNORM,
232
233 [PIPE_FORMAT_R8_UINT] = ISL_FORMAT_R8_UINT,
234 [PIPE_FORMAT_R8G8_UINT] = ISL_FORMAT_R8G8_UINT,
235 [PIPE_FORMAT_R8G8B8_UINT] = ISL_FORMAT_R8G8B8_UINT,
236 [PIPE_FORMAT_R8G8B8A8_UINT] = ISL_FORMAT_R8G8B8A8_UINT,
237
238 [PIPE_FORMAT_R8_SINT] = ISL_FORMAT_R8_SINT,
239 [PIPE_FORMAT_R8G8_SINT] = ISL_FORMAT_R8G8_SINT,
240 [PIPE_FORMAT_R8G8B8_SINT] = ISL_FORMAT_R8G8B8_SINT,
241 [PIPE_FORMAT_R8G8B8A8_SINT] = ISL_FORMAT_R8G8B8A8_SINT,
242
243 [PIPE_FORMAT_R16_UINT] = ISL_FORMAT_R16_UINT,
244 [PIPE_FORMAT_R16G16_UINT] = ISL_FORMAT_R16G16_UINT,
245 [PIPE_FORMAT_R16G16B16_UINT] = ISL_FORMAT_R16G16B16_UINT,
246 [PIPE_FORMAT_R16G16B16A16_UINT] = ISL_FORMAT_R16G16B16A16_UINT,
247
248 [PIPE_FORMAT_R16_SINT] = ISL_FORMAT_R16_SINT,
249 [PIPE_FORMAT_R16G16_SINT] = ISL_FORMAT_R16G16_SINT,
250 [PIPE_FORMAT_R16G16B16_SINT] = ISL_FORMAT_R16G16B16_SINT,
251 [PIPE_FORMAT_R16G16B16A16_SINT] = ISL_FORMAT_R16G16B16A16_SINT,
252
253 [PIPE_FORMAT_R32_UINT] = ISL_FORMAT_R32_UINT,
254 [PIPE_FORMAT_R32G32_UINT] = ISL_FORMAT_R32G32_UINT,
255 [PIPE_FORMAT_R32G32B32_UINT] = ISL_FORMAT_R32G32B32_UINT,
256 [PIPE_FORMAT_R32G32B32A32_UINT] = ISL_FORMAT_R32G32B32A32_UINT,
257
258 [PIPE_FORMAT_R32_SINT] = ISL_FORMAT_R32_SINT,
259 [PIPE_FORMAT_R32G32_SINT] = ISL_FORMAT_R32G32_SINT,
260 [PIPE_FORMAT_R32G32B32_SINT] = ISL_FORMAT_R32G32B32_SINT,
261 [PIPE_FORMAT_R32G32B32A32_SINT] = ISL_FORMAT_R32G32B32A32_SINT,
262
263 /*
264 [PIPE_FORMAT_A8_UINT] = ISL_FORMAT_R8_UINT,
265 [PIPE_FORMAT_I8_UINT] = ISL_FORMAT_R8_UINT,
266 [PIPE_FORMAT_L8_UINT] = ISL_FORMAT_R8_UINT,
267 [PIPE_FORMAT_L8A8_UINT] = ISL_FORMAT_R8G8_UINT,
268
269 [PIPE_FORMAT_A8_SINT] = ISL_FORMAT_R8_SINT,
270 [PIPE_FORMAT_I8_SINT] = ISL_FORMAT_R8_SINT,
271 [PIPE_FORMAT_L8_SINT] = ISL_FORMAT_R8_SINT,
272 [PIPE_FORMAT_L8A8_SINT] = ISL_FORMAT_R8G8_SINT,
273
274 [PIPE_FORMAT_A16_UINT] = ISL_FORMAT_R16_UINT,
275 [PIPE_FORMAT_I16_UINT] = ISL_FORMAT_R16_UINT,
276 [PIPE_FORMAT_L16_UINT] = ISL_FORMAT_R16_UINT,
277 [PIPE_FORMAT_L16A16_UINT] = ISL_FORMAT_R16G16_UINT,
278
279 [PIPE_FORMAT_A16_SINT] = ISL_FORMAT_R16_SINT,
280 [PIPE_FORMAT_I16_SINT] = ISL_FORMAT_R16_SINT,
281 [PIPE_FORMAT_L16_SINT] = ISL_FORMAT_R16_SINT,
282 [PIPE_FORMAT_L16A16_SINT] = ISL_FORMAT_R16G16_SINT,
283
284 [PIPE_FORMAT_A32_UINT] = ISL_FORMAT_R32_UINT,
285 [PIPE_FORMAT_I32_UINT] = ISL_FORMAT_R32_UINT,
286 [PIPE_FORMAT_L32_UINT] = ISL_FORMAT_R32_UINT,
287 [PIPE_FORMAT_L32A32_UINT] = ISL_FORMAT_R32G32_UINT,
288
289 [PIPE_FORMAT_A32_SINT] = ISL_FORMAT_R32_SINT,
290 [PIPE_FORMAT_I32_SINT] = ISL_FORMAT_R32_SINT,
291 [PIPE_FORMAT_L32_SINT] = ISL_FORMAT_R32_SINT,
292 [PIPE_FORMAT_L32A32_SINT] = ISL_FORMAT_R32G32_SINT,
293 */
294
295 [PIPE_FORMAT_B10G10R10A2_UINT] = ISL_FORMAT_B10G10R10A2_UINT,
296
297 [PIPE_FORMAT_ETC1_RGB8] = ISL_FORMAT_ETC1_RGB8,
298
299 //[PIPE_FORMAT_R8G8_R8B8_UNORM] = ISL_FORMAT_R8G8_R8B8_UNORM,
300 //[PIPE_FORMAT_G8R8_B8R8_UNORM] = ISL_FORMAT_G8R8_B8R8_UNORM,
301
302 //[PIPE_FORMAT_R8G8B8X8_SNORM] = ISL_FORMAT_R8G8B8X8_SNORM,
303 [PIPE_FORMAT_R8G8B8X8_SRGB] = ISL_FORMAT_R8G8B8X8_UNORM_SRGB,
304 //[PIPE_FORMAT_R8G8B8X8_UINT] = ISL_FORMAT_R8G8B8X8_UINT,
305 //[PIPE_FORMAT_R8G8B8X8_SINT] = ISL_FORMAT_R8G8B8X8_SINT,
306 [PIPE_FORMAT_B10G10R10X2_UNORM] = ISL_FORMAT_B10G10R10X2_UNORM,
307 [PIPE_FORMAT_R16G16B16X16_UNORM] = ISL_FORMAT_R16G16B16X16_UNORM,
308 //[PIPE_FORMAT_R16G16B16X16_SNORM] = ISL_FORMAT_R16G16B16X16_SNORM,
309 [PIPE_FORMAT_R16G16B16X16_FLOAT] = ISL_FORMAT_R16G16B16X16_FLOAT,
310 //[PIPE_FORMAT_R16G16B16X16_UINT] = ISL_FORMAT_R16G16B16X16_UINT,
311 //[PIPE_FORMAT_R16G16B16X16_SINT] = ISL_FORMAT_R16G16B16X16_SINT,
312 [PIPE_FORMAT_R32G32B32X32_FLOAT] = ISL_FORMAT_R32G32B32X32_FLOAT,
313 //[PIPE_FORMAT_R32G32B32X32_UINT] = ISL_FORMAT_R32G32B32X32_UINT,
314 //[PIPE_FORMAT_R32G32B32X32_SINT] = ISL_FORMAT_R32G32B32X32_SINT,
315
316 //[PIPE_FORMAT_R8A8_SNORM] = ISL_FORMAT_R8A8_SNORM,
317 //[PIPE_FORMAT_R16A16_UNORM] = ISL_FORMAT_R16A16_UNORM,
318 //[PIPE_FORMAT_R16A16_SNORM] = ISL_FORMAT_R16A16_SNORM,
319 //[PIPE_FORMAT_R16A16_FLOAT] = ISL_FORMAT_R16A16_FLOAT,
320 //[PIPE_FORMAT_R32A32_FLOAT] = ISL_FORMAT_R32A32_FLOAT,
321 //[PIPE_FORMAT_R8A8_UINT] = ISL_FORMAT_R8A8_UINT,
322 //[PIPE_FORMAT_R8A8_SINT] = ISL_FORMAT_R8A8_SINT,
323 //[PIPE_FORMAT_R16A16_UINT] = ISL_FORMAT_R16A16_UINT,
324 //[PIPE_FORMAT_R16A16_SINT] = ISL_FORMAT_R16A16_SINT,
325 //[PIPE_FORMAT_R32A32_UINT] = ISL_FORMAT_R32A32_UINT,
326 //[PIPE_FORMAT_R32A32_SINT] = ISL_FORMAT_R32A32_SINT,
327 [PIPE_FORMAT_R10G10B10A2_UINT] = ISL_FORMAT_R10G10B10A2_UINT,
328
329 [PIPE_FORMAT_B5G6R5_SRGB] = ISL_FORMAT_B5G6R5_UNORM_SRGB,
330
331 [PIPE_FORMAT_BPTC_RGBA_UNORM] = ISL_FORMAT_BC7_UNORM,
332 [PIPE_FORMAT_BPTC_SRGBA] = ISL_FORMAT_BC7_UNORM_SRGB,
333 [PIPE_FORMAT_BPTC_RGB_FLOAT] = ISL_FORMAT_BC6H_SF16,
334 [PIPE_FORMAT_BPTC_RGB_UFLOAT] = ISL_FORMAT_BC6H_UF16,
335
336 //[PIPE_FORMAT_A8L8_UNORM] = ISL_FORMAT_A8L8_UNORM,
337 //[PIPE_FORMAT_A8L8_SNORM] = ISL_FORMAT_A8L8_SNORM,
338 //[PIPE_FORMAT_A8L8_SRGB] = ISL_FORMAT_A8L8_SRGB,
339 //[PIPE_FORMAT_A16L16_UNORM] = ISL_FORMAT_A16L16_UNORM,
340
341 //[PIPE_FORMAT_G8R8_UNORM] = ISL_FORMAT_G8R8_UNORM,
342 //[PIPE_FORMAT_G8R8_SNORM] = ISL_FORMAT_G8R8_SNORM,
343 //[PIPE_FORMAT_G16R16_UNORM] = ISL_FORMAT_G16R16_UNORM,
344 //[PIPE_FORMAT_G16R16_SNORM] = ISL_FORMAT_G16R16_SNORM,
345
346 //[PIPE_FORMAT_A8B8G8R8_SNORM] = ISL_FORMAT_A8B8G8R8_SNORM,
347 //[PIPE_FORMAT_X8B8G8R8_SNORM] = ISL_FORMAT_X8B8G8R8_SNORM,
348
349 [PIPE_FORMAT_ETC2_RGB8] = ISL_FORMAT_ETC2_RGB8,
350 [PIPE_FORMAT_ETC2_SRGB8] = ISL_FORMAT_ETC2_SRGB8,
351 [PIPE_FORMAT_ETC2_RGB8A1] = ISL_FORMAT_ETC2_RGB8_PTA,
352 [PIPE_FORMAT_ETC2_SRGB8A1] = ISL_FORMAT_ETC2_SRGB8_PTA,
353 [PIPE_FORMAT_ETC2_RGBA8] = ISL_FORMAT_ETC2_EAC_RGBA8,
354 [PIPE_FORMAT_ETC2_SRGBA8] = ISL_FORMAT_ETC2_EAC_SRGB8_A8,
355 [PIPE_FORMAT_ETC2_R11_UNORM] = ISL_FORMAT_EAC_R11,
356 [PIPE_FORMAT_ETC2_R11_SNORM] = ISL_FORMAT_EAC_SIGNED_R11,
357 [PIPE_FORMAT_ETC2_RG11_UNORM] = ISL_FORMAT_EAC_RG11,
358 [PIPE_FORMAT_ETC2_RG11_SNORM] = ISL_FORMAT_EAC_SIGNED_RG11,
359
360
361 [PIPE_FORMAT_ASTC_4x4] = ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16,
362 [PIPE_FORMAT_ASTC_5x4] = ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16,
363 [PIPE_FORMAT_ASTC_5x5] = ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16,
364 [PIPE_FORMAT_ASTC_6x5] = ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16,
365 [PIPE_FORMAT_ASTC_6x6] = ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16,
366 [PIPE_FORMAT_ASTC_8x5] = ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16,
367 [PIPE_FORMAT_ASTC_8x6] = ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16,
368 [PIPE_FORMAT_ASTC_8x8] = ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16,
369 [PIPE_FORMAT_ASTC_10x5] = ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16,
370 [PIPE_FORMAT_ASTC_10x6] = ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16,
371 [PIPE_FORMAT_ASTC_10x8] = ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16,
372 [PIPE_FORMAT_ASTC_10x10] = ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16,
373 [PIPE_FORMAT_ASTC_12x10] = ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16,
374 [PIPE_FORMAT_ASTC_12x12] = ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16,
375
376 [PIPE_FORMAT_ASTC_4x4_SRGB] = ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB,
377 [PIPE_FORMAT_ASTC_5x4_SRGB] = ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB,
378 [PIPE_FORMAT_ASTC_5x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB,
379 [PIPE_FORMAT_ASTC_6x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB,
380 [PIPE_FORMAT_ASTC_6x6_SRGB] = ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB,
381 [PIPE_FORMAT_ASTC_8x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB,
382 [PIPE_FORMAT_ASTC_8x6_SRGB] = ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB,
383 [PIPE_FORMAT_ASTC_8x8_SRGB] = ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB,
384 [PIPE_FORMAT_ASTC_10x5_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB,
385 [PIPE_FORMAT_ASTC_10x6_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB,
386 [PIPE_FORMAT_ASTC_10x8_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB,
387 [PIPE_FORMAT_ASTC_10x10_SRGB] = ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB,
388 [PIPE_FORMAT_ASTC_12x10_SRGB] = ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB,
389 [PIPE_FORMAT_ASTC_12x12_SRGB] = ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB,
390
391 //[PIPE_FORMAT_P016] = ISL_FORMAT_P016,
392
393 //[PIPE_FORMAT_R10G10B10X2_UNORM] = ISL_FORMAT_R10G10B10X2_UNORM,
394 [PIPE_FORMAT_A1B5G5R5_UNORM] = ISL_FORMAT_A1B5G5R5_UNORM,
395 //[PIPE_FORMAT_X1B5G5R5_UNORM] = ISL_FORMAT_X1B5G5R5_UNORM,
396 };
397 assert(pf < PIPE_FORMAT_COUNT);
398 return table[pf];
399 }
400
401 enum isl_format
402 iris_isl_format_for_usage(const struct gen_device_info *devinfo,
403 enum pipe_format pformat,
404 isl_surf_usage_flags_t usage)
405 {
406 enum isl_format format = iris_isl_format_for_pipe_format(pformat);
407
408 /* Convert RGBX into RGBA for rendering or typed image access. */
409 if (isl_format_is_rgbx(format) &&
410 (((usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
411 !isl_format_supports_rendering(devinfo, format)) ||
412 ((usage & ISL_SURF_USAGE_STORAGE_BIT) &&
413 !(isl_format_supports_typed_writes(devinfo, format) &&
414 isl_format_supports_typed_reads(devinfo, format))))) {
415 format = isl_format_rgbx_to_rgba(format);
416 }
417
418 return format;
419 }
420
421 /**
422 * The pscreen->is_format_supported() driver hook.
423 *
424 * Returns true if the given format is supported for the given usage
425 * (PIPE_BIND_*) and sample count.
426 */
427 boolean
428 iris_is_format_supported(struct pipe_screen *pscreen,
429 enum pipe_format pformat,
430 enum pipe_texture_target target,
431 unsigned sample_count,
432 unsigned storage_sample_count,
433 unsigned usage)
434 {
435 struct iris_screen *screen = (struct iris_screen *) pscreen;
436 const struct gen_device_info *devinfo = &screen->devinfo;
437
438 // XXX: msaa max
439 if (sample_count > 16 || !util_is_power_of_two_or_zero(sample_count))
440 return false;
441
442 if (pformat == PIPE_FORMAT_NONE)
443 return true;
444
445 enum isl_format format = iris_isl_format_for_pipe_format(pformat);
446
447 if (format == ISL_FORMAT_UNSUPPORTED)
448 return false;
449
450 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
451 const bool is_integer = isl_format_has_int_channel(format);
452 bool supported = true;
453
454 if (sample_count > 1)
455 supported &= isl_format_supports_multisampling(devinfo, format);
456
457 if (usage & PIPE_BIND_DEPTH_STENCIL) {
458 supported &= format == ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS ||
459 format == ISL_FORMAT_R32_FLOAT ||
460 format == ISL_FORMAT_R24_UNORM_X8_TYPELESS ||
461 format == ISL_FORMAT_R16_UNORM ||
462 format == ISL_FORMAT_R8_UINT;
463 }
464
465 if (usage & PIPE_BIND_RENDER_TARGET) {
466 supported &= isl_format_supports_rendering(devinfo, format);
467 if (!is_integer)
468 supported &= isl_format_supports_alpha_blending(devinfo, format);
469 }
470
471 if (usage & PIPE_BIND_SHADER_IMAGE) {
472 // XXX: allow untyped reads
473 supported &= isl_format_supports_typed_reads(devinfo, format) &&
474 isl_format_supports_typed_writes(devinfo, format);
475 }
476
477 if (usage & PIPE_BIND_SAMPLER_VIEW) {
478 supported &= isl_format_supports_sampling(devinfo, format);
479 if (!is_integer)
480 supported &= isl_format_supports_filtering(devinfo, format);
481
482 /* Don't advertise 3-component RGB formats. This ensures that they
483 * are renderable from an API perspective since the state tracker will
484 * fall back to RGBA or RGBX, which are renderable. We want to render
485 * internally for copies and blits, even if the application doesn't.
486 */
487 supported &= fmtl->bpb != 24 && fmtl->bpb != 48 && fmtl->bpb != 96;
488 }
489
490 if (usage & PIPE_BIND_VERTEX_BUFFER)
491 supported &= isl_format_supports_vertex_fetch(devinfo, format);
492
493 if (usage & PIPE_BIND_INDEX_BUFFER) {
494 supported &= format == ISL_FORMAT_R8_UINT ||
495 format == ISL_FORMAT_R16_UINT ||
496 format == ISL_FORMAT_R32_UINT;
497 }
498
499 if (usage & PIPE_BIND_CONSTANT_BUFFER) {
500 // XXX:
501 }
502
503 if (usage & PIPE_BIND_STREAM_OUTPUT) {
504 // XXX:
505 }
506
507 if (usage & PIPE_BIND_CURSOR) {
508 // XXX:
509 }
510
511 if (usage & PIPE_BIND_CUSTOM) {
512 // XXX:
513 }
514
515 if (usage & PIPE_BIND_SHADER_BUFFER) {
516 // XXX:
517 }
518
519 if (usage & PIPE_BIND_COMPUTE_RESOURCE) {
520 // XXX:
521 }
522
523 if (usage & PIPE_BIND_COMMAND_ARGS_BUFFER) {
524 // XXX:
525 }
526
527 if (usage & PIPE_BIND_QUERY_BUFFER) {
528 // XXX:
529 }
530
531 return supported;
532 }
533