2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_program.c
26 * This file contains the driver interface for compiling shaders.
28 * See iris_program_cache.c for the in-memory program cache where the
29 * compiled shaders are stored.
34 #include "pipe/p_defines.h"
35 #include "pipe/p_state.h"
36 #include "pipe/p_context.h"
37 #include "pipe/p_screen.h"
38 #include "util/u_atomic.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/debug.h"
41 #include "compiler/nir/nir.h"
42 #include "compiler/nir/nir_builder.h"
43 #include "compiler/nir/nir_serialize.h"
44 #include "intel/compiler/brw_compiler.h"
45 #include "intel/compiler/brw_nir.h"
46 #include "iris_context.h"
47 #include "nir/tgsi_to_nir.h"
49 #define KEY_ID(prefix) .prefix.program_string_id = ish->program_id
50 #define BRW_KEY_INIT(gen, prog_id) \
51 .base.program_string_id = prog_id, \
52 .base.subgroup_size_type = BRW_SUBGROUP_SIZE_UNIFORM, \
53 .base.tex.swizzles[0 ... MAX_SAMPLERS - 1] = 0x688, \
54 .base.tex.compressed_multisample_layout_mask = ~0, \
55 .base.tex.msaa_16 = (gen >= 9 ? ~0 : 0)
58 get_new_program_id(struct iris_screen
*screen
)
60 return p_atomic_inc_return(&screen
->program_id
);
64 upload_state(struct u_upload_mgr
*uploader
,
65 struct iris_state_ref
*ref
,
70 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
75 iris_upload_ubo_ssbo_surf_state(struct iris_context
*ice
,
76 struct pipe_shader_buffer
*buf
,
77 struct iris_state_ref
*surf_state
,
80 struct pipe_context
*ctx
= &ice
->ctx
;
81 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
84 upload_state(ice
->state
.surface_uploader
, surf_state
,
85 screen
->isl_dev
.ss
.size
, 64);
87 surf_state
->res
= NULL
;
91 struct iris_resource
*res
= (void *) buf
->buffer
;
92 struct iris_bo
*surf_bo
= iris_resource_bo(surf_state
->res
);
93 surf_state
->offset
+= iris_bo_offset_from_base_address(surf_bo
);
95 isl_buffer_fill_state(&screen
->isl_dev
, map
,
96 .address
= res
->bo
->gtt_offset
+ res
->offset
+
98 .size_B
= buf
->buffer_size
- res
->offset
,
99 .format
= ssbo
? ISL_FORMAT_RAW
100 : ISL_FORMAT_R32G32B32A32_FLOAT
,
101 .swizzle
= ISL_SWIZZLE_IDENTITY
,
103 .mocs
= ice
->vtbl
.mocs(res
->bo
, &screen
->isl_dev
));
107 get_aoa_deref_offset(nir_builder
*b
,
108 nir_deref_instr
*deref
,
111 unsigned array_size
= elem_size
;
112 nir_ssa_def
*offset
= nir_imm_int(b
, 0);
114 while (deref
->deref_type
!= nir_deref_type_var
) {
115 assert(deref
->deref_type
== nir_deref_type_array
);
117 /* This level's element size is the previous level's array size */
118 nir_ssa_def
*index
= nir_ssa_for_src(b
, deref
->arr
.index
, 1);
119 assert(deref
->arr
.index
.ssa
);
120 offset
= nir_iadd(b
, offset
,
121 nir_imul(b
, index
, nir_imm_int(b
, array_size
)));
123 deref
= nir_deref_instr_parent(deref
);
124 assert(glsl_type_is_array(deref
->type
));
125 array_size
*= glsl_get_length(deref
->type
);
128 /* Accessing an invalid surface index with the dataport can result in a
129 * hang. According to the spec "if the index used to select an individual
130 * element is negative or greater than or equal to the size of the array,
131 * the results of the operation are undefined but may not lead to
132 * termination" -- which is one of the possible outcomes of the hang.
133 * Clamp the index to prevent access outside of the array bounds.
135 return nir_umin(b
, offset
, nir_imm_int(b
, array_size
- elem_size
));
139 iris_lower_storage_image_derefs(nir_shader
*nir
)
141 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
144 nir_builder_init(&b
, impl
);
146 nir_foreach_block(block
, impl
) {
147 nir_foreach_instr_safe(instr
, block
) {
148 if (instr
->type
!= nir_instr_type_intrinsic
)
151 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
152 switch (intrin
->intrinsic
) {
153 case nir_intrinsic_image_deref_load
:
154 case nir_intrinsic_image_deref_store
:
155 case nir_intrinsic_image_deref_atomic_add
:
156 case nir_intrinsic_image_deref_atomic_imin
:
157 case nir_intrinsic_image_deref_atomic_umin
:
158 case nir_intrinsic_image_deref_atomic_imax
:
159 case nir_intrinsic_image_deref_atomic_umax
:
160 case nir_intrinsic_image_deref_atomic_and
:
161 case nir_intrinsic_image_deref_atomic_or
:
162 case nir_intrinsic_image_deref_atomic_xor
:
163 case nir_intrinsic_image_deref_atomic_exchange
:
164 case nir_intrinsic_image_deref_atomic_comp_swap
:
165 case nir_intrinsic_image_deref_size
:
166 case nir_intrinsic_image_deref_samples
:
167 case nir_intrinsic_image_deref_load_raw_intel
:
168 case nir_intrinsic_image_deref_store_raw_intel
: {
169 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
170 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
172 b
.cursor
= nir_before_instr(&intrin
->instr
);
174 nir_iadd(&b
, nir_imm_int(&b
, var
->data
.driver_location
),
175 get_aoa_deref_offset(&b
, deref
, 1));
176 nir_rewrite_image_intrinsic(intrin
, index
, false);
187 // XXX: need unify_interfaces() at link time...
190 * Undo nir_lower_passthrough_edgeflags but keep the inputs_read flag.
193 iris_fix_edge_flags(nir_shader
*nir
)
195 if (nir
->info
.stage
!= MESA_SHADER_VERTEX
)
198 nir_variable
*var
= NULL
;
199 nir_foreach_variable(v
, &nir
->outputs
) {
200 if (v
->data
.location
== VARYING_SLOT_EDGE
) {
209 exec_node_remove(&var
->node
);
210 var
->data
.mode
= nir_var_shader_temp
;
211 exec_list_push_tail(&nir
->globals
, &var
->node
);
212 nir
->info
.outputs_written
&= ~VARYING_BIT_EDGE
;
213 nir
->info
.inputs_read
&= ~VERT_BIT_EDGEFLAG
;
214 nir_fixup_deref_modes(nir
);
216 nir_foreach_function(f
, nir
) {
218 nir_metadata_preserve(f
->impl
, nir_metadata_block_index
|
219 nir_metadata_dominance
|
220 nir_metadata_live_ssa_defs
|
221 nir_metadata_loop_analysis
);
229 * Fix an uncompiled shader's stream output info.
231 * Core Gallium stores output->register_index as a "slot" number, where
232 * slots are assigned consecutively to all outputs in info->outputs_written.
233 * This naive packing of outputs doesn't work for us - we too have slots,
234 * but the layout is defined by the VUE map, which we won't have until we
235 * compile a specific shader variant. So, we remap these and simply store
236 * VARYING_SLOT_* in our copy's output->register_index fields.
238 * We also fix up VARYING_SLOT_{LAYER,VIEWPORT,PSIZ} to select the Y/Z/W
239 * components of our VUE header. See brw_vue_map.c for the layout.
242 update_so_info(struct pipe_stream_output_info
*so_info
,
243 uint64_t outputs_written
)
245 uint8_t reverse_map
[64] = {};
247 while (outputs_written
) {
248 reverse_map
[slot
++] = u_bit_scan64(&outputs_written
);
251 for (unsigned i
= 0; i
< so_info
->num_outputs
; i
++) {
252 struct pipe_stream_output
*output
= &so_info
->output
[i
];
254 /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
255 output
->register_index
= reverse_map
[output
->register_index
];
257 /* The VUE header contains three scalar fields packed together:
258 * - gl_PointSize is stored in VARYING_SLOT_PSIZ.w
259 * - gl_Layer is stored in VARYING_SLOT_PSIZ.y
260 * - gl_ViewportIndex is stored in VARYING_SLOT_PSIZ.z
262 switch (output
->register_index
) {
263 case VARYING_SLOT_LAYER
:
264 assert(output
->num_components
== 1);
265 output
->register_index
= VARYING_SLOT_PSIZ
;
266 output
->start_component
= 1;
268 case VARYING_SLOT_VIEWPORT
:
269 assert(output
->num_components
== 1);
270 output
->register_index
= VARYING_SLOT_PSIZ
;
271 output
->start_component
= 2;
273 case VARYING_SLOT_PSIZ
:
274 assert(output
->num_components
== 1);
275 output
->start_component
= 3;
279 //info->outputs_written |= 1ull << output->register_index;
284 setup_vec4_image_sysval(uint32_t *sysvals
, uint32_t idx
,
285 unsigned offset
, unsigned n
)
287 assert(offset
% sizeof(uint32_t) == 0);
289 for (unsigned i
= 0; i
< n
; ++i
)
290 sysvals
[i
] = BRW_PARAM_IMAGE(idx
, offset
/ sizeof(uint32_t) + i
);
292 for (unsigned i
= n
; i
< 4; ++i
)
293 sysvals
[i
] = BRW_PARAM_BUILTIN_ZERO
;
297 * Associate NIR uniform variables with the prog_data->param[] mechanism
298 * used by the backend. Also, decide which UBOs we'd like to push in an
299 * ideal situation (though the backend can reduce this).
302 iris_setup_uniforms(const struct brw_compiler
*compiler
,
305 struct brw_stage_prog_data
*prog_data
,
306 enum brw_param_builtin
**out_system_values
,
307 unsigned *out_num_system_values
,
308 unsigned *out_num_cbufs
)
310 UNUSED
const struct gen_device_info
*devinfo
= compiler
->devinfo
;
312 const unsigned IRIS_MAX_SYSTEM_VALUES
=
313 PIPE_MAX_SHADER_IMAGES
* BRW_IMAGE_PARAM_SIZE
;
314 enum brw_param_builtin
*system_values
=
315 rzalloc_array(mem_ctx
, enum brw_param_builtin
, IRIS_MAX_SYSTEM_VALUES
);
316 unsigned num_system_values
= 0;
318 unsigned patch_vert_idx
= -1;
319 unsigned ucp_idx
[IRIS_MAX_CLIP_PLANES
];
320 unsigned img_idx
[PIPE_MAX_SHADER_IMAGES
];
321 memset(ucp_idx
, -1, sizeof(ucp_idx
));
322 memset(img_idx
, -1, sizeof(img_idx
));
324 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
327 nir_builder_init(&b
, impl
);
329 b
.cursor
= nir_before_block(nir_start_block(impl
));
330 nir_ssa_def
*temp_ubo_name
= nir_ssa_undef(&b
, 1, 32);
331 nir_ssa_def
*temp_const_ubo_name
= NULL
;
333 /* Turn system value intrinsics into uniforms */
334 nir_foreach_block(block
, impl
) {
335 nir_foreach_instr_safe(instr
, block
) {
336 if (instr
->type
!= nir_instr_type_intrinsic
)
339 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
342 switch (intrin
->intrinsic
) {
343 case nir_intrinsic_load_constant
: {
344 /* This one is special because it reads from the shader constant
345 * data and not cbuf0 which gallium uploads for us.
347 b
.cursor
= nir_before_instr(instr
);
348 nir_ssa_def
*offset
=
349 nir_iadd_imm(&b
, nir_ssa_for_src(&b
, intrin
->src
[0], 1),
350 nir_intrinsic_base(intrin
));
352 if (temp_const_ubo_name
== NULL
)
353 temp_const_ubo_name
= nir_imm_int(&b
, 0);
355 nir_intrinsic_instr
*load_ubo
=
356 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ubo
);
357 load_ubo
->num_components
= intrin
->num_components
;
358 load_ubo
->src
[0] = nir_src_for_ssa(temp_const_ubo_name
);
359 load_ubo
->src
[1] = nir_src_for_ssa(offset
);
360 nir_ssa_dest_init(&load_ubo
->instr
, &load_ubo
->dest
,
361 intrin
->dest
.ssa
.num_components
,
362 intrin
->dest
.ssa
.bit_size
,
363 intrin
->dest
.ssa
.name
);
364 nir_builder_instr_insert(&b
, &load_ubo
->instr
);
366 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
367 nir_src_for_ssa(&load_ubo
->dest
.ssa
));
368 nir_instr_remove(&intrin
->instr
);
371 case nir_intrinsic_load_user_clip_plane
: {
372 unsigned ucp
= nir_intrinsic_ucp_id(intrin
);
374 if (ucp_idx
[ucp
] == -1) {
375 ucp_idx
[ucp
] = num_system_values
;
376 num_system_values
+= 4;
379 for (int i
= 0; i
< 4; i
++) {
380 system_values
[ucp_idx
[ucp
] + i
] =
381 BRW_PARAM_BUILTIN_CLIP_PLANE(ucp
, i
);
384 b
.cursor
= nir_before_instr(instr
);
385 offset
= nir_imm_int(&b
, ucp_idx
[ucp
] * sizeof(uint32_t));
388 case nir_intrinsic_load_patch_vertices_in
:
389 if (patch_vert_idx
== -1)
390 patch_vert_idx
= num_system_values
++;
392 system_values
[patch_vert_idx
] =
393 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
;
395 b
.cursor
= nir_before_instr(instr
);
396 offset
= nir_imm_int(&b
, patch_vert_idx
* sizeof(uint32_t));
398 case nir_intrinsic_image_deref_load_param_intel
: {
399 assert(devinfo
->gen
< 9);
400 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
401 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
403 if (img_idx
[var
->data
.binding
] == -1) {
404 /* GL only allows arrays of arrays of images. */
405 assert(glsl_type_is_image(glsl_without_array(var
->type
)));
406 unsigned num_images
= MAX2(1, glsl_get_aoa_size(var
->type
));
408 for (int i
= 0; i
< num_images
; i
++) {
409 const unsigned img
= var
->data
.binding
+ i
;
411 img_idx
[img
] = num_system_values
;
412 num_system_values
+= BRW_IMAGE_PARAM_SIZE
;
414 uint32_t *img_sv
= &system_values
[img_idx
[img
]];
416 setup_vec4_image_sysval(
417 img_sv
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
, img
,
418 offsetof(struct brw_image_param
, offset
), 2);
419 setup_vec4_image_sysval(
420 img_sv
+ BRW_IMAGE_PARAM_SIZE_OFFSET
, img
,
421 offsetof(struct brw_image_param
, size
), 3);
422 setup_vec4_image_sysval(
423 img_sv
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
, img
,
424 offsetof(struct brw_image_param
, stride
), 4);
425 setup_vec4_image_sysval(
426 img_sv
+ BRW_IMAGE_PARAM_TILING_OFFSET
, img
,
427 offsetof(struct brw_image_param
, tiling
), 3);
428 setup_vec4_image_sysval(
429 img_sv
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
, img
,
430 offsetof(struct brw_image_param
, swizzling
), 2);
434 b
.cursor
= nir_before_instr(instr
);
435 offset
= nir_iadd(&b
,
436 get_aoa_deref_offset(&b
, deref
, BRW_IMAGE_PARAM_SIZE
* 4),
437 nir_imm_int(&b
, img_idx
[var
->data
.binding
] * 4 +
438 nir_intrinsic_base(intrin
) * 16));
445 unsigned comps
= nir_intrinsic_dest_components(intrin
);
447 nir_intrinsic_instr
*load
=
448 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_ubo
);
449 load
->num_components
= comps
;
450 load
->src
[0] = nir_src_for_ssa(temp_ubo_name
);
451 load
->src
[1] = nir_src_for_ssa(offset
);
452 nir_ssa_dest_init(&load
->instr
, &load
->dest
, comps
, 32, NULL
);
453 nir_builder_instr_insert(&b
, &load
->instr
);
454 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
455 nir_src_for_ssa(&load
->dest
.ssa
));
456 nir_instr_remove(instr
);
460 nir_validate_shader(nir
, "before remapping");
462 /* Uniforms are stored in constant buffer 0, the
463 * user-facing UBOs are indexed by one. So if any constant buffer is
464 * needed, the constant buffer 0 will be needed, so account for it.
466 unsigned num_cbufs
= nir
->info
.num_ubos
;
467 if (num_cbufs
|| nir
->num_uniforms
)
470 /* Place the new params in a new cbuf. */
471 if (num_system_values
> 0) {
472 unsigned sysval_cbuf_index
= num_cbufs
;
475 system_values
= reralloc(mem_ctx
, system_values
, enum brw_param_builtin
,
478 nir_foreach_block(block
, impl
) {
479 nir_foreach_instr_safe(instr
, block
) {
480 if (instr
->type
!= nir_instr_type_intrinsic
)
483 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
485 if (load
->intrinsic
!= nir_intrinsic_load_ubo
)
488 b
.cursor
= nir_before_instr(instr
);
490 assert(load
->src
[0].is_ssa
);
492 if (load
->src
[0].ssa
== temp_ubo_name
) {
493 nir_ssa_def
*imm
= nir_imm_int(&b
, sysval_cbuf_index
);
494 nir_instr_rewrite_src(instr
, &load
->src
[0],
495 nir_src_for_ssa(imm
));
500 /* We need to fold the new iadds for brw_nir_analyze_ubo_ranges */
501 nir_opt_constant_folding(nir
);
503 ralloc_free(system_values
);
504 system_values
= NULL
;
507 assert(num_cbufs
< PIPE_MAX_CONSTANT_BUFFERS
);
508 nir_validate_shader(nir
, "after remap");
510 /* We don't use params[] but gallium leaves num_uniforms set. We use this
511 * to detect when cbuf0 exists but we don't need it anymore when we get
512 * here. Instead, zero it out so that the back-end doesn't get confused
513 * when nr_params * 4 != num_uniforms != nr_params * 4.
515 nir
->num_uniforms
= 0;
517 /* Constant loads (if any) need to go at the end of the constant buffers so
518 * we need to know num_cbufs before we can lower to them.
520 if (temp_const_ubo_name
!= NULL
) {
521 nir_load_const_instr
*const_ubo_index
=
522 nir_instr_as_load_const(temp_const_ubo_name
->parent_instr
);
523 assert(const_ubo_index
->def
.bit_size
== 32);
524 const_ubo_index
->value
[0].u32
= num_cbufs
;
527 *out_system_values
= system_values
;
528 *out_num_system_values
= num_system_values
;
529 *out_num_cbufs
= num_cbufs
;
532 static const char *surface_group_names
[] = {
533 [IRIS_SURFACE_GROUP_RENDER_TARGET
] = "render target",
534 [IRIS_SURFACE_GROUP_RENDER_TARGET_READ
] = "non-coherent render target read",
535 [IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = "CS work groups",
536 [IRIS_SURFACE_GROUP_TEXTURE
] = "texture",
537 [IRIS_SURFACE_GROUP_UBO
] = "ubo",
538 [IRIS_SURFACE_GROUP_SSBO
] = "ssbo",
539 [IRIS_SURFACE_GROUP_IMAGE
] = "image",
543 iris_print_binding_table(FILE *fp
, const char *name
,
544 const struct iris_binding_table
*bt
)
546 STATIC_ASSERT(ARRAY_SIZE(surface_group_names
) == IRIS_SURFACE_GROUP_COUNT
);
549 uint32_t compacted
= 0;
551 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
552 uint32_t size
= bt
->sizes
[i
];
555 compacted
+= util_bitcount64(bt
->used_mask
[i
]);
559 fprintf(fp
, "Binding table for %s is empty\n\n", name
);
563 if (total
!= compacted
) {
564 fprintf(fp
, "Binding table for %s "
565 "(compacted to %u entries from %u entries)\n",
566 name
, compacted
, total
);
568 fprintf(fp
, "Binding table for %s (%u entries)\n", name
, total
);
572 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
573 uint64_t mask
= bt
->used_mask
[i
];
575 int index
= u_bit_scan64(&mask
);
576 fprintf(fp
, " [%u] %s #%d\n", entry
++, surface_group_names
[i
], index
);
583 /* Max elements in a surface group. */
584 SURFACE_GROUP_MAX_ELEMENTS
= 64,
588 * Map a <group, index> pair to a binding table index.
590 * For example: <UBO, 5> => binding table index 12
593 iris_group_index_to_bti(const struct iris_binding_table
*bt
,
594 enum iris_surface_group group
, uint32_t index
)
596 assert(index
< bt
->sizes
[group
]);
597 uint64_t mask
= bt
->used_mask
[group
];
598 uint64_t bit
= 1ull << index
;
600 return bt
->offsets
[group
] + util_bitcount64((bit
- 1) & mask
);
602 return IRIS_SURFACE_NOT_USED
;
607 * Map a binding table index back to a <group, index> pair.
609 * For example: binding table index 12 => <UBO, 5>
612 iris_bti_to_group_index(const struct iris_binding_table
*bt
,
613 enum iris_surface_group group
, uint32_t bti
)
615 uint64_t used_mask
= bt
->used_mask
[group
];
616 assert(bti
>= bt
->offsets
[group
]);
618 uint32_t c
= bti
- bt
->offsets
[group
];
620 int i
= u_bit_scan64(&used_mask
);
626 return IRIS_SURFACE_NOT_USED
;
630 rewrite_src_with_bti(nir_builder
*b
, struct iris_binding_table
*bt
,
631 nir_instr
*instr
, nir_src
*src
,
632 enum iris_surface_group group
)
634 assert(bt
->sizes
[group
] > 0);
636 b
->cursor
= nir_before_instr(instr
);
638 if (nir_src_is_const(*src
)) {
639 uint32_t index
= nir_src_as_uint(*src
);
640 bti
= nir_imm_intN_t(b
, iris_group_index_to_bti(bt
, group
, index
),
643 /* Indirect usage makes all the surfaces of the group to be available,
644 * so we can just add the base.
646 assert(bt
->used_mask
[group
] == BITFIELD64_MASK(bt
->sizes
[group
]));
647 bti
= nir_iadd_imm(b
, src
->ssa
, bt
->offsets
[group
]);
649 nir_instr_rewrite_src(instr
, src
, nir_src_for_ssa(bti
));
653 mark_used_with_src(struct iris_binding_table
*bt
, nir_src
*src
,
654 enum iris_surface_group group
)
656 assert(bt
->sizes
[group
] > 0);
658 if (nir_src_is_const(*src
)) {
659 uint64_t index
= nir_src_as_uint(*src
);
660 assert(index
< bt
->sizes
[group
]);
661 bt
->used_mask
[group
] |= 1ull << index
;
663 /* There's an indirect usage, we need all the surfaces. */
664 bt
->used_mask
[group
] = BITFIELD64_MASK(bt
->sizes
[group
]);
669 skip_compacting_binding_tables(void)
671 static int skip
= -1;
673 skip
= env_var_as_boolean("INTEL_DISABLE_COMPACT_BINDING_TABLE", false);
678 * Set up the binding table indices and apply to the shader.
681 iris_setup_binding_table(const struct gen_device_info
*devinfo
,
682 struct nir_shader
*nir
,
683 struct iris_binding_table
*bt
,
684 unsigned num_render_targets
,
685 unsigned num_system_values
,
688 const struct shader_info
*info
= &nir
->info
;
690 memset(bt
, 0, sizeof(*bt
));
692 /* Set the sizes for each surface group. For some groups, we already know
693 * upfront how many will be used, so mark them.
695 if (info
->stage
== MESA_SHADER_FRAGMENT
) {
696 bt
->sizes
[IRIS_SURFACE_GROUP_RENDER_TARGET
] = num_render_targets
;
697 /* All render targets used. */
698 bt
->used_mask
[IRIS_SURFACE_GROUP_RENDER_TARGET
] =
699 BITFIELD64_MASK(num_render_targets
);
701 /* Setup render target read surface group inorder to support non-coherent
702 * framebuffer fetch on Gen8
704 if (devinfo
->gen
== 8 && info
->outputs_read
) {
705 bt
->sizes
[IRIS_SURFACE_GROUP_RENDER_TARGET_READ
] = num_render_targets
;
706 bt
->used_mask
[IRIS_SURFACE_GROUP_RENDER_TARGET_READ
] =
707 BITFIELD64_MASK(num_render_targets
);
709 } else if (info
->stage
== MESA_SHADER_COMPUTE
) {
710 bt
->sizes
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = 1;
713 bt
->sizes
[IRIS_SURFACE_GROUP_TEXTURE
] = util_last_bit(info
->textures_used
);
714 bt
->used_mask
[IRIS_SURFACE_GROUP_TEXTURE
] = info
->textures_used
;
716 bt
->sizes
[IRIS_SURFACE_GROUP_IMAGE
] = info
->num_images
;
718 /* Allocate an extra slot in the UBO section for NIR constants.
719 * Binding table compaction will remove it if unnecessary.
721 * We don't include them in iris_compiled_shader::num_cbufs because
722 * they are uploaded separately from shs->constbuf[], but from a shader
723 * point of view, they're another UBO (at the end of the section).
725 bt
->sizes
[IRIS_SURFACE_GROUP_UBO
] = num_cbufs
+ 1;
727 bt
->sizes
[IRIS_SURFACE_GROUP_SSBO
] = info
->num_ssbos
;
729 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++)
730 assert(bt
->sizes
[i
] <= SURFACE_GROUP_MAX_ELEMENTS
);
732 /* Mark surfaces used for the cases we don't have the information available
735 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
736 nir_foreach_block (block
, impl
) {
737 nir_foreach_instr (instr
, block
) {
738 if (instr
->type
!= nir_instr_type_intrinsic
)
741 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
742 switch (intrin
->intrinsic
) {
743 case nir_intrinsic_load_num_work_groups
:
744 bt
->used_mask
[IRIS_SURFACE_GROUP_CS_WORK_GROUPS
] = 1;
747 case nir_intrinsic_load_output
:
748 if (devinfo
->gen
== 8) {
749 mark_used_with_src(bt
, &intrin
->src
[0],
750 IRIS_SURFACE_GROUP_RENDER_TARGET_READ
);
754 case nir_intrinsic_image_size
:
755 case nir_intrinsic_image_load
:
756 case nir_intrinsic_image_store
:
757 case nir_intrinsic_image_atomic_add
:
758 case nir_intrinsic_image_atomic_imin
:
759 case nir_intrinsic_image_atomic_umin
:
760 case nir_intrinsic_image_atomic_imax
:
761 case nir_intrinsic_image_atomic_umax
:
762 case nir_intrinsic_image_atomic_and
:
763 case nir_intrinsic_image_atomic_or
:
764 case nir_intrinsic_image_atomic_xor
:
765 case nir_intrinsic_image_atomic_exchange
:
766 case nir_intrinsic_image_atomic_comp_swap
:
767 case nir_intrinsic_image_load_raw_intel
:
768 case nir_intrinsic_image_store_raw_intel
:
769 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_IMAGE
);
772 case nir_intrinsic_load_ubo
:
773 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_UBO
);
776 case nir_intrinsic_store_ssbo
:
777 mark_used_with_src(bt
, &intrin
->src
[1], IRIS_SURFACE_GROUP_SSBO
);
780 case nir_intrinsic_get_buffer_size
:
781 case nir_intrinsic_ssbo_atomic_add
:
782 case nir_intrinsic_ssbo_atomic_imin
:
783 case nir_intrinsic_ssbo_atomic_umin
:
784 case nir_intrinsic_ssbo_atomic_imax
:
785 case nir_intrinsic_ssbo_atomic_umax
:
786 case nir_intrinsic_ssbo_atomic_and
:
787 case nir_intrinsic_ssbo_atomic_or
:
788 case nir_intrinsic_ssbo_atomic_xor
:
789 case nir_intrinsic_ssbo_atomic_exchange
:
790 case nir_intrinsic_ssbo_atomic_comp_swap
:
791 case nir_intrinsic_ssbo_atomic_fmin
:
792 case nir_intrinsic_ssbo_atomic_fmax
:
793 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
794 case nir_intrinsic_load_ssbo
:
795 mark_used_with_src(bt
, &intrin
->src
[0], IRIS_SURFACE_GROUP_SSBO
);
804 /* When disable we just mark everything as used. */
805 if (unlikely(skip_compacting_binding_tables())) {
806 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++)
807 bt
->used_mask
[i
] = BITFIELD64_MASK(bt
->sizes
[i
]);
810 /* Calculate the offsets and the binding table size based on the used
811 * surfaces. After this point, the functions to go between "group indices"
812 * and binding table indices can be used.
815 for (int i
= 0; i
< IRIS_SURFACE_GROUP_COUNT
; i
++) {
816 if (bt
->used_mask
[i
] != 0) {
817 bt
->offsets
[i
] = next
;
818 next
+= util_bitcount64(bt
->used_mask
[i
]);
821 bt
->size_bytes
= next
* 4;
823 if (unlikely(INTEL_DEBUG
& DEBUG_BT
)) {
824 iris_print_binding_table(stderr
, gl_shader_stage_name(info
->stage
), bt
);
827 /* Apply the binding table indices. The backend compiler is not expected
828 * to change those, as we haven't set any of the *_start entries in brw
832 nir_builder_init(&b
, impl
);
834 nir_foreach_block (block
, impl
) {
835 nir_foreach_instr (instr
, block
) {
836 if (instr
->type
== nir_instr_type_tex
) {
837 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
839 iris_group_index_to_bti(bt
, IRIS_SURFACE_GROUP_TEXTURE
,
844 if (instr
->type
!= nir_instr_type_intrinsic
)
847 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
848 switch (intrin
->intrinsic
) {
849 case nir_intrinsic_image_size
:
850 case nir_intrinsic_image_load
:
851 case nir_intrinsic_image_store
:
852 case nir_intrinsic_image_atomic_add
:
853 case nir_intrinsic_image_atomic_imin
:
854 case nir_intrinsic_image_atomic_umin
:
855 case nir_intrinsic_image_atomic_imax
:
856 case nir_intrinsic_image_atomic_umax
:
857 case nir_intrinsic_image_atomic_and
:
858 case nir_intrinsic_image_atomic_or
:
859 case nir_intrinsic_image_atomic_xor
:
860 case nir_intrinsic_image_atomic_exchange
:
861 case nir_intrinsic_image_atomic_comp_swap
:
862 case nir_intrinsic_image_load_raw_intel
:
863 case nir_intrinsic_image_store_raw_intel
:
864 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
865 IRIS_SURFACE_GROUP_IMAGE
);
868 case nir_intrinsic_load_ubo
:
869 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
870 IRIS_SURFACE_GROUP_UBO
);
873 case nir_intrinsic_store_ssbo
:
874 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[1],
875 IRIS_SURFACE_GROUP_SSBO
);
878 case nir_intrinsic_load_output
:
879 if (devinfo
->gen
== 8) {
880 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
881 IRIS_SURFACE_GROUP_RENDER_TARGET_READ
);
885 case nir_intrinsic_get_buffer_size
:
886 case nir_intrinsic_ssbo_atomic_add
:
887 case nir_intrinsic_ssbo_atomic_imin
:
888 case nir_intrinsic_ssbo_atomic_umin
:
889 case nir_intrinsic_ssbo_atomic_imax
:
890 case nir_intrinsic_ssbo_atomic_umax
:
891 case nir_intrinsic_ssbo_atomic_and
:
892 case nir_intrinsic_ssbo_atomic_or
:
893 case nir_intrinsic_ssbo_atomic_xor
:
894 case nir_intrinsic_ssbo_atomic_exchange
:
895 case nir_intrinsic_ssbo_atomic_comp_swap
:
896 case nir_intrinsic_ssbo_atomic_fmin
:
897 case nir_intrinsic_ssbo_atomic_fmax
:
898 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
899 case nir_intrinsic_load_ssbo
:
900 rewrite_src_with_bti(&b
, bt
, instr
, &intrin
->src
[0],
901 IRIS_SURFACE_GROUP_SSBO
);
912 iris_debug_recompile(struct iris_context
*ice
,
913 struct shader_info
*info
,
914 const struct brw_base_prog_key
*key
)
916 struct iris_screen
*screen
= (struct iris_screen
*) ice
->ctx
.screen
;
917 const struct brw_compiler
*c
= screen
->compiler
;
922 c
->shader_perf_log(&ice
->dbg
, "Recompiling %s shader for program %s: %s\n",
923 _mesa_shader_stage_to_string(info
->stage
),
924 info
->name
? info
->name
: "(no identifier)",
925 info
->label
? info
->label
: "");
927 const void *old_key
=
928 iris_find_previous_compile(ice
, info
->stage
, key
->program_string_id
);
930 brw_debug_key_recompile(c
, &ice
->dbg
, info
->stage
, old_key
, key
);
934 * Get the shader for the last enabled geometry stage.
936 * This stage is the one which will feed stream output and the rasterizer.
938 static gl_shader_stage
939 last_vue_stage(struct iris_context
*ice
)
941 if (ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
942 return MESA_SHADER_GEOMETRY
;
944 if (ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
945 return MESA_SHADER_TESS_EVAL
;
947 return MESA_SHADER_VERTEX
;
951 * Compile a vertex shader, and upload the assembly.
953 static struct iris_compiled_shader
*
954 iris_compile_vs(struct iris_context
*ice
,
955 struct iris_uncompiled_shader
*ish
,
956 const struct iris_vs_prog_key
*key
)
958 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
959 const struct brw_compiler
*compiler
= screen
->compiler
;
960 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
961 void *mem_ctx
= ralloc_context(NULL
);
962 struct brw_vs_prog_data
*vs_prog_data
=
963 rzalloc(mem_ctx
, struct brw_vs_prog_data
);
964 struct brw_vue_prog_data
*vue_prog_data
= &vs_prog_data
->base
;
965 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
966 enum brw_param_builtin
*system_values
;
967 unsigned num_system_values
;
970 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
972 if (key
->vue
.nr_userclip_plane_consts
) {
973 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
974 nir_lower_clip_vs(nir
, (1 << key
->vue
.nr_userclip_plane_consts
) - 1,
976 nir_lower_io_to_temporaries(nir
, impl
, true, false);
977 nir_lower_global_vars_to_local(nir
);
978 nir_lower_vars_to_ssa(nir
);
979 nir_shader_gather_info(nir
, impl
);
982 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
984 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
985 &num_system_values
, &num_cbufs
);
987 struct iris_binding_table bt
;
988 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
989 num_system_values
, num_cbufs
);
991 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
993 brw_compute_vue_map(devinfo
,
994 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
995 nir
->info
.separate_shader
);
997 struct brw_vs_prog_key brw_key
= {
998 BRW_KEY_INIT(devinfo
->gen
, key
->vue
.base
.program_string_id
),
1000 /* Don't tell the backend about our clip plane constants, we've
1001 * already lowered them in NIR and don't want it doing it again.
1003 .nr_userclip_plane_consts
= 0,
1006 char *error_str
= NULL
;
1007 const unsigned *program
=
1008 brw_compile_vs(compiler
, &ice
->dbg
, mem_ctx
, &brw_key
, vs_prog_data
,
1009 nir
, -1, NULL
, &error_str
);
1010 if (program
== NULL
) {
1011 dbg_printf("Failed to compile vertex shader: %s\n", error_str
);
1012 ralloc_free(mem_ctx
);
1016 if (ish
->compiled_once
) {
1017 iris_debug_recompile(ice
, &nir
->info
, &brw_key
.base
);
1019 ish
->compiled_once
= true;
1022 uint32_t *so_decls
=
1023 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1024 &vue_prog_data
->vue_map
);
1026 struct iris_compiled_shader
*shader
=
1027 iris_upload_shader(ice
, IRIS_CACHE_VS
, sizeof(*key
), key
, program
,
1028 prog_data
, so_decls
, system_values
, num_system_values
,
1031 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1033 ralloc_free(mem_ctx
);
1038 * Update the current vertex shader variant.
1040 * Fill out the key, look in the cache, compile and bind if needed.
1043 iris_update_compiled_vs(struct iris_context
*ice
)
1045 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
1046 struct iris_uncompiled_shader
*ish
=
1047 ice
->shaders
.uncompiled
[MESA_SHADER_VERTEX
];
1049 struct iris_vs_prog_key key
= { KEY_ID(vue
.base
) };
1050 ice
->vtbl
.populate_vs_key(ice
, &ish
->nir
->info
, last_vue_stage(ice
), &key
);
1052 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_VS
];
1053 struct iris_compiled_shader
*shader
=
1054 iris_find_cached_shader(ice
, IRIS_CACHE_VS
, sizeof(key
), &key
);
1057 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1060 shader
= iris_compile_vs(ice
, ish
, &key
);
1062 if (old
!= shader
) {
1063 ice
->shaders
.prog
[IRIS_CACHE_VS
] = shader
;
1064 ice
->state
.dirty
|= IRIS_DIRTY_VS
|
1065 IRIS_DIRTY_BINDINGS_VS
|
1066 IRIS_DIRTY_CONSTANTS_VS
|
1068 shs
->sysvals_need_upload
= true;
1070 const struct brw_vs_prog_data
*vs_prog_data
=
1071 (void *) shader
->prog_data
;
1072 const bool uses_draw_params
= vs_prog_data
->uses_firstvertex
||
1073 vs_prog_data
->uses_baseinstance
;
1074 const bool uses_derived_draw_params
= vs_prog_data
->uses_drawid
||
1075 vs_prog_data
->uses_is_indexed_draw
;
1076 const bool needs_sgvs_element
= uses_draw_params
||
1077 vs_prog_data
->uses_instanceid
||
1078 vs_prog_data
->uses_vertexid
;
1080 if (ice
->state
.vs_uses_draw_params
!= uses_draw_params
||
1081 ice
->state
.vs_uses_derived_draw_params
!= uses_derived_draw_params
||
1082 ice
->state
.vs_needs_edge_flag
!= ish
->needs_edge_flag
) {
1083 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
|
1084 IRIS_DIRTY_VERTEX_ELEMENTS
;
1086 ice
->state
.vs_uses_draw_params
= uses_draw_params
;
1087 ice
->state
.vs_uses_derived_draw_params
= uses_derived_draw_params
;
1088 ice
->state
.vs_needs_sgvs_element
= needs_sgvs_element
;
1089 ice
->state
.vs_needs_edge_flag
= ish
->needs_edge_flag
;
1094 * Get the shader_info for a given stage, or NULL if the stage is disabled.
1096 const struct shader_info
*
1097 iris_get_shader_info(const struct iris_context
*ice
, gl_shader_stage stage
)
1099 const struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[stage
];
1104 const nir_shader
*nir
= ish
->nir
;
1109 * Get the union of TCS output and TES input slots.
1111 * TCS and TES need to agree on a common URB entry layout. In particular,
1112 * the data for all patch vertices is stored in a single URB entry (unlike
1113 * GS which has one entry per input vertex). This means that per-vertex
1114 * array indexing needs a stride.
1116 * SSO requires locations to match, but doesn't require the number of
1117 * outputs/inputs to match (in fact, the TCS often has extra outputs).
1118 * So, we need to take the extra step of unifying these on the fly.
1121 get_unified_tess_slots(const struct iris_context
*ice
,
1122 uint64_t *per_vertex_slots
,
1123 uint32_t *per_patch_slots
)
1125 const struct shader_info
*tcs
=
1126 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
1127 const struct shader_info
*tes
=
1128 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
1130 *per_vertex_slots
= tes
->inputs_read
;
1131 *per_patch_slots
= tes
->patch_inputs_read
;
1134 *per_vertex_slots
|= tcs
->outputs_written
;
1135 *per_patch_slots
|= tcs
->patch_outputs_written
;
1140 * Compile a tessellation control shader, and upload the assembly.
1142 static struct iris_compiled_shader
*
1143 iris_compile_tcs(struct iris_context
*ice
,
1144 struct iris_uncompiled_shader
*ish
,
1145 const struct iris_tcs_prog_key
*key
)
1147 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1148 const struct brw_compiler
*compiler
= screen
->compiler
;
1149 const struct nir_shader_compiler_options
*options
=
1150 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].NirOptions
;
1151 void *mem_ctx
= ralloc_context(NULL
);
1152 struct brw_tcs_prog_data
*tcs_prog_data
=
1153 rzalloc(mem_ctx
, struct brw_tcs_prog_data
);
1154 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
1155 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1156 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1157 enum brw_param_builtin
*system_values
= NULL
;
1158 unsigned num_system_values
= 0;
1159 unsigned num_cbufs
= 0;
1163 struct iris_binding_table bt
;
1165 struct brw_tcs_prog_key brw_key
= {
1166 BRW_KEY_INIT(devinfo
->gen
, key
->vue
.base
.program_string_id
),
1167 .tes_primitive_mode
= key
->tes_primitive_mode
,
1168 .input_vertices
= key
->input_vertices
,
1169 .patch_outputs_written
= key
->patch_outputs_written
,
1170 .outputs_written
= key
->outputs_written
,
1171 .quads_workaround
= key
->quads_workaround
,
1175 nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1177 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1178 &num_system_values
, &num_cbufs
);
1179 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
1180 num_system_values
, num_cbufs
);
1181 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1184 brw_nir_create_passthrough_tcs(mem_ctx
, compiler
, options
, &brw_key
);
1186 /* Reserve space for passing the default tess levels as constants. */
1188 num_system_values
= 8;
1190 rzalloc_array(mem_ctx
, enum brw_param_builtin
, num_system_values
);
1191 prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t, num_system_values
);
1192 prog_data
->nr_params
= num_system_values
;
1194 if (key
->tes_primitive_mode
== GL_QUADS
) {
1195 for (int i
= 0; i
< 4; i
++)
1196 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
1198 system_values
[3] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
1199 system_values
[2] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
;
1200 } else if (key
->tes_primitive_mode
== GL_TRIANGLES
) {
1201 for (int i
= 0; i
< 3; i
++)
1202 system_values
[7 - i
] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
+ i
;
1204 system_values
[4] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
;
1206 assert(key
->tes_primitive_mode
== GL_ISOLINES
);
1207 system_values
[7] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
;
1208 system_values
[6] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
1211 /* Manually setup the TCS binding table. */
1212 memset(&bt
, 0, sizeof(bt
));
1213 bt
.sizes
[IRIS_SURFACE_GROUP_UBO
] = 1;
1214 bt
.used_mask
[IRIS_SURFACE_GROUP_UBO
] = 1;
1217 prog_data
->ubo_ranges
[0].length
= 1;
1220 char *error_str
= NULL
;
1221 const unsigned *program
=
1222 brw_compile_tcs(compiler
, &ice
->dbg
, mem_ctx
, &brw_key
, tcs_prog_data
,
1223 nir
, -1, NULL
, &error_str
);
1224 if (program
== NULL
) {
1225 dbg_printf("Failed to compile control shader: %s\n", error_str
);
1226 ralloc_free(mem_ctx
);
1231 if (ish
->compiled_once
) {
1232 iris_debug_recompile(ice
, &nir
->info
, &brw_key
.base
);
1234 ish
->compiled_once
= true;
1238 struct iris_compiled_shader
*shader
=
1239 iris_upload_shader(ice
, IRIS_CACHE_TCS
, sizeof(*key
), key
, program
,
1240 prog_data
, NULL
, system_values
, num_system_values
,
1244 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1246 ralloc_free(mem_ctx
);
1251 * Update the current tessellation control shader variant.
1253 * Fill out the key, look in the cache, compile and bind if needed.
1256 iris_update_compiled_tcs(struct iris_context
*ice
)
1258 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
1259 struct iris_uncompiled_shader
*tcs
=
1260 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_CTRL
];
1261 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1262 const struct brw_compiler
*compiler
= screen
->compiler
;
1263 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1265 const struct shader_info
*tes_info
=
1266 iris_get_shader_info(ice
, MESA_SHADER_TESS_EVAL
);
1267 struct iris_tcs_prog_key key
= {
1268 .vue
.base
.program_string_id
= tcs
? tcs
->program_id
: 0,
1269 .tes_primitive_mode
= tes_info
->tess
.primitive_mode
,
1271 !tcs
|| compiler
->use_tcs_8_patch
? ice
->state
.vertices_per_patch
: 0,
1272 .quads_workaround
= devinfo
->gen
< 9 &&
1273 tes_info
->tess
.primitive_mode
== GL_QUADS
&&
1274 tes_info
->tess
.spacing
== TESS_SPACING_EQUAL
,
1276 get_unified_tess_slots(ice
, &key
.outputs_written
,
1277 &key
.patch_outputs_written
);
1278 ice
->vtbl
.populate_tcs_key(ice
, &key
);
1280 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TCS
];
1281 struct iris_compiled_shader
*shader
=
1282 iris_find_cached_shader(ice
, IRIS_CACHE_TCS
, sizeof(key
), &key
);
1285 shader
= iris_disk_cache_retrieve(ice
, tcs
, &key
, sizeof(key
));
1288 shader
= iris_compile_tcs(ice
, tcs
, &key
);
1290 if (old
!= shader
) {
1291 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = shader
;
1292 ice
->state
.dirty
|= IRIS_DIRTY_TCS
|
1293 IRIS_DIRTY_BINDINGS_TCS
|
1294 IRIS_DIRTY_CONSTANTS_TCS
;
1295 shs
->sysvals_need_upload
= true;
1300 * Compile a tessellation evaluation shader, and upload the assembly.
1302 static struct iris_compiled_shader
*
1303 iris_compile_tes(struct iris_context
*ice
,
1304 struct iris_uncompiled_shader
*ish
,
1305 const struct iris_tes_prog_key
*key
)
1307 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1308 const struct brw_compiler
*compiler
= screen
->compiler
;
1309 void *mem_ctx
= ralloc_context(NULL
);
1310 struct brw_tes_prog_data
*tes_prog_data
=
1311 rzalloc(mem_ctx
, struct brw_tes_prog_data
);
1312 struct brw_vue_prog_data
*vue_prog_data
= &tes_prog_data
->base
;
1313 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1314 enum brw_param_builtin
*system_values
;
1315 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1316 unsigned num_system_values
;
1319 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1321 if (key
->vue
.nr_userclip_plane_consts
) {
1322 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
1323 nir_lower_clip_vs(nir
, (1 << key
->vue
.nr_userclip_plane_consts
) - 1,
1325 nir_lower_io_to_temporaries(nir
, impl
, true, false);
1326 nir_lower_global_vars_to_local(nir
);
1327 nir_lower_vars_to_ssa(nir
);
1328 nir_shader_gather_info(nir
, impl
);
1331 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1332 &num_system_values
, &num_cbufs
);
1334 struct iris_binding_table bt
;
1335 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
1336 num_system_values
, num_cbufs
);
1338 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1340 struct brw_vue_map input_vue_map
;
1341 brw_compute_tess_vue_map(&input_vue_map
, key
->inputs_read
,
1342 key
->patch_inputs_read
);
1344 struct brw_tes_prog_key brw_key
= {
1345 BRW_KEY_INIT(devinfo
->gen
, key
->vue
.base
.program_string_id
),
1346 .patch_inputs_read
= key
->patch_inputs_read
,
1347 .inputs_read
= key
->inputs_read
,
1350 char *error_str
= NULL
;
1351 const unsigned *program
=
1352 brw_compile_tes(compiler
, &ice
->dbg
, mem_ctx
, &brw_key
, &input_vue_map
,
1353 tes_prog_data
, nir
, -1, NULL
, &error_str
);
1354 if (program
== NULL
) {
1355 dbg_printf("Failed to compile evaluation shader: %s\n", error_str
);
1356 ralloc_free(mem_ctx
);
1360 if (ish
->compiled_once
) {
1361 iris_debug_recompile(ice
, &nir
->info
, &brw_key
.base
);
1363 ish
->compiled_once
= true;
1366 uint32_t *so_decls
=
1367 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1368 &vue_prog_data
->vue_map
);
1371 struct iris_compiled_shader
*shader
=
1372 iris_upload_shader(ice
, IRIS_CACHE_TES
, sizeof(*key
), key
, program
,
1373 prog_data
, so_decls
, system_values
, num_system_values
,
1376 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1378 ralloc_free(mem_ctx
);
1383 * Update the current tessellation evaluation shader variant.
1385 * Fill out the key, look in the cache, compile and bind if needed.
1388 iris_update_compiled_tes(struct iris_context
*ice
)
1390 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
];
1391 struct iris_uncompiled_shader
*ish
=
1392 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1394 struct iris_tes_prog_key key
= { KEY_ID(vue
.base
) };
1395 get_unified_tess_slots(ice
, &key
.inputs_read
, &key
.patch_inputs_read
);
1396 ice
->vtbl
.populate_tes_key(ice
, &ish
->nir
->info
, last_vue_stage(ice
), &key
);
1398 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_TES
];
1399 struct iris_compiled_shader
*shader
=
1400 iris_find_cached_shader(ice
, IRIS_CACHE_TES
, sizeof(key
), &key
);
1403 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1406 shader
= iris_compile_tes(ice
, ish
, &key
);
1408 if (old
!= shader
) {
1409 ice
->shaders
.prog
[IRIS_CACHE_TES
] = shader
;
1410 ice
->state
.dirty
|= IRIS_DIRTY_TES
|
1411 IRIS_DIRTY_BINDINGS_TES
|
1412 IRIS_DIRTY_CONSTANTS_TES
;
1413 shs
->sysvals_need_upload
= true;
1416 /* TODO: Could compare and avoid flagging this. */
1417 const struct shader_info
*tes_info
= &ish
->nir
->info
;
1418 if (tes_info
->system_values_read
& (1ull << SYSTEM_VALUE_VERTICES_IN
)) {
1419 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TES
;
1420 ice
->state
.shaders
[MESA_SHADER_TESS_EVAL
].sysvals_need_upload
= true;
1425 * Compile a geometry shader, and upload the assembly.
1427 static struct iris_compiled_shader
*
1428 iris_compile_gs(struct iris_context
*ice
,
1429 struct iris_uncompiled_shader
*ish
,
1430 const struct iris_gs_prog_key
*key
)
1432 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1433 const struct brw_compiler
*compiler
= screen
->compiler
;
1434 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1435 void *mem_ctx
= ralloc_context(NULL
);
1436 struct brw_gs_prog_data
*gs_prog_data
=
1437 rzalloc(mem_ctx
, struct brw_gs_prog_data
);
1438 struct brw_vue_prog_data
*vue_prog_data
= &gs_prog_data
->base
;
1439 struct brw_stage_prog_data
*prog_data
= &vue_prog_data
->base
;
1440 enum brw_param_builtin
*system_values
;
1441 unsigned num_system_values
;
1444 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1446 if (key
->vue
.nr_userclip_plane_consts
) {
1447 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
1448 nir_lower_clip_gs(nir
, (1 << key
->vue
.nr_userclip_plane_consts
) - 1,
1450 nir_lower_io_to_temporaries(nir
, impl
, true, false);
1451 nir_lower_global_vars_to_local(nir
);
1452 nir_lower_vars_to_ssa(nir
);
1453 nir_shader_gather_info(nir
, impl
);
1456 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1457 &num_system_values
, &num_cbufs
);
1459 struct iris_binding_table bt
;
1460 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
1461 num_system_values
, num_cbufs
);
1463 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1465 brw_compute_vue_map(devinfo
,
1466 &vue_prog_data
->vue_map
, nir
->info
.outputs_written
,
1467 nir
->info
.separate_shader
);
1469 struct brw_gs_prog_key brw_key
= {
1470 BRW_KEY_INIT(devinfo
->gen
, key
->vue
.base
.program_string_id
),
1473 char *error_str
= NULL
;
1474 const unsigned *program
=
1475 brw_compile_gs(compiler
, &ice
->dbg
, mem_ctx
, &brw_key
, gs_prog_data
,
1476 nir
, NULL
, -1, NULL
, &error_str
);
1477 if (program
== NULL
) {
1478 dbg_printf("Failed to compile geometry shader: %s\n", error_str
);
1479 ralloc_free(mem_ctx
);
1483 if (ish
->compiled_once
) {
1484 iris_debug_recompile(ice
, &nir
->info
, &brw_key
.base
);
1486 ish
->compiled_once
= true;
1489 uint32_t *so_decls
=
1490 ice
->vtbl
.create_so_decl_list(&ish
->stream_output
,
1491 &vue_prog_data
->vue_map
);
1493 struct iris_compiled_shader
*shader
=
1494 iris_upload_shader(ice
, IRIS_CACHE_GS
, sizeof(*key
), key
, program
,
1495 prog_data
, so_decls
, system_values
, num_system_values
,
1498 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1500 ralloc_free(mem_ctx
);
1505 * Update the current geometry shader variant.
1507 * Fill out the key, look in the cache, compile and bind if needed.
1510 iris_update_compiled_gs(struct iris_context
*ice
)
1512 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_GEOMETRY
];
1513 struct iris_uncompiled_shader
*ish
=
1514 ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
];
1515 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_GS
];
1516 struct iris_compiled_shader
*shader
= NULL
;
1519 struct iris_gs_prog_key key
= { KEY_ID(vue
.base
) };
1520 ice
->vtbl
.populate_gs_key(ice
, &ish
->nir
->info
, last_vue_stage(ice
), &key
);
1523 iris_find_cached_shader(ice
, IRIS_CACHE_GS
, sizeof(key
), &key
);
1526 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1529 shader
= iris_compile_gs(ice
, ish
, &key
);
1532 if (old
!= shader
) {
1533 ice
->shaders
.prog
[IRIS_CACHE_GS
] = shader
;
1534 ice
->state
.dirty
|= IRIS_DIRTY_GS
|
1535 IRIS_DIRTY_BINDINGS_GS
|
1536 IRIS_DIRTY_CONSTANTS_GS
;
1537 shs
->sysvals_need_upload
= true;
1542 * Compile a fragment (pixel) shader, and upload the assembly.
1544 static struct iris_compiled_shader
*
1545 iris_compile_fs(struct iris_context
*ice
,
1546 struct iris_uncompiled_shader
*ish
,
1547 const struct iris_fs_prog_key
*key
,
1548 struct brw_vue_map
*vue_map
)
1550 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1551 const struct brw_compiler
*compiler
= screen
->compiler
;
1552 void *mem_ctx
= ralloc_context(NULL
);
1553 struct brw_wm_prog_data
*fs_prog_data
=
1554 rzalloc(mem_ctx
, struct brw_wm_prog_data
);
1555 struct brw_stage_prog_data
*prog_data
= &fs_prog_data
->base
;
1556 enum brw_param_builtin
*system_values
;
1557 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1558 unsigned num_system_values
;
1561 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1563 prog_data
->use_alt_mode
= ish
->use_alt_mode
;
1565 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1566 &num_system_values
, &num_cbufs
);
1568 /* Lower output variables to load_output intrinsics before setting up
1569 * binding tables, so iris_setup_binding_table can map any load_output
1570 * intrinsics to IRIS_SURFACE_GROUP_RENDER_TARGET_READ on Gen8 for
1571 * non-coherent framebuffer fetches.
1573 brw_nir_lower_fs_outputs(nir
);
1575 /* On Gen11+, shader RT write messages have a "Null Render Target" bit
1576 * and do not need a binding table entry with a null surface. Earlier
1577 * generations need an entry for a null surface.
1579 int null_rts
= devinfo
->gen
< 11 ? 1 : 0;
1581 struct iris_binding_table bt
;
1582 iris_setup_binding_table(devinfo
, nir
, &bt
,
1583 MAX2(key
->nr_color_regions
, null_rts
),
1584 num_system_values
, num_cbufs
);
1586 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
1588 struct brw_wm_prog_key brw_key
= {
1589 BRW_KEY_INIT(devinfo
->gen
, key
->base
.program_string_id
),
1590 .nr_color_regions
= key
->nr_color_regions
,
1591 .flat_shade
= key
->flat_shade
,
1592 .alpha_test_replicate_alpha
= key
->alpha_test_replicate_alpha
,
1593 .alpha_to_coverage
= key
->alpha_to_coverage
,
1594 .clamp_fragment_color
= key
->clamp_fragment_color
,
1595 .persample_interp
= key
->persample_interp
,
1596 .multisample_fbo
= key
->multisample_fbo
,
1597 .force_dual_color_blend
= key
->force_dual_color_blend
,
1598 .coherent_fb_fetch
= key
->coherent_fb_fetch
,
1599 .color_outputs_valid
= key
->color_outputs_valid
,
1600 .input_slots_valid
= key
->input_slots_valid
,
1603 char *error_str
= NULL
;
1604 const unsigned *program
=
1605 brw_compile_fs(compiler
, &ice
->dbg
, mem_ctx
, &brw_key
, fs_prog_data
,
1606 nir
, -1, -1, -1, true, false, vue_map
,
1608 if (program
== NULL
) {
1609 dbg_printf("Failed to compile fragment shader: %s\n", error_str
);
1610 ralloc_free(mem_ctx
);
1614 if (ish
->compiled_once
) {
1615 iris_debug_recompile(ice
, &nir
->info
, &brw_key
.base
);
1617 ish
->compiled_once
= true;
1620 struct iris_compiled_shader
*shader
=
1621 iris_upload_shader(ice
, IRIS_CACHE_FS
, sizeof(*key
), key
, program
,
1622 prog_data
, NULL
, system_values
, num_system_values
,
1625 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1627 ralloc_free(mem_ctx
);
1632 * Update the current fragment shader variant.
1634 * Fill out the key, look in the cache, compile and bind if needed.
1637 iris_update_compiled_fs(struct iris_context
*ice
)
1639 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_FRAGMENT
];
1640 struct iris_uncompiled_shader
*ish
=
1641 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
1642 struct iris_fs_prog_key key
= { KEY_ID(base
) };
1643 ice
->vtbl
.populate_fs_key(ice
, &ish
->nir
->info
, &key
);
1645 if (ish
->nos
& (1ull << IRIS_NOS_LAST_VUE_MAP
))
1646 key
.input_slots_valid
= ice
->shaders
.last_vue_map
->slots_valid
;
1648 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_FS
];
1649 struct iris_compiled_shader
*shader
=
1650 iris_find_cached_shader(ice
, IRIS_CACHE_FS
, sizeof(key
), &key
);
1653 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1656 shader
= iris_compile_fs(ice
, ish
, &key
, ice
->shaders
.last_vue_map
);
1658 if (old
!= shader
) {
1659 // XXX: only need to flag CLIP if barycentric has NONPERSPECTIVE
1660 // toggles. might be able to avoid flagging SBE too.
1661 ice
->shaders
.prog
[IRIS_CACHE_FS
] = shader
;
1662 ice
->state
.dirty
|= IRIS_DIRTY_FS
|
1663 IRIS_DIRTY_BINDINGS_FS
|
1664 IRIS_DIRTY_CONSTANTS_FS
|
1668 shs
->sysvals_need_upload
= true;
1673 * Update the last enabled stage's VUE map.
1675 * When the shader feeding the rasterizer's output interface changes, we
1676 * need to re-emit various packets.
1679 update_last_vue_map(struct iris_context
*ice
,
1680 struct brw_stage_prog_data
*prog_data
)
1682 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
1683 struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
1684 struct brw_vue_map
*old_map
= ice
->shaders
.last_vue_map
;
1685 const uint64_t changed_slots
=
1686 (old_map
? old_map
->slots_valid
: 0ull) ^ vue_map
->slots_valid
;
1688 if (changed_slots
& VARYING_BIT_VIEWPORT
) {
1689 ice
->state
.num_viewports
=
1690 (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
) ? IRIS_MAX_VIEWPORTS
: 1;
1691 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
1692 IRIS_DIRTY_SF_CL_VIEWPORT
|
1693 IRIS_DIRTY_CC_VIEWPORT
|
1694 IRIS_DIRTY_SCISSOR_RECT
|
1695 IRIS_DIRTY_UNCOMPILED_FS
|
1696 ice
->state
.dirty_for_nos
[IRIS_NOS_LAST_VUE_MAP
];
1699 if (changed_slots
|| (old_map
&& old_map
->separate
!= vue_map
->separate
)) {
1700 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1703 ice
->shaders
.last_vue_map
= &vue_prog_data
->vue_map
;
1707 iris_update_pull_constant_descriptors(struct iris_context
*ice
,
1708 gl_shader_stage stage
)
1710 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
1712 if (!shader
|| !shader
->prog_data
->has_ubo_pull
)
1715 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1716 bool any_new_descriptors
=
1717 shader
->num_system_values
> 0 && shs
->sysvals_need_upload
;
1719 unsigned bound_cbufs
= shs
->bound_cbufs
;
1721 while (bound_cbufs
) {
1722 const int i
= u_bit_scan(&bound_cbufs
);
1723 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[i
];
1724 struct iris_state_ref
*surf_state
= &shs
->constbuf_surf_state
[i
];
1725 if (!surf_state
->res
&& cbuf
->buffer
) {
1726 iris_upload_ubo_ssbo_surf_state(ice
, cbuf
, surf_state
, false);
1727 any_new_descriptors
= true;
1731 if (any_new_descriptors
)
1732 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
1736 * Get the prog_data for a given stage, or NULL if the stage is disabled.
1738 static struct brw_vue_prog_data
*
1739 get_vue_prog_data(struct iris_context
*ice
, gl_shader_stage stage
)
1741 if (!ice
->shaders
.prog
[stage
])
1744 return (void *) ice
->shaders
.prog
[stage
]->prog_data
;
1747 // XXX: iris_compiled_shaders are space-leaking :(
1748 // XXX: do remember to unbind them if deleting them.
1751 * Update the current shader variants for the given state.
1753 * This should be called on every draw call to ensure that the correct
1754 * shaders are bound. It will also flag any dirty state triggered by
1755 * swapping out those shaders.
1758 iris_update_compiled_shaders(struct iris_context
*ice
)
1760 const uint64_t dirty
= ice
->state
.dirty
;
1762 struct brw_vue_prog_data
*old_prog_datas
[4];
1763 if (!(dirty
& IRIS_DIRTY_URB
)) {
1764 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++)
1765 old_prog_datas
[i
] = get_vue_prog_data(ice
, i
);
1768 if (dirty
& (IRIS_DIRTY_UNCOMPILED_TCS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1769 struct iris_uncompiled_shader
*tes
=
1770 ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
];
1772 iris_update_compiled_tcs(ice
);
1773 iris_update_compiled_tes(ice
);
1775 ice
->shaders
.prog
[IRIS_CACHE_TCS
] = NULL
;
1776 ice
->shaders
.prog
[IRIS_CACHE_TES
] = NULL
;
1778 IRIS_DIRTY_TCS
| IRIS_DIRTY_TES
|
1779 IRIS_DIRTY_BINDINGS_TCS
| IRIS_DIRTY_BINDINGS_TES
|
1780 IRIS_DIRTY_CONSTANTS_TCS
| IRIS_DIRTY_CONSTANTS_TES
;
1784 if (dirty
& IRIS_DIRTY_UNCOMPILED_VS
)
1785 iris_update_compiled_vs(ice
);
1786 if (dirty
& IRIS_DIRTY_UNCOMPILED_GS
)
1787 iris_update_compiled_gs(ice
);
1789 if (dirty
& (IRIS_DIRTY_UNCOMPILED_GS
| IRIS_DIRTY_UNCOMPILED_TES
)) {
1790 const struct iris_compiled_shader
*gs
=
1791 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
];
1792 const struct iris_compiled_shader
*tes
=
1793 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
];
1795 bool points_or_lines
= false;
1798 const struct brw_gs_prog_data
*gs_prog_data
= (void *) gs
->prog_data
;
1800 gs_prog_data
->output_topology
== _3DPRIM_POINTLIST
||
1801 gs_prog_data
->output_topology
== _3DPRIM_LINESTRIP
;
1803 const struct brw_tes_prog_data
*tes_data
= (void *) tes
->prog_data
;
1805 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_LINE
||
1806 tes_data
->output_topology
== BRW_TESS_OUTPUT_TOPOLOGY_POINT
;
1809 if (ice
->shaders
.output_topology_is_points_or_lines
!= points_or_lines
) {
1810 /* Outbound to XY Clip enables */
1811 ice
->shaders
.output_topology_is_points_or_lines
= points_or_lines
;
1812 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1816 gl_shader_stage last_stage
= last_vue_stage(ice
);
1817 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[last_stage
];
1818 struct iris_uncompiled_shader
*ish
= ice
->shaders
.uncompiled
[last_stage
];
1819 update_last_vue_map(ice
, shader
->prog_data
);
1820 if (ice
->state
.streamout
!= shader
->streamout
) {
1821 ice
->state
.streamout
= shader
->streamout
;
1822 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
| IRIS_DIRTY_STREAMOUT
;
1825 if (ice
->state
.streamout_active
) {
1826 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
1827 struct iris_stream_output_target
*so
=
1828 (void *) ice
->state
.so_target
[i
];
1830 so
->stride
= ish
->stream_output
.stride
[i
] * sizeof(uint32_t);
1834 if (dirty
& IRIS_DIRTY_UNCOMPILED_FS
)
1835 iris_update_compiled_fs(ice
);
1837 /* Changing shader interfaces may require a URB configuration. */
1838 if (!(dirty
& IRIS_DIRTY_URB
)) {
1839 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
1840 struct brw_vue_prog_data
*old
= old_prog_datas
[i
];
1841 struct brw_vue_prog_data
*new = get_vue_prog_data(ice
, i
);
1842 if (!!old
!= !!new ||
1843 (new && new->urb_entry_size
!= old
->urb_entry_size
)) {
1844 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
1850 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_FRAGMENT
; i
++) {
1851 if (ice
->state
.dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< i
))
1852 iris_update_pull_constant_descriptors(ice
, i
);
1856 static struct iris_compiled_shader
*
1857 iris_compile_cs(struct iris_context
*ice
,
1858 struct iris_uncompiled_shader
*ish
,
1859 const struct iris_cs_prog_key
*key
)
1861 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1862 const struct brw_compiler
*compiler
= screen
->compiler
;
1863 void *mem_ctx
= ralloc_context(NULL
);
1864 struct brw_cs_prog_data
*cs_prog_data
=
1865 rzalloc(mem_ctx
, struct brw_cs_prog_data
);
1866 struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1867 enum brw_param_builtin
*system_values
;
1868 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1869 unsigned num_system_values
;
1872 nir_shader
*nir
= nir_shader_clone(mem_ctx
, ish
->nir
);
1874 iris_setup_uniforms(compiler
, mem_ctx
, nir
, prog_data
, &system_values
,
1875 &num_system_values
, &num_cbufs
);
1877 struct iris_binding_table bt
;
1878 iris_setup_binding_table(devinfo
, nir
, &bt
, /* num_render_targets */ 0,
1879 num_system_values
, num_cbufs
);
1881 struct brw_cs_prog_key brw_key
= {
1882 BRW_KEY_INIT(devinfo
->gen
, key
->base
.program_string_id
),
1885 char *error_str
= NULL
;
1886 const unsigned *program
=
1887 brw_compile_cs(compiler
, &ice
->dbg
, mem_ctx
, &brw_key
, cs_prog_data
,
1888 nir
, -1, NULL
, &error_str
);
1889 if (program
== NULL
) {
1890 dbg_printf("Failed to compile compute shader: %s\n", error_str
);
1891 ralloc_free(mem_ctx
);
1895 if (ish
->compiled_once
) {
1896 iris_debug_recompile(ice
, &nir
->info
, &brw_key
.base
);
1898 ish
->compiled_once
= true;
1901 struct iris_compiled_shader
*shader
=
1902 iris_upload_shader(ice
, IRIS_CACHE_CS
, sizeof(*key
), key
, program
,
1903 prog_data
, NULL
, system_values
, num_system_values
,
1906 iris_disk_cache_store(screen
->disk_cache
, ish
, shader
, key
, sizeof(*key
));
1908 ralloc_free(mem_ctx
);
1913 iris_update_compiled_cs(struct iris_context
*ice
)
1915 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
1916 struct iris_uncompiled_shader
*ish
=
1917 ice
->shaders
.uncompiled
[MESA_SHADER_COMPUTE
];
1919 struct iris_cs_prog_key key
= { KEY_ID(base
) };
1920 ice
->vtbl
.populate_cs_key(ice
, &key
);
1922 struct iris_compiled_shader
*old
= ice
->shaders
.prog
[IRIS_CACHE_CS
];
1923 struct iris_compiled_shader
*shader
=
1924 iris_find_cached_shader(ice
, IRIS_CACHE_CS
, sizeof(key
), &key
);
1927 shader
= iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
));
1930 shader
= iris_compile_cs(ice
, ish
, &key
);
1932 if (old
!= shader
) {
1933 ice
->shaders
.prog
[IRIS_CACHE_CS
] = shader
;
1934 ice
->state
.dirty
|= IRIS_DIRTY_CS
|
1935 IRIS_DIRTY_BINDINGS_CS
|
1936 IRIS_DIRTY_CONSTANTS_CS
;
1937 shs
->sysvals_need_upload
= true;
1942 iris_update_compiled_compute_shader(struct iris_context
*ice
)
1944 if (ice
->state
.dirty
& IRIS_DIRTY_UNCOMPILED_CS
)
1945 iris_update_compiled_cs(ice
);
1947 if (ice
->state
.dirty
& IRIS_DIRTY_CONSTANTS_CS
)
1948 iris_update_pull_constant_descriptors(ice
, MESA_SHADER_COMPUTE
);
1952 iris_fill_cs_push_const_buffer(struct brw_cs_prog_data
*cs_prog_data
,
1955 assert(cs_prog_data
->push
.total
.size
> 0);
1956 assert(cs_prog_data
->push
.cross_thread
.size
== 0);
1957 assert(cs_prog_data
->push
.per_thread
.dwords
== 1);
1958 assert(cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
1959 for (unsigned t
= 0; t
< cs_prog_data
->threads
; t
++)
1964 * Allocate scratch BOs as needed for the given per-thread size and stage.
1967 iris_get_scratch_space(struct iris_context
*ice
,
1968 unsigned per_thread_scratch
,
1969 gl_shader_stage stage
)
1971 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
1972 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1973 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1975 unsigned encoded_size
= ffs(per_thread_scratch
) - 11;
1976 assert(encoded_size
< (1 << 16));
1978 struct iris_bo
**bop
= &ice
->shaders
.scratch_bos
[encoded_size
][stage
];
1980 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
1982 * "Scratch Space per slice is computed based on 4 sub-slices. SW
1983 * must allocate scratch space enough so that each slice has 4
1986 * According to the other driver team, this applies to compute shaders
1987 * as well. This is not currently documented at all.
1989 * This hack is no longer necessary on Gen11+.
1991 unsigned subslice_total
= screen
->subslice_total
;
1992 if (devinfo
->gen
< 11)
1993 subslice_total
= 4 * devinfo
->num_slices
;
1994 assert(subslice_total
>= screen
->subslice_total
);
1997 unsigned scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
1999 if (devinfo
->gen
>= 11) {
2000 /* The MEDIA_VFE_STATE docs say:
2002 * "Starting with this configuration, the Maximum Number of
2003 * Threads must be set to (#EU * 8) for GPGPU dispatches.
2005 * Although there are only 7 threads per EU in the configuration,
2006 * the FFTID is calculated as if there are 8 threads per EU,
2007 * which in turn requires a larger amount of Scratch Space to be
2008 * allocated by the driver."
2010 scratch_ids_per_subslice
= 8 * 8;
2013 uint32_t max_threads
[] = {
2014 [MESA_SHADER_VERTEX
] = devinfo
->max_vs_threads
,
2015 [MESA_SHADER_TESS_CTRL
] = devinfo
->max_tcs_threads
,
2016 [MESA_SHADER_TESS_EVAL
] = devinfo
->max_tes_threads
,
2017 [MESA_SHADER_GEOMETRY
] = devinfo
->max_gs_threads
,
2018 [MESA_SHADER_FRAGMENT
] = devinfo
->max_wm_threads
,
2019 [MESA_SHADER_COMPUTE
] = scratch_ids_per_subslice
* subslice_total
,
2022 uint32_t size
= per_thread_scratch
* max_threads
[stage
];
2024 *bop
= iris_bo_alloc(bufmgr
, "scratch", size
, IRIS_MEMZONE_SHADER
);
2030 /* ------------------------------------------------------------------- */
2033 * The pipe->create_[stage]_state() driver hooks.
2035 * Performs basic NIR preprocessing, records any state dependencies, and
2036 * returns an iris_uncompiled_shader as the Gallium CSO.
2038 * Actual shader compilation to assembly happens later, at first use.
2041 iris_create_uncompiled_shader(struct pipe_context
*ctx
,
2043 const struct pipe_stream_output_info
*so_info
)
2045 struct iris_context
*ice
= (void *)ctx
;
2046 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2047 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2049 struct iris_uncompiled_shader
*ish
=
2050 calloc(1, sizeof(struct iris_uncompiled_shader
));
2054 NIR_PASS(ish
->needs_edge_flag
, nir
, iris_fix_edge_flags
);
2056 brw_preprocess_nir(screen
->compiler
, nir
, NULL
);
2058 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
2059 NIR_PASS_V(nir
, iris_lower_storage_image_derefs
);
2063 if (nir
->constant_data_size
> 0) {
2064 unsigned data_offset
;
2065 u_upload_data(ice
->shaders
.uploader
, 0, nir
->constant_data_size
,
2066 32, nir
->constant_data
, &data_offset
, &ish
->const_data
);
2068 struct pipe_shader_buffer psb
= {
2069 .buffer
= ish
->const_data
,
2070 .buffer_offset
= data_offset
,
2071 .buffer_size
= nir
->constant_data_size
,
2073 iris_upload_ubo_ssbo_surf_state(ice
, &psb
, &ish
->const_data_state
, false);
2076 ish
->program_id
= get_new_program_id(screen
);
2079 memcpy(&ish
->stream_output
, so_info
, sizeof(*so_info
));
2080 update_so_info(&ish
->stream_output
, nir
->info
.outputs_written
);
2083 /* Save this now before potentially dropping nir->info.name */
2084 if (nir
->info
.name
&& strncmp(nir
->info
.name
, "ARB", 3) == 0)
2085 ish
->use_alt_mode
= true;
2087 if (screen
->disk_cache
) {
2088 /* Serialize the NIR to a binary blob that we can hash for the disk
2089 * cache. Drop unnecessary information (like variable names)
2090 * so the serialized NIR is smaller, and also to let us detect more
2091 * isomorphic shaders when hashing, increasing cache hits.
2095 nir_serialize(&blob
, nir
, true);
2096 _mesa_sha1_compute(blob
.data
, blob
.size
, ish
->nir_sha1
);
2103 static struct iris_uncompiled_shader
*
2104 iris_create_shader_state(struct pipe_context
*ctx
,
2105 const struct pipe_shader_state
*state
)
2107 struct nir_shader
*nir
;
2109 if (state
->type
== PIPE_SHADER_IR_TGSI
)
2110 nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
2112 nir
= state
->ir
.nir
;
2114 return iris_create_uncompiled_shader(ctx
, nir
, &state
->stream_output
);
2118 iris_create_vs_state(struct pipe_context
*ctx
,
2119 const struct pipe_shader_state
*state
)
2121 struct iris_context
*ice
= (void *) ctx
;
2122 struct iris_screen
*screen
= (void *) ctx
->screen
;
2123 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2125 /* User clip planes */
2126 if (ish
->nir
->info
.clip_distance_array_size
== 0)
2127 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
2129 if (screen
->precompile
) {
2130 struct iris_vs_prog_key key
= { KEY_ID(vue
.base
) };
2132 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2133 iris_compile_vs(ice
, ish
, &key
);
2140 iris_create_tcs_state(struct pipe_context
*ctx
,
2141 const struct pipe_shader_state
*state
)
2143 struct iris_context
*ice
= (void *) ctx
;
2144 struct iris_screen
*screen
= (void *) ctx
->screen
;
2145 const struct brw_compiler
*compiler
= screen
->compiler
;
2146 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2147 struct shader_info
*info
= &ish
->nir
->info
;
2149 if (screen
->precompile
) {
2150 const unsigned _GL_TRIANGLES
= 0x0004;
2151 struct iris_tcs_prog_key key
= {
2153 // XXX: make sure the linker fills this out from the TES...
2154 .tes_primitive_mode
=
2155 info
->tess
.primitive_mode
? info
->tess
.primitive_mode
2157 .outputs_written
= info
->outputs_written
,
2158 .patch_outputs_written
= info
->patch_outputs_written
,
2161 /* 8_PATCH mode needs the key to contain the input patch dimensionality.
2162 * We don't have that information, so we randomly guess that the input
2163 * and output patches are the same size. This is a bad guess, but we
2164 * can't do much better.
2166 if (compiler
->use_tcs_8_patch
)
2167 key
.input_vertices
= info
->tess
.tcs_vertices_out
;
2169 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2170 iris_compile_tcs(ice
, ish
, &key
);
2177 iris_create_tes_state(struct pipe_context
*ctx
,
2178 const struct pipe_shader_state
*state
)
2180 struct iris_context
*ice
= (void *) ctx
;
2181 struct iris_screen
*screen
= (void *) ctx
->screen
;
2182 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2183 struct shader_info
*info
= &ish
->nir
->info
;
2185 /* User clip planes */
2186 if (ish
->nir
->info
.clip_distance_array_size
== 0)
2187 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
2189 if (screen
->precompile
) {
2190 struct iris_tes_prog_key key
= {
2192 // XXX: not ideal, need TCS output/TES input unification
2193 .inputs_read
= info
->inputs_read
,
2194 .patch_inputs_read
= info
->patch_inputs_read
,
2197 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2198 iris_compile_tes(ice
, ish
, &key
);
2205 iris_create_gs_state(struct pipe_context
*ctx
,
2206 const struct pipe_shader_state
*state
)
2208 struct iris_context
*ice
= (void *) ctx
;
2209 struct iris_screen
*screen
= (void *) ctx
->screen
;
2210 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2212 /* User clip planes */
2213 if (ish
->nir
->info
.clip_distance_array_size
== 0)
2214 ish
->nos
|= (1ull << IRIS_NOS_RASTERIZER
);
2216 if (screen
->precompile
) {
2217 struct iris_gs_prog_key key
= { KEY_ID(vue
.base
) };
2219 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2220 iris_compile_gs(ice
, ish
, &key
);
2227 iris_create_fs_state(struct pipe_context
*ctx
,
2228 const struct pipe_shader_state
*state
)
2230 struct iris_context
*ice
= (void *) ctx
;
2231 struct iris_screen
*screen
= (void *) ctx
->screen
;
2232 struct iris_uncompiled_shader
*ish
= iris_create_shader_state(ctx
, state
);
2233 struct shader_info
*info
= &ish
->nir
->info
;
2235 ish
->nos
|= (1ull << IRIS_NOS_FRAMEBUFFER
) |
2236 (1ull << IRIS_NOS_DEPTH_STENCIL_ALPHA
) |
2237 (1ull << IRIS_NOS_RASTERIZER
) |
2238 (1ull << IRIS_NOS_BLEND
);
2240 /* The program key needs the VUE map if there are > 16 inputs */
2241 if (util_bitcount64(ish
->nir
->info
.inputs_read
&
2242 BRW_FS_VARYING_INPUT_MASK
) > 16) {
2243 ish
->nos
|= (1ull << IRIS_NOS_LAST_VUE_MAP
);
2246 if (screen
->precompile
) {
2247 const uint64_t color_outputs
= info
->outputs_written
&
2248 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
2249 BITFIELD64_BIT(FRAG_RESULT_STENCIL
) |
2250 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
));
2252 bool can_rearrange_varyings
=
2253 util_bitcount64(info
->inputs_read
& BRW_FS_VARYING_INPUT_MASK
) <= 16;
2255 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2256 struct iris_fs_prog_key key
= {
2258 .nr_color_regions
= util_bitcount(color_outputs
),
2259 .coherent_fb_fetch
= devinfo
->gen
>= 9,
2260 .input_slots_valid
=
2261 can_rearrange_varyings
? 0 : info
->inputs_read
| VARYING_BIT_POS
,
2264 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2265 iris_compile_fs(ice
, ish
, &key
, NULL
);
2272 iris_create_compute_state(struct pipe_context
*ctx
,
2273 const struct pipe_compute_state
*state
)
2275 assert(state
->ir_type
== PIPE_SHADER_IR_NIR
);
2277 struct iris_context
*ice
= (void *) ctx
;
2278 struct iris_screen
*screen
= (void *) ctx
->screen
;
2279 struct iris_uncompiled_shader
*ish
=
2280 iris_create_uncompiled_shader(ctx
, (void *) state
->prog
, NULL
);
2282 // XXX: disallow more than 64KB of shared variables
2284 if (screen
->precompile
) {
2285 struct iris_cs_prog_key key
= { KEY_ID(base
) };
2287 if (!iris_disk_cache_retrieve(ice
, ish
, &key
, sizeof(key
)))
2288 iris_compile_cs(ice
, ish
, &key
);
2295 * The pipe->delete_[stage]_state() driver hooks.
2297 * Frees the iris_uncompiled_shader.
2300 iris_delete_shader_state(struct pipe_context
*ctx
, void *state
, gl_shader_stage stage
)
2302 struct iris_uncompiled_shader
*ish
= state
;
2303 struct iris_context
*ice
= (void *) ctx
;
2305 if (ice
->shaders
.uncompiled
[stage
] == ish
) {
2306 ice
->shaders
.uncompiled
[stage
] = NULL
;
2307 ice
->state
.dirty
|= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
2310 if (ish
->const_data
) {
2311 pipe_resource_reference(&ish
->const_data
, NULL
);
2312 pipe_resource_reference(&ish
->const_data_state
.res
, NULL
);
2315 ralloc_free(ish
->nir
);
2320 iris_delete_vs_state(struct pipe_context
*ctx
, void *state
)
2322 iris_delete_shader_state(ctx
, state
, MESA_SHADER_VERTEX
);
2326 iris_delete_tcs_state(struct pipe_context
*ctx
, void *state
)
2328 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_CTRL
);
2332 iris_delete_tes_state(struct pipe_context
*ctx
, void *state
)
2334 iris_delete_shader_state(ctx
, state
, MESA_SHADER_TESS_EVAL
);
2338 iris_delete_gs_state(struct pipe_context
*ctx
, void *state
)
2340 iris_delete_shader_state(ctx
, state
, MESA_SHADER_GEOMETRY
);
2344 iris_delete_fs_state(struct pipe_context
*ctx
, void *state
)
2346 iris_delete_shader_state(ctx
, state
, MESA_SHADER_FRAGMENT
);
2350 iris_delete_cs_state(struct pipe_context
*ctx
, void *state
)
2352 iris_delete_shader_state(ctx
, state
, MESA_SHADER_COMPUTE
);
2356 * The pipe->bind_[stage]_state() driver hook.
2358 * Binds an uncompiled shader as the current one for a particular stage.
2359 * Updates dirty tracking to account for the shader's NOS.
2362 bind_shader_state(struct iris_context
*ice
,
2363 struct iris_uncompiled_shader
*ish
,
2364 gl_shader_stage stage
)
2366 uint64_t dirty_bit
= IRIS_DIRTY_UNCOMPILED_VS
<< stage
;
2367 const uint64_t nos
= ish
? ish
->nos
: 0;
2369 const struct shader_info
*old_info
= iris_get_shader_info(ice
, stage
);
2370 const struct shader_info
*new_info
= ish
? &ish
->nir
->info
: NULL
;
2372 if ((old_info
? util_last_bit(old_info
->textures_used
) : 0) !=
2373 (new_info
? util_last_bit(new_info
->textures_used
) : 0)) {
2374 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
2377 ice
->shaders
.uncompiled
[stage
] = ish
;
2378 ice
->state
.dirty
|= dirty_bit
;
2380 /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
2381 * (or that they no longer need to do so).
2383 for (int i
= 0; i
< IRIS_NOS_COUNT
; i
++) {
2385 ice
->state
.dirty_for_nos
[i
] |= dirty_bit
;
2387 ice
->state
.dirty_for_nos
[i
] &= ~dirty_bit
;
2392 iris_bind_vs_state(struct pipe_context
*ctx
, void *state
)
2394 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2395 struct iris_uncompiled_shader
*new_ish
= state
;
2398 ice
->state
.window_space_position
!=
2399 new_ish
->nir
->info
.vs
.window_space_position
) {
2400 ice
->state
.window_space_position
=
2401 new_ish
->nir
->info
.vs
.window_space_position
;
2403 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
|
2405 IRIS_DIRTY_CC_VIEWPORT
;
2408 bind_shader_state((void *) ctx
, state
, MESA_SHADER_VERTEX
);
2412 iris_bind_tcs_state(struct pipe_context
*ctx
, void *state
)
2414 bind_shader_state((void *) ctx
, state
, MESA_SHADER_TESS_CTRL
);
2418 iris_bind_tes_state(struct pipe_context
*ctx
, void *state
)
2420 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2422 /* Enabling/disabling optional stages requires a URB reconfiguration. */
2423 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_TESS_EVAL
])
2424 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
2426 bind_shader_state((void *) ctx
, state
, MESA_SHADER_TESS_EVAL
);
2430 iris_bind_gs_state(struct pipe_context
*ctx
, void *state
)
2432 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2434 /* Enabling/disabling optional stages requires a URB reconfiguration. */
2435 if (!!state
!= !!ice
->shaders
.uncompiled
[MESA_SHADER_GEOMETRY
])
2436 ice
->state
.dirty
|= IRIS_DIRTY_URB
;
2438 bind_shader_state((void *) ctx
, state
, MESA_SHADER_GEOMETRY
);
2442 iris_bind_fs_state(struct pipe_context
*ctx
, void *state
)
2444 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2445 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
2446 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2447 struct iris_uncompiled_shader
*old_ish
=
2448 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
2449 struct iris_uncompiled_shader
*new_ish
= state
;
2451 const unsigned color_bits
=
2452 BITFIELD64_BIT(FRAG_RESULT_COLOR
) |
2453 BITFIELD64_RANGE(FRAG_RESULT_DATA0
, BRW_MAX_DRAW_BUFFERS
);
2455 /* Fragment shader outputs influence HasWriteableRT */
2456 if (!old_ish
|| !new_ish
||
2457 (old_ish
->nir
->info
.outputs_written
& color_bits
) !=
2458 (new_ish
->nir
->info
.outputs_written
& color_bits
))
2459 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
2461 if (devinfo
->gen
== 8)
2462 ice
->state
.dirty
|= IRIS_DIRTY_PMA_FIX
;
2464 bind_shader_state((void *) ctx
, state
, MESA_SHADER_FRAGMENT
);
2468 iris_bind_cs_state(struct pipe_context
*ctx
, void *state
)
2470 bind_shader_state((void *) ctx
, state
, MESA_SHADER_COMPUTE
);
2474 iris_init_program_functions(struct pipe_context
*ctx
)
2476 ctx
->create_vs_state
= iris_create_vs_state
;
2477 ctx
->create_tcs_state
= iris_create_tcs_state
;
2478 ctx
->create_tes_state
= iris_create_tes_state
;
2479 ctx
->create_gs_state
= iris_create_gs_state
;
2480 ctx
->create_fs_state
= iris_create_fs_state
;
2481 ctx
->create_compute_state
= iris_create_compute_state
;
2483 ctx
->delete_vs_state
= iris_delete_vs_state
;
2484 ctx
->delete_tcs_state
= iris_delete_tcs_state
;
2485 ctx
->delete_tes_state
= iris_delete_tes_state
;
2486 ctx
->delete_gs_state
= iris_delete_gs_state
;
2487 ctx
->delete_fs_state
= iris_delete_fs_state
;
2488 ctx
->delete_compute_state
= iris_delete_cs_state
;
2490 ctx
->bind_vs_state
= iris_bind_vs_state
;
2491 ctx
->bind_tcs_state
= iris_bind_tcs_state
;
2492 ctx
->bind_tes_state
= iris_bind_tes_state
;
2493 ctx
->bind_gs_state
= iris_bind_gs_state
;
2494 ctx
->bind_fs_state
= iris_bind_fs_state
;
2495 ctx
->bind_compute_state
= iris_bind_cs_state
;