2 * Copyright © 2017 Intel Corporation
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20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resolve.c
26 * This file handles resolve tracking for main and auxiliary surfaces.
28 * It also handles our cache tracking. We have sets for the render cache,
29 * depth cache, and so on. If a BO is in a cache's set, then it may have
30 * data in that cache. The helpers take care of emitting flushes for
31 * render-to-texture, format reinterpretation issues, and other situations.
34 #include "util/hash_table.h"
36 #include "iris_context.h"
37 #include "compiler/nir/nir.h"
40 * Disable auxiliary buffers if a renderbuffer is also bound as a texture
41 * or shader image. This causes a self-dependency, where both rendering
42 * and sampling may concurrently read or write the CCS buffer, causing
46 disable_rb_aux_buffer(struct iris_context
*ice
,
47 bool *draw_aux_buffer_disabled
,
48 struct iris_resource
*tex_res
,
49 unsigned min_level
, unsigned num_levels
,
52 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
55 /* We only need to worry about color compression and fast clears. */
56 if (tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
&&
57 tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
60 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
61 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
65 struct iris_resource
*rb_res
= (void *) surf
->base
.texture
;
67 if (rb_res
->bo
== tex_res
->bo
&&
68 surf
->base
.u
.tex
.level
>= min_level
&&
69 surf
->base
.u
.tex
.level
< min_level
+ num_levels
) {
70 found
= draw_aux_buffer_disabled
[i
] = true;
76 "Disabling CCS because a renderbuffer is also bound %s.\n",
84 resolve_sampler_views(struct iris_context
*ice
,
85 struct iris_batch
*batch
,
86 struct iris_shader_state
*shs
,
87 const struct shader_info
*info
,
88 bool *draw_aux_buffer_disabled
,
89 bool consider_framebuffer
)
91 uint32_t views
= info
? (shs
->bound_sampler_views
& info
->textures_used
) : 0;
94 const int i
= u_bit_scan(&views
);
95 struct iris_sampler_view
*isv
= shs
->textures
[i
];
96 struct iris_resource
*res
= (void *) isv
->base
.texture
;
98 if (res
->base
.target
!= PIPE_BUFFER
) {
99 if (consider_framebuffer
) {
100 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
101 res
, isv
->view
.base_level
, isv
->view
.levels
,
105 iris_resource_prepare_texture(ice
, res
, isv
->view
.format
,
106 isv
->view
.base_level
, isv
->view
.levels
,
107 isv
->view
.base_array_layer
,
108 isv
->view
.array_len
);
111 iris_emit_buffer_barrier_for(batch
, res
->bo
, IRIS_DOMAIN_OTHER_READ
);
116 resolve_image_views(struct iris_context
*ice
,
117 struct iris_batch
*batch
,
118 struct iris_shader_state
*shs
,
119 const struct shader_info
*info
,
120 bool *draw_aux_buffer_disabled
,
121 bool consider_framebuffer
)
123 uint32_t views
= info
? (shs
->bound_image_views
& info
->images_used
) : 0;
126 const int i
= u_bit_scan(&views
);
127 struct pipe_image_view
*pview
= &shs
->image
[i
].base
;
128 struct iris_resource
*res
= (void *) pview
->resource
;
130 if (res
->base
.target
!= PIPE_BUFFER
) {
131 if (consider_framebuffer
) {
132 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
133 res
, pview
->u
.tex
.level
, 1,
134 "as a shader image");
137 unsigned num_layers
=
138 pview
->u
.tex
.last_layer
- pview
->u
.tex
.first_layer
+ 1;
140 enum isl_aux_usage aux_usage
=
141 iris_image_view_aux_usage(ice
, pview
, info
);
143 iris_resource_prepare_access(ice
, res
,
144 pview
->u
.tex
.level
, 1,
145 pview
->u
.tex
.first_layer
, num_layers
,
149 iris_emit_buffer_barrier_for(batch
, res
->bo
, IRIS_DOMAIN_OTHER_READ
);
155 * \brief Resolve buffers before drawing.
157 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
158 * enabled depth texture, and flush the render cache for any dirty textures.
161 iris_predraw_resolve_inputs(struct iris_context
*ice
,
162 struct iris_batch
*batch
,
163 bool *draw_aux_buffer_disabled
,
164 gl_shader_stage stage
,
165 bool consider_framebuffer
)
167 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
168 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
170 uint64_t stage_dirty
= (IRIS_STAGE_DIRTY_BINDINGS_VS
<< stage
) |
171 (consider_framebuffer
? IRIS_STAGE_DIRTY_BINDINGS_FS
: 0);
173 if (ice
->state
.stage_dirty
& stage_dirty
) {
174 resolve_sampler_views(ice
, batch
, shs
, info
, draw_aux_buffer_disabled
,
175 consider_framebuffer
);
176 resolve_image_views(ice
, batch
, shs
, info
, draw_aux_buffer_disabled
,
177 consider_framebuffer
);
182 iris_predraw_resolve_framebuffer(struct iris_context
*ice
,
183 struct iris_batch
*batch
,
184 bool *draw_aux_buffer_disabled
)
186 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
187 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
188 struct gen_device_info
*devinfo
= &screen
->devinfo
;
189 struct iris_uncompiled_shader
*ish
=
190 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
191 const nir_shader
*nir
= ish
->nir
;
193 if (ice
->state
.dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
194 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
197 struct iris_resource
*z_res
, *s_res
;
198 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
199 unsigned num_layers
=
200 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
203 iris_resource_prepare_depth(ice
, batch
, z_res
,
204 zs_surf
->u
.tex
.level
,
205 zs_surf
->u
.tex
.first_layer
,
207 iris_emit_buffer_barrier_for(batch
, z_res
->bo
,
208 IRIS_DOMAIN_DEPTH_WRITE
);
212 iris_emit_buffer_barrier_for(batch
, s_res
->bo
,
213 IRIS_DOMAIN_DEPTH_WRITE
);
218 if (devinfo
->gen
== 8 && nir
->info
.outputs_read
!= 0) {
219 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
220 if (cso_fb
->cbufs
[i
]) {
221 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
222 struct iris_resource
*res
= (void *) cso_fb
->cbufs
[i
]->texture
;
224 iris_resource_prepare_texture(ice
, res
, surf
->view
.format
,
225 surf
->view
.base_level
, 1,
226 surf
->view
.base_array_layer
,
227 surf
->view
.array_len
);
232 if ((ice
->state
.dirty
& IRIS_DIRTY_BLEND_STATE
) ||
233 (ice
->state
.stage_dirty
& IRIS_STAGE_DIRTY_BINDINGS_FS
)) {
234 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
235 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
239 struct iris_resource
*res
= (void *) surf
->base
.texture
;
241 enum isl_aux_usage aux_usage
=
242 iris_resource_render_aux_usage(ice
, res
, surf
->view
.format
,
243 ice
->state
.blend_enables
& (1u << i
),
244 draw_aux_buffer_disabled
[i
]);
246 if (ice
->state
.draw_aux_usage
[i
] != aux_usage
) {
247 ice
->state
.draw_aux_usage
[i
] = aux_usage
;
248 /* XXX: Need to track which bindings to make dirty */
249 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_BUFFER
;
250 ice
->state
.stage_dirty
|= IRIS_ALL_STAGE_DIRTY_BINDINGS
;
253 iris_resource_prepare_render(ice
, batch
, res
, surf
->view
.base_level
,
254 surf
->view
.base_array_layer
,
255 surf
->view
.array_len
,
258 iris_cache_flush_for_render(batch
, res
->bo
, surf
->view
.format
,
265 * \brief Call this after drawing to mark which buffers need resolving
267 * If the depth buffer was written to and if it has an accompanying HiZ
268 * buffer, then mark that it needs a depth resolve.
270 * If the color buffer is a multisample window system buffer, then
271 * mark that it needs a downsample.
273 * Also mark any render targets which will be textured as needing a render
277 iris_postdraw_update_resolve_tracking(struct iris_context
*ice
,
278 struct iris_batch
*batch
)
280 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
282 // XXX: front buffer drawing?
284 bool may_have_resolved_depth
=
285 ice
->state
.dirty
& (IRIS_DIRTY_DEPTH_BUFFER
|
286 IRIS_DIRTY_WM_DEPTH_STENCIL
);
288 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
290 struct iris_resource
*z_res
, *s_res
;
291 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
292 unsigned num_layers
=
293 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
296 if (may_have_resolved_depth
) {
297 iris_resource_finish_depth(ice
, z_res
, zs_surf
->u
.tex
.level
,
298 zs_surf
->u
.tex
.first_layer
, num_layers
,
299 ice
->state
.depth_writes_enabled
);
304 if (may_have_resolved_depth
&& ice
->state
.stencil_writes_enabled
) {
305 iris_resource_finish_write(ice
, s_res
, zs_surf
->u
.tex
.level
,
306 zs_surf
->u
.tex
.first_layer
, num_layers
,
312 bool may_have_resolved_color
=
313 (ice
->state
.dirty
& IRIS_DIRTY_BLEND_STATE
) ||
314 (ice
->state
.stage_dirty
& IRIS_STAGE_DIRTY_BINDINGS_FS
);
316 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
317 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
321 struct iris_resource
*res
= (void *) surf
->base
.texture
;
322 enum isl_aux_usage aux_usage
= ice
->state
.draw_aux_usage
[i
];
324 if (may_have_resolved_color
) {
325 union pipe_surface_desc
*desc
= &surf
->base
.u
;
326 unsigned num_layers
=
327 desc
->tex
.last_layer
- desc
->tex
.first_layer
+ 1;
328 iris_resource_finish_render(ice
, res
, desc
->tex
.level
,
329 desc
->tex
.first_layer
, num_layers
,
336 format_aux_tuple(enum isl_format format
, enum isl_aux_usage aux_usage
)
338 return (void *)(uintptr_t)((uint32_t)format
<< 8 | aux_usage
);
342 iris_cache_flush_for_render(struct iris_batch
*batch
,
344 enum isl_format format
,
345 enum isl_aux_usage aux_usage
)
347 iris_emit_buffer_barrier_for(batch
, bo
, IRIS_DOMAIN_RENDER_WRITE
);
349 /* Check to see if this bo has been used by a previous rendering operation
350 * but with a different format or aux usage. If it has, flush the render
351 * cache so we ensure that it's only in there with one format or aux usage
354 * Even though it's not obvious, this can easily happen in practice.
355 * Suppose a client is blending on a surface with sRGB encode enabled on
356 * gen9. This implies that you get AUX_USAGE_CCS_D at best. If the client
357 * then disables sRGB decode and continues blending we will flip on
358 * AUX_USAGE_CCS_E without doing any sort of resolve in-between (this is
359 * perfectly valid since CCS_E is a subset of CCS_D). However, this means
360 * that we have fragments in-flight which are rendering with UNORM+CCS_E
361 * and other fragments in-flight with SRGB+CCS_D on the same surface at the
362 * same time and the pixel scoreboard and color blender are trying to sort
363 * it all out. This ends badly (i.e. GPU hangs).
365 * To date, we have never observed GPU hangs or even corruption to be
366 * associated with switching the format, only the aux usage. However,
367 * there are comments in various docs which indicate that the render cache
368 * isn't 100% resilient to format changes. We may as well be conservative
369 * and flush on format changes too. We can always relax this later if we
370 * find it to be a performance problem.
372 struct hash_entry
*entry
=
373 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
375 _mesa_hash_table_insert_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
,
376 format_aux_tuple(format
, aux_usage
));
377 } else if (entry
->data
!= format_aux_tuple(format
, aux_usage
)) {
378 iris_emit_pipe_control_flush(batch
,
379 "cache tracker: render format mismatch",
380 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
381 PIPE_CONTROL_CS_STALL
);
382 entry
->data
= format_aux_tuple(format
, aux_usage
);
387 iris_resolve_color(struct iris_context
*ice
,
388 struct iris_batch
*batch
,
389 struct iris_resource
*res
,
390 unsigned level
, unsigned layer
,
391 enum isl_aux_op resolve_op
)
393 //DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer);
395 struct blorp_surf surf
;
396 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
, &surf
,
397 &res
->base
, res
->aux
.usage
, level
, true);
399 iris_batch_maybe_flush(batch
, 1500);
401 /* Ivybridge PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
403 * "Any transition from any value in {Clear, Render, Resolve} to a
404 * different value in {Clear, Render, Resolve} requires end of pipe
407 * In other words, fast clear ops are not properly synchronized with
408 * other drawing. We need to use a PIPE_CONTROL to ensure that the
409 * contents of the previous draw hit the render target before we resolve
410 * and again afterwards to ensure that the resolve is complete before we
411 * do any more regular drawing.
413 iris_emit_end_of_pipe_sync(batch
, "color resolve: pre-flush",
414 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
416 iris_batch_sync_region_start(batch
);
417 struct blorp_batch blorp_batch
;
418 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
419 /* On Gen >= 12, Stencil buffer with lossless compression needs to be
420 * resolve with WM_HZ_OP packet.
422 if (res
->aux
.usage
== ISL_AUX_USAGE_STC_CCS
) {
423 blorp_hiz_stencil_op(&blorp_batch
, &surf
, level
, layer
,
426 blorp_ccs_resolve(&blorp_batch
, &surf
, level
, layer
, 1,
427 isl_format_srgb_to_linear(res
->surf
.format
),
430 blorp_batch_finish(&blorp_batch
);
432 /* See comment above */
433 iris_emit_end_of_pipe_sync(batch
, "color resolve: post-flush",
434 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
435 iris_batch_sync_region_end(batch
);
439 iris_mcs_partial_resolve(struct iris_context
*ice
,
440 struct iris_batch
*batch
,
441 struct iris_resource
*res
,
442 uint32_t start_layer
,
445 //DBG("%s to mt %p layers %u-%u\n", __FUNCTION__, mt,
446 //start_layer, start_layer + num_layers - 1);
448 assert(isl_aux_usage_has_mcs(res
->aux
.usage
));
450 struct blorp_surf surf
;
451 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
, &surf
,
452 &res
->base
, res
->aux
.usage
, 0, true);
453 iris_emit_buffer_barrier_for(batch
, res
->bo
, IRIS_DOMAIN_RENDER_WRITE
);
455 struct blorp_batch blorp_batch
;
456 iris_batch_sync_region_start(batch
);
457 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
458 blorp_mcs_partial_resolve(&blorp_batch
, &surf
,
459 isl_format_srgb_to_linear(res
->surf
.format
),
460 start_layer
, num_layers
);
461 blorp_batch_finish(&blorp_batch
);
462 iris_batch_sync_region_end(batch
);
467 * Return true if the format that will be used to access the resource is
468 * CCS_E-compatible with the resource's linear/non-sRGB format.
470 * Why use the linear format? Well, although the resourcemay be specified
471 * with an sRGB format, the usage of that color space/format can be toggled.
472 * Since our HW tends to support more linear formats than sRGB ones, we use
473 * this format variant for check for CCS_E compatibility.
476 format_ccs_e_compat_with_resource(const struct gen_device_info
*devinfo
,
477 const struct iris_resource
*res
,
478 enum isl_format access_format
)
480 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
);
482 enum isl_format isl_format
= isl_format_srgb_to_linear(res
->surf
.format
);
483 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
487 iris_sample_with_depth_aux(const struct gen_device_info
*devinfo
,
488 const struct iris_resource
*res
)
490 switch (res
->aux
.usage
) {
491 case ISL_AUX_USAGE_HIZ
:
492 if (devinfo
->has_sample_with_hiz
)
495 case ISL_AUX_USAGE_HIZ_CCS
:
497 case ISL_AUX_USAGE_HIZ_CCS_WT
:
503 /* It seems the hardware won't fallback to the depth buffer if some of the
504 * mipmap levels aren't available in the HiZ buffer. So we need all levels
505 * of the texture to be HiZ enabled.
507 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
508 if (!iris_resource_level_has_hiz(res
, level
))
512 /* If compressed multisampling is enabled, then we use it for the auxiliary
515 * From the BDW PRM (Volume 2d: Command Reference: Structures
516 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
518 * "If this field is set to AUX_HIZ, Number of Multisamples must be
519 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
521 * There is no such blurb for 1D textures, but there is sufficient evidence
522 * that this is broken on SKL+.
524 // XXX: i965 disables this for arrays too, is that reasonable?
525 return res
->surf
.samples
== 1 && res
->surf
.dim
== ISL_SURF_DIM_2D
;
529 * Perform a HiZ or depth resolve operation.
531 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
532 * PRM, Volume 1, Part 2:
533 * - 7.5.3.1 Depth Buffer Clear
534 * - 7.5.3.2 Depth Buffer Resolve
535 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
538 iris_hiz_exec(struct iris_context
*ice
,
539 struct iris_batch
*batch
,
540 struct iris_resource
*res
,
541 unsigned int level
, unsigned int start_layer
,
542 unsigned int num_layers
, enum isl_aux_op op
,
543 bool update_clear_depth
)
545 assert(iris_resource_level_has_hiz(res
, level
));
546 assert(op
!= ISL_AUX_OP_NONE
);
547 UNUSED
const char *name
= NULL
;
550 case ISL_AUX_OP_FULL_RESOLVE
:
551 name
= "depth resolve";
553 case ISL_AUX_OP_AMBIGUATE
:
554 name
= "hiz ambiguate";
556 case ISL_AUX_OP_FAST_CLEAR
:
557 name
= "depth clear";
559 case ISL_AUX_OP_PARTIAL_RESOLVE
:
560 case ISL_AUX_OP_NONE
:
561 unreachable("Invalid HiZ op");
564 //DBG("%s %s to mt %p level %d layers %d-%d\n",
565 //__func__, name, mt, level, start_layer, start_layer + num_layers - 1);
567 /* The following stalls and flushes are only documented to be required
568 * for HiZ clear operations. However, they also seem to be required for
569 * resolve operations.
571 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
573 * "If other rendering operations have preceded this clear, a
574 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
575 * enabled must be issued before the rectangle primitive used for
576 * the depth buffer clear operation."
578 * Same applies for Gen8 and Gen9.
580 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
581 * PIPE_CONTROL, Depth Cache Flush Enable:
583 * "This bit must not be set when Depth Stall Enable bit is set in
586 * This is confirmed to hold for real, Haswell gets immediate gpu hangs.
588 * Therefore issue two pipe control flushes, one for cache flush and
589 * another for depth stall.
591 iris_emit_pipe_control_flush(batch
,
592 "hiz op: pre-flushes (1/2)",
593 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
594 PIPE_CONTROL_CS_STALL
);
596 iris_emit_pipe_control_flush(batch
, "hiz op: pre-flushes (2/2)",
597 PIPE_CONTROL_DEPTH_STALL
);
599 assert(isl_aux_usage_has_hiz(res
->aux
.usage
) && res
->aux
.bo
);
601 iris_batch_maybe_flush(batch
, 1500);
603 iris_batch_sync_region_start(batch
);
605 struct blorp_surf surf
;
606 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
, &surf
,
607 &res
->base
, res
->aux
.usage
, level
, true);
609 struct blorp_batch blorp_batch
;
610 enum blorp_batch_flags flags
= 0;
611 flags
|= update_clear_depth
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
612 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, flags
);
613 blorp_hiz_op(&blorp_batch
, &surf
, level
, start_layer
, num_layers
, op
);
614 blorp_batch_finish(&blorp_batch
);
616 /* The following stalls and flushes are only documented to be required
617 * for HiZ clear operations. However, they also seem to be required for
618 * resolve operations.
620 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
622 * "Depth buffer clear pass using any of the methods (WM_STATE,
623 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
624 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
625 * "set" before starting to render. DepthStall and DepthFlush are
626 * not needed between consecutive depth clear passes nor is it
627 * required if the depth clear pass was done with
628 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
630 * TODO: Such as the spec says, this could be conditional.
632 iris_emit_pipe_control_flush(batch
,
633 "hiz op: post flush",
634 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
635 PIPE_CONTROL_DEPTH_STALL
);
637 iris_batch_sync_region_end(batch
);
641 level_has_aux(const struct iris_resource
*res
, uint32_t level
)
643 return isl_aux_usage_has_hiz(res
->aux
.usage
) ?
644 iris_resource_level_has_hiz(res
, level
) :
645 res
->aux
.usage
!= ISL_AUX_USAGE_NONE
;
649 * Does the resource's slice have hiz enabled?
652 iris_resource_level_has_hiz(const struct iris_resource
*res
, uint32_t level
)
654 iris_resource_check_level_layer(res
, level
, 0);
655 return res
->aux
.has_hiz
& 1 << level
;
658 /** \brief Assert that the level and layer are valid for the resource. */
660 iris_resource_check_level_layer(UNUSED
const struct iris_resource
*res
,
661 UNUSED
uint32_t level
, UNUSED
uint32_t layer
)
663 assert(level
< res
->surf
.levels
);
664 assert(layer
< util_num_layers(&res
->base
, level
));
667 static inline uint32_t
668 miptree_level_range_length(const struct iris_resource
*res
,
669 uint32_t start_level
, uint32_t num_levels
)
671 assert(start_level
< res
->surf
.levels
);
673 if (num_levels
== INTEL_REMAINING_LAYERS
)
674 num_levels
= res
->surf
.levels
;
676 /* Check for overflow */
677 assert(start_level
+ num_levels
>= start_level
);
678 assert(start_level
+ num_levels
<= res
->surf
.levels
);
683 static inline uint32_t
684 miptree_layer_range_length(const struct iris_resource
*res
, uint32_t level
,
685 uint32_t start_layer
, uint32_t num_layers
)
687 assert(level
<= res
->base
.last_level
);
689 const uint32_t total_num_layers
= iris_get_num_logical_layers(res
, level
);
690 assert(start_layer
< total_num_layers
);
691 if (num_layers
== INTEL_REMAINING_LAYERS
)
692 num_layers
= total_num_layers
- start_layer
;
693 /* Check for overflow */
694 assert(start_layer
+ num_layers
>= start_layer
);
695 assert(start_layer
+ num_layers
<= total_num_layers
);
701 iris_has_color_unresolved(const struct iris_resource
*res
,
702 unsigned start_level
, unsigned num_levels
,
703 unsigned start_layer
, unsigned num_layers
)
708 /* Clamp the level range to fit the resource */
709 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
711 for (uint32_t l
= 0; l
< num_levels
; l
++) {
712 const uint32_t level
= start_level
+ l
;
713 const uint32_t level_layers
=
714 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
715 for (unsigned a
= 0; a
< level_layers
; a
++) {
716 enum isl_aux_state aux_state
=
717 iris_resource_get_aux_state(res
, level
, start_layer
+ a
);
718 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
719 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
728 iris_resource_prepare_access(struct iris_context
*ice
,
729 struct iris_resource
*res
,
730 uint32_t start_level
, uint32_t num_levels
,
731 uint32_t start_layer
, uint32_t num_layers
,
732 enum isl_aux_usage aux_usage
,
733 bool fast_clear_supported
)
735 /* We can't do resolves on the compute engine, so awkwardly, we have to
736 * do them on the render batch...
738 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
740 const uint32_t clamped_levels
=
741 miptree_level_range_length(res
, start_level
, num_levels
);
742 for (uint32_t l
= 0; l
< clamped_levels
; l
++) {
743 const uint32_t level
= start_level
+ l
;
744 if (!level_has_aux(res
, level
))
747 const uint32_t level_layers
=
748 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
749 for (uint32_t a
= 0; a
< level_layers
; a
++) {
750 const uint32_t layer
= start_layer
+ a
;
751 const enum isl_aux_state aux_state
=
752 iris_resource_get_aux_state(res
, level
, layer
);
753 const enum isl_aux_op aux_op
=
754 isl_aux_prepare_access(aux_state
, aux_usage
, fast_clear_supported
);
756 if (aux_op
== ISL_AUX_OP_NONE
) {
757 /* Nothing to do here. */
758 } else if (isl_aux_usage_has_mcs(res
->aux
.usage
)) {
759 assert(aux_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
760 iris_mcs_partial_resolve(ice
, batch
, res
, layer
, 1);
761 } else if (isl_aux_usage_has_hiz(res
->aux
.usage
)) {
762 iris_hiz_exec(ice
, batch
, res
, level
, layer
, 1, aux_op
, false);
764 assert(isl_aux_usage_has_ccs(res
->aux
.usage
));
765 iris_resolve_color(ice
, batch
, res
, level
, layer
, aux_op
);
768 const enum isl_aux_state new_state
=
769 isl_aux_state_transition_aux_op(aux_state
, res
->aux
.usage
, aux_op
);
770 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1, new_state
);
776 iris_resource_finish_write(struct iris_context
*ice
,
777 struct iris_resource
*res
, uint32_t level
,
778 uint32_t start_layer
, uint32_t num_layers
,
779 enum isl_aux_usage aux_usage
)
781 if (!level_has_aux(res
, level
))
784 const uint32_t level_layers
=
785 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
787 for (uint32_t a
= 0; a
< level_layers
; a
++) {
788 const uint32_t layer
= start_layer
+ a
;
789 const enum isl_aux_state aux_state
=
790 iris_resource_get_aux_state(res
, level
, layer
);
791 const enum isl_aux_state new_aux_state
=
792 isl_aux_state_transition_write(aux_state
, aux_usage
, false);
793 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1, new_aux_state
);
798 iris_resource_get_aux_state(const struct iris_resource
*res
,
799 uint32_t level
, uint32_t layer
)
801 iris_resource_check_level_layer(res
, level
, layer
);
803 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
804 assert(iris_resource_level_has_hiz(res
, level
));
806 assert(res
->surf
.samples
== 1 ||
807 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
810 return res
->aux
.state
[level
][layer
];
814 iris_resource_set_aux_state(struct iris_context
*ice
,
815 struct iris_resource
*res
, uint32_t level
,
816 uint32_t start_layer
, uint32_t num_layers
,
817 enum isl_aux_state aux_state
)
819 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
821 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
822 assert(iris_resource_level_has_hiz(res
, level
));
824 assert(res
->surf
.samples
== 1 ||
825 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
828 for (unsigned a
= 0; a
< num_layers
; a
++) {
829 if (res
->aux
.state
[level
][start_layer
+ a
] != aux_state
) {
830 res
->aux
.state
[level
][start_layer
+ a
] = aux_state
;
831 /* XXX: Need to track which bindings to make dirty */
832 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_BUFFER
;
833 ice
->state
.stage_dirty
|= IRIS_ALL_STAGE_DIRTY_BINDINGS
;
838 /* On Gen9 color buffers may be compressed by the hardware (lossless
839 * compression). There are, however, format restrictions and care needs to be
840 * taken that the sampler engine is capable for re-interpreting a buffer with
841 * format different the buffer was originally written with.
843 * For example, SRGB formats are not compressible and the sampler engine isn't
844 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
845 * color buffer needs to be resolved so that the sampling surface can be
846 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
850 can_texture_with_ccs(const struct gen_device_info
*devinfo
,
851 struct pipe_debug_callback
*dbg
,
852 const struct iris_resource
*res
,
853 enum isl_format view_format
)
855 if (res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
858 if (!format_ccs_e_compat_with_resource(devinfo
, res
, view_format
)) {
859 const struct isl_format_layout
*res_fmtl
=
860 isl_format_get_layout(res
->surf
.format
);
861 const struct isl_format_layout
*view_fmtl
=
862 isl_format_get_layout(view_format
);
864 perf_debug(dbg
, "Incompatible sampling format (%s) for CCS (%s)\n",
865 view_fmtl
->name
, res_fmtl
->name
);
874 iris_resource_texture_aux_usage(struct iris_context
*ice
,
875 const struct iris_resource
*res
,
876 enum isl_format view_format
)
878 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
879 struct gen_device_info
*devinfo
= &screen
->devinfo
;
881 switch (res
->aux
.usage
) {
882 case ISL_AUX_USAGE_HIZ
:
883 if (iris_sample_with_depth_aux(devinfo
, res
))
884 return ISL_AUX_USAGE_HIZ
;
887 case ISL_AUX_USAGE_HIZ_CCS
:
888 assert(!iris_sample_with_depth_aux(devinfo
, res
));
889 return ISL_AUX_USAGE_NONE
;
891 case ISL_AUX_USAGE_HIZ_CCS_WT
:
892 if (iris_sample_with_depth_aux(devinfo
, res
))
893 return ISL_AUX_USAGE_HIZ_CCS_WT
;
896 case ISL_AUX_USAGE_MCS
:
897 case ISL_AUX_USAGE_MCS_CCS
:
898 case ISL_AUX_USAGE_STC_CCS
:
899 return res
->aux
.usage
;
901 case ISL_AUX_USAGE_CCS_D
:
902 case ISL_AUX_USAGE_CCS_E
:
903 /* If we don't have any unresolved color, report an aux usage of
904 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
905 * aux surface and we can save some bandwidth.
907 if (!iris_has_color_unresolved(res
, 0, INTEL_REMAINING_LEVELS
,
908 0, INTEL_REMAINING_LAYERS
))
909 return ISL_AUX_USAGE_NONE
;
911 if (can_texture_with_ccs(devinfo
, &ice
->dbg
, res
, view_format
))
912 return ISL_AUX_USAGE_CCS_E
;
919 return ISL_AUX_USAGE_NONE
;
923 iris_image_view_aux_usage(struct iris_context
*ice
,
924 const struct pipe_image_view
*pview
,
925 const struct shader_info
*info
)
928 return ISL_AUX_USAGE_NONE
;
930 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
931 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
932 struct iris_resource
*res
= (void *) pview
->resource
;
934 enum isl_format view_format
= iris_image_view_get_format(ice
, pview
);
935 enum isl_aux_usage aux_usage
=
936 iris_resource_texture_aux_usage(ice
, res
, view_format
);
938 bool uses_atomic_load_store
=
939 ice
->shaders
.uncompiled
[info
->stage
]->uses_atomic_load_store
;
941 if ((devinfo
->gen
== 12 && aux_usage
== ISL_AUX_USAGE_CCS_E
) &&
942 !uses_atomic_load_store
)
943 return ISL_AUX_USAGE_CCS_E
;
945 return ISL_AUX_USAGE_NONE
;
949 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
951 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
952 * values so sRGB curve application was a no-op for all fast-clearable
955 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
956 * values, the hardware interprets the floats, not as what would be
957 * returned from the sampler (or written by the shader), but as being
958 * between format conversion and sRGB curve application. This means that
959 * we can switch between sRGB and UNORM without having to whack the clear
962 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
966 iris_resource_prepare_texture(struct iris_context
*ice
,
967 struct iris_resource
*res
,
968 enum isl_format view_format
,
969 uint32_t start_level
, uint32_t num_levels
,
970 uint32_t start_layer
, uint32_t num_layers
)
972 enum isl_aux_usage aux_usage
=
973 iris_resource_texture_aux_usage(ice
, res
, view_format
);
975 bool clear_supported
= isl_aux_usage_has_fast_clears(aux_usage
);
977 /* Clear color is specified as ints or floats and the conversion is done by
978 * the sampler. If we have a texture view, we would have to perform the
979 * clear color conversion manually. Just disable clear color.
981 if (!isl_formats_are_fast_clear_compatible(res
->surf
.format
, view_format
))
982 clear_supported
= false;
984 iris_resource_prepare_access(ice
, res
, start_level
, num_levels
,
985 start_layer
, num_layers
,
986 aux_usage
, clear_supported
);
990 iris_resource_render_aux_usage(struct iris_context
*ice
,
991 struct iris_resource
*res
,
992 enum isl_format render_format
,
994 bool draw_aux_disabled
)
996 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
997 struct gen_device_info
*devinfo
= &screen
->devinfo
;
999 if (draw_aux_disabled
)
1000 return ISL_AUX_USAGE_NONE
;
1002 switch (res
->aux
.usage
) {
1003 case ISL_AUX_USAGE_MCS
:
1004 case ISL_AUX_USAGE_MCS_CCS
:
1005 return res
->aux
.usage
;
1007 case ISL_AUX_USAGE_CCS_D
:
1008 case ISL_AUX_USAGE_CCS_E
:
1009 /* Gen9+ hardware technically supports non-0/1 clear colors with sRGB
1010 * formats. However, there are issues with blending where it doesn't
1011 * properly apply the sRGB curve to the clear color when blending.
1013 if (devinfo
->gen
>= 9 && blend_enabled
&&
1014 isl_format_is_srgb(render_format
) &&
1015 !isl_color_value_is_zero_one(res
->aux
.clear_color
, render_format
))
1016 return ISL_AUX_USAGE_NONE
;
1018 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
&&
1019 format_ccs_e_compat_with_resource(devinfo
, res
, render_format
))
1020 return ISL_AUX_USAGE_CCS_E
;
1022 /* Otherwise, we try to fall back to CCS_D */
1023 if (isl_format_supports_ccs_d(devinfo
, render_format
))
1024 return ISL_AUX_USAGE_CCS_D
;
1027 return ISL_AUX_USAGE_NONE
;
1032 iris_resource_prepare_render(struct iris_context
*ice
,
1033 struct iris_batch
*batch
,
1034 struct iris_resource
*res
, uint32_t level
,
1035 uint32_t start_layer
, uint32_t layer_count
,
1036 enum isl_aux_usage aux_usage
)
1038 iris_resource_prepare_access(ice
, res
, level
, 1, start_layer
,
1039 layer_count
, aux_usage
,
1040 isl_aux_usage_has_fast_clears(aux_usage
));
1044 iris_resource_finish_render(struct iris_context
*ice
,
1045 struct iris_resource
*res
, uint32_t level
,
1046 uint32_t start_layer
, uint32_t layer_count
,
1047 enum isl_aux_usage aux_usage
)
1049 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,
1054 iris_resource_prepare_depth(struct iris_context
*ice
,
1055 struct iris_batch
*batch
,
1056 struct iris_resource
*res
, uint32_t level
,
1057 uint32_t start_layer
, uint32_t layer_count
)
1059 iris_resource_prepare_access(ice
, res
, level
, 1, start_layer
,
1060 layer_count
, res
->aux
.usage
, !!res
->aux
.bo
);
1064 iris_resource_finish_depth(struct iris_context
*ice
,
1065 struct iris_resource
*res
, uint32_t level
,
1066 uint32_t start_layer
, uint32_t layer_count
,
1069 if (depth_written
) {
1070 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,