2 * Copyright © 2017 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
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15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resolve.c
26 * This file handles resolve tracking for main and auxiliary surfaces.
28 * It also handles our cache tracking. We have sets for the render cache,
29 * depth cache, and so on. If a BO is in a cache's set, then it may have
30 * data in that cache. The helpers take care of emitting flushes for
31 * render-to-texture, format reinterpretation issues, and other situations.
34 #include "util/hash_table.h"
36 #include "iris_context.h"
37 #include "compiler/nir/nir.h"
40 * Disable auxiliary buffers if a renderbuffer is also bound as a texture
41 * or shader image. This causes a self-dependency, where both rendering
42 * and sampling may concurrently read or write the CCS buffer, causing
46 disable_rb_aux_buffer(struct iris_context
*ice
,
47 bool *draw_aux_buffer_disabled
,
48 struct iris_resource
*tex_res
,
49 unsigned min_level
, unsigned num_levels
,
52 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
55 /* We only need to worry about color compression and fast clears. */
56 if (tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
&&
57 tex_res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
60 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
61 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
65 struct iris_resource
*rb_res
= (void *) surf
->base
.texture
;
67 if (rb_res
->bo
== tex_res
->bo
&&
68 surf
->base
.u
.tex
.level
>= min_level
&&
69 surf
->base
.u
.tex
.level
< min_level
+ num_levels
) {
70 found
= draw_aux_buffer_disabled
[i
] = true;
76 "Disabling CCS because a renderbuffer is also bound %s.\n",
84 resolve_sampler_views(struct iris_context
*ice
,
85 struct iris_batch
*batch
,
86 struct iris_shader_state
*shs
,
87 const struct shader_info
*info
,
88 bool *draw_aux_buffer_disabled
,
89 bool consider_framebuffer
)
91 uint32_t views
= info
? (shs
->bound_sampler_views
& info
->textures_used
) : 0;
94 const int i
= u_bit_scan(&views
);
95 struct iris_sampler_view
*isv
= shs
->textures
[i
];
96 struct iris_resource
*res
= (void *) isv
->base
.texture
;
98 if (res
->base
.target
!= PIPE_BUFFER
) {
99 if (consider_framebuffer
) {
100 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
101 res
, isv
->view
.base_level
, isv
->view
.levels
,
105 iris_resource_prepare_texture(ice
, res
, isv
->view
.format
,
106 isv
->view
.base_level
, isv
->view
.levels
,
107 isv
->view
.base_array_layer
,
108 isv
->view
.array_len
);
111 iris_emit_buffer_barrier_for(batch
, res
->bo
, IRIS_DOMAIN_OTHER_READ
);
116 resolve_image_views(struct iris_context
*ice
,
117 struct iris_batch
*batch
,
118 struct iris_shader_state
*shs
,
119 const struct shader_info
*info
,
120 bool *draw_aux_buffer_disabled
,
121 bool consider_framebuffer
)
123 uint32_t views
= info
? (shs
->bound_image_views
& info
->images_used
) : 0;
126 const int i
= u_bit_scan(&views
);
127 struct pipe_image_view
*pview
= &shs
->image
[i
].base
;
128 struct iris_resource
*res
= (void *) pview
->resource
;
130 if (res
->base
.target
!= PIPE_BUFFER
) {
131 if (consider_framebuffer
) {
132 disable_rb_aux_buffer(ice
, draw_aux_buffer_disabled
,
133 res
, pview
->u
.tex
.level
, 1,
134 "as a shader image");
137 unsigned num_layers
=
138 pview
->u
.tex
.last_layer
- pview
->u
.tex
.first_layer
+ 1;
140 enum isl_aux_usage aux_usage
=
141 iris_image_view_aux_usage(ice
, pview
, info
);
143 iris_resource_prepare_access(ice
, res
,
144 pview
->u
.tex
.level
, 1,
145 pview
->u
.tex
.first_layer
, num_layers
,
149 iris_emit_buffer_barrier_for(batch
, res
->bo
, IRIS_DOMAIN_OTHER_READ
);
155 * \brief Resolve buffers before drawing.
157 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
158 * enabled depth texture, and flush the render cache for any dirty textures.
161 iris_predraw_resolve_inputs(struct iris_context
*ice
,
162 struct iris_batch
*batch
,
163 bool *draw_aux_buffer_disabled
,
164 gl_shader_stage stage
,
165 bool consider_framebuffer
)
167 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
168 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
170 uint64_t stage_dirty
= (IRIS_STAGE_DIRTY_BINDINGS_VS
<< stage
) |
171 (consider_framebuffer
? IRIS_STAGE_DIRTY_BINDINGS_FS
: 0);
173 if (ice
->state
.stage_dirty
& stage_dirty
) {
174 resolve_sampler_views(ice
, batch
, shs
, info
, draw_aux_buffer_disabled
,
175 consider_framebuffer
);
176 resolve_image_views(ice
, batch
, shs
, info
, draw_aux_buffer_disabled
,
177 consider_framebuffer
);
182 iris_predraw_resolve_framebuffer(struct iris_context
*ice
,
183 struct iris_batch
*batch
,
184 bool *draw_aux_buffer_disabled
)
186 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
187 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
188 struct gen_device_info
*devinfo
= &screen
->devinfo
;
189 struct iris_uncompiled_shader
*ish
=
190 ice
->shaders
.uncompiled
[MESA_SHADER_FRAGMENT
];
191 const nir_shader
*nir
= ish
->nir
;
193 if (ice
->state
.dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
194 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
197 struct iris_resource
*z_res
, *s_res
;
198 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
199 unsigned num_layers
=
200 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
203 iris_resource_prepare_depth(ice
, batch
, z_res
,
204 zs_surf
->u
.tex
.level
,
205 zs_surf
->u
.tex
.first_layer
,
207 iris_emit_buffer_barrier_for(batch
, z_res
->bo
,
208 IRIS_DOMAIN_DEPTH_WRITE
);
212 iris_emit_buffer_barrier_for(batch
, s_res
->bo
,
213 IRIS_DOMAIN_DEPTH_WRITE
);
218 if (devinfo
->gen
== 8 && nir
->info
.outputs_read
!= 0) {
219 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
220 if (cso_fb
->cbufs
[i
]) {
221 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
222 struct iris_resource
*res
= (void *) cso_fb
->cbufs
[i
]->texture
;
224 iris_resource_prepare_texture(ice
, res
, surf
->view
.format
,
225 surf
->view
.base_level
, 1,
226 surf
->view
.base_array_layer
,
227 surf
->view
.array_len
);
232 if ((ice
->state
.dirty
& IRIS_DIRTY_BLEND_STATE
) ||
233 (ice
->state
.stage_dirty
& IRIS_STAGE_DIRTY_BINDINGS_FS
)) {
234 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
235 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
239 struct iris_resource
*res
= (void *) surf
->base
.texture
;
241 enum isl_aux_usage aux_usage
=
242 iris_resource_render_aux_usage(ice
, res
, surf
->view
.format
,
243 ice
->state
.blend_enables
& (1u << i
),
244 draw_aux_buffer_disabled
[i
]);
246 if (ice
->state
.draw_aux_usage
[i
] != aux_usage
) {
247 ice
->state
.draw_aux_usage
[i
] = aux_usage
;
248 /* XXX: Need to track which bindings to make dirty */
249 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_BUFFER
;
250 ice
->state
.stage_dirty
|= IRIS_ALL_STAGE_DIRTY_BINDINGS
;
253 iris_resource_prepare_render(ice
, batch
, res
, surf
->view
.base_level
,
254 surf
->view
.base_array_layer
,
255 surf
->view
.array_len
,
258 iris_cache_flush_for_render(batch
, res
->bo
, surf
->view
.format
,
265 * \brief Call this after drawing to mark which buffers need resolving
267 * If the depth buffer was written to and if it has an accompanying HiZ
268 * buffer, then mark that it needs a depth resolve.
270 * If the color buffer is a multisample window system buffer, then
271 * mark that it needs a downsample.
273 * Also mark any render targets which will be textured as needing a render
277 iris_postdraw_update_resolve_tracking(struct iris_context
*ice
,
278 struct iris_batch
*batch
)
280 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
282 // XXX: front buffer drawing?
284 bool may_have_resolved_depth
=
285 ice
->state
.dirty
& (IRIS_DIRTY_DEPTH_BUFFER
|
286 IRIS_DIRTY_WM_DEPTH_STENCIL
);
288 struct pipe_surface
*zs_surf
= cso_fb
->zsbuf
;
290 struct iris_resource
*z_res
, *s_res
;
291 iris_get_depth_stencil_resources(zs_surf
->texture
, &z_res
, &s_res
);
292 unsigned num_layers
=
293 zs_surf
->u
.tex
.last_layer
- zs_surf
->u
.tex
.first_layer
+ 1;
296 if (may_have_resolved_depth
) {
297 iris_resource_finish_depth(ice
, z_res
, zs_surf
->u
.tex
.level
,
298 zs_surf
->u
.tex
.first_layer
, num_layers
,
299 ice
->state
.depth_writes_enabled
);
304 if (may_have_resolved_depth
&& ice
->state
.stencil_writes_enabled
) {
305 iris_resource_finish_write(ice
, s_res
, zs_surf
->u
.tex
.level
,
306 zs_surf
->u
.tex
.first_layer
, num_layers
,
312 bool may_have_resolved_color
=
313 (ice
->state
.dirty
& IRIS_DIRTY_BLEND_STATE
) ||
314 (ice
->state
.stage_dirty
& IRIS_STAGE_DIRTY_BINDINGS_FS
);
316 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
317 struct iris_surface
*surf
= (void *) cso_fb
->cbufs
[i
];
321 struct iris_resource
*res
= (void *) surf
->base
.texture
;
322 enum isl_aux_usage aux_usage
= ice
->state
.draw_aux_usage
[i
];
324 if (may_have_resolved_color
) {
325 union pipe_surface_desc
*desc
= &surf
->base
.u
;
326 unsigned num_layers
=
327 desc
->tex
.last_layer
- desc
->tex
.first_layer
+ 1;
328 iris_resource_finish_render(ice
, res
, desc
->tex
.level
,
329 desc
->tex
.first_layer
, num_layers
,
336 * Emits an appropriate flush for a BO if it has been rendered to within the
337 * same batchbuffer as a read that's about to be emitted.
339 * The GPU has separate, incoherent caches for the render cache and the
340 * sampler cache, along with other caches. Usually data in the different
341 * caches don't interact (e.g. we don't render to our driver-generated
342 * immediate constant data), but for render-to-texture in FBOs we definitely
343 * do. When a batchbuffer is flushed, the kernel will ensure that everything
344 * necessary is flushed before another use of that BO, but for reuse from
345 * different caches within a batchbuffer, it's all our responsibility.
348 iris_flush_depth_and_render_caches(struct iris_batch
*batch
)
350 iris_emit_pipe_control_flush(batch
,
351 "cache tracker: render-to-texture",
352 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
353 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
354 PIPE_CONTROL_CS_STALL
);
356 iris_emit_pipe_control_flush(batch
,
357 "cache tracker: render-to-texture",
358 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
359 PIPE_CONTROL_CONST_CACHE_INVALIDATE
);
363 format_aux_tuple(enum isl_format format
, enum isl_aux_usage aux_usage
)
365 return (void *)(uintptr_t)((uint32_t)format
<< 8 | aux_usage
);
369 iris_cache_flush_for_render(struct iris_batch
*batch
,
371 enum isl_format format
,
372 enum isl_aux_usage aux_usage
)
374 iris_emit_buffer_barrier_for(batch
, bo
, IRIS_DOMAIN_RENDER_WRITE
);
376 /* Check to see if this bo has been used by a previous rendering operation
377 * but with a different format or aux usage. If it has, flush the render
378 * cache so we ensure that it's only in there with one format or aux usage
381 * Even though it's not obvious, this can easily happen in practice.
382 * Suppose a client is blending on a surface with sRGB encode enabled on
383 * gen9. This implies that you get AUX_USAGE_CCS_D at best. If the client
384 * then disables sRGB decode and continues blending we will flip on
385 * AUX_USAGE_CCS_E without doing any sort of resolve in-between (this is
386 * perfectly valid since CCS_E is a subset of CCS_D). However, this means
387 * that we have fragments in-flight which are rendering with UNORM+CCS_E
388 * and other fragments in-flight with SRGB+CCS_D on the same surface at the
389 * same time and the pixel scoreboard and color blender are trying to sort
390 * it all out. This ends badly (i.e. GPU hangs).
392 * To date, we have never observed GPU hangs or even corruption to be
393 * associated with switching the format, only the aux usage. However,
394 * there are comments in various docs which indicate that the render cache
395 * isn't 100% resilient to format changes. We may as well be conservative
396 * and flush on format changes too. We can always relax this later if we
397 * find it to be a performance problem.
399 struct hash_entry
*entry
=
400 _mesa_hash_table_search_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
);
402 _mesa_hash_table_insert_pre_hashed(batch
->cache
.render
, bo
->hash
, bo
,
403 format_aux_tuple(format
, aux_usage
));
404 } else if (entry
->data
!= format_aux_tuple(format
, aux_usage
)) {
405 iris_emit_pipe_control_flush(batch
,
406 "cache tracker: render format mismatch",
407 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
408 PIPE_CONTROL_CS_STALL
);
409 entry
->data
= format_aux_tuple(format
, aux_usage
);
414 iris_resolve_color(struct iris_context
*ice
,
415 struct iris_batch
*batch
,
416 struct iris_resource
*res
,
417 unsigned level
, unsigned layer
,
418 enum isl_aux_op resolve_op
)
420 //DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer);
422 struct blorp_surf surf
;
423 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
, &surf
,
424 &res
->base
, res
->aux
.usage
, level
, true);
426 iris_batch_maybe_flush(batch
, 1500);
428 /* Ivybridge PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
430 * "Any transition from any value in {Clear, Render, Resolve} to a
431 * different value in {Clear, Render, Resolve} requires end of pipe
434 * In other words, fast clear ops are not properly synchronized with
435 * other drawing. We need to use a PIPE_CONTROL to ensure that the
436 * contents of the previous draw hit the render target before we resolve
437 * and again afterwards to ensure that the resolve is complete before we
438 * do any more regular drawing.
440 iris_emit_end_of_pipe_sync(batch
, "color resolve: pre-flush",
441 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
443 iris_batch_sync_region_start(batch
);
444 struct blorp_batch blorp_batch
;
445 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
446 /* On Gen >= 12, Stencil buffer with lossless compression needs to be
447 * resolve with WM_HZ_OP packet.
449 if (res
->aux
.usage
== ISL_AUX_USAGE_STC_CCS
) {
450 blorp_hiz_stencil_op(&blorp_batch
, &surf
, level
, layer
,
453 blorp_ccs_resolve(&blorp_batch
, &surf
, level
, layer
, 1,
454 isl_format_srgb_to_linear(res
->surf
.format
),
457 blorp_batch_finish(&blorp_batch
);
459 /* See comment above */
460 iris_emit_end_of_pipe_sync(batch
, "color resolve: post-flush",
461 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
462 iris_batch_sync_region_end(batch
);
466 iris_mcs_partial_resolve(struct iris_context
*ice
,
467 struct iris_batch
*batch
,
468 struct iris_resource
*res
,
469 uint32_t start_layer
,
472 //DBG("%s to mt %p layers %u-%u\n", __FUNCTION__, mt,
473 //start_layer, start_layer + num_layers - 1);
475 assert(isl_aux_usage_has_mcs(res
->aux
.usage
));
477 struct blorp_surf surf
;
478 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
, &surf
,
479 &res
->base
, res
->aux
.usage
, 0, true);
481 struct blorp_batch blorp_batch
;
482 iris_batch_sync_region_start(batch
);
483 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, 0);
484 blorp_mcs_partial_resolve(&blorp_batch
, &surf
,
485 isl_format_srgb_to_linear(res
->surf
.format
),
486 start_layer
, num_layers
);
487 blorp_batch_finish(&blorp_batch
);
488 iris_batch_sync_region_end(batch
);
493 * Return true if the format that will be used to access the resource is
494 * CCS_E-compatible with the resource's linear/non-sRGB format.
496 * Why use the linear format? Well, although the resourcemay be specified
497 * with an sRGB format, the usage of that color space/format can be toggled.
498 * Since our HW tends to support more linear formats than sRGB ones, we use
499 * this format variant for check for CCS_E compatibility.
502 format_ccs_e_compat_with_resource(const struct gen_device_info
*devinfo
,
503 const struct iris_resource
*res
,
504 enum isl_format access_format
)
506 assert(res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
);
508 enum isl_format isl_format
= isl_format_srgb_to_linear(res
->surf
.format
);
509 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
513 iris_sample_with_depth_aux(const struct gen_device_info
*devinfo
,
514 const struct iris_resource
*res
)
516 switch (res
->aux
.usage
) {
517 case ISL_AUX_USAGE_HIZ
:
518 if (devinfo
->has_sample_with_hiz
)
521 case ISL_AUX_USAGE_HIZ_CCS
:
523 case ISL_AUX_USAGE_HIZ_CCS_WT
:
529 /* It seems the hardware won't fallback to the depth buffer if some of the
530 * mipmap levels aren't available in the HiZ buffer. So we need all levels
531 * of the texture to be HiZ enabled.
533 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
534 if (!iris_resource_level_has_hiz(res
, level
))
538 /* If compressed multisampling is enabled, then we use it for the auxiliary
541 * From the BDW PRM (Volume 2d: Command Reference: Structures
542 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
544 * "If this field is set to AUX_HIZ, Number of Multisamples must be
545 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
547 * There is no such blurb for 1D textures, but there is sufficient evidence
548 * that this is broken on SKL+.
550 // XXX: i965 disables this for arrays too, is that reasonable?
551 return res
->surf
.samples
== 1 && res
->surf
.dim
== ISL_SURF_DIM_2D
;
555 * Perform a HiZ or depth resolve operation.
557 * For an overview of HiZ ops, see the following sections of the Sandy Bridge
558 * PRM, Volume 1, Part 2:
559 * - 7.5.3.1 Depth Buffer Clear
560 * - 7.5.3.2 Depth Buffer Resolve
561 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
564 iris_hiz_exec(struct iris_context
*ice
,
565 struct iris_batch
*batch
,
566 struct iris_resource
*res
,
567 unsigned int level
, unsigned int start_layer
,
568 unsigned int num_layers
, enum isl_aux_op op
,
569 bool update_clear_depth
)
571 assert(iris_resource_level_has_hiz(res
, level
));
572 assert(op
!= ISL_AUX_OP_NONE
);
573 UNUSED
const char *name
= NULL
;
576 case ISL_AUX_OP_FULL_RESOLVE
:
577 name
= "depth resolve";
579 case ISL_AUX_OP_AMBIGUATE
:
580 name
= "hiz ambiguate";
582 case ISL_AUX_OP_FAST_CLEAR
:
583 name
= "depth clear";
585 case ISL_AUX_OP_PARTIAL_RESOLVE
:
586 case ISL_AUX_OP_NONE
:
587 unreachable("Invalid HiZ op");
590 //DBG("%s %s to mt %p level %d layers %d-%d\n",
591 //__func__, name, mt, level, start_layer, start_layer + num_layers - 1);
593 /* The following stalls and flushes are only documented to be required
594 * for HiZ clear operations. However, they also seem to be required for
595 * resolve operations.
597 * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
599 * "If other rendering operations have preceded this clear, a
600 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
601 * enabled must be issued before the rectangle primitive used for
602 * the depth buffer clear operation."
604 * Same applies for Gen8 and Gen9.
606 * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1
607 * PIPE_CONTROL, Depth Cache Flush Enable:
609 * "This bit must not be set when Depth Stall Enable bit is set in
612 * This is confirmed to hold for real, Haswell gets immediate gpu hangs.
614 * Therefore issue two pipe control flushes, one for cache flush and
615 * another for depth stall.
617 iris_emit_pipe_control_flush(batch
,
618 "hiz op: pre-flushes (1/2)",
619 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
620 PIPE_CONTROL_CS_STALL
);
622 iris_emit_pipe_control_flush(batch
, "hiz op: pre-flushes (2/2)",
623 PIPE_CONTROL_DEPTH_STALL
);
625 assert(isl_aux_usage_has_hiz(res
->aux
.usage
) && res
->aux
.bo
);
627 iris_batch_maybe_flush(batch
, 1500);
629 iris_batch_sync_region_start(batch
);
631 struct blorp_surf surf
;
632 iris_blorp_surf_for_resource(&batch
->screen
->isl_dev
, &surf
,
633 &res
->base
, res
->aux
.usage
, level
, true);
635 struct blorp_batch blorp_batch
;
636 enum blorp_batch_flags flags
= 0;
637 flags
|= update_clear_depth
? 0 : BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
;
638 blorp_batch_init(&ice
->blorp
, &blorp_batch
, batch
, flags
);
639 blorp_hiz_op(&blorp_batch
, &surf
, level
, start_layer
, num_layers
, op
);
640 blorp_batch_finish(&blorp_batch
);
642 /* The following stalls and flushes are only documented to be required
643 * for HiZ clear operations. However, they also seem to be required for
644 * resolve operations.
646 * From the Broadwell PRM, volume 7, "Depth Buffer Clear":
648 * "Depth buffer clear pass using any of the methods (WM_STATE,
649 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
650 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
651 * "set" before starting to render. DepthStall and DepthFlush are
652 * not needed between consecutive depth clear passes nor is it
653 * required if the depth clear pass was done with
654 * 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
656 * TODO: Such as the spec says, this could be conditional.
658 iris_emit_pipe_control_flush(batch
,
659 "hiz op: post flush",
660 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
661 PIPE_CONTROL_DEPTH_STALL
);
663 iris_batch_sync_region_end(batch
);
667 level_has_aux(const struct iris_resource
*res
, uint32_t level
)
669 return isl_aux_usage_has_hiz(res
->aux
.usage
) ?
670 iris_resource_level_has_hiz(res
, level
) :
671 res
->aux
.usage
!= ISL_AUX_USAGE_NONE
;
675 * Does the resource's slice have hiz enabled?
678 iris_resource_level_has_hiz(const struct iris_resource
*res
, uint32_t level
)
680 iris_resource_check_level_layer(res
, level
, 0);
681 return res
->aux
.has_hiz
& 1 << level
;
684 /** \brief Assert that the level and layer are valid for the resource. */
686 iris_resource_check_level_layer(UNUSED
const struct iris_resource
*res
,
687 UNUSED
uint32_t level
, UNUSED
uint32_t layer
)
689 assert(level
< res
->surf
.levels
);
690 assert(layer
< util_num_layers(&res
->base
, level
));
693 static inline uint32_t
694 miptree_level_range_length(const struct iris_resource
*res
,
695 uint32_t start_level
, uint32_t num_levels
)
697 assert(start_level
< res
->surf
.levels
);
699 if (num_levels
== INTEL_REMAINING_LAYERS
)
700 num_levels
= res
->surf
.levels
;
702 /* Check for overflow */
703 assert(start_level
+ num_levels
>= start_level
);
704 assert(start_level
+ num_levels
<= res
->surf
.levels
);
709 static inline uint32_t
710 miptree_layer_range_length(const struct iris_resource
*res
, uint32_t level
,
711 uint32_t start_layer
, uint32_t num_layers
)
713 assert(level
<= res
->base
.last_level
);
715 const uint32_t total_num_layers
= iris_get_num_logical_layers(res
, level
);
716 assert(start_layer
< total_num_layers
);
717 if (num_layers
== INTEL_REMAINING_LAYERS
)
718 num_layers
= total_num_layers
- start_layer
;
719 /* Check for overflow */
720 assert(start_layer
+ num_layers
>= start_layer
);
721 assert(start_layer
+ num_layers
<= total_num_layers
);
727 iris_has_color_unresolved(const struct iris_resource
*res
,
728 unsigned start_level
, unsigned num_levels
,
729 unsigned start_layer
, unsigned num_layers
)
734 /* Clamp the level range to fit the resource */
735 num_levels
= miptree_level_range_length(res
, start_level
, num_levels
);
737 for (uint32_t l
= 0; l
< num_levels
; l
++) {
738 const uint32_t level
= start_level
+ l
;
739 const uint32_t level_layers
=
740 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
741 for (unsigned a
= 0; a
< level_layers
; a
++) {
742 enum isl_aux_state aux_state
=
743 iris_resource_get_aux_state(res
, level
, start_layer
+ a
);
744 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
745 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
754 iris_resource_prepare_access(struct iris_context
*ice
,
755 struct iris_resource
*res
,
756 uint32_t start_level
, uint32_t num_levels
,
757 uint32_t start_layer
, uint32_t num_layers
,
758 enum isl_aux_usage aux_usage
,
759 bool fast_clear_supported
)
761 /* We can't do resolves on the compute engine, so awkwardly, we have to
762 * do them on the render batch...
764 struct iris_batch
*batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
766 const uint32_t clamped_levels
=
767 miptree_level_range_length(res
, start_level
, num_levels
);
768 for (uint32_t l
= 0; l
< clamped_levels
; l
++) {
769 const uint32_t level
= start_level
+ l
;
770 if (!level_has_aux(res
, level
))
773 const uint32_t level_layers
=
774 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
775 for (uint32_t a
= 0; a
< level_layers
; a
++) {
776 const uint32_t layer
= start_layer
+ a
;
777 const enum isl_aux_state aux_state
=
778 iris_resource_get_aux_state(res
, level
, layer
);
779 const enum isl_aux_op aux_op
=
780 isl_aux_prepare_access(aux_state
, aux_usage
, fast_clear_supported
);
782 if (aux_op
== ISL_AUX_OP_NONE
) {
783 /* Nothing to do here. */
784 } else if (isl_aux_usage_has_mcs(res
->aux
.usage
)) {
785 assert(aux_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
786 iris_mcs_partial_resolve(ice
, batch
, res
, layer
, 1);
787 } else if (isl_aux_usage_has_hiz(res
->aux
.usage
)) {
788 iris_hiz_exec(ice
, batch
, res
, level
, layer
, 1, aux_op
, false);
790 assert(isl_aux_usage_has_ccs(res
->aux
.usage
));
791 iris_resolve_color(ice
, batch
, res
, level
, layer
, aux_op
);
794 const enum isl_aux_state new_state
=
795 isl_aux_state_transition_aux_op(aux_state
, res
->aux
.usage
, aux_op
);
796 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1, new_state
);
802 iris_resource_finish_write(struct iris_context
*ice
,
803 struct iris_resource
*res
, uint32_t level
,
804 uint32_t start_layer
, uint32_t num_layers
,
805 enum isl_aux_usage aux_usage
)
807 if (!level_has_aux(res
, level
))
810 const uint32_t level_layers
=
811 miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
813 for (uint32_t a
= 0; a
< level_layers
; a
++) {
814 const uint32_t layer
= start_layer
+ a
;
815 const enum isl_aux_state aux_state
=
816 iris_resource_get_aux_state(res
, level
, layer
);
817 const enum isl_aux_state new_aux_state
=
818 isl_aux_state_transition_write(aux_state
, aux_usage
, false);
819 iris_resource_set_aux_state(ice
, res
, level
, layer
, 1, new_aux_state
);
824 iris_resource_get_aux_state(const struct iris_resource
*res
,
825 uint32_t level
, uint32_t layer
)
827 iris_resource_check_level_layer(res
, level
, layer
);
829 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
830 assert(iris_resource_level_has_hiz(res
, level
));
832 assert(res
->surf
.samples
== 1 ||
833 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
836 return res
->aux
.state
[level
][layer
];
840 iris_resource_set_aux_state(struct iris_context
*ice
,
841 struct iris_resource
*res
, uint32_t level
,
842 uint32_t start_layer
, uint32_t num_layers
,
843 enum isl_aux_state aux_state
)
845 num_layers
= miptree_layer_range_length(res
, level
, start_layer
, num_layers
);
847 if (res
->surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) {
848 assert(iris_resource_level_has_hiz(res
, level
));
850 assert(res
->surf
.samples
== 1 ||
851 res
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
854 for (unsigned a
= 0; a
< num_layers
; a
++) {
855 if (res
->aux
.state
[level
][start_layer
+ a
] != aux_state
) {
856 res
->aux
.state
[level
][start_layer
+ a
] = aux_state
;
857 /* XXX: Need to track which bindings to make dirty */
858 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_BUFFER
;
859 ice
->state
.stage_dirty
|= IRIS_ALL_STAGE_DIRTY_BINDINGS
;
864 /* On Gen9 color buffers may be compressed by the hardware (lossless
865 * compression). There are, however, format restrictions and care needs to be
866 * taken that the sampler engine is capable for re-interpreting a buffer with
867 * format different the buffer was originally written with.
869 * For example, SRGB formats are not compressible and the sampler engine isn't
870 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
871 * color buffer needs to be resolved so that the sampling surface can be
872 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
876 can_texture_with_ccs(const struct gen_device_info
*devinfo
,
877 struct pipe_debug_callback
*dbg
,
878 const struct iris_resource
*res
,
879 enum isl_format view_format
)
881 if (res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
)
884 if (!format_ccs_e_compat_with_resource(devinfo
, res
, view_format
)) {
885 const struct isl_format_layout
*res_fmtl
=
886 isl_format_get_layout(res
->surf
.format
);
887 const struct isl_format_layout
*view_fmtl
=
888 isl_format_get_layout(view_format
);
890 perf_debug(dbg
, "Incompatible sampling format (%s) for CCS (%s)\n",
891 view_fmtl
->name
, res_fmtl
->name
);
900 iris_resource_texture_aux_usage(struct iris_context
*ice
,
901 const struct iris_resource
*res
,
902 enum isl_format view_format
)
904 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
905 struct gen_device_info
*devinfo
= &screen
->devinfo
;
907 switch (res
->aux
.usage
) {
908 case ISL_AUX_USAGE_HIZ
:
909 if (iris_sample_with_depth_aux(devinfo
, res
))
910 return ISL_AUX_USAGE_HIZ
;
913 case ISL_AUX_USAGE_HIZ_CCS
:
914 assert(!iris_sample_with_depth_aux(devinfo
, res
));
915 return ISL_AUX_USAGE_NONE
;
917 case ISL_AUX_USAGE_HIZ_CCS_WT
:
918 if (iris_sample_with_depth_aux(devinfo
, res
))
919 return ISL_AUX_USAGE_HIZ_CCS_WT
;
922 case ISL_AUX_USAGE_MCS
:
923 case ISL_AUX_USAGE_MCS_CCS
:
924 case ISL_AUX_USAGE_STC_CCS
:
925 return res
->aux
.usage
;
927 case ISL_AUX_USAGE_CCS_D
:
928 case ISL_AUX_USAGE_CCS_E
:
929 /* If we don't have any unresolved color, report an aux usage of
930 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
931 * aux surface and we can save some bandwidth.
933 if (!iris_has_color_unresolved(res
, 0, INTEL_REMAINING_LEVELS
,
934 0, INTEL_REMAINING_LAYERS
))
935 return ISL_AUX_USAGE_NONE
;
937 if (can_texture_with_ccs(devinfo
, &ice
->dbg
, res
, view_format
))
938 return ISL_AUX_USAGE_CCS_E
;
945 return ISL_AUX_USAGE_NONE
;
949 iris_image_view_aux_usage(struct iris_context
*ice
,
950 const struct pipe_image_view
*pview
,
951 const struct shader_info
*info
)
954 return ISL_AUX_USAGE_NONE
;
956 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
957 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
958 struct iris_resource
*res
= (void *) pview
->resource
;
960 enum isl_format view_format
= iris_image_view_get_format(ice
, pview
);
961 enum isl_aux_usage aux_usage
=
962 iris_resource_texture_aux_usage(ice
, res
, view_format
);
964 bool uses_atomic_load_store
=
965 ice
->shaders
.uncompiled
[info
->stage
]->uses_atomic_load_store
;
967 if ((devinfo
->gen
== 12 && aux_usage
== ISL_AUX_USAGE_CCS_E
) &&
968 !uses_atomic_load_store
)
969 return ISL_AUX_USAGE_CCS_E
;
971 return ISL_AUX_USAGE_NONE
;
975 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
977 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
978 * values so sRGB curve application was a no-op for all fast-clearable
981 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
982 * values, the hardware interprets the floats, not as what would be
983 * returned from the sampler (or written by the shader), but as being
984 * between format conversion and sRGB curve application. This means that
985 * we can switch between sRGB and UNORM without having to whack the clear
988 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
992 iris_resource_prepare_texture(struct iris_context
*ice
,
993 struct iris_resource
*res
,
994 enum isl_format view_format
,
995 uint32_t start_level
, uint32_t num_levels
,
996 uint32_t start_layer
, uint32_t num_layers
)
998 enum isl_aux_usage aux_usage
=
999 iris_resource_texture_aux_usage(ice
, res
, view_format
);
1001 bool clear_supported
= isl_aux_usage_has_fast_clears(aux_usage
);
1003 /* Clear color is specified as ints or floats and the conversion is done by
1004 * the sampler. If we have a texture view, we would have to perform the
1005 * clear color conversion manually. Just disable clear color.
1007 if (!isl_formats_are_fast_clear_compatible(res
->surf
.format
, view_format
))
1008 clear_supported
= false;
1010 iris_resource_prepare_access(ice
, res
, start_level
, num_levels
,
1011 start_layer
, num_layers
,
1012 aux_usage
, clear_supported
);
1016 iris_resource_render_aux_usage(struct iris_context
*ice
,
1017 struct iris_resource
*res
,
1018 enum isl_format render_format
,
1020 bool draw_aux_disabled
)
1022 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
1023 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1025 if (draw_aux_disabled
)
1026 return ISL_AUX_USAGE_NONE
;
1028 switch (res
->aux
.usage
) {
1029 case ISL_AUX_USAGE_MCS
:
1030 case ISL_AUX_USAGE_MCS_CCS
:
1031 return res
->aux
.usage
;
1033 case ISL_AUX_USAGE_CCS_D
:
1034 case ISL_AUX_USAGE_CCS_E
:
1035 /* Gen9+ hardware technically supports non-0/1 clear colors with sRGB
1036 * formats. However, there are issues with blending where it doesn't
1037 * properly apply the sRGB curve to the clear color when blending.
1039 if (devinfo
->gen
>= 9 && blend_enabled
&&
1040 isl_format_is_srgb(render_format
) &&
1041 !isl_color_value_is_zero_one(res
->aux
.clear_color
, render_format
))
1042 return ISL_AUX_USAGE_NONE
;
1044 if (res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
&&
1045 format_ccs_e_compat_with_resource(devinfo
, res
, render_format
))
1046 return ISL_AUX_USAGE_CCS_E
;
1048 /* Otherwise, we try to fall back to CCS_D */
1049 if (isl_format_supports_ccs_d(devinfo
, render_format
))
1050 return ISL_AUX_USAGE_CCS_D
;
1053 return ISL_AUX_USAGE_NONE
;
1058 iris_resource_prepare_render(struct iris_context
*ice
,
1059 struct iris_batch
*batch
,
1060 struct iris_resource
*res
, uint32_t level
,
1061 uint32_t start_layer
, uint32_t layer_count
,
1062 enum isl_aux_usage aux_usage
)
1064 iris_resource_prepare_access(ice
, res
, level
, 1, start_layer
,
1065 layer_count
, aux_usage
,
1066 isl_aux_usage_has_fast_clears(aux_usage
));
1070 iris_resource_finish_render(struct iris_context
*ice
,
1071 struct iris_resource
*res
, uint32_t level
,
1072 uint32_t start_layer
, uint32_t layer_count
,
1073 enum isl_aux_usage aux_usage
)
1075 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,
1080 iris_resource_prepare_depth(struct iris_context
*ice
,
1081 struct iris_batch
*batch
,
1082 struct iris_resource
*res
, uint32_t level
,
1083 uint32_t start_layer
, uint32_t layer_count
)
1085 iris_resource_prepare_access(ice
, res
, level
, 1, start_layer
,
1086 layer_count
, res
->aux
.usage
, !!res
->aux
.bo
);
1090 iris_resource_finish_depth(struct iris_context
*ice
,
1091 struct iris_resource
*res
, uint32_t level
,
1092 uint32_t start_layer
, uint32_t layer_count
,
1095 if (depth_written
) {
1096 iris_resource_finish_write(ice
, res
, level
, start_layer
, layer_count
,