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iris: Drop old comment on clear color BO allocation
[mesa.git] / src / gallium / drivers / iris / iris_resource.c
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 /**
24 * @file iris_resource.c
25 *
26 * Resources are images, buffers, and other objects used by the GPU.
27 *
28 * XXX: explain resources
29 */
30
31 #include <stdio.h>
32 #include <errno.h>
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/format/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/common/gen_aux_map.h"
51 #include "intel/dev/gen_debug.h"
52 #include "isl/isl.h"
53 #include "drm-uapi/drm_fourcc.h"
54 #include "drm-uapi/i915_drm.h"
55
56 enum modifier_priority {
57 MODIFIER_PRIORITY_INVALID = 0,
58 MODIFIER_PRIORITY_LINEAR,
59 MODIFIER_PRIORITY_X,
60 MODIFIER_PRIORITY_Y,
61 MODIFIER_PRIORITY_Y_CCS,
62 MODIFIER_PRIORITY_Y_GEN12_RC_CCS,
63 };
64
65 static const uint64_t priority_to_modifier[] = {
66 [MODIFIER_PRIORITY_INVALID] = DRM_FORMAT_MOD_INVALID,
67 [MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
68 [MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
69 [MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
70 [MODIFIER_PRIORITY_Y_CCS] = I915_FORMAT_MOD_Y_TILED_CCS,
71 [MODIFIER_PRIORITY_Y_GEN12_RC_CCS] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
72 };
73
74 static bool
75 modifier_is_supported(const struct gen_device_info *devinfo,
76 enum pipe_format pfmt, uint64_t modifier)
77 {
78 /* Check for basic device support. */
79 switch (modifier) {
80 case DRM_FORMAT_MOD_LINEAR:
81 case I915_FORMAT_MOD_X_TILED:
82 case I915_FORMAT_MOD_Y_TILED:
83 break;
84 case I915_FORMAT_MOD_Y_TILED_CCS:
85 if (devinfo->gen <= 8 || devinfo->gen >= 12)
86 return false;
87 break;
88 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
89 if (devinfo->gen != 12)
90 return false;
91 break;
92 case DRM_FORMAT_MOD_INVALID:
93 default:
94 return false;
95 }
96
97 /* Check remaining requirements. */
98 switch (modifier) {
99 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
100 case I915_FORMAT_MOD_Y_TILED_CCS: {
101 if (unlikely(INTEL_DEBUG & DEBUG_NO_RBC))
102 return false;
103
104 enum isl_format rt_format =
105 iris_format_for_usage(devinfo, pfmt,
106 ISL_SURF_USAGE_RENDER_TARGET_BIT).fmt;
107
108 if (rt_format == ISL_FORMAT_UNSUPPORTED ||
109 !isl_format_supports_ccs_e(devinfo, rt_format))
110 return false;
111 break;
112 }
113 default:
114 break;
115 }
116
117 return true;
118 }
119
120 static uint64_t
121 select_best_modifier(struct gen_device_info *devinfo, enum pipe_format pfmt,
122 const uint64_t *modifiers,
123 int count)
124 {
125 enum modifier_priority prio = MODIFIER_PRIORITY_INVALID;
126
127 for (int i = 0; i < count; i++) {
128 if (!modifier_is_supported(devinfo, pfmt, modifiers[i]))
129 continue;
130
131 switch (modifiers[i]) {
132 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
133 prio = MAX2(prio, MODIFIER_PRIORITY_Y_GEN12_RC_CCS);
134 break;
135 case I915_FORMAT_MOD_Y_TILED_CCS:
136 prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS);
137 break;
138 case I915_FORMAT_MOD_Y_TILED:
139 prio = MAX2(prio, MODIFIER_PRIORITY_Y);
140 break;
141 case I915_FORMAT_MOD_X_TILED:
142 prio = MAX2(prio, MODIFIER_PRIORITY_X);
143 break;
144 case DRM_FORMAT_MOD_LINEAR:
145 prio = MAX2(prio, MODIFIER_PRIORITY_LINEAR);
146 break;
147 case DRM_FORMAT_MOD_INVALID:
148 default:
149 break;
150 }
151 }
152
153 return priority_to_modifier[prio];
154 }
155
156 enum isl_surf_dim
157 target_to_isl_surf_dim(enum pipe_texture_target target)
158 {
159 switch (target) {
160 case PIPE_BUFFER:
161 case PIPE_TEXTURE_1D:
162 case PIPE_TEXTURE_1D_ARRAY:
163 return ISL_SURF_DIM_1D;
164 case PIPE_TEXTURE_2D:
165 case PIPE_TEXTURE_CUBE:
166 case PIPE_TEXTURE_RECT:
167 case PIPE_TEXTURE_2D_ARRAY:
168 case PIPE_TEXTURE_CUBE_ARRAY:
169 return ISL_SURF_DIM_2D;
170 case PIPE_TEXTURE_3D:
171 return ISL_SURF_DIM_3D;
172 case PIPE_MAX_TEXTURE_TYPES:
173 break;
174 }
175 unreachable("invalid texture type");
176 }
177
178 static void
179 iris_query_dmabuf_modifiers(struct pipe_screen *pscreen,
180 enum pipe_format pfmt,
181 int max,
182 uint64_t *modifiers,
183 unsigned int *external_only,
184 int *count)
185 {
186 struct iris_screen *screen = (void *) pscreen;
187 const struct gen_device_info *devinfo = &screen->devinfo;
188
189 uint64_t all_modifiers[] = {
190 DRM_FORMAT_MOD_LINEAR,
191 I915_FORMAT_MOD_X_TILED,
192 I915_FORMAT_MOD_Y_TILED,
193 I915_FORMAT_MOD_Y_TILED_CCS,
194 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
195 };
196
197 int supported_mods = 0;
198
199 for (int i = 0; i < ARRAY_SIZE(all_modifiers); i++) {
200 if (!modifier_is_supported(devinfo, pfmt, all_modifiers[i]))
201 continue;
202
203 if (supported_mods < max) {
204 if (modifiers)
205 modifiers[supported_mods] = all_modifiers[i];
206
207 if (external_only)
208 external_only[supported_mods] = util_format_is_yuv(pfmt);
209 }
210
211 supported_mods++;
212 }
213
214 *count = supported_mods;
215 }
216
217 static isl_surf_usage_flags_t
218 pipe_bind_to_isl_usage(unsigned bindings)
219 {
220 isl_surf_usage_flags_t usage = 0;
221
222 if (bindings & PIPE_BIND_RENDER_TARGET)
223 usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
224
225 if (bindings & PIPE_BIND_SAMPLER_VIEW)
226 usage |= ISL_SURF_USAGE_TEXTURE_BIT;
227
228 if (bindings & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SHADER_BUFFER))
229 usage |= ISL_SURF_USAGE_STORAGE_BIT;
230
231 if (bindings & PIPE_BIND_SCANOUT)
232 usage |= ISL_SURF_USAGE_DISPLAY_BIT;
233
234 return usage;
235 }
236
237 enum isl_format
238 iris_image_view_get_format(struct iris_context *ice,
239 const struct pipe_image_view *img)
240 {
241 struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
242 const struct gen_device_info *devinfo = &screen->devinfo;
243
244 isl_surf_usage_flags_t usage = ISL_SURF_USAGE_STORAGE_BIT;
245 enum isl_format isl_fmt =
246 iris_format_for_usage(devinfo, img->format, usage).fmt;
247
248 if (img->shader_access & PIPE_IMAGE_ACCESS_READ) {
249 /* On Gen8, try to use typed surfaces reads (which support a
250 * limited number of formats), and if not possible, fall back
251 * to untyped reads.
252 */
253 if (devinfo->gen == 8 &&
254 !isl_has_matching_typed_storage_image_format(devinfo, isl_fmt))
255 return ISL_FORMAT_RAW;
256 else
257 return isl_lower_storage_image_format(devinfo, isl_fmt);
258 }
259
260 return isl_fmt;
261 }
262
263 struct pipe_resource *
264 iris_resource_get_separate_stencil(struct pipe_resource *p_res)
265 {
266 /* For packed depth-stencil, we treat depth as the primary resource
267 * and store S8 as the "second plane" resource.
268 */
269 if (p_res->next && p_res->next->format == PIPE_FORMAT_S8_UINT)
270 return p_res->next;
271
272 return NULL;
273
274 }
275
276 static void
277 iris_resource_set_separate_stencil(struct pipe_resource *p_res,
278 struct pipe_resource *stencil)
279 {
280 assert(util_format_has_depth(util_format_description(p_res->format)));
281 pipe_resource_reference(&p_res->next, stencil);
282 }
283
284 void
285 iris_get_depth_stencil_resources(struct pipe_resource *res,
286 struct iris_resource **out_z,
287 struct iris_resource **out_s)
288 {
289 if (!res) {
290 *out_z = NULL;
291 *out_s = NULL;
292 return;
293 }
294
295 if (res->format != PIPE_FORMAT_S8_UINT) {
296 *out_z = (void *) res;
297 *out_s = (void *) iris_resource_get_separate_stencil(res);
298 } else {
299 *out_z = NULL;
300 *out_s = (void *) res;
301 }
302 }
303
304 enum isl_dim_layout
305 iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
306 enum isl_tiling tiling,
307 enum pipe_texture_target target)
308 {
309 switch (target) {
310 case PIPE_TEXTURE_1D:
311 case PIPE_TEXTURE_1D_ARRAY:
312 return (devinfo->gen >= 9 && tiling == ISL_TILING_LINEAR ?
313 ISL_DIM_LAYOUT_GEN9_1D : ISL_DIM_LAYOUT_GEN4_2D);
314
315 case PIPE_TEXTURE_2D:
316 case PIPE_TEXTURE_2D_ARRAY:
317 case PIPE_TEXTURE_RECT:
318 case PIPE_TEXTURE_CUBE:
319 case PIPE_TEXTURE_CUBE_ARRAY:
320 return ISL_DIM_LAYOUT_GEN4_2D;
321
322 case PIPE_TEXTURE_3D:
323 return (devinfo->gen >= 9 ?
324 ISL_DIM_LAYOUT_GEN4_2D : ISL_DIM_LAYOUT_GEN4_3D);
325
326 case PIPE_MAX_TEXTURE_TYPES:
327 case PIPE_BUFFER:
328 break;
329 }
330 unreachable("invalid texture type");
331 }
332
333 void
334 iris_resource_disable_aux(struct iris_resource *res)
335 {
336 iris_bo_unreference(res->aux.bo);
337 iris_bo_unreference(res->aux.clear_color_bo);
338 free(res->aux.state);
339
340 res->aux.usage = ISL_AUX_USAGE_NONE;
341 res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
342 res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE;
343 res->aux.has_hiz = 0;
344 res->aux.surf.size_B = 0;
345 res->aux.bo = NULL;
346 res->aux.extra_aux.surf.size_B = 0;
347 res->aux.clear_color_bo = NULL;
348 res->aux.state = NULL;
349 }
350
351 static void
352 iris_resource_destroy(struct pipe_screen *screen,
353 struct pipe_resource *resource)
354 {
355 struct iris_resource *res = (struct iris_resource *)resource;
356
357 if (resource->target == PIPE_BUFFER)
358 util_range_destroy(&res->valid_buffer_range);
359
360 iris_resource_disable_aux(res);
361
362 iris_bo_unreference(res->bo);
363 iris_pscreen_unref(res->base.screen);
364
365 free(res);
366 }
367
368 static struct iris_resource *
369 iris_alloc_resource(struct pipe_screen *pscreen,
370 const struct pipe_resource *templ)
371 {
372 struct iris_resource *res = calloc(1, sizeof(struct iris_resource));
373 if (!res)
374 return NULL;
375
376 res->base = *templ;
377 res->base.screen = iris_pscreen_ref(pscreen);
378 pipe_reference_init(&res->base.reference, 1);
379
380 res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
381 res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE;
382
383 if (templ->target == PIPE_BUFFER)
384 util_range_init(&res->valid_buffer_range);
385
386 return res;
387 }
388
389 unsigned
390 iris_get_num_logical_layers(const struct iris_resource *res, unsigned level)
391 {
392 if (res->surf.dim == ISL_SURF_DIM_3D)
393 return minify(res->surf.logical_level0_px.depth, level);
394 else
395 return res->surf.logical_level0_px.array_len;
396 }
397
398 static enum isl_aux_state **
399 create_aux_state_map(struct iris_resource *res, enum isl_aux_state initial)
400 {
401 assert(res->aux.state == NULL);
402
403 uint32_t total_slices = 0;
404 for (uint32_t level = 0; level < res->surf.levels; level++)
405 total_slices += iris_get_num_logical_layers(res, level);
406
407 const size_t per_level_array_size =
408 res->surf.levels * sizeof(enum isl_aux_state *);
409
410 /* We're going to allocate a single chunk of data for both the per-level
411 * reference array and the arrays of aux_state. This makes cleanup
412 * significantly easier.
413 */
414 const size_t total_size =
415 per_level_array_size + total_slices * sizeof(enum isl_aux_state);
416
417 void *data = malloc(total_size);
418 if (!data)
419 return NULL;
420
421 enum isl_aux_state **per_level_arr = data;
422 enum isl_aux_state *s = data + per_level_array_size;
423 for (uint32_t level = 0; level < res->surf.levels; level++) {
424 per_level_arr[level] = s;
425 const unsigned level_layers = iris_get_num_logical_layers(res, level);
426 for (uint32_t a = 0; a < level_layers; a++)
427 *(s++) = initial;
428 }
429 assert((void *)s == data + total_size);
430
431 return per_level_arr;
432 }
433
434 static unsigned
435 iris_get_aux_clear_color_state_size(struct iris_screen *screen)
436 {
437 const struct gen_device_info *devinfo = &screen->devinfo;
438 return devinfo->gen >= 10 ? screen->isl_dev.ss.clear_color_state_size : 0;
439 }
440
441 static void
442 map_aux_addresses(struct iris_screen *screen, struct iris_resource *res)
443 {
444 const struct gen_device_info *devinfo = &screen->devinfo;
445 if (devinfo->gen >= 12 && isl_aux_usage_has_ccs(res->aux.usage)) {
446 void *aux_map_ctx = iris_bufmgr_get_aux_map_context(screen->bufmgr);
447 assert(aux_map_ctx);
448 const unsigned aux_offset = res->aux.extra_aux.surf.size_B > 0 ?
449 res->aux.extra_aux.offset : res->aux.offset;
450 gen_aux_map_add_image(aux_map_ctx, &res->surf, res->bo->gtt_offset,
451 res->aux.bo->gtt_offset + aux_offset);
452 res->bo->aux_map_address = res->aux.bo->gtt_offset;
453 }
454 }
455
456 static bool
457 want_ccs_e_for_format(const struct gen_device_info *devinfo,
458 enum isl_format format)
459 {
460 if (!isl_format_supports_ccs_e(devinfo, format))
461 return false;
462
463 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
464
465 /* CCS_E seems to significantly hurt performance with 32-bit floating
466 * point formats. For example, Paraview's "Wavelet Volume" case uses
467 * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
468 * formats causes a 62% FPS drop.
469 *
470 * However, many benchmarks seem to use 16-bit float with no issues.
471 */
472 if (fmtl->channels.r.bits == 32 && fmtl->channels.r.type == ISL_SFLOAT)
473 return false;
474
475 return true;
476 }
477
478 /**
479 * Configure aux for the resource, but don't allocate it. For images which
480 * might be shared with modifiers, we must allocate the image and aux data in
481 * a single bo.
482 *
483 * Returns false on unexpected error (e.g. allocation failed, or invalid
484 * configuration result).
485 */
486 static bool
487 iris_resource_configure_aux(struct iris_screen *screen,
488 struct iris_resource *res, bool imported,
489 uint64_t *aux_size_B)
490 {
491 const struct gen_device_info *devinfo = &screen->devinfo;
492
493 /* Try to create the auxiliary surfaces allowed by the modifier or by
494 * the user if no modifier is specified.
495 */
496 assert(!res->mod_info ||
497 res->mod_info->aux_usage == ISL_AUX_USAGE_NONE ||
498 res->mod_info->aux_usage == ISL_AUX_USAGE_CCS_E ||
499 res->mod_info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E);
500
501 const bool has_mcs = !res->mod_info &&
502 isl_surf_get_mcs_surf(&screen->isl_dev, &res->surf, &res->aux.surf);
503
504 const bool has_hiz = !res->mod_info && !(INTEL_DEBUG & DEBUG_NO_HIZ) &&
505 isl_surf_get_hiz_surf(&screen->isl_dev, &res->surf, &res->aux.surf);
506
507 const bool has_ccs =
508 ((!res->mod_info && !(INTEL_DEBUG & DEBUG_NO_RBC)) ||
509 (res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE)) &&
510 isl_surf_get_ccs_surf(&screen->isl_dev, &res->surf, &res->aux.surf,
511 &res->aux.extra_aux.surf, 0);
512
513 /* Having both HIZ and MCS is impossible. */
514 assert(!has_mcs || !has_hiz);
515
516 /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */
517 if (has_ccs && (has_mcs || has_hiz)) {
518 assert(res->aux.extra_aux.surf.size_B > 0 &&
519 res->aux.extra_aux.surf.usage & ISL_SURF_USAGE_CCS_BIT);
520 assert(res->aux.surf.size_B > 0 &&
521 res->aux.surf.usage &
522 (ISL_SURF_USAGE_HIZ_BIT | ISL_SURF_USAGE_MCS_BIT));
523 }
524
525 if (res->mod_info && has_ccs) {
526 /* Only allow a CCS modifier if the aux was created successfully. */
527 res->aux.possible_usages |= 1 << res->mod_info->aux_usage;
528 } else if (has_mcs) {
529 res->aux.possible_usages |=
530 1 << (has_ccs ? ISL_AUX_USAGE_MCS_CCS : ISL_AUX_USAGE_MCS);
531 } else if (has_hiz) {
532 if (!has_ccs) {
533 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ;
534 } else if (res->surf.samples == 1 &&
535 (res->surf.usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
536 /* If this resource is single-sampled and will be used as a texture,
537 * put the HiZ surface in write-through mode so that we can sample
538 * from it.
539 */
540 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ_CCS_WT;
541 } else {
542 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ_CCS;
543 }
544 } else if (has_ccs && isl_surf_usage_is_stencil(res->surf.usage)) {
545 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_STC_CCS;
546 } else if (has_ccs) {
547 if (want_ccs_e_for_format(devinfo, res->surf.format)) {
548 res->aux.possible_usages |= devinfo->gen < 12 ?
549 1 << ISL_AUX_USAGE_CCS_E : 1 << ISL_AUX_USAGE_GEN12_CCS_E;
550 } else if (isl_format_supports_ccs_d(devinfo, res->surf.format)) {
551 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_D;
552 }
553 }
554
555 res->aux.usage = util_last_bit(res->aux.possible_usages) - 1;
556
557 res->aux.sampler_usages = res->aux.possible_usages;
558
559 /* We don't always support sampling with hiz. But when we do, it must be
560 * single sampled.
561 */
562 if (!devinfo->has_sample_with_hiz || res->surf.samples > 1)
563 res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ);
564
565 /* ISL_AUX_USAGE_HIZ_CCS doesn't support sampling at all */
566 res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ_CCS);
567
568 enum isl_aux_state initial_state;
569 *aux_size_B = 0;
570 assert(!res->aux.bo);
571
572 switch (res->aux.usage) {
573 case ISL_AUX_USAGE_NONE:
574 /* Having no aux buffer is only okay if there's no modifier with aux. */
575 return !res->mod_info || res->mod_info->aux_usage == ISL_AUX_USAGE_NONE;
576 case ISL_AUX_USAGE_HIZ:
577 case ISL_AUX_USAGE_HIZ_CCS:
578 case ISL_AUX_USAGE_HIZ_CCS_WT:
579 initial_state = ISL_AUX_STATE_AUX_INVALID;
580 break;
581 case ISL_AUX_USAGE_MCS:
582 case ISL_AUX_USAGE_MCS_CCS:
583 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
584 *
585 * "When MCS buffer is enabled and bound to MSRT, it is required
586 * that it is cleared prior to any rendering."
587 *
588 * Since we only use the MCS buffer for rendering, we just clear it
589 * immediately on allocation. The clear value for MCS buffers is all
590 * 1's, so we simply memset it to 0xff.
591 */
592 initial_state = ISL_AUX_STATE_CLEAR;
593 break;
594 case ISL_AUX_USAGE_CCS_D:
595 case ISL_AUX_USAGE_CCS_E:
596 case ISL_AUX_USAGE_GEN12_CCS_E:
597 case ISL_AUX_USAGE_STC_CCS:
598 /* When CCS_E is used, we need to ensure that the CCS starts off in
599 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
600 * Target(s)":
601 *
602 * "If Software wants to enable Color Compression without Fast
603 * clear, Software needs to initialize MCS with zeros."
604 *
605 * A CCS value of 0 indicates that the corresponding block is in the
606 * pass-through state which is what we want.
607 *
608 * For CCS_D, do the same thing. On Gen9+, this avoids having any
609 * undefined bits in the aux buffer.
610 */
611 if (imported) {
612 assert(res->aux.usage != ISL_AUX_USAGE_STC_CCS);
613 initial_state =
614 isl_drm_modifier_get_default_aux_state(res->mod_info->modifier);
615 } else {
616 initial_state = ISL_AUX_STATE_PASS_THROUGH;
617 }
618 break;
619 case ISL_AUX_USAGE_MC:
620 default:
621 unreachable("Unsupported aux mode");
622 }
623
624 /* Create the aux_state for the auxiliary buffer. */
625 res->aux.state = create_aux_state_map(res, initial_state);
626 if (!res->aux.state)
627 return false;
628
629 /* Allocate space in the buffer for storing the aux surface. */
630 res->aux.offset =
631 ALIGN(res->surf.size_B, res->aux.surf.alignment_B);
632 uint64_t size = res->aux.surf.size_B;
633
634 /* Allocate space in the buffer for storing the CCS. */
635 if (res->aux.extra_aux.surf.size_B > 0) {
636 const uint64_t padded_aux_size =
637 ALIGN(size, res->aux.extra_aux.surf.alignment_B);
638 res->aux.extra_aux.offset = res->aux.offset + padded_aux_size;
639 size = padded_aux_size + res->aux.extra_aux.surf.size_B;
640 }
641
642 /* Allocate space in the buffer for storing the indirect clear color.
643 *
644 * Also add some padding to make sure the fast clear color state buffer
645 * starts at a 4K alignment. We believe that 256B might be enough, but due
646 * to lack of testing we will leave this as 4K for now.
647 */
648 size = ALIGN(size, 4096);
649 res->aux.clear_color_offset = res->aux.offset + size;
650 size += iris_get_aux_clear_color_state_size(screen);
651 *aux_size_B = size;
652
653 if (isl_aux_usage_has_hiz(res->aux.usage)) {
654 for (unsigned level = 0; level < res->surf.levels; ++level) {
655 uint32_t width = u_minify(res->surf.phys_level0_sa.width, level);
656 uint32_t height = u_minify(res->surf.phys_level0_sa.height, level);
657
658 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
659 * For LOD == 0, we can grow the dimensions to make it work.
660 */
661 if (level == 0 || ((width & 7) == 0 && (height & 3) == 0))
662 res->aux.has_hiz |= 1 << level;
663 }
664 }
665
666 return true;
667 }
668
669 /**
670 * Initialize the aux buffer contents.
671 *
672 * Returns false on unexpected error (e.g. mapping a BO failed).
673 */
674 static bool
675 iris_resource_init_aux_buf(struct iris_resource *res,
676 unsigned clear_color_state_size)
677 {
678 void *map = iris_bo_map(NULL, res->aux.bo, MAP_WRITE | MAP_RAW);
679
680 if (!map)
681 return false;
682
683 if (iris_resource_get_aux_state(res, 0, 0) != ISL_AUX_STATE_AUX_INVALID) {
684 /* See iris_resource_configure_aux for the memset_value rationale. */
685 uint8_t memset_value = isl_aux_usage_has_mcs(res->aux.usage) ? 0xFF : 0;
686 memset((char*)map + res->aux.offset, memset_value,
687 res->aux.surf.size_B);
688 }
689
690 memset((char*)map + res->aux.extra_aux.offset,
691 0, res->aux.extra_aux.surf.size_B);
692
693 /* Zero the indirect clear color to match ::fast_clear_color. */
694 memset((char *)map + res->aux.clear_color_offset, 0,
695 clear_color_state_size);
696
697 iris_bo_unmap(res->aux.bo);
698
699 if (clear_color_state_size > 0) {
700 res->aux.clear_color_bo = res->aux.bo;
701 iris_bo_reference(res->aux.clear_color_bo);
702 }
703
704 return true;
705 }
706
707 void
708 iris_resource_finish_aux_import(struct pipe_screen *pscreen,
709 struct iris_resource *res)
710 {
711 struct iris_screen *screen = (struct iris_screen *)pscreen;
712 assert(iris_resource_unfinished_aux_import(res));
713 assert(!res->mod_info->supports_clear_color);
714
715 struct iris_resource *aux_res = (void *) res->base.next;
716 assert(aux_res->aux.surf.row_pitch_B && aux_res->aux.offset &&
717 aux_res->aux.bo);
718
719 assert(res->bo == aux_res->aux.bo);
720 iris_bo_reference(aux_res->aux.bo);
721 res->aux.bo = aux_res->aux.bo;
722
723 res->aux.offset = aux_res->aux.offset;
724
725 assert(res->bo->size >= (res->aux.offset + res->aux.surf.size_B));
726 assert(res->aux.clear_color_bo == NULL);
727 res->aux.clear_color_offset = 0;
728
729 assert(aux_res->aux.surf.row_pitch_B == res->aux.surf.row_pitch_B);
730
731 unsigned clear_color_state_size =
732 iris_get_aux_clear_color_state_size(screen);
733
734 if (clear_color_state_size > 0) {
735 res->aux.clear_color_bo =
736 iris_bo_alloc_tiled(screen->bufmgr, "clear color_buffer",
737 clear_color_state_size, 1, IRIS_MEMZONE_OTHER,
738 I915_TILING_NONE, 0, BO_ALLOC_ZEROED);
739 res->aux.clear_color_offset = 0;
740 }
741
742 iris_resource_destroy(&screen->base, res->base.next);
743 res->base.next = NULL;
744
745 map_aux_addresses(screen, res);
746 }
747
748 static struct pipe_resource *
749 iris_resource_create_for_buffer(struct pipe_screen *pscreen,
750 const struct pipe_resource *templ)
751 {
752 struct iris_screen *screen = (struct iris_screen *)pscreen;
753 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
754
755 assert(templ->target == PIPE_BUFFER);
756 assert(templ->height0 <= 1);
757 assert(templ->depth0 <= 1);
758 assert(templ->format == PIPE_FORMAT_NONE ||
759 util_format_get_blocksize(templ->format) == 1);
760
761 res->internal_format = templ->format;
762 res->surf.tiling = ISL_TILING_LINEAR;
763
764 enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
765 const char *name = templ->target == PIPE_BUFFER ? "buffer" : "miptree";
766 if (templ->flags & IRIS_RESOURCE_FLAG_SHADER_MEMZONE) {
767 memzone = IRIS_MEMZONE_SHADER;
768 name = "shader kernels";
769 } else if (templ->flags & IRIS_RESOURCE_FLAG_SURFACE_MEMZONE) {
770 memzone = IRIS_MEMZONE_SURFACE;
771 name = "surface state";
772 } else if (templ->flags & IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE) {
773 memzone = IRIS_MEMZONE_DYNAMIC;
774 name = "dynamic state";
775 }
776
777 res->bo = iris_bo_alloc(screen->bufmgr, name, templ->width0, memzone);
778 if (!res->bo) {
779 iris_resource_destroy(pscreen, &res->base);
780 return NULL;
781 }
782
783 if (templ->bind & PIPE_BIND_SHARED)
784 iris_bo_make_external(res->bo);
785
786 return &res->base;
787 }
788
789 static struct pipe_resource *
790 iris_resource_create_with_modifiers(struct pipe_screen *pscreen,
791 const struct pipe_resource *templ,
792 const uint64_t *modifiers,
793 int modifiers_count)
794 {
795 struct iris_screen *screen = (struct iris_screen *)pscreen;
796 struct gen_device_info *devinfo = &screen->devinfo;
797 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
798
799 if (!res)
800 return NULL;
801
802 const struct util_format_description *format_desc =
803 util_format_description(templ->format);
804 const bool has_depth = util_format_has_depth(format_desc);
805 uint64_t modifier =
806 select_best_modifier(devinfo, templ->format, modifiers, modifiers_count);
807
808 isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK;
809
810 if (modifier != DRM_FORMAT_MOD_INVALID) {
811 res->mod_info = isl_drm_modifier_get_info(modifier);
812
813 tiling_flags = 1 << res->mod_info->tiling;
814 } else {
815 if (modifiers_count > 0) {
816 fprintf(stderr, "Unsupported modifier, resource creation failed.\n");
817 goto fail;
818 }
819
820 /* Use linear for staging buffers */
821 if (templ->usage == PIPE_USAGE_STAGING ||
822 templ->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR) ) {
823 tiling_flags = ISL_TILING_LINEAR_BIT;
824 } else if (templ->bind & PIPE_BIND_SCANOUT) {
825 if (devinfo->has_tiling_uapi)
826 tiling_flags = ISL_TILING_X_BIT;
827 else
828 tiling_flags = ISL_TILING_LINEAR_BIT;
829 }
830 }
831
832 isl_surf_usage_flags_t usage = pipe_bind_to_isl_usage(templ->bind);
833
834 if (templ->target == PIPE_TEXTURE_CUBE ||
835 templ->target == PIPE_TEXTURE_CUBE_ARRAY)
836 usage |= ISL_SURF_USAGE_CUBE_BIT;
837
838 if (templ->usage != PIPE_USAGE_STAGING) {
839 if (templ->format == PIPE_FORMAT_S8_UINT)
840 usage |= ISL_SURF_USAGE_STENCIL_BIT;
841 else if (has_depth)
842 usage |= ISL_SURF_USAGE_DEPTH_BIT;
843 }
844
845 enum pipe_format pfmt = templ->format;
846 res->internal_format = pfmt;
847
848 /* Should be handled by u_transfer_helper */
849 assert(!util_format_is_depth_and_stencil(pfmt));
850
851 struct iris_format_info fmt = iris_format_for_usage(devinfo, pfmt, usage);
852 assert(fmt.fmt != ISL_FORMAT_UNSUPPORTED);
853
854 UNUSED const bool isl_surf_created_successfully =
855 isl_surf_init(&screen->isl_dev, &res->surf,
856 .dim = target_to_isl_surf_dim(templ->target),
857 .format = fmt.fmt,
858 .width = templ->width0,
859 .height = templ->height0,
860 .depth = templ->depth0,
861 .levels = templ->last_level + 1,
862 .array_len = templ->array_size,
863 .samples = MAX2(templ->nr_samples, 1),
864 .min_alignment_B = 0,
865 .row_pitch_B = 0,
866 .usage = usage,
867 .tiling_flags = tiling_flags);
868 assert(isl_surf_created_successfully);
869
870 const char *name = "miptree";
871 enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
872
873 unsigned int flags = 0;
874 if (templ->usage == PIPE_USAGE_STAGING)
875 flags |= BO_ALLOC_COHERENT;
876
877 /* These are for u_upload_mgr buffers only */
878 assert(!(templ->flags & (IRIS_RESOURCE_FLAG_SHADER_MEMZONE |
879 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE |
880 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE)));
881
882 uint64_t aux_size = 0;
883 if (!iris_resource_configure_aux(screen, res, false, &aux_size))
884 goto fail;
885
886 /* Modifiers require the aux data to be in the same buffer as the main
887 * surface, but we combine them even when a modifiers is not being used.
888 */
889 const uint64_t bo_size =
890 MAX2(res->surf.size_B, res->aux.offset + aux_size);
891 uint32_t alignment = MAX2(4096, res->surf.alignment_B);
892 res->bo = iris_bo_alloc_tiled(screen->bufmgr, name, bo_size, alignment,
893 memzone,
894 isl_tiling_to_i915_tiling(res->surf.tiling),
895 res->surf.row_pitch_B, flags);
896
897 if (!res->bo)
898 goto fail;
899
900 if (aux_size > 0) {
901 res->aux.bo = res->bo;
902 iris_bo_reference(res->aux.bo);
903 unsigned clear_color_state_size =
904 iris_get_aux_clear_color_state_size(screen);
905 if (!iris_resource_init_aux_buf(res, clear_color_state_size))
906 goto fail;
907 map_aux_addresses(screen, res);
908 }
909
910 if (templ->bind & PIPE_BIND_SHARED)
911 iris_bo_make_external(res->bo);
912
913 return &res->base;
914
915 fail:
916 fprintf(stderr, "XXX: resource creation failed\n");
917 iris_resource_destroy(pscreen, &res->base);
918 return NULL;
919
920 }
921
922 static struct pipe_resource *
923 iris_resource_create(struct pipe_screen *pscreen,
924 const struct pipe_resource *templ)
925 {
926 if (templ->target == PIPE_BUFFER)
927 return iris_resource_create_for_buffer(pscreen, templ);
928 else
929 return iris_resource_create_with_modifiers(pscreen, templ, NULL, 0);
930 }
931
932 static uint64_t
933 tiling_to_modifier(uint32_t tiling)
934 {
935 static const uint64_t map[] = {
936 [I915_TILING_NONE] = DRM_FORMAT_MOD_LINEAR,
937 [I915_TILING_X] = I915_FORMAT_MOD_X_TILED,
938 [I915_TILING_Y] = I915_FORMAT_MOD_Y_TILED,
939 };
940
941 assert(tiling < ARRAY_SIZE(map));
942
943 return map[tiling];
944 }
945
946 static struct pipe_resource *
947 iris_resource_from_user_memory(struct pipe_screen *pscreen,
948 const struct pipe_resource *templ,
949 void *user_memory)
950 {
951 struct iris_screen *screen = (struct iris_screen *)pscreen;
952 struct iris_bufmgr *bufmgr = screen->bufmgr;
953 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
954 if (!res)
955 return NULL;
956
957 assert(templ->target == PIPE_BUFFER);
958
959 res->internal_format = templ->format;
960 res->bo = iris_bo_create_userptr(bufmgr, "user",
961 user_memory, templ->width0,
962 IRIS_MEMZONE_OTHER);
963 if (!res->bo) {
964 iris_resource_destroy(pscreen, &res->base);
965 return NULL;
966 }
967
968 util_range_add(&res->base, &res->valid_buffer_range, 0, templ->width0);
969
970 return &res->base;
971 }
972
973 static struct pipe_resource *
974 iris_resource_from_handle(struct pipe_screen *pscreen,
975 const struct pipe_resource *templ,
976 struct winsys_handle *whandle,
977 unsigned usage)
978 {
979 struct iris_screen *screen = (struct iris_screen *)pscreen;
980 struct gen_device_info *devinfo = &screen->devinfo;
981 struct iris_bufmgr *bufmgr = screen->bufmgr;
982 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
983 const struct isl_drm_modifier_info *mod_inf =
984 isl_drm_modifier_get_info(whandle->modifier);
985
986 if (!res)
987 return NULL;
988
989 switch (whandle->type) {
990 case WINSYS_HANDLE_TYPE_FD:
991 res->bo = iris_bo_import_dmabuf(bufmgr, whandle->handle,
992 whandle->modifier);
993 break;
994 case WINSYS_HANDLE_TYPE_SHARED:
995 res->bo = iris_bo_gem_create_from_name(bufmgr, "winsys image",
996 whandle->handle);
997 break;
998 default:
999 unreachable("invalid winsys handle type");
1000 }
1001 if (!res->bo)
1002 goto fail;
1003
1004 res->offset = whandle->offset;
1005
1006 if (mod_inf == NULL) {
1007 mod_inf =
1008 isl_drm_modifier_get_info(tiling_to_modifier(res->bo->tiling_mode));
1009 }
1010 assert(mod_inf);
1011
1012 res->external_format = whandle->format;
1013 res->mod_info = mod_inf;
1014
1015 isl_surf_usage_flags_t isl_usage = pipe_bind_to_isl_usage(templ->bind);
1016
1017 const struct iris_format_info fmt =
1018 iris_format_for_usage(devinfo, templ->format, isl_usage);
1019 res->internal_format = templ->format;
1020
1021 if (templ->target == PIPE_BUFFER) {
1022 res->surf.tiling = ISL_TILING_LINEAR;
1023 } else {
1024 /* Create a surface for each plane specified by the external format. */
1025 if (whandle->plane < util_format_get_num_planes(whandle->format)) {
1026 UNUSED const bool isl_surf_created_successfully =
1027 isl_surf_init(&screen->isl_dev, &res->surf,
1028 .dim = target_to_isl_surf_dim(templ->target),
1029 .format = fmt.fmt,
1030 .width = templ->width0,
1031 .height = templ->height0,
1032 .depth = templ->depth0,
1033 .levels = templ->last_level + 1,
1034 .array_len = templ->array_size,
1035 .samples = MAX2(templ->nr_samples, 1),
1036 .min_alignment_B = 0,
1037 .row_pitch_B = whandle->stride,
1038 .usage = isl_usage,
1039 .tiling_flags = 1 << res->mod_info->tiling);
1040 assert(isl_surf_created_successfully);
1041 assert(res->bo->tiling_mode ==
1042 isl_tiling_to_i915_tiling(res->surf.tiling));
1043
1044 uint64_t size;
1045 bool ok = iris_resource_configure_aux(screen, res, true, &size);
1046 assert(ok);
1047 /* The gallium dri layer will create a separate plane resource
1048 * for the aux image. iris_resource_finish_aux_import will
1049 * merge the separate aux parameters back into a single
1050 * iris_resource.
1051 */
1052 } else {
1053 /* Save modifier import information to reconstruct later. After
1054 * import, this will be available under a second image accessible
1055 * from the main image with res->base.next. See
1056 * iris_resource_finish_aux_import.
1057 */
1058 res->aux.surf.row_pitch_B = whandle->stride;
1059 res->aux.offset = whandle->offset;
1060 res->aux.bo = res->bo;
1061 res->bo = NULL;
1062 }
1063 }
1064
1065 return &res->base;
1066
1067 fail:
1068 iris_resource_destroy(pscreen, &res->base);
1069 return NULL;
1070 }
1071
1072 static void
1073 iris_flush_resource(struct pipe_context *ctx, struct pipe_resource *resource)
1074 {
1075 struct iris_context *ice = (struct iris_context *)ctx;
1076 struct iris_resource *res = (void *) resource;
1077 const struct isl_drm_modifier_info *mod = res->mod_info;
1078
1079 iris_resource_prepare_access(ice, res,
1080 0, INTEL_REMAINING_LEVELS,
1081 0, INTEL_REMAINING_LAYERS,
1082 mod ? mod->aux_usage : ISL_AUX_USAGE_NONE,
1083 mod ? mod->supports_clear_color : false);
1084 }
1085
1086 static void
1087 iris_resource_disable_aux_on_first_query(struct pipe_resource *resource,
1088 unsigned usage)
1089 {
1090 struct iris_resource *res = (struct iris_resource *)resource;
1091 bool mod_with_aux =
1092 res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
1093
1094 /* Disable aux usage if explicit flush not set and this is the first time
1095 * we are dealing with this resource and the resource was not created with
1096 * a modifier with aux.
1097 */
1098 if (!mod_with_aux &&
1099 (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && res->aux.usage != 0) &&
1100 p_atomic_read(&resource->reference.count) == 1) {
1101 iris_resource_disable_aux(res);
1102 }
1103 }
1104
1105 static bool
1106 iris_resource_get_param(struct pipe_screen *pscreen,
1107 struct pipe_context *context,
1108 struct pipe_resource *resource,
1109 unsigned plane,
1110 unsigned layer,
1111 enum pipe_resource_param param,
1112 unsigned handle_usage,
1113 uint64_t *value)
1114 {
1115 struct iris_screen *screen = (struct iris_screen *)pscreen;
1116 struct iris_resource *res = (struct iris_resource *)resource;
1117 bool mod_with_aux =
1118 res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
1119 bool wants_aux = mod_with_aux && plane > 0;
1120 bool result;
1121 unsigned handle;
1122
1123 if (iris_resource_unfinished_aux_import(res))
1124 iris_resource_finish_aux_import(pscreen, res);
1125
1126 struct iris_bo *bo = wants_aux ? res->aux.bo : res->bo;
1127
1128 iris_resource_disable_aux_on_first_query(resource, handle_usage);
1129
1130 switch (param) {
1131 case PIPE_RESOURCE_PARAM_NPLANES:
1132 if (mod_with_aux) {
1133 *value = 2;
1134 } else {
1135 unsigned count = 0;
1136 for (struct pipe_resource *cur = resource; cur; cur = cur->next)
1137 count++;
1138 *value = count;
1139 }
1140 return true;
1141 case PIPE_RESOURCE_PARAM_STRIDE:
1142 *value = wants_aux ? res->aux.surf.row_pitch_B : res->surf.row_pitch_B;
1143 return true;
1144 case PIPE_RESOURCE_PARAM_OFFSET:
1145 *value = wants_aux ? res->aux.offset : 0;
1146 return true;
1147 case PIPE_RESOURCE_PARAM_MODIFIER:
1148 *value = res->mod_info ? res->mod_info->modifier :
1149 tiling_to_modifier(res->bo->tiling_mode);
1150 return true;
1151 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED:
1152 result = iris_bo_flink(bo, &handle) == 0;
1153 if (result)
1154 *value = handle;
1155 return result;
1156 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS: {
1157 /* Because we share the same drm file across multiple iris_screen, when
1158 * we export a GEM handle we must make sure it is valid in the DRM file
1159 * descriptor the caller is using (this is the FD given at screen
1160 * creation).
1161 */
1162 uint32_t handle;
1163 if (iris_bo_export_gem_handle_for_device(bo, screen->winsys_fd, &handle))
1164 return false;
1165 *value = handle;
1166 return true;
1167 }
1168
1169 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD:
1170 result = iris_bo_export_dmabuf(bo, (int *) &handle) == 0;
1171 if (result)
1172 *value = handle;
1173 return result;
1174 default:
1175 return false;
1176 }
1177 }
1178
1179 static bool
1180 iris_resource_get_handle(struct pipe_screen *pscreen,
1181 struct pipe_context *ctx,
1182 struct pipe_resource *resource,
1183 struct winsys_handle *whandle,
1184 unsigned usage)
1185 {
1186 struct iris_screen *screen = (struct iris_screen *) pscreen;
1187 struct iris_resource *res = (struct iris_resource *)resource;
1188 bool mod_with_aux =
1189 res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
1190
1191 iris_resource_disable_aux_on_first_query(resource, usage);
1192
1193 struct iris_bo *bo;
1194 if (mod_with_aux && whandle->plane > 0) {
1195 assert(res->aux.bo);
1196 bo = res->aux.bo;
1197 whandle->stride = res->aux.surf.row_pitch_B;
1198 whandle->offset = res->aux.offset;
1199 } else {
1200 /* If this is a buffer, stride should be 0 - no need to special case */
1201 whandle->stride = res->surf.row_pitch_B;
1202 bo = res->bo;
1203 }
1204
1205 whandle->format = res->external_format;
1206 whandle->modifier =
1207 res->mod_info ? res->mod_info->modifier
1208 : tiling_to_modifier(res->bo->tiling_mode);
1209
1210 #ifndef NDEBUG
1211 enum isl_aux_usage allowed_usage =
1212 res->mod_info ? res->mod_info->aux_usage : ISL_AUX_USAGE_NONE;
1213
1214 if (res->aux.usage != allowed_usage) {
1215 enum isl_aux_state aux_state = iris_resource_get_aux_state(res, 0, 0);
1216 assert(aux_state == ISL_AUX_STATE_RESOLVED ||
1217 aux_state == ISL_AUX_STATE_PASS_THROUGH);
1218 }
1219 #endif
1220
1221 switch (whandle->type) {
1222 case WINSYS_HANDLE_TYPE_SHARED:
1223 return iris_bo_flink(bo, &whandle->handle) == 0;
1224 case WINSYS_HANDLE_TYPE_KMS: {
1225 /* Because we share the same drm file across multiple iris_screen, when
1226 * we export a GEM handle we must make sure it is valid in the DRM file
1227 * descriptor the caller is using (this is the FD given at screen
1228 * creation).
1229 */
1230 uint32_t handle;
1231 if (iris_bo_export_gem_handle_for_device(bo, screen->winsys_fd, &handle))
1232 return false;
1233 whandle->handle = handle;
1234 return true;
1235 }
1236 case WINSYS_HANDLE_TYPE_FD:
1237 return iris_bo_export_dmabuf(bo, (int *) &whandle->handle) == 0;
1238 }
1239
1240 return false;
1241 }
1242
1243 static bool
1244 resource_is_busy(struct iris_context *ice,
1245 struct iris_resource *res)
1246 {
1247 bool busy = iris_bo_busy(res->bo);
1248
1249 for (int i = 0; i < IRIS_BATCH_COUNT; i++)
1250 busy |= iris_batch_references(&ice->batches[i], res->bo);
1251
1252 return busy;
1253 }
1254
1255 static void
1256 iris_invalidate_resource(struct pipe_context *ctx,
1257 struct pipe_resource *resource)
1258 {
1259 struct iris_screen *screen = (void *) ctx->screen;
1260 struct iris_context *ice = (void *) ctx;
1261 struct iris_resource *res = (void *) resource;
1262
1263 if (resource->target != PIPE_BUFFER)
1264 return;
1265
1266 /* If it's already invalidated, don't bother doing anything. */
1267 if (res->valid_buffer_range.start > res->valid_buffer_range.end)
1268 return;
1269
1270 if (!resource_is_busy(ice, res)) {
1271 /* The resource is idle, so just mark that it contains no data and
1272 * keep using the same underlying buffer object.
1273 */
1274 util_range_set_empty(&res->valid_buffer_range);
1275 return;
1276 }
1277
1278 /* Otherwise, try and replace the backing storage with a new BO. */
1279
1280 /* We can't reallocate memory we didn't allocate in the first place. */
1281 if (res->bo->userptr)
1282 return;
1283
1284 // XXX: We should support this.
1285 if (res->bind_history & PIPE_BIND_STREAM_OUTPUT)
1286 return;
1287
1288 struct iris_bo *old_bo = res->bo;
1289 struct iris_bo *new_bo =
1290 iris_bo_alloc(screen->bufmgr, res->bo->name, resource->width0,
1291 iris_memzone_for_address(old_bo->gtt_offset));
1292 if (!new_bo)
1293 return;
1294
1295 /* Swap out the backing storage */
1296 res->bo = new_bo;
1297
1298 /* Rebind the buffer, replacing any state referring to the old BO's
1299 * address, and marking state dirty so it's reemitted.
1300 */
1301 screen->vtbl.rebind_buffer(ice, res);
1302
1303 util_range_set_empty(&res->valid_buffer_range);
1304
1305 iris_bo_unreference(old_bo);
1306 }
1307
1308 static void
1309 iris_flush_staging_region(struct pipe_transfer *xfer,
1310 const struct pipe_box *flush_box)
1311 {
1312 if (!(xfer->usage & PIPE_TRANSFER_WRITE))
1313 return;
1314
1315 struct iris_transfer *map = (void *) xfer;
1316
1317 struct pipe_box src_box = *flush_box;
1318
1319 /* Account for extra alignment padding in staging buffer */
1320 if (xfer->resource->target == PIPE_BUFFER)
1321 src_box.x += xfer->box.x % IRIS_MAP_BUFFER_ALIGNMENT;
1322
1323 struct pipe_box dst_box = (struct pipe_box) {
1324 .x = xfer->box.x + flush_box->x,
1325 .y = xfer->box.y + flush_box->y,
1326 .z = xfer->box.z + flush_box->z,
1327 .width = flush_box->width,
1328 .height = flush_box->height,
1329 .depth = flush_box->depth,
1330 };
1331
1332 iris_copy_region(map->blorp, map->batch, xfer->resource, xfer->level,
1333 dst_box.x, dst_box.y, dst_box.z, map->staging, 0,
1334 &src_box);
1335 }
1336
1337 static void
1338 iris_unmap_copy_region(struct iris_transfer *map)
1339 {
1340 iris_resource_destroy(map->staging->screen, map->staging);
1341
1342 map->ptr = NULL;
1343 }
1344
1345 static void
1346 iris_map_copy_region(struct iris_transfer *map)
1347 {
1348 struct pipe_screen *pscreen = &map->batch->screen->base;
1349 struct pipe_transfer *xfer = &map->base;
1350 struct pipe_box *box = &xfer->box;
1351 struct iris_resource *res = (void *) xfer->resource;
1352
1353 unsigned extra = xfer->resource->target == PIPE_BUFFER ?
1354 box->x % IRIS_MAP_BUFFER_ALIGNMENT : 0;
1355
1356 struct pipe_resource templ = (struct pipe_resource) {
1357 .usage = PIPE_USAGE_STAGING,
1358 .width0 = box->width + extra,
1359 .height0 = box->height,
1360 .depth0 = 1,
1361 .nr_samples = xfer->resource->nr_samples,
1362 .nr_storage_samples = xfer->resource->nr_storage_samples,
1363 .array_size = box->depth,
1364 .format = res->internal_format,
1365 };
1366
1367 if (xfer->resource->target == PIPE_BUFFER)
1368 templ.target = PIPE_BUFFER;
1369 else if (templ.array_size > 1)
1370 templ.target = PIPE_TEXTURE_2D_ARRAY;
1371 else
1372 templ.target = PIPE_TEXTURE_2D;
1373
1374 map->staging = iris_resource_create(pscreen, &templ);
1375 assert(map->staging);
1376
1377 if (templ.target != PIPE_BUFFER) {
1378 struct isl_surf *surf = &((struct iris_resource *) map->staging)->surf;
1379 xfer->stride = isl_surf_get_row_pitch_B(surf);
1380 xfer->layer_stride = isl_surf_get_array_pitch(surf);
1381 }
1382
1383 if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
1384 iris_copy_region(map->blorp, map->batch, map->staging, 0, extra, 0, 0,
1385 xfer->resource, xfer->level, box);
1386 /* Ensure writes to the staging BO land before we map it below. */
1387 iris_emit_pipe_control_flush(map->batch,
1388 "transfer read: flush before mapping",
1389 PIPE_CONTROL_RENDER_TARGET_FLUSH |
1390 PIPE_CONTROL_CS_STALL);
1391 }
1392
1393 struct iris_bo *staging_bo = iris_resource_bo(map->staging);
1394
1395 if (iris_batch_references(map->batch, staging_bo))
1396 iris_batch_flush(map->batch);
1397
1398 map->ptr =
1399 iris_bo_map(map->dbg, staging_bo, xfer->usage & MAP_FLAGS) + extra;
1400
1401 map->unmap = iris_unmap_copy_region;
1402 }
1403
1404 static void
1405 get_image_offset_el(const struct isl_surf *surf, unsigned level, unsigned z,
1406 unsigned *out_x0_el, unsigned *out_y0_el)
1407 {
1408 if (surf->dim == ISL_SURF_DIM_3D) {
1409 isl_surf_get_image_offset_el(surf, level, 0, z, out_x0_el, out_y0_el);
1410 } else {
1411 isl_surf_get_image_offset_el(surf, level, z, 0, out_x0_el, out_y0_el);
1412 }
1413 }
1414
1415 /**
1416 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1417 * different tiling patterns.
1418 */
1419 static void
1420 iris_resource_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
1421 uint32_t *tile_w, uint32_t *tile_h)
1422 {
1423 switch (tiling) {
1424 case ISL_TILING_X:
1425 *tile_w = 512;
1426 *tile_h = 8;
1427 break;
1428 case ISL_TILING_Y0:
1429 *tile_w = 128;
1430 *tile_h = 32;
1431 break;
1432 case ISL_TILING_LINEAR:
1433 *tile_w = cpp;
1434 *tile_h = 1;
1435 break;
1436 default:
1437 unreachable("not reached");
1438 }
1439
1440 }
1441
1442 /**
1443 * This function computes masks that may be used to select the bits of the X
1444 * and Y coordinates that indicate the offset within a tile. If the BO is
1445 * untiled, the masks are set to 0.
1446 */
1447 static void
1448 iris_resource_get_tile_masks(enum isl_tiling tiling, uint32_t cpp,
1449 uint32_t *mask_x, uint32_t *mask_y)
1450 {
1451 uint32_t tile_w_bytes, tile_h;
1452
1453 iris_resource_get_tile_dims(tiling, cpp, &tile_w_bytes, &tile_h);
1454
1455 *mask_x = tile_w_bytes / cpp - 1;
1456 *mask_y = tile_h - 1;
1457 }
1458
1459 /**
1460 * Compute the offset (in bytes) from the start of the BO to the given x
1461 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1462 * multiples of the tile size.
1463 */
1464 static uint32_t
1465 iris_resource_get_aligned_offset(const struct iris_resource *res,
1466 uint32_t x, uint32_t y)
1467 {
1468 const struct isl_format_layout *fmtl = isl_format_get_layout(res->surf.format);
1469 unsigned cpp = fmtl->bpb / 8;
1470 uint32_t pitch = res->surf.row_pitch_B;
1471
1472 switch (res->surf.tiling) {
1473 default:
1474 unreachable("not reached");
1475 case ISL_TILING_LINEAR:
1476 return y * pitch + x * cpp;
1477 case ISL_TILING_X:
1478 assert((x % (512 / cpp)) == 0);
1479 assert((y % 8) == 0);
1480 return y * pitch + x / (512 / cpp) * 4096;
1481 case ISL_TILING_Y0:
1482 assert((x % (128 / cpp)) == 0);
1483 assert((y % 32) == 0);
1484 return y * pitch + x / (128 / cpp) * 4096;
1485 }
1486 }
1487
1488 /**
1489 * Rendering with tiled buffers requires that the base address of the buffer
1490 * be aligned to a page boundary. For renderbuffers, and sometimes with
1491 * textures, we may want the surface to point at a texture image level that
1492 * isn't at a page boundary.
1493 *
1494 * This function returns an appropriately-aligned base offset
1495 * according to the tiling restrictions, plus any required x/y offset
1496 * from there.
1497 */
1498 uint32_t
1499 iris_resource_get_tile_offsets(const struct iris_resource *res,
1500 uint32_t level, uint32_t z,
1501 uint32_t *tile_x, uint32_t *tile_y)
1502 {
1503 uint32_t x, y;
1504 uint32_t mask_x, mask_y;
1505
1506 const struct isl_format_layout *fmtl = isl_format_get_layout(res->surf.format);
1507 const unsigned cpp = fmtl->bpb / 8;
1508
1509 iris_resource_get_tile_masks(res->surf.tiling, cpp, &mask_x, &mask_y);
1510 get_image_offset_el(&res->surf, level, z, &x, &y);
1511
1512 *tile_x = x & mask_x;
1513 *tile_y = y & mask_y;
1514
1515 return iris_resource_get_aligned_offset(res, x & ~mask_x, y & ~mask_y);
1516 }
1517
1518 /**
1519 * Get pointer offset into stencil buffer.
1520 *
1521 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1522 * must decode the tile's layout in software.
1523 *
1524 * See
1525 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1526 * Format.
1527 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1528 *
1529 * Even though the returned offset is always positive, the return type is
1530 * signed due to
1531 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1532 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1533 */
1534 static intptr_t
1535 s8_offset(uint32_t stride, uint32_t x, uint32_t y)
1536 {
1537 uint32_t tile_size = 4096;
1538 uint32_t tile_width = 64;
1539 uint32_t tile_height = 64;
1540 uint32_t row_size = 64 * stride / 2; /* Two rows are interleaved. */
1541
1542 uint32_t tile_x = x / tile_width;
1543 uint32_t tile_y = y / tile_height;
1544
1545 /* The byte's address relative to the tile's base addres. */
1546 uint32_t byte_x = x % tile_width;
1547 uint32_t byte_y = y % tile_height;
1548
1549 uintptr_t u = tile_y * row_size
1550 + tile_x * tile_size
1551 + 512 * (byte_x / 8)
1552 + 64 * (byte_y / 8)
1553 + 32 * ((byte_y / 4) % 2)
1554 + 16 * ((byte_x / 4) % 2)
1555 + 8 * ((byte_y / 2) % 2)
1556 + 4 * ((byte_x / 2) % 2)
1557 + 2 * (byte_y % 2)
1558 + 1 * (byte_x % 2);
1559
1560 return u;
1561 }
1562
1563 static void
1564 iris_unmap_s8(struct iris_transfer *map)
1565 {
1566 struct pipe_transfer *xfer = &map->base;
1567 const struct pipe_box *box = &xfer->box;
1568 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1569 struct isl_surf *surf = &res->surf;
1570
1571 if (xfer->usage & PIPE_TRANSFER_WRITE) {
1572 uint8_t *untiled_s8_map = map->ptr;
1573 uint8_t *tiled_s8_map =
1574 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1575
1576 for (int s = 0; s < box->depth; s++) {
1577 unsigned x0_el, y0_el;
1578 get_image_offset_el(surf, xfer->level, box->z + s, &x0_el, &y0_el);
1579
1580 for (uint32_t y = 0; y < box->height; y++) {
1581 for (uint32_t x = 0; x < box->width; x++) {
1582 ptrdiff_t offset = s8_offset(surf->row_pitch_B,
1583 x0_el + box->x + x,
1584 y0_el + box->y + y);
1585 tiled_s8_map[offset] =
1586 untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x];
1587 }
1588 }
1589 }
1590 }
1591
1592 free(map->buffer);
1593 }
1594
1595 static void
1596 iris_map_s8(struct iris_transfer *map)
1597 {
1598 struct pipe_transfer *xfer = &map->base;
1599 const struct pipe_box *box = &xfer->box;
1600 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1601 struct isl_surf *surf = &res->surf;
1602
1603 xfer->stride = surf->row_pitch_B;
1604 xfer->layer_stride = xfer->stride * box->height;
1605
1606 /* The tiling and detiling functions require that the linear buffer has
1607 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1608 * over-allocate the linear buffer to get the proper alignment.
1609 */
1610 map->buffer = map->ptr = malloc(xfer->layer_stride * box->depth);
1611 assert(map->buffer);
1612
1613 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1614 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1615 * invalidate is set, since we'll be writing the whole rectangle from our
1616 * temporary buffer back out.
1617 */
1618 if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
1619 uint8_t *untiled_s8_map = map->ptr;
1620 uint8_t *tiled_s8_map =
1621 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1622
1623 for (int s = 0; s < box->depth; s++) {
1624 unsigned x0_el, y0_el;
1625 get_image_offset_el(surf, xfer->level, box->z + s, &x0_el, &y0_el);
1626
1627 for (uint32_t y = 0; y < box->height; y++) {
1628 for (uint32_t x = 0; x < box->width; x++) {
1629 ptrdiff_t offset = s8_offset(surf->row_pitch_B,
1630 x0_el + box->x + x,
1631 y0_el + box->y + y);
1632 untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x] =
1633 tiled_s8_map[offset];
1634 }
1635 }
1636 }
1637 }
1638
1639 map->unmap = iris_unmap_s8;
1640 }
1641
1642 /* Compute extent parameters for use with tiled_memcpy functions.
1643 * xs are in units of bytes and ys are in units of strides.
1644 */
1645 static inline void
1646 tile_extents(const struct isl_surf *surf,
1647 const struct pipe_box *box,
1648 unsigned level, int z,
1649 unsigned *x1_B, unsigned *x2_B,
1650 unsigned *y1_el, unsigned *y2_el)
1651 {
1652 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1653 const unsigned cpp = fmtl->bpb / 8;
1654
1655 assert(box->x % fmtl->bw == 0);
1656 assert(box->y % fmtl->bh == 0);
1657
1658 unsigned x0_el, y0_el;
1659 get_image_offset_el(surf, level, box->z + z, &x0_el, &y0_el);
1660
1661 *x1_B = (box->x / fmtl->bw + x0_el) * cpp;
1662 *y1_el = box->y / fmtl->bh + y0_el;
1663 *x2_B = (DIV_ROUND_UP(box->x + box->width, fmtl->bw) + x0_el) * cpp;
1664 *y2_el = DIV_ROUND_UP(box->y + box->height, fmtl->bh) + y0_el;
1665 }
1666
1667 static void
1668 iris_unmap_tiled_memcpy(struct iris_transfer *map)
1669 {
1670 struct pipe_transfer *xfer = &map->base;
1671 const struct pipe_box *box = &xfer->box;
1672 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1673 struct isl_surf *surf = &res->surf;
1674
1675 const bool has_swizzling = false;
1676
1677 if (xfer->usage & PIPE_TRANSFER_WRITE) {
1678 char *dst =
1679 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1680
1681 for (int s = 0; s < box->depth; s++) {
1682 unsigned x1, x2, y1, y2;
1683 tile_extents(surf, box, xfer->level, s, &x1, &x2, &y1, &y2);
1684
1685 void *ptr = map->ptr + s * xfer->layer_stride;
1686
1687 isl_memcpy_linear_to_tiled(x1, x2, y1, y2, dst, ptr,
1688 surf->row_pitch_B, xfer->stride,
1689 has_swizzling, surf->tiling, ISL_MEMCPY);
1690 }
1691 }
1692 os_free_aligned(map->buffer);
1693 map->buffer = map->ptr = NULL;
1694 }
1695
1696 static void
1697 iris_map_tiled_memcpy(struct iris_transfer *map)
1698 {
1699 struct pipe_transfer *xfer = &map->base;
1700 const struct pipe_box *box = &xfer->box;
1701 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1702 struct isl_surf *surf = &res->surf;
1703
1704 xfer->stride = ALIGN(surf->row_pitch_B, 16);
1705 xfer->layer_stride = xfer->stride * box->height;
1706
1707 unsigned x1, x2, y1, y2;
1708 tile_extents(surf, box, xfer->level, 0, &x1, &x2, &y1, &y2);
1709
1710 /* The tiling and detiling functions require that the linear buffer has
1711 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1712 * over-allocate the linear buffer to get the proper alignment.
1713 */
1714 map->buffer =
1715 os_malloc_aligned(xfer->layer_stride * box->depth, 16);
1716 assert(map->buffer);
1717 map->ptr = (char *)map->buffer + (x1 & 0xf);
1718
1719 const bool has_swizzling = false;
1720
1721 if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
1722 char *src =
1723 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1724
1725 for (int s = 0; s < box->depth; s++) {
1726 unsigned x1, x2, y1, y2;
1727 tile_extents(surf, box, xfer->level, s, &x1, &x2, &y1, &y2);
1728
1729 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1730 void *ptr = map->ptr + s * xfer->layer_stride;
1731
1732 isl_memcpy_tiled_to_linear(x1, x2, y1, y2, ptr, src, xfer->stride,
1733 surf->row_pitch_B, has_swizzling,
1734 surf->tiling, ISL_MEMCPY_STREAMING_LOAD);
1735 }
1736 }
1737
1738 map->unmap = iris_unmap_tiled_memcpy;
1739 }
1740
1741 static void
1742 iris_map_direct(struct iris_transfer *map)
1743 {
1744 struct pipe_transfer *xfer = &map->base;
1745 struct pipe_box *box = &xfer->box;
1746 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1747
1748 void *ptr = iris_bo_map(map->dbg, res->bo, xfer->usage & MAP_FLAGS);
1749
1750 if (res->base.target == PIPE_BUFFER) {
1751 xfer->stride = 0;
1752 xfer->layer_stride = 0;
1753
1754 map->ptr = ptr + box->x;
1755 } else {
1756 struct isl_surf *surf = &res->surf;
1757 const struct isl_format_layout *fmtl =
1758 isl_format_get_layout(surf->format);
1759 const unsigned cpp = fmtl->bpb / 8;
1760 unsigned x0_el, y0_el;
1761
1762 get_image_offset_el(surf, xfer->level, box->z, &x0_el, &y0_el);
1763
1764 xfer->stride = isl_surf_get_row_pitch_B(surf);
1765 xfer->layer_stride = isl_surf_get_array_pitch(surf);
1766
1767 map->ptr = ptr + (y0_el + box->y) * xfer->stride + (x0_el + box->x) * cpp;
1768 }
1769 }
1770
1771 static bool
1772 can_promote_to_async(const struct iris_resource *res,
1773 const struct pipe_box *box,
1774 enum pipe_transfer_usage usage)
1775 {
1776 /* If we're writing to a section of the buffer that hasn't even been
1777 * initialized with useful data, then we can safely promote this write
1778 * to be unsynchronized. This helps the common pattern of appending data.
1779 */
1780 return res->base.target == PIPE_BUFFER && (usage & PIPE_TRANSFER_WRITE) &&
1781 !(usage & TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED) &&
1782 !util_ranges_intersect(&res->valid_buffer_range, box->x,
1783 box->x + box->width);
1784 }
1785
1786 static void *
1787 iris_transfer_map(struct pipe_context *ctx,
1788 struct pipe_resource *resource,
1789 unsigned level,
1790 enum pipe_transfer_usage usage,
1791 const struct pipe_box *box,
1792 struct pipe_transfer **ptransfer)
1793 {
1794 struct iris_context *ice = (struct iris_context *)ctx;
1795 struct iris_resource *res = (struct iris_resource *)resource;
1796 struct isl_surf *surf = &res->surf;
1797
1798 if (iris_resource_unfinished_aux_import(res))
1799 iris_resource_finish_aux_import(ctx->screen, res);
1800
1801 if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
1802 /* Replace the backing storage with a fresh buffer for non-async maps */
1803 if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED |
1804 TC_TRANSFER_MAP_NO_INVALIDATE)))
1805 iris_invalidate_resource(ctx, resource);
1806
1807 /* If we can discard the whole resource, we can discard the range. */
1808 usage |= PIPE_TRANSFER_DISCARD_RANGE;
1809 }
1810
1811 if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
1812 can_promote_to_async(res, box, usage)) {
1813 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1814 }
1815
1816 bool need_resolve = false;
1817 bool need_color_resolve = false;
1818
1819 if (resource->target != PIPE_BUFFER) {
1820 bool need_hiz_resolve = iris_resource_level_has_hiz(res, level);
1821 bool need_stencil_resolve = res->aux.usage == ISL_AUX_USAGE_STC_CCS;
1822
1823 need_color_resolve =
1824 (res->aux.usage == ISL_AUX_USAGE_CCS_D ||
1825 res->aux.usage == ISL_AUX_USAGE_CCS_E ||
1826 res->aux.usage == ISL_AUX_USAGE_GEN12_CCS_E) &&
1827 iris_has_color_unresolved(res, level, 1, box->z, box->depth);
1828
1829 need_resolve = need_color_resolve ||
1830 need_hiz_resolve ||
1831 need_stencil_resolve;
1832 }
1833
1834 bool map_would_stall = false;
1835
1836 if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
1837 map_would_stall = need_resolve || resource_is_busy(ice, res);
1838
1839 if (map_would_stall && (usage & PIPE_TRANSFER_DONTBLOCK) &&
1840 (usage & PIPE_TRANSFER_MAP_DIRECTLY))
1841 return NULL;
1842 }
1843
1844 if (surf->tiling != ISL_TILING_LINEAR &&
1845 (usage & PIPE_TRANSFER_MAP_DIRECTLY))
1846 return NULL;
1847
1848 struct iris_transfer *map = slab_alloc(&ice->transfer_pool);
1849 struct pipe_transfer *xfer = &map->base;
1850
1851 if (!map)
1852 return NULL;
1853
1854 memset(map, 0, sizeof(*map));
1855 map->dbg = &ice->dbg;
1856
1857 pipe_resource_reference(&xfer->resource, resource);
1858 xfer->level = level;
1859 xfer->usage = usage;
1860 xfer->box = *box;
1861 *ptransfer = xfer;
1862
1863 map->dest_had_defined_contents =
1864 util_ranges_intersect(&res->valid_buffer_range, box->x,
1865 box->x + box->width);
1866
1867 if (usage & PIPE_TRANSFER_WRITE)
1868 util_range_add(&res->base, &res->valid_buffer_range, box->x, box->x + box->width);
1869
1870 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1871 * there is to access them simultaneously on the CPU & GPU. This also
1872 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1873 * contain state we're constructing for a GPU draw call, which would
1874 * kill us with infinite stack recursion.
1875 */
1876 bool no_gpu = usage & (PIPE_TRANSFER_PERSISTENT |
1877 PIPE_TRANSFER_COHERENT |
1878 PIPE_TRANSFER_MAP_DIRECTLY);
1879
1880 /* GPU copies are not useful for buffer reads. Instead of stalling to
1881 * read from the original buffer, we'd simply copy it to a temporary...
1882 * then stall (a bit longer) to read from that buffer.
1883 *
1884 * Images are less clear-cut. Color resolves are destructive, removing
1885 * the underlying compression, so we'd rather blit the data to a linear
1886 * temporary and map that, to avoid the resolve. (It might be better to
1887 * a tiled temporary and use the tiled_memcpy paths...)
1888 */
1889 if (!(usage & PIPE_TRANSFER_DISCARD_RANGE) && !need_color_resolve)
1890 no_gpu = true;
1891
1892 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1893 if (fmtl->txc == ISL_TXC_ASTC)
1894 no_gpu = true;
1895
1896 if ((map_would_stall ||
1897 res->aux.usage == ISL_AUX_USAGE_CCS_E ||
1898 res->aux.usage == ISL_AUX_USAGE_GEN12_CCS_E) && !no_gpu) {
1899 /* If we need a synchronous mapping and the resource is busy, or needs
1900 * resolving, we copy to/from a linear temporary buffer using the GPU.
1901 */
1902 map->batch = &ice->batches[IRIS_BATCH_RENDER];
1903 map->blorp = &ice->blorp;
1904 iris_map_copy_region(map);
1905 } else {
1906 /* Otherwise we're free to map on the CPU. */
1907
1908 if (need_resolve) {
1909 iris_resource_access_raw(ice, res, level, box->z, box->depth,
1910 usage & PIPE_TRANSFER_WRITE);
1911 }
1912
1913 if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
1914 for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
1915 if (iris_batch_references(&ice->batches[i], res->bo))
1916 iris_batch_flush(&ice->batches[i]);
1917 }
1918 }
1919
1920 if (surf->tiling == ISL_TILING_W) {
1921 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1922 iris_map_s8(map);
1923 } else if (surf->tiling != ISL_TILING_LINEAR) {
1924 iris_map_tiled_memcpy(map);
1925 } else {
1926 iris_map_direct(map);
1927 }
1928 }
1929
1930 return map->ptr;
1931 }
1932
1933 static void
1934 iris_transfer_flush_region(struct pipe_context *ctx,
1935 struct pipe_transfer *xfer,
1936 const struct pipe_box *box)
1937 {
1938 struct iris_context *ice = (struct iris_context *)ctx;
1939 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1940 struct iris_transfer *map = (void *) xfer;
1941
1942 if (map->staging)
1943 iris_flush_staging_region(xfer, box);
1944
1945 uint32_t history_flush = 0;
1946
1947 if (res->base.target == PIPE_BUFFER) {
1948 if (map->staging)
1949 history_flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
1950
1951 if (map->dest_had_defined_contents)
1952 history_flush |= iris_flush_bits_for_history(res);
1953
1954 util_range_add(&res->base, &res->valid_buffer_range, box->x, box->x + box->width);
1955 }
1956
1957 if (history_flush & ~PIPE_CONTROL_CS_STALL) {
1958 for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
1959 struct iris_batch *batch = &ice->batches[i];
1960 if (batch->contains_draw || batch->cache.render->entries) {
1961 iris_batch_maybe_flush(batch, 24);
1962 iris_emit_pipe_control_flush(batch,
1963 "cache history: transfer flush",
1964 history_flush);
1965 }
1966 }
1967 }
1968
1969 /* Make sure we flag constants dirty even if there's no need to emit
1970 * any PIPE_CONTROLs to a batch.
1971 */
1972 iris_dirty_for_history(ice, res);
1973 }
1974
1975 static void
1976 iris_transfer_unmap(struct pipe_context *ctx, struct pipe_transfer *xfer)
1977 {
1978 struct iris_context *ice = (struct iris_context *)ctx;
1979 struct iris_transfer *map = (void *) xfer;
1980
1981 if (!(xfer->usage & (PIPE_TRANSFER_FLUSH_EXPLICIT |
1982 PIPE_TRANSFER_COHERENT))) {
1983 struct pipe_box flush_box = {
1984 .x = 0, .y = 0, .z = 0,
1985 .width = xfer->box.width,
1986 .height = xfer->box.height,
1987 .depth = xfer->box.depth,
1988 };
1989 iris_transfer_flush_region(ctx, xfer, &flush_box);
1990 }
1991
1992 if (map->unmap)
1993 map->unmap(map);
1994
1995 pipe_resource_reference(&xfer->resource, NULL);
1996 slab_free(&ice->transfer_pool, map);
1997 }
1998
1999 /**
2000 * The pipe->texture_subdata() driver hook.
2001 *
2002 * Mesa's state tracker takes this path whenever possible, even with
2003 * PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER set.
2004 */
2005 static void
2006 iris_texture_subdata(struct pipe_context *ctx,
2007 struct pipe_resource *resource,
2008 unsigned level,
2009 unsigned usage,
2010 const struct pipe_box *box,
2011 const void *data,
2012 unsigned stride,
2013 unsigned layer_stride)
2014 {
2015 struct iris_context *ice = (struct iris_context *)ctx;
2016 struct iris_resource *res = (struct iris_resource *)resource;
2017 const struct isl_surf *surf = &res->surf;
2018
2019 assert(resource->target != PIPE_BUFFER);
2020
2021 if (iris_resource_unfinished_aux_import(res))
2022 iris_resource_finish_aux_import(ctx->screen, res);
2023
2024 /* Just use the transfer-based path for linear buffers - it will already
2025 * do a direct mapping, or a simple linear staging buffer.
2026 *
2027 * Linear staging buffers appear to be better than tiled ones, too, so
2028 * take that path if we need the GPU to perform color compression, or
2029 * stall-avoidance blits.
2030 */
2031 if (surf->tiling == ISL_TILING_LINEAR ||
2032 (isl_aux_usage_has_ccs(res->aux.usage) &&
2033 res->aux.usage != ISL_AUX_USAGE_CCS_D) ||
2034 resource_is_busy(ice, res)) {
2035 return u_default_texture_subdata(ctx, resource, level, usage, box,
2036 data, stride, layer_stride);
2037 }
2038
2039 /* No state trackers pass any flags other than PIPE_TRANSFER_WRITE */
2040
2041 iris_resource_access_raw(ice, res, level, box->z, box->depth, true);
2042
2043 for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
2044 if (iris_batch_references(&ice->batches[i], res->bo))
2045 iris_batch_flush(&ice->batches[i]);
2046 }
2047
2048 uint8_t *dst = iris_bo_map(&ice->dbg, res->bo, MAP_WRITE | MAP_RAW);
2049
2050 for (int s = 0; s < box->depth; s++) {
2051 const uint8_t *src = data + s * layer_stride;
2052
2053 if (surf->tiling == ISL_TILING_W) {
2054 unsigned x0_el, y0_el;
2055 get_image_offset_el(surf, level, box->z + s, &x0_el, &y0_el);
2056
2057 for (unsigned y = 0; y < box->height; y++) {
2058 for (unsigned x = 0; x < box->width; x++) {
2059 ptrdiff_t offset = s8_offset(surf->row_pitch_B,
2060 x0_el + box->x + x,
2061 y0_el + box->y + y);
2062 dst[offset] = src[y * stride + x];
2063 }
2064 }
2065 } else {
2066 unsigned x1, x2, y1, y2;
2067
2068 tile_extents(surf, box, level, s, &x1, &x2, &y1, &y2);
2069
2070 isl_memcpy_linear_to_tiled(x1, x2, y1, y2,
2071 (void *)dst, (void *)src,
2072 surf->row_pitch_B, stride,
2073 false, surf->tiling, ISL_MEMCPY);
2074 }
2075 }
2076 }
2077
2078 /**
2079 * Mark state dirty that needs to be re-emitted when a resource is written.
2080 */
2081 void
2082 iris_dirty_for_history(struct iris_context *ice,
2083 struct iris_resource *res)
2084 {
2085 uint64_t stage_dirty = 0ull;
2086
2087 if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
2088 stage_dirty |= ((uint64_t)res->bind_stages)
2089 << IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS;
2090 }
2091
2092 ice->state.stage_dirty |= stage_dirty;
2093 }
2094
2095 /**
2096 * Produce a set of PIPE_CONTROL bits which ensure data written to a
2097 * resource becomes visible, and any stale read cache data is invalidated.
2098 */
2099 uint32_t
2100 iris_flush_bits_for_history(struct iris_resource *res)
2101 {
2102 uint32_t flush = PIPE_CONTROL_CS_STALL;
2103
2104 if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
2105 flush |= PIPE_CONTROL_CONST_CACHE_INVALIDATE |
2106 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
2107 }
2108
2109 if (res->bind_history & PIPE_BIND_SAMPLER_VIEW)
2110 flush |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
2111
2112 if (res->bind_history & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
2113 flush |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
2114
2115 if (res->bind_history & (PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE))
2116 flush |= PIPE_CONTROL_DATA_CACHE_FLUSH;
2117
2118 return flush;
2119 }
2120
2121 void
2122 iris_flush_and_dirty_for_history(struct iris_context *ice,
2123 struct iris_batch *batch,
2124 struct iris_resource *res,
2125 uint32_t extra_flags,
2126 const char *reason)
2127 {
2128 if (res->base.target != PIPE_BUFFER)
2129 return;
2130
2131 uint32_t flush = iris_flush_bits_for_history(res) | extra_flags;
2132
2133 iris_emit_pipe_control_flush(batch, reason, flush);
2134
2135 iris_dirty_for_history(ice, res);
2136 }
2137
2138 bool
2139 iris_resource_set_clear_color(struct iris_context *ice,
2140 struct iris_resource *res,
2141 union isl_color_value color)
2142 {
2143 if (memcmp(&res->aux.clear_color, &color, sizeof(color)) != 0) {
2144 res->aux.clear_color = color;
2145 return true;
2146 }
2147
2148 return false;
2149 }
2150
2151 union isl_color_value
2152 iris_resource_get_clear_color(const struct iris_resource *res,
2153 struct iris_bo **clear_color_bo,
2154 uint64_t *clear_color_offset)
2155 {
2156 assert(res->aux.bo);
2157
2158 if (clear_color_bo)
2159 *clear_color_bo = res->aux.clear_color_bo;
2160 if (clear_color_offset)
2161 *clear_color_offset = res->aux.clear_color_offset;
2162 return res->aux.clear_color;
2163 }
2164
2165 static enum pipe_format
2166 iris_resource_get_internal_format(struct pipe_resource *p_res)
2167 {
2168 struct iris_resource *res = (void *) p_res;
2169 return res->internal_format;
2170 }
2171
2172 static const struct u_transfer_vtbl transfer_vtbl = {
2173 .resource_create = iris_resource_create,
2174 .resource_destroy = iris_resource_destroy,
2175 .transfer_map = iris_transfer_map,
2176 .transfer_unmap = iris_transfer_unmap,
2177 .transfer_flush_region = iris_transfer_flush_region,
2178 .get_internal_format = iris_resource_get_internal_format,
2179 .set_stencil = iris_resource_set_separate_stencil,
2180 .get_stencil = iris_resource_get_separate_stencil,
2181 };
2182
2183 void
2184 iris_init_screen_resource_functions(struct pipe_screen *pscreen)
2185 {
2186 pscreen->query_dmabuf_modifiers = iris_query_dmabuf_modifiers;
2187 pscreen->resource_create_with_modifiers =
2188 iris_resource_create_with_modifiers;
2189 pscreen->resource_create = u_transfer_helper_resource_create;
2190 pscreen->resource_from_user_memory = iris_resource_from_user_memory;
2191 pscreen->resource_from_handle = iris_resource_from_handle;
2192 pscreen->resource_get_handle = iris_resource_get_handle;
2193 pscreen->resource_get_param = iris_resource_get_param;
2194 pscreen->resource_destroy = u_transfer_helper_resource_destroy;
2195 pscreen->transfer_helper =
2196 u_transfer_helper_create(&transfer_vtbl, true, true, false, true);
2197 }
2198
2199 void
2200 iris_init_resource_functions(struct pipe_context *ctx)
2201 {
2202 ctx->flush_resource = iris_flush_resource;
2203 ctx->invalidate_resource = iris_invalidate_resource;
2204 ctx->transfer_map = u_transfer_helper_transfer_map;
2205 ctx->transfer_flush_region = u_transfer_helper_transfer_flush_region;
2206 ctx->transfer_unmap = u_transfer_helper_transfer_unmap;
2207 ctx->buffer_subdata = u_default_buffer_subdata;
2208 ctx->texture_subdata = iris_texture_subdata;
2209 }