2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/dev/gen_debug.h"
52 #include "drm-uapi/drm_fourcc.h"
53 #include "drm-uapi/i915_drm.h"
55 enum modifier_priority
{
56 MODIFIER_PRIORITY_INVALID
= 0,
57 MODIFIER_PRIORITY_LINEAR
,
60 MODIFIER_PRIORITY_Y_CCS
,
63 static const uint64_t priority_to_modifier
[] = {
64 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
65 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
66 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
67 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
68 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
72 modifier_is_supported(const struct gen_device_info
*devinfo
,
73 enum pipe_format pfmt
, uint64_t modifier
)
75 /* XXX: do something real */
77 case I915_FORMAT_MOD_Y_TILED_CCS
: {
78 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
81 enum isl_format rt_format
=
82 iris_format_for_usage(devinfo
, pfmt
,
83 ISL_SURF_USAGE_RENDER_TARGET_BIT
).fmt
;
85 enum isl_format linear_format
= isl_format_srgb_to_linear(rt_format
);
87 if (!isl_format_supports_ccs_e(devinfo
, linear_format
))
92 case I915_FORMAT_MOD_Y_TILED
:
93 case I915_FORMAT_MOD_X_TILED
:
94 case DRM_FORMAT_MOD_LINEAR
:
96 case DRM_FORMAT_MOD_INVALID
:
103 select_best_modifier(struct gen_device_info
*devinfo
, enum pipe_format pfmt
,
104 const uint64_t *modifiers
,
107 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
109 for (int i
= 0; i
< count
; i
++) {
110 if (!modifier_is_supported(devinfo
, pfmt
, modifiers
[i
]))
113 switch (modifiers
[i
]) {
114 case I915_FORMAT_MOD_Y_TILED_CCS
:
115 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
117 case I915_FORMAT_MOD_Y_TILED
:
118 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
120 case I915_FORMAT_MOD_X_TILED
:
121 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
123 case DRM_FORMAT_MOD_LINEAR
:
124 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
126 case DRM_FORMAT_MOD_INVALID
:
132 return priority_to_modifier
[prio
];
135 static enum isl_surf_dim
136 target_to_isl_surf_dim(enum pipe_texture_target target
)
140 case PIPE_TEXTURE_1D
:
141 case PIPE_TEXTURE_1D_ARRAY
:
142 return ISL_SURF_DIM_1D
;
143 case PIPE_TEXTURE_2D
:
144 case PIPE_TEXTURE_CUBE
:
145 case PIPE_TEXTURE_RECT
:
146 case PIPE_TEXTURE_2D_ARRAY
:
147 case PIPE_TEXTURE_CUBE_ARRAY
:
148 return ISL_SURF_DIM_2D
;
149 case PIPE_TEXTURE_3D
:
150 return ISL_SURF_DIM_3D
;
151 case PIPE_MAX_TEXTURE_TYPES
:
154 unreachable("invalid texture type");
158 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
159 enum pipe_format pfmt
,
162 unsigned int *external_only
,
165 struct iris_screen
*screen
= (void *) pscreen
;
166 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
168 uint64_t all_modifiers
[] = {
169 DRM_FORMAT_MOD_LINEAR
,
170 I915_FORMAT_MOD_X_TILED
,
171 I915_FORMAT_MOD_Y_TILED
,
172 I915_FORMAT_MOD_Y_TILED_CCS
,
175 int supported_mods
= 0;
177 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
178 if (!modifier_is_supported(devinfo
, pfmt
, all_modifiers
[i
]))
181 if (supported_mods
< max
) {
183 modifiers
[supported_mods
] = all_modifiers
[i
];
186 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
192 *count
= supported_mods
;
195 static isl_surf_usage_flags_t
196 pipe_bind_to_isl_usage(unsigned bindings
)
198 isl_surf_usage_flags_t usage
= 0;
200 if (bindings
& PIPE_BIND_RENDER_TARGET
)
201 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
203 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
204 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
206 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
207 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
209 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
210 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
215 struct pipe_resource
*
216 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
218 /* For packed depth-stencil, we treat depth as the primary resource
219 * and store S8 as the "second plane" resource.
221 if (p_res
->next
&& p_res
->next
->format
== PIPE_FORMAT_S8_UINT
)
229 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
230 struct pipe_resource
*stencil
)
232 assert(util_format_has_depth(util_format_description(p_res
->format
)));
233 pipe_resource_reference(&p_res
->next
, stencil
);
237 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
238 struct iris_resource
**out_z
,
239 struct iris_resource
**out_s
)
247 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
248 *out_z
= (void *) res
;
249 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
252 *out_s
= (void *) res
;
257 iris_resource_disable_aux(struct iris_resource
*res
)
259 iris_bo_unreference(res
->aux
.bo
);
260 iris_bo_unreference(res
->aux
.clear_color_bo
);
261 free(res
->aux
.state
);
263 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
264 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
265 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
266 res
->aux
.surf
.size_B
= 0;
268 res
->aux
.clear_color_bo
= NULL
;
269 res
->aux
.state
= NULL
;
273 iris_resource_destroy(struct pipe_screen
*screen
,
274 struct pipe_resource
*resource
)
276 struct iris_resource
*res
= (struct iris_resource
*)resource
;
278 if (resource
->target
== PIPE_BUFFER
)
279 util_range_destroy(&res
->valid_buffer_range
);
281 iris_resource_disable_aux(res
);
283 iris_bo_unreference(res
->bo
);
287 static struct iris_resource
*
288 iris_alloc_resource(struct pipe_screen
*pscreen
,
289 const struct pipe_resource
*templ
)
291 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
296 res
->base
.screen
= pscreen
;
297 pipe_reference_init(&res
->base
.reference
, 1);
299 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
300 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
302 if (templ
->target
== PIPE_BUFFER
)
303 util_range_init(&res
->valid_buffer_range
);
309 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
311 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
312 return minify(res
->surf
.logical_level0_px
.depth
, level
);
314 return res
->surf
.logical_level0_px
.array_len
;
317 static enum isl_aux_state
**
318 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
320 uint32_t total_slices
= 0;
321 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
322 total_slices
+= iris_get_num_logical_layers(res
, level
);
324 const size_t per_level_array_size
=
325 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
327 /* We're going to allocate a single chunk of data for both the per-level
328 * reference array and the arrays of aux_state. This makes cleanup
329 * significantly easier.
331 const size_t total_size
=
332 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
334 void *data
= malloc(total_size
);
338 enum isl_aux_state
**per_level_arr
= data
;
339 enum isl_aux_state
*s
= data
+ per_level_array_size
;
340 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
341 per_level_arr
[level
] = s
;
342 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
343 for (uint32_t a
= 0; a
< level_layers
; a
++)
346 assert((void *)s
== data
+ total_size
);
348 return per_level_arr
;
352 iris_get_aux_clear_color_state_size(struct iris_screen
*screen
)
354 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
356 (devinfo
->gen
>= 10 ? screen
->isl_dev
.ss
.clear_color_state_size
:
357 (devinfo
->gen
>= 9 ? screen
->isl_dev
.ss
.clear_value_size
: 0));
361 * Configure aux for the resource, but don't allocate it. For images which
362 * might be shared with modifiers, we must allocate the image and aux data in
366 iris_resource_configure_aux(struct iris_screen
*screen
,
367 struct iris_resource
*res
, bool imported
,
368 uint64_t *aux_size_B
,
369 uint32_t *alloc_flags
)
371 struct isl_device
*isl_dev
= &screen
->isl_dev
;
372 enum isl_aux_state initial_state
;
373 UNUSED
bool ok
= false;
377 assert(!res
->aux
.bo
);
379 switch (res
->aux
.usage
) {
380 case ISL_AUX_USAGE_NONE
:
381 res
->aux
.surf
.size_B
= 0;
384 case ISL_AUX_USAGE_HIZ
:
385 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
386 ok
= isl_surf_get_hiz_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
388 case ISL_AUX_USAGE_MCS
:
389 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
391 * "When MCS buffer is enabled and bound to MSRT, it is required
392 * that it is cleared prior to any rendering."
394 * Since we only use the MCS buffer for rendering, we just clear it
395 * immediately on allocation. The clear value for MCS buffers is all
396 * 1's, so we simply memset it to 0xff.
398 initial_state
= ISL_AUX_STATE_CLEAR
;
399 ok
= isl_surf_get_mcs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
);
401 case ISL_AUX_USAGE_CCS_D
:
402 case ISL_AUX_USAGE_CCS_E
:
403 /* When CCS_E is used, we need to ensure that the CCS starts off in
404 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
407 * "If Software wants to enable Color Compression without Fast
408 * clear, Software needs to initialize MCS with zeros."
410 * A CCS value of 0 indicates that the corresponding block is in the
411 * pass-through state which is what we want.
413 * For CCS_D, do the same thing. On Gen9+, this avoids having any
414 * undefined bits in the aux buffer.
418 isl_drm_modifier_get_default_aux_state(res
->mod_info
->modifier
);
420 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
421 *alloc_flags
|= BO_ALLOC_ZEROED
;
422 ok
= isl_surf_get_ccs_surf(isl_dev
, &res
->surf
, &res
->aux
.surf
, 0);
426 /* We should have a valid aux_surf. */
430 /* No work is needed for a zero-sized auxiliary buffer. */
431 if (res
->aux
.surf
.size_B
== 0)
434 if (!res
->aux
.state
) {
435 /* Create the aux_state for the auxiliary buffer. */
436 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
441 uint64_t size
= res
->aux
.surf
.size_B
;
443 /* Allocate space in the buffer for storing the clear color. On modern
444 * platforms (gen > 9), we can read it directly from such buffer.
446 * On gen <= 9, we are going to store the clear color on the buffer
447 * anyways, and copy it back to the surface state during state emission.
449 res
->aux
.clear_color_offset
= size
;
450 size
+= iris_get_aux_clear_color_state_size(screen
);
453 if (res
->aux
.usage
== ISL_AUX_USAGE_HIZ
) {
454 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
455 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
456 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
458 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
459 * For LOD == 0, we can grow the dimensions to make it work.
461 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
462 res
->aux
.has_hiz
|= 1 << level
;
470 * Initialize the aux buffer contents.
473 iris_resource_init_aux_buf(struct iris_resource
*res
, uint32_t alloc_flags
,
474 unsigned clear_color_state_size
)
476 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
477 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
480 iris_resource_disable_aux(res
);
484 if (iris_resource_get_aux_state(res
, 0, 0) != ISL_AUX_STATE_AUX_INVALID
) {
485 uint8_t memset_value
= res
->aux
.usage
== ISL_AUX_USAGE_MCS
? 0xFF : 0;
486 memset((char*)map
+ res
->aux
.offset
, memset_value
,
487 res
->aux
.surf
.size_B
);
490 /* Zero the indirect clear color to match ::fast_clear_color. */
491 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
492 clear_color_state_size
);
494 iris_bo_unmap(res
->aux
.bo
);
497 if (clear_color_state_size
> 0) {
498 res
->aux
.clear_color_bo
= res
->aux
.bo
;
499 iris_bo_reference(res
->aux
.clear_color_bo
);
506 * Allocate the initial aux surface for a resource based on aux.usage
509 iris_resource_alloc_separate_aux(struct iris_screen
*screen
,
510 struct iris_resource
*res
)
512 uint32_t alloc_flags
;
514 if (!iris_resource_configure_aux(screen
, res
, false, &size
, &alloc_flags
))
520 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
521 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
522 * of bytes instead of trying to recalculate based on different format
525 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
, 4096,
526 IRIS_MEMZONE_OTHER
, I915_TILING_Y
,
527 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
532 if (!iris_resource_init_aux_buf(res
, alloc_flags
,
533 iris_get_aux_clear_color_state_size(screen
)))
540 iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
541 struct iris_resource
*res
)
543 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
544 assert(iris_resource_unfinished_aux_import(res
));
545 assert(!res
->mod_info
->supports_clear_color
);
547 struct iris_resource
*aux_res
= (void *) res
->base
.next
;
548 assert(aux_res
->aux
.surf
.row_pitch_B
&& aux_res
->aux
.offset
&&
551 assert(res
->bo
== aux_res
->aux
.bo
);
552 iris_bo_reference(aux_res
->aux
.bo
);
553 res
->aux
.bo
= aux_res
->aux
.bo
;
555 res
->aux
.offset
= aux_res
->aux
.offset
;
557 assert(res
->bo
->size
>= (res
->aux
.offset
+ res
->aux
.surf
.size_B
));
558 assert(res
->aux
.clear_color_bo
== NULL
);
559 res
->aux
.clear_color_offset
= 0;
561 assert(aux_res
->aux
.surf
.row_pitch_B
== res
->aux
.surf
.row_pitch_B
);
563 unsigned clear_color_state_size
=
564 iris_get_aux_clear_color_state_size(screen
);
566 if (clear_color_state_size
> 0) {
567 res
->aux
.clear_color_bo
=
568 iris_bo_alloc(screen
->bufmgr
, "clear color buffer",
569 clear_color_state_size
, IRIS_MEMZONE_OTHER
);
570 res
->aux
.clear_color_offset
= 0;
573 iris_resource_destroy(&screen
->base
, res
->base
.next
);
574 res
->base
.next
= NULL
;
578 supports_mcs(const struct isl_surf
*surf
)
580 /* MCS compression only applies to multisampled resources. */
581 if (surf
->samples
<= 1)
584 /* Depth and stencil buffers use the IMS (interleaved) layout. */
585 if (isl_surf_usage_is_depth_or_stencil(surf
->usage
))
592 supports_ccs(const struct gen_device_info
*devinfo
,
593 const struct isl_surf
*surf
)
595 /* CCS only supports singlesampled resources. */
596 if (surf
->samples
> 1)
599 /* Note: still need to check the format! */
604 static struct pipe_resource
*
605 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
606 const struct pipe_resource
*templ
)
608 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
609 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
611 assert(templ
->target
== PIPE_BUFFER
);
612 assert(templ
->height0
<= 1);
613 assert(templ
->depth0
<= 1);
614 assert(templ
->format
== PIPE_FORMAT_NONE
||
615 util_format_get_blocksize(templ
->format
) == 1);
617 res
->internal_format
= templ
->format
;
618 res
->surf
.tiling
= ISL_TILING_LINEAR
;
620 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
621 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
622 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
623 memzone
= IRIS_MEMZONE_SHADER
;
624 name
= "shader kernels";
625 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
626 memzone
= IRIS_MEMZONE_SURFACE
;
627 name
= "surface state";
628 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
629 memzone
= IRIS_MEMZONE_DYNAMIC
;
630 name
= "dynamic state";
633 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
635 iris_resource_destroy(pscreen
, &res
->base
);
642 static struct pipe_resource
*
643 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
644 const struct pipe_resource
*templ
,
645 const uint64_t *modifiers
,
648 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
649 struct gen_device_info
*devinfo
= &screen
->devinfo
;
650 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
655 const struct util_format_description
*format_desc
=
656 util_format_description(templ
->format
);
657 const bool has_depth
= util_format_has_depth(format_desc
);
659 select_best_modifier(devinfo
, templ
->format
, modifiers
, modifiers_count
);
661 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
663 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
664 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
666 tiling_flags
= 1 << res
->mod_info
->tiling
;
668 if (modifiers_count
> 0) {
669 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
673 /* No modifiers - we can select our own tiling. */
676 /* Depth must be Y-tiled */
677 tiling_flags
= ISL_TILING_Y0_BIT
;
678 } else if (templ
->format
== PIPE_FORMAT_S8_UINT
) {
679 /* Stencil must be W-tiled */
680 tiling_flags
= ISL_TILING_W_BIT
;
681 } else if (templ
->target
== PIPE_BUFFER
||
682 templ
->target
== PIPE_TEXTURE_1D
||
683 templ
->target
== PIPE_TEXTURE_1D_ARRAY
) {
684 /* Use linear for buffers and 1D textures */
685 tiling_flags
= ISL_TILING_LINEAR_BIT
;
688 /* Use linear for staging buffers */
689 if (templ
->usage
== PIPE_USAGE_STAGING
||
690 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
691 tiling_flags
= ISL_TILING_LINEAR_BIT
;
694 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
696 if (templ
->target
== PIPE_TEXTURE_CUBE
||
697 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
698 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
700 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
701 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
702 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
704 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
707 enum pipe_format pfmt
= templ
->format
;
708 res
->internal_format
= pfmt
;
710 /* Should be handled by u_transfer_helper */
711 assert(!util_format_is_depth_and_stencil(pfmt
));
713 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
714 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
716 UNUSED
const bool isl_surf_created_successfully
=
717 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
718 .dim
= target_to_isl_surf_dim(templ
->target
),
720 .width
= templ
->width0
,
721 .height
= templ
->height0
,
722 .depth
= templ
->depth0
,
723 .levels
= templ
->last_level
+ 1,
724 .array_len
= templ
->array_size
,
725 .samples
= MAX2(templ
->nr_samples
, 1),
726 .min_alignment_B
= 0,
729 .tiling_flags
= tiling_flags
);
730 assert(isl_surf_created_successfully
);
733 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
734 } else if (supports_mcs(&res
->surf
)) {
735 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_MCS
;
736 } else if (has_depth
) {
737 if (likely(!(INTEL_DEBUG
& DEBUG_NO_HIZ
)))
738 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
739 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO_RBC
)) &&
740 supports_ccs(devinfo
, &res
->surf
)) {
741 if (isl_format_supports_ccs_e(devinfo
, res
->surf
.format
))
742 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_E
;
744 if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
))
745 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
748 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
750 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
752 /* We don't always support sampling with hiz. But when we do, it must be
755 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1) {
756 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
759 const char *name
= "miptree";
760 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
762 unsigned int flags
= 0;
763 if (templ
->usage
== PIPE_USAGE_STAGING
)
764 flags
|= BO_ALLOC_COHERENT
;
766 /* These are for u_upload_mgr buffers only */
767 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
768 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
769 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
771 uint32_t aux_preferred_alloc_flags
;
772 uint64_t aux_size
= 0;
774 iris_resource_configure_aux(screen
, res
, false, &aux_size
,
775 &aux_preferred_alloc_flags
);
776 aux_enabled
= aux_enabled
&& res
->aux
.surf
.size_B
> 0;
777 const bool separate_aux
= aux_enabled
&& !res
->mod_info
;
781 if (aux_enabled
&& !separate_aux
) {
782 /* Allocate aux data with main surface. This is required for modifiers
783 * with aux data (ccs).
785 aux_offset
= ALIGN(res
->surf
.size_B
, res
->aux
.surf
.alignment_B
);
786 bo_size
= aux_offset
+ aux_size
;
789 bo_size
= res
->surf
.size_B
;
792 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, bo_size
, 4096, memzone
,
793 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
794 res
->surf
.row_pitch_B
, flags
);
801 if (!iris_resource_alloc_separate_aux(screen
, res
))
804 res
->aux
.bo
= res
->bo
;
805 iris_bo_reference(res
->aux
.bo
);
806 res
->aux
.offset
+= aux_offset
;
807 unsigned clear_color_state_size
=
808 iris_get_aux_clear_color_state_size(screen
);
809 if (clear_color_state_size
> 0)
810 res
->aux
.clear_color_offset
+= aux_offset
;
811 if (!iris_resource_init_aux_buf(res
, flags
, clear_color_state_size
))
817 iris_resource_disable_aux(res
);
822 fprintf(stderr
, "XXX: resource creation failed\n");
823 iris_resource_destroy(pscreen
, &res
->base
);
828 static struct pipe_resource
*
829 iris_resource_create(struct pipe_screen
*pscreen
,
830 const struct pipe_resource
*templ
)
832 if (templ
->target
== PIPE_BUFFER
)
833 return iris_resource_create_for_buffer(pscreen
, templ
);
835 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
839 tiling_to_modifier(uint32_t tiling
)
841 static const uint64_t map
[] = {
842 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
843 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
844 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
847 assert(tiling
< ARRAY_SIZE(map
));
852 static struct pipe_resource
*
853 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
854 const struct pipe_resource
*templ
,
857 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
858 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
859 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
863 assert(templ
->target
== PIPE_BUFFER
);
865 res
->internal_format
= templ
->format
;
866 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
867 user_memory
, templ
->width0
,
874 util_range_add(&res
->valid_buffer_range
, 0, templ
->width0
);
879 static struct pipe_resource
*
880 iris_resource_from_handle(struct pipe_screen
*pscreen
,
881 const struct pipe_resource
*templ
,
882 struct winsys_handle
*whandle
,
885 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
886 struct gen_device_info
*devinfo
= &screen
->devinfo
;
887 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
888 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
892 switch (whandle
->type
) {
893 case WINSYS_HANDLE_TYPE_FD
:
894 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
);
896 case WINSYS_HANDLE_TYPE_SHARED
:
897 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
901 unreachable("invalid winsys handle type");
906 res
->offset
= whandle
->offset
;
908 uint64_t modifier
= whandle
->modifier
;
909 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
910 modifier
= tiling_to_modifier(res
->bo
->tiling_mode
);
912 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
913 assert(res
->mod_info
);
915 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
917 const struct iris_format_info fmt
=
918 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
919 res
->internal_format
= templ
->format
;
921 if (templ
->target
== PIPE_BUFFER
) {
922 res
->surf
.tiling
= ISL_TILING_LINEAR
;
924 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
|| whandle
->plane
== 0) {
925 UNUSED
const bool isl_surf_created_successfully
=
926 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
927 .dim
= target_to_isl_surf_dim(templ
->target
),
929 .width
= templ
->width0
,
930 .height
= templ
->height0
,
931 .depth
= templ
->depth0
,
932 .levels
= templ
->last_level
+ 1,
933 .array_len
= templ
->array_size
,
934 .samples
= MAX2(templ
->nr_samples
, 1),
935 .min_alignment_B
= 0,
936 .row_pitch_B
= whandle
->stride
,
938 .tiling_flags
= 1 << res
->mod_info
->tiling
);
939 assert(isl_surf_created_successfully
);
940 assert(res
->bo
->tiling_mode
==
941 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
943 // XXX: create_ccs_buf_for_image?
944 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
) {
945 if (!iris_resource_alloc_separate_aux(screen
, res
))
948 if (res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
949 uint32_t alloc_flags
;
951 res
->aux
.usage
= res
->mod_info
->aux_usage
;
952 res
->aux
.possible_usages
= 1 << res
->mod_info
->aux_usage
;
953 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
954 bool ok
= iris_resource_configure_aux(screen
, res
, true, &size
,
957 /* The gallium dri layer will create a separate plane resource
958 * for the aux image. iris_resource_finish_aux_import will
959 * merge the separate aux parameters back into a single
965 /* Save modifier import information to reconstruct later. After
966 * import, this will be available under a second image accessible
967 * from the main image with res->base.next. See
968 * iris_resource_finish_aux_import.
970 res
->aux
.surf
.row_pitch_B
= whandle
->stride
;
971 res
->aux
.offset
= whandle
->offset
;
972 res
->aux
.bo
= res
->bo
;
980 iris_resource_destroy(pscreen
, &res
->base
);
985 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
987 struct iris_context
*ice
= (struct iris_context
*)ctx
;
988 struct iris_batch
*render_batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
989 struct iris_resource
*res
= (void *) resource
;
990 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
992 iris_resource_prepare_access(ice
, render_batch
, res
,
993 0, INTEL_REMAINING_LEVELS
,
994 0, INTEL_REMAINING_LAYERS
,
995 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
996 mod
? mod
->supports_clear_color
: false);
1000 iris_resource_get_param(struct pipe_screen
*screen
,
1001 struct pipe_resource
*resource
,
1003 enum pipe_resource_param param
,
1006 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1008 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1009 bool wants_aux
= mod_with_aux
&& plane
> 0;
1010 struct iris_bo
*bo
= wants_aux
? res
->aux
.bo
: res
->bo
;
1015 case PIPE_RESOURCE_PARAM_NPLANES
:
1016 *value
= mod_with_aux
? 2 : 1;
1018 case PIPE_RESOURCE_PARAM_STRIDE
:
1019 *value
= wants_aux
? res
->aux
.surf
.row_pitch_B
: res
->surf
.row_pitch_B
;
1021 case PIPE_RESOURCE_PARAM_OFFSET
:
1022 *value
= wants_aux
? res
->aux
.offset
: 0;
1024 case PIPE_RESOURCE_PARAM_MODIFIER
:
1025 *value
= res
->mod_info
? res
->mod_info
->modifier
:
1026 tiling_to_modifier(res
->bo
->tiling_mode
);
1028 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
1029 result
= iris_bo_flink(bo
, &handle
) == 0;
1033 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
:
1034 *value
= iris_bo_export_gem_handle(bo
);
1036 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
1037 result
= iris_bo_export_dmabuf(bo
, (int *) &handle
) == 0;
1047 iris_resource_get_handle(struct pipe_screen
*pscreen
,
1048 struct pipe_context
*ctx
,
1049 struct pipe_resource
*resource
,
1050 struct winsys_handle
*whandle
,
1053 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1055 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1057 /* Disable aux usage if explicit flush not set and this is the first time
1058 * we are dealing with this resource and the resource was not created with
1059 * a modifier with aux.
1061 if (!mod_with_aux
&&
1062 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0) &&
1063 p_atomic_read(&resource
->reference
.count
) == 1) {
1064 iris_resource_disable_aux(res
);
1068 if (mod_with_aux
&& whandle
->plane
> 0) {
1069 assert(res
->aux
.bo
);
1071 whandle
->stride
= res
->aux
.surf
.row_pitch_B
;
1072 whandle
->offset
= res
->aux
.offset
;
1074 /* If this is a buffer, stride should be 0 - no need to special case */
1075 whandle
->stride
= res
->surf
.row_pitch_B
;
1079 res
->mod_info
? res
->mod_info
->modifier
1080 : tiling_to_modifier(res
->bo
->tiling_mode
);
1083 enum isl_aux_usage allowed_usage
=
1084 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
1086 if (res
->aux
.usage
!= allowed_usage
) {
1087 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
1088 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
1089 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
1093 switch (whandle
->type
) {
1094 case WINSYS_HANDLE_TYPE_SHARED
:
1095 return iris_bo_flink(bo
, &whandle
->handle
) == 0;
1096 case WINSYS_HANDLE_TYPE_KMS
:
1097 whandle
->handle
= iris_bo_export_gem_handle(bo
);
1099 case WINSYS_HANDLE_TYPE_FD
:
1100 return iris_bo_export_dmabuf(bo
, (int *) &whandle
->handle
) == 0;
1107 resource_is_busy(struct iris_context
*ice
,
1108 struct iris_resource
*res
)
1110 bool busy
= iris_bo_busy(res
->bo
);
1112 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1113 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1119 iris_invalidate_resource(struct pipe_context
*ctx
,
1120 struct pipe_resource
*resource
)
1122 struct iris_screen
*screen
= (void *) ctx
->screen
;
1123 struct iris_context
*ice
= (void *) ctx
;
1124 struct iris_resource
*res
= (void *) resource
;
1126 if (resource
->target
!= PIPE_BUFFER
)
1129 if (!resource_is_busy(ice
, res
)) {
1130 /* The resource is idle, so just mark that it contains no data and
1131 * keep using the same underlying buffer object.
1133 util_range_set_empty(&res
->valid_buffer_range
);
1137 /* Otherwise, try and replace the backing storage with a new BO. */
1139 /* We can't reallocate memory we didn't allocate in the first place. */
1140 if (res
->bo
->userptr
)
1143 // XXX: We should support this.
1144 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
1147 struct iris_bo
*old_bo
= res
->bo
;
1148 struct iris_bo
*new_bo
=
1149 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
1150 iris_memzone_for_address(old_bo
->gtt_offset
));
1154 /* Swap out the backing storage */
1157 /* Rebind the buffer, replacing any state referring to the old BO's
1158 * address, and marking state dirty so it's reemitted.
1160 ice
->vtbl
.rebind_buffer(ice
, res
, old_bo
->gtt_offset
);
1162 util_range_set_empty(&res
->valid_buffer_range
);
1164 iris_bo_unreference(old_bo
);
1168 iris_flush_staging_region(struct pipe_transfer
*xfer
,
1169 const struct pipe_box
*flush_box
)
1171 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
1174 struct iris_transfer
*map
= (void *) xfer
;
1176 struct pipe_box src_box
= *flush_box
;
1178 /* Account for extra alignment padding in staging buffer */
1179 if (xfer
->resource
->target
== PIPE_BUFFER
)
1180 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
1182 struct pipe_box dst_box
= (struct pipe_box
) {
1183 .x
= xfer
->box
.x
+ flush_box
->x
,
1184 .y
= xfer
->box
.y
+ flush_box
->y
,
1185 .z
= xfer
->box
.z
+ flush_box
->z
,
1186 .width
= flush_box
->width
,
1187 .height
= flush_box
->height
,
1188 .depth
= flush_box
->depth
,
1191 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
1192 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
1197 iris_unmap_copy_region(struct iris_transfer
*map
)
1199 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
1205 iris_map_copy_region(struct iris_transfer
*map
)
1207 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
1208 struct pipe_transfer
*xfer
= &map
->base
;
1209 struct pipe_box
*box
= &xfer
->box
;
1210 struct iris_resource
*res
= (void *) xfer
->resource
;
1212 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
1213 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
1215 struct pipe_resource templ
= (struct pipe_resource
) {
1216 .usage
= PIPE_USAGE_STAGING
,
1217 .width0
= box
->width
+ extra
,
1218 .height0
= box
->height
,
1220 .nr_samples
= xfer
->resource
->nr_samples
,
1221 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
1222 .array_size
= box
->depth
,
1225 if (xfer
->resource
->target
== PIPE_BUFFER
)
1226 templ
.target
= PIPE_BUFFER
;
1227 else if (templ
.array_size
> 1)
1228 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1230 templ
.target
= PIPE_TEXTURE_2D
;
1232 /* Depth, stencil, and ASTC can't be linear surfaces, so we can't use
1233 * xfer->resource->format directly. Pick a bpb compatible format so
1234 * resource creation will succeed; blorp_copy will override it anyway.
1236 switch (util_format_get_blocksizebits(res
->internal_format
)) {
1237 case 8: templ
.format
= PIPE_FORMAT_R8_UINT
; break;
1238 case 16: templ
.format
= PIPE_FORMAT_R8G8_UINT
; break;
1239 case 24: templ
.format
= PIPE_FORMAT_R8G8B8_UINT
; break;
1240 case 32: templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
; break;
1241 case 48: templ
.format
= PIPE_FORMAT_R16G16B16_UINT
; break;
1242 case 64: templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
; break;
1243 case 96: templ
.format
= PIPE_FORMAT_R32G32B32_UINT
; break;
1244 case 128: templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
; break;
1245 default: unreachable("Invalid bpb");
1248 map
->staging
= iris_resource_create(pscreen
, &templ
);
1249 assert(map
->staging
);
1251 if (templ
.target
!= PIPE_BUFFER
) {
1252 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1253 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1254 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1257 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1258 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1259 xfer
->resource
, xfer
->level
, box
);
1260 /* Ensure writes to the staging BO land before we map it below. */
1261 iris_emit_pipe_control_flush(map
->batch
,
1262 "transfer read: flush before mapping",
1263 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1264 PIPE_CONTROL_CS_STALL
);
1267 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1269 if (iris_batch_references(map
->batch
, staging_bo
))
1270 iris_batch_flush(map
->batch
);
1273 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1275 map
->unmap
= iris_unmap_copy_region
;
1279 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1280 unsigned *out_x0_el
, unsigned *out_y0_el
)
1282 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1283 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1285 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1290 * Get pointer offset into stencil buffer.
1292 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1293 * must decode the tile's layout in software.
1296 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1298 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1300 * Even though the returned offset is always positive, the return type is
1302 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1303 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1306 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1308 uint32_t tile_size
= 4096;
1309 uint32_t tile_width
= 64;
1310 uint32_t tile_height
= 64;
1311 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1313 uint32_t tile_x
= x
/ tile_width
;
1314 uint32_t tile_y
= y
/ tile_height
;
1316 /* The byte's address relative to the tile's base addres. */
1317 uint32_t byte_x
= x
% tile_width
;
1318 uint32_t byte_y
= y
% tile_height
;
1320 uintptr_t u
= tile_y
* row_size
1321 + tile_x
* tile_size
1322 + 512 * (byte_x
/ 8)
1324 + 32 * ((byte_y
/ 4) % 2)
1325 + 16 * ((byte_x
/ 4) % 2)
1326 + 8 * ((byte_y
/ 2) % 2)
1327 + 4 * ((byte_x
/ 2) % 2)
1332 /* adjust for bit6 swizzling */
1333 if (((byte_x
/ 8) % 2) == 1) {
1334 if (((byte_y
/ 8) % 2) == 0) {
1346 iris_unmap_s8(struct iris_transfer
*map
)
1348 struct pipe_transfer
*xfer
= &map
->base
;
1349 const struct pipe_box
*box
= &xfer
->box
;
1350 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1351 struct isl_surf
*surf
= &res
->surf
;
1352 const bool has_swizzling
= false;
1354 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1355 uint8_t *untiled_s8_map
= map
->ptr
;
1356 uint8_t *tiled_s8_map
=
1357 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1359 for (int s
= 0; s
< box
->depth
; s
++) {
1360 unsigned x0_el
, y0_el
;
1361 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1363 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1364 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1365 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1369 tiled_s8_map
[offset
] =
1370 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1380 iris_map_s8(struct iris_transfer
*map
)
1382 struct pipe_transfer
*xfer
= &map
->base
;
1383 const struct pipe_box
*box
= &xfer
->box
;
1384 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1385 struct isl_surf
*surf
= &res
->surf
;
1387 xfer
->stride
= surf
->row_pitch_B
;
1388 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1390 /* The tiling and detiling functions require that the linear buffer has
1391 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1392 * over-allocate the linear buffer to get the proper alignment.
1394 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1395 assert(map
->buffer
);
1397 const bool has_swizzling
= false;
1399 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1400 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1401 * invalidate is set, since we'll be writing the whole rectangle from our
1402 * temporary buffer back out.
1404 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1405 uint8_t *untiled_s8_map
= map
->ptr
;
1406 uint8_t *tiled_s8_map
=
1407 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1409 for (int s
= 0; s
< box
->depth
; s
++) {
1410 unsigned x0_el
, y0_el
;
1411 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1413 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1414 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1415 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1419 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1420 tiled_s8_map
[offset
];
1426 map
->unmap
= iris_unmap_s8
;
1429 /* Compute extent parameters for use with tiled_memcpy functions.
1430 * xs are in units of bytes and ys are in units of strides.
1433 tile_extents(const struct isl_surf
*surf
,
1434 const struct pipe_box
*box
,
1435 unsigned level
, int z
,
1436 unsigned *x1_B
, unsigned *x2_B
,
1437 unsigned *y1_el
, unsigned *y2_el
)
1439 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1440 const unsigned cpp
= fmtl
->bpb
/ 8;
1442 assert(box
->x
% fmtl
->bw
== 0);
1443 assert(box
->y
% fmtl
->bh
== 0);
1445 unsigned x0_el
, y0_el
;
1446 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1448 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1449 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1450 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1451 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1455 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1457 struct pipe_transfer
*xfer
= &map
->base
;
1458 const struct pipe_box
*box
= &xfer
->box
;
1459 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1460 struct isl_surf
*surf
= &res
->surf
;
1462 const bool has_swizzling
= false;
1464 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1466 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1468 for (int s
= 0; s
< box
->depth
; s
++) {
1469 unsigned x1
, x2
, y1
, y2
;
1470 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1472 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1474 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1475 surf
->row_pitch_B
, xfer
->stride
,
1476 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1479 os_free_aligned(map
->buffer
);
1480 map
->buffer
= map
->ptr
= NULL
;
1484 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1486 struct pipe_transfer
*xfer
= &map
->base
;
1487 const struct pipe_box
*box
= &xfer
->box
;
1488 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1489 struct isl_surf
*surf
= &res
->surf
;
1491 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1492 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1494 unsigned x1
, x2
, y1
, y2
;
1495 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1497 /* The tiling and detiling functions require that the linear buffer has
1498 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1499 * over-allocate the linear buffer to get the proper alignment.
1502 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1503 assert(map
->buffer
);
1504 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1506 const bool has_swizzling
= false;
1508 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1510 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1512 for (int s
= 0; s
< box
->depth
; s
++) {
1513 unsigned x1
, x2
, y1
, y2
;
1514 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1516 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1517 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1519 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1520 surf
->row_pitch_B
, has_swizzling
,
1521 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1525 map
->unmap
= iris_unmap_tiled_memcpy
;
1529 iris_map_direct(struct iris_transfer
*map
)
1531 struct pipe_transfer
*xfer
= &map
->base
;
1532 struct pipe_box
*box
= &xfer
->box
;
1533 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1535 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1537 if (res
->base
.target
== PIPE_BUFFER
) {
1539 xfer
->layer_stride
= 0;
1541 map
->ptr
= ptr
+ box
->x
;
1543 struct isl_surf
*surf
= &res
->surf
;
1544 const struct isl_format_layout
*fmtl
=
1545 isl_format_get_layout(surf
->format
);
1546 const unsigned cpp
= fmtl
->bpb
/ 8;
1547 unsigned x0_el
, y0_el
;
1549 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1551 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1552 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1554 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1559 can_promote_to_async(const struct iris_resource
*res
,
1560 const struct pipe_box
*box
,
1561 enum pipe_transfer_usage usage
)
1563 /* If we're writing to a section of the buffer that hasn't even been
1564 * initialized with useful data, then we can safely promote this write
1565 * to be unsynchronized. This helps the common pattern of appending data.
1567 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1568 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1569 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1570 box
->x
+ box
->width
);
1574 iris_transfer_map(struct pipe_context
*ctx
,
1575 struct pipe_resource
*resource
,
1577 enum pipe_transfer_usage usage
,
1578 const struct pipe_box
*box
,
1579 struct pipe_transfer
**ptransfer
)
1581 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1582 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1583 struct isl_surf
*surf
= &res
->surf
;
1585 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1586 /* Replace the backing storage with a fresh buffer for non-async maps */
1587 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1588 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1589 iris_invalidate_resource(ctx
, resource
);
1591 /* If we can discard the whole resource, we can discard the range. */
1592 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1595 bool map_would_stall
= false;
1597 if (resource
->target
!= PIPE_BUFFER
) {
1598 iris_resource_access_raw(ice
, &ice
->batches
[IRIS_BATCH_RENDER
], res
,
1599 level
, box
->z
, box
->depth
,
1600 usage
& PIPE_TRANSFER_WRITE
);
1603 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1604 can_promote_to_async(res
, box
, usage
)) {
1605 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1608 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1609 map_would_stall
= resource_is_busy(ice
, res
);
1611 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1612 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1616 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1617 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1620 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1621 struct pipe_transfer
*xfer
= &map
->base
;
1626 memset(map
, 0, sizeof(*map
));
1627 map
->dbg
= &ice
->dbg
;
1629 pipe_resource_reference(&xfer
->resource
, resource
);
1630 xfer
->level
= level
;
1631 xfer
->usage
= usage
;
1635 if (usage
& PIPE_TRANSFER_WRITE
)
1636 util_range_add(&res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1638 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1639 * there is to access them simultaneously on the CPU & GPU. This also
1640 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1641 * contain state we're constructing for a GPU draw call, which would
1642 * kill us with infinite stack recursion.
1644 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1645 PIPE_TRANSFER_COHERENT
|
1646 PIPE_TRANSFER_MAP_DIRECTLY
);
1648 /* GPU copies are not useful for buffer reads. Instead of stalling to
1649 * read from the original buffer, we'd simply copy it to a temporary...
1650 * then stall (a bit longer) to read from that buffer.
1652 * Images are less clear-cut. Color resolves are destructive, removing
1653 * the underlying compression, so we'd rather blit the data to a linear
1654 * temporary and map that, to avoid the resolve. (It might be better to
1655 * a tiled temporary and use the tiled_memcpy paths...)
1657 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) &&
1658 res
->aux
.usage
!= ISL_AUX_USAGE_CCS_E
&&
1659 res
->aux
.usage
!= ISL_AUX_USAGE_CCS_D
) {
1663 if ((map_would_stall
|| res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
) && !no_gpu
) {
1664 /* If we need a synchronous mapping and the resource is busy,
1665 * we copy to/from a linear temporary buffer using the GPU.
1667 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1668 map
->blorp
= &ice
->blorp
;
1669 iris_map_copy_region(map
);
1671 /* Otherwise we're free to map on the CPU. Flush if needed. */
1672 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1673 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1674 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1675 iris_batch_flush(&ice
->batches
[i
]);
1679 if (surf
->tiling
== ISL_TILING_W
) {
1680 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1682 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1683 iris_map_tiled_memcpy(map
);
1685 iris_map_direct(map
);
1693 iris_transfer_flush_region(struct pipe_context
*ctx
,
1694 struct pipe_transfer
*xfer
,
1695 const struct pipe_box
*box
)
1697 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1698 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1699 struct iris_transfer
*map
= (void *) xfer
;
1702 iris_flush_staging_region(xfer
, box
);
1704 uint32_t history_flush
= 0;
1706 if (res
->base
.target
== PIPE_BUFFER
) {
1707 history_flush
|= iris_flush_bits_for_history(res
) |
1708 (map
->staging
? PIPE_CONTROL_RENDER_TARGET_FLUSH
: 0);
1711 if (history_flush
& ~PIPE_CONTROL_CS_STALL
) {
1712 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1713 struct iris_batch
*batch
= &ice
->batches
[i
];
1714 if (batch
->contains_draw
|| batch
->cache
.render
->entries
) {
1715 iris_batch_maybe_flush(batch
, 24);
1716 iris_emit_pipe_control_flush(batch
,
1717 "cache history: transfer flush",
1723 /* Make sure we flag constants dirty even if there's no need to emit
1724 * any PIPE_CONTROLs to a batch.
1726 iris_dirty_for_history(ice
, res
);
1730 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
1732 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1733 struct iris_transfer
*map
= (void *) xfer
;
1735 if (!(xfer
->usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
)) {
1736 struct pipe_box flush_box
= {
1737 .x
= 0, .y
= 0, .z
= 0,
1738 .width
= xfer
->box
.width
,
1739 .height
= xfer
->box
.height
,
1740 .depth
= xfer
->box
.depth
,
1742 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
1748 pipe_resource_reference(&xfer
->resource
, NULL
);
1749 slab_free(&ice
->transfer_pool
, map
);
1753 * Mark state dirty that needs to be re-emitted when a resource is written.
1756 iris_dirty_for_history(struct iris_context
*ice
,
1757 struct iris_resource
*res
)
1759 uint64_t dirty
= 0ull;
1761 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1762 dirty
|= IRIS_DIRTY_CONSTANTS_VS
|
1763 IRIS_DIRTY_CONSTANTS_TCS
|
1764 IRIS_DIRTY_CONSTANTS_TES
|
1765 IRIS_DIRTY_CONSTANTS_GS
|
1766 IRIS_DIRTY_CONSTANTS_FS
|
1767 IRIS_DIRTY_CONSTANTS_CS
|
1768 IRIS_ALL_DIRTY_BINDINGS
;
1771 ice
->state
.dirty
|= dirty
;
1775 * Produce a set of PIPE_CONTROL bits which ensure data written to a
1776 * resource becomes visible, and any stale read cache data is invalidated.
1779 iris_flush_bits_for_history(struct iris_resource
*res
)
1781 uint32_t flush
= PIPE_CONTROL_CS_STALL
;
1783 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1784 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
1785 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1788 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
1789 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1791 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
1792 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1794 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
1795 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
1801 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
1802 struct iris_batch
*batch
,
1803 struct iris_resource
*res
,
1804 uint32_t extra_flags
,
1807 if (res
->base
.target
!= PIPE_BUFFER
)
1810 uint32_t flush
= iris_flush_bits_for_history(res
) | extra_flags
;
1812 iris_emit_pipe_control_flush(batch
, reason
, flush
);
1814 iris_dirty_for_history(ice
, res
);
1818 iris_resource_set_clear_color(struct iris_context
*ice
,
1819 struct iris_resource
*res
,
1820 union isl_color_value color
)
1822 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
1823 res
->aux
.clear_color
= color
;
1830 union isl_color_value
1831 iris_resource_get_clear_color(const struct iris_resource
*res
,
1832 struct iris_bo
**clear_color_bo
,
1833 uint64_t *clear_color_offset
)
1835 assert(res
->aux
.bo
);
1838 *clear_color_bo
= res
->aux
.clear_color_bo
;
1839 if (clear_color_offset
)
1840 *clear_color_offset
= res
->aux
.clear_color_offset
;
1841 return res
->aux
.clear_color
;
1844 static enum pipe_format
1845 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
1847 struct iris_resource
*res
= (void *) p_res
;
1848 return res
->internal_format
;
1851 static const struct u_transfer_vtbl transfer_vtbl
= {
1852 .resource_create
= iris_resource_create
,
1853 .resource_destroy
= iris_resource_destroy
,
1854 .transfer_map
= iris_transfer_map
,
1855 .transfer_unmap
= iris_transfer_unmap
,
1856 .transfer_flush_region
= iris_transfer_flush_region
,
1857 .get_internal_format
= iris_resource_get_internal_format
,
1858 .set_stencil
= iris_resource_set_separate_stencil
,
1859 .get_stencil
= iris_resource_get_separate_stencil
,
1863 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
1865 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
1866 pscreen
->resource_create_with_modifiers
=
1867 iris_resource_create_with_modifiers
;
1868 pscreen
->resource_create
= u_transfer_helper_resource_create
;
1869 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
1870 pscreen
->resource_from_handle
= iris_resource_from_handle
;
1871 pscreen
->resource_get_handle
= iris_resource_get_handle
;
1872 pscreen
->resource_get_param
= iris_resource_get_param
;
1873 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
1874 pscreen
->transfer_helper
=
1875 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
1879 iris_init_resource_functions(struct pipe_context
*ctx
)
1881 ctx
->flush_resource
= iris_flush_resource
;
1882 ctx
->invalidate_resource
= iris_invalidate_resource
;
1883 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
1884 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
1885 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
1886 ctx
->buffer_subdata
= u_default_buffer_subdata
;
1887 ctx
->texture_subdata
= u_default_texture_subdata
;