2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
24 * @file iris_resource.c
26 * Resources are images, buffers, and other objects used by the GPU.
28 * XXX: explain resources
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/format/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/common/gen_aux_map.h"
51 #include "intel/dev/gen_debug.h"
53 #include "drm-uapi/drm_fourcc.h"
54 #include "drm-uapi/i915_drm.h"
56 enum modifier_priority
{
57 MODIFIER_PRIORITY_INVALID
= 0,
58 MODIFIER_PRIORITY_LINEAR
,
61 MODIFIER_PRIORITY_Y_CCS
,
64 static const uint64_t priority_to_modifier
[] = {
65 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
66 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
67 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
68 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
69 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
73 modifier_is_supported(const struct gen_device_info
*devinfo
,
74 enum pipe_format pfmt
, uint64_t modifier
)
76 /* XXX: do something real */
78 case I915_FORMAT_MOD_Y_TILED_CCS
: {
79 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
82 enum isl_format rt_format
=
83 iris_format_for_usage(devinfo
, pfmt
,
84 ISL_SURF_USAGE_RENDER_TARGET_BIT
).fmt
;
86 if (rt_format
== ISL_FORMAT_UNSUPPORTED
||
87 !isl_format_supports_ccs_e(devinfo
, rt_format
))
90 return devinfo
->gen
>= 9 && devinfo
->gen
<= 11;
92 case I915_FORMAT_MOD_Y_TILED
:
93 case I915_FORMAT_MOD_X_TILED
:
94 case DRM_FORMAT_MOD_LINEAR
:
96 case DRM_FORMAT_MOD_INVALID
:
103 select_best_modifier(struct gen_device_info
*devinfo
, enum pipe_format pfmt
,
104 const uint64_t *modifiers
,
107 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
109 for (int i
= 0; i
< count
; i
++) {
110 if (!modifier_is_supported(devinfo
, pfmt
, modifiers
[i
]))
113 switch (modifiers
[i
]) {
114 case I915_FORMAT_MOD_Y_TILED_CCS
:
115 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
117 case I915_FORMAT_MOD_Y_TILED
:
118 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
120 case I915_FORMAT_MOD_X_TILED
:
121 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
123 case DRM_FORMAT_MOD_LINEAR
:
124 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
126 case DRM_FORMAT_MOD_INVALID
:
132 return priority_to_modifier
[prio
];
136 target_to_isl_surf_dim(enum pipe_texture_target target
)
140 case PIPE_TEXTURE_1D
:
141 case PIPE_TEXTURE_1D_ARRAY
:
142 return ISL_SURF_DIM_1D
;
143 case PIPE_TEXTURE_2D
:
144 case PIPE_TEXTURE_CUBE
:
145 case PIPE_TEXTURE_RECT
:
146 case PIPE_TEXTURE_2D_ARRAY
:
147 case PIPE_TEXTURE_CUBE_ARRAY
:
148 return ISL_SURF_DIM_2D
;
149 case PIPE_TEXTURE_3D
:
150 return ISL_SURF_DIM_3D
;
151 case PIPE_MAX_TEXTURE_TYPES
:
154 unreachable("invalid texture type");
158 iris_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
159 enum pipe_format pfmt
,
162 unsigned int *external_only
,
165 struct iris_screen
*screen
= (void *) pscreen
;
166 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
168 uint64_t all_modifiers
[] = {
169 DRM_FORMAT_MOD_LINEAR
,
170 I915_FORMAT_MOD_X_TILED
,
171 I915_FORMAT_MOD_Y_TILED
,
172 I915_FORMAT_MOD_Y_TILED_CCS
,
175 int supported_mods
= 0;
177 for (int i
= 0; i
< ARRAY_SIZE(all_modifiers
); i
++) {
178 if (!modifier_is_supported(devinfo
, pfmt
, all_modifiers
[i
]))
181 if (supported_mods
< max
) {
183 modifiers
[supported_mods
] = all_modifiers
[i
];
186 external_only
[supported_mods
] = util_format_is_yuv(pfmt
);
192 *count
= supported_mods
;
195 static isl_surf_usage_flags_t
196 pipe_bind_to_isl_usage(unsigned bindings
)
198 isl_surf_usage_flags_t usage
= 0;
200 if (bindings
& PIPE_BIND_RENDER_TARGET
)
201 usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
203 if (bindings
& PIPE_BIND_SAMPLER_VIEW
)
204 usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
206 if (bindings
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SHADER_BUFFER
))
207 usage
|= ISL_SURF_USAGE_STORAGE_BIT
;
209 if (bindings
& PIPE_BIND_DISPLAY_TARGET
)
210 usage
|= ISL_SURF_USAGE_DISPLAY_BIT
;
216 iris_image_view_get_format(struct iris_context
*ice
,
217 const struct pipe_image_view
*img
)
219 struct iris_screen
*screen
= (struct iris_screen
*)ice
->ctx
.screen
;
220 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
222 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
223 enum isl_format isl_fmt
=
224 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
226 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
227 /* On Gen8, try to use typed surfaces reads (which support a
228 * limited number of formats), and if not possible, fall back
231 if (devinfo
->gen
== 8 &&
232 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
))
233 return ISL_FORMAT_RAW
;
235 return isl_lower_storage_image_format(devinfo
, isl_fmt
);
241 struct pipe_resource
*
242 iris_resource_get_separate_stencil(struct pipe_resource
*p_res
)
244 /* For packed depth-stencil, we treat depth as the primary resource
245 * and store S8 as the "second plane" resource.
247 if (p_res
->next
&& p_res
->next
->format
== PIPE_FORMAT_S8_UINT
)
255 iris_resource_set_separate_stencil(struct pipe_resource
*p_res
,
256 struct pipe_resource
*stencil
)
258 assert(util_format_has_depth(util_format_description(p_res
->format
)));
259 pipe_resource_reference(&p_res
->next
, stencil
);
263 iris_get_depth_stencil_resources(struct pipe_resource
*res
,
264 struct iris_resource
**out_z
,
265 struct iris_resource
**out_s
)
273 if (res
->format
!= PIPE_FORMAT_S8_UINT
) {
274 *out_z
= (void *) res
;
275 *out_s
= (void *) iris_resource_get_separate_stencil(res
);
278 *out_s
= (void *) res
;
283 iris_get_isl_dim_layout(const struct gen_device_info
*devinfo
,
284 enum isl_tiling tiling
,
285 enum pipe_texture_target target
)
288 case PIPE_TEXTURE_1D
:
289 case PIPE_TEXTURE_1D_ARRAY
:
290 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
291 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
293 case PIPE_TEXTURE_2D
:
294 case PIPE_TEXTURE_2D_ARRAY
:
295 case PIPE_TEXTURE_RECT
:
296 case PIPE_TEXTURE_CUBE
:
297 case PIPE_TEXTURE_CUBE_ARRAY
:
298 return ISL_DIM_LAYOUT_GEN4_2D
;
300 case PIPE_TEXTURE_3D
:
301 return (devinfo
->gen
>= 9 ?
302 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
304 case PIPE_MAX_TEXTURE_TYPES
:
308 unreachable("invalid texture type");
312 iris_resource_disable_aux(struct iris_resource
*res
)
314 iris_bo_unreference(res
->aux
.bo
);
315 iris_bo_unreference(res
->aux
.clear_color_bo
);
316 free(res
->aux
.state
);
318 res
->aux
.usage
= ISL_AUX_USAGE_NONE
;
319 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
320 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
321 res
->aux
.has_hiz
= 0;
322 res
->aux
.surf
.size_B
= 0;
324 res
->aux
.extra_aux
.surf
.size_B
= 0;
325 res
->aux
.clear_color_bo
= NULL
;
326 res
->aux
.state
= NULL
;
330 iris_resource_destroy(struct pipe_screen
*screen
,
331 struct pipe_resource
*resource
)
333 struct iris_resource
*res
= (struct iris_resource
*)resource
;
335 if (resource
->target
== PIPE_BUFFER
)
336 util_range_destroy(&res
->valid_buffer_range
);
338 iris_resource_disable_aux(res
);
340 iris_bo_unreference(res
->bo
);
341 iris_pscreen_unref(res
->base
.screen
);
346 static struct iris_resource
*
347 iris_alloc_resource(struct pipe_screen
*pscreen
,
348 const struct pipe_resource
*templ
)
350 struct iris_resource
*res
= calloc(1, sizeof(struct iris_resource
));
355 res
->base
.screen
= iris_pscreen_ref(pscreen
);
356 pipe_reference_init(&res
->base
.reference
, 1);
358 res
->aux
.possible_usages
= 1 << ISL_AUX_USAGE_NONE
;
359 res
->aux
.sampler_usages
= 1 << ISL_AUX_USAGE_NONE
;
361 if (templ
->target
== PIPE_BUFFER
)
362 util_range_init(&res
->valid_buffer_range
);
368 iris_get_num_logical_layers(const struct iris_resource
*res
, unsigned level
)
370 if (res
->surf
.dim
== ISL_SURF_DIM_3D
)
371 return minify(res
->surf
.logical_level0_px
.depth
, level
);
373 return res
->surf
.logical_level0_px
.array_len
;
376 static enum isl_aux_state
**
377 create_aux_state_map(struct iris_resource
*res
, enum isl_aux_state initial
)
379 assert(res
->aux
.state
== NULL
);
381 uint32_t total_slices
= 0;
382 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++)
383 total_slices
+= iris_get_num_logical_layers(res
, level
);
385 const size_t per_level_array_size
=
386 res
->surf
.levels
* sizeof(enum isl_aux_state
*);
388 /* We're going to allocate a single chunk of data for both the per-level
389 * reference array and the arrays of aux_state. This makes cleanup
390 * significantly easier.
392 const size_t total_size
=
393 per_level_array_size
+ total_slices
* sizeof(enum isl_aux_state
);
395 void *data
= malloc(total_size
);
399 enum isl_aux_state
**per_level_arr
= data
;
400 enum isl_aux_state
*s
= data
+ per_level_array_size
;
401 for (uint32_t level
= 0; level
< res
->surf
.levels
; level
++) {
402 per_level_arr
[level
] = s
;
403 const unsigned level_layers
= iris_get_num_logical_layers(res
, level
);
404 for (uint32_t a
= 0; a
< level_layers
; a
++)
407 assert((void *)s
== data
+ total_size
);
409 return per_level_arr
;
413 iris_get_aux_clear_color_state_size(struct iris_screen
*screen
)
415 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
416 return devinfo
->gen
>= 10 ? screen
->isl_dev
.ss
.clear_color_state_size
: 0;
420 map_aux_addresses(struct iris_screen
*screen
, struct iris_resource
*res
)
422 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
423 if (devinfo
->gen
>= 12 && isl_aux_usage_has_ccs(res
->aux
.usage
)) {
424 void *aux_map_ctx
= iris_bufmgr_get_aux_map_context(screen
->bufmgr
);
426 const unsigned aux_offset
= res
->aux
.extra_aux
.surf
.size_B
> 0 ?
427 res
->aux
.extra_aux
.offset
: res
->aux
.offset
;
428 gen_aux_map_add_image(aux_map_ctx
, &res
->surf
, res
->bo
->gtt_offset
,
429 res
->aux
.bo
->gtt_offset
+ aux_offset
);
430 res
->bo
->aux_map_address
= res
->aux
.bo
->gtt_offset
;
435 want_ccs_e_for_format(const struct gen_device_info
*devinfo
,
436 enum isl_format format
)
438 if (!isl_format_supports_ccs_e(devinfo
, format
))
441 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
443 /* CCS_E seems to significantly hurt performance with 32-bit floating
444 * point formats. For example, Paraview's "Wavelet Volume" case uses
445 * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
446 * formats causes a 62% FPS drop.
448 * However, many benchmarks seem to use 16-bit float with no issues.
450 if (fmtl
->channels
.r
.bits
== 32 && fmtl
->channels
.r
.type
== ISL_SFLOAT
)
457 * Configure aux for the resource, but don't allocate it. For images which
458 * might be shared with modifiers, we must allocate the image and aux data in
461 * Returns false on unexpected error (e.g. allocation failed, or invalid
462 * configuration result).
465 iris_resource_configure_aux(struct iris_screen
*screen
,
466 struct iris_resource
*res
, bool imported
,
467 uint64_t *aux_size_B
,
468 uint32_t *alloc_flags
)
470 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
472 /* Try to create the auxiliary surfaces allowed by the modifier or by
473 * the user if no modifier is specified.
475 assert(!res
->mod_info
||
476 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
||
477 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
478 res
->mod_info
->aux_usage
== ISL_AUX_USAGE_GEN12_CCS_E
);
480 const bool has_mcs
= !res
->mod_info
&&
481 isl_surf_get_mcs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
483 const bool has_hiz
= !res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_HIZ
) &&
484 isl_surf_get_hiz_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
);
487 ((!res
->mod_info
&& !(INTEL_DEBUG
& DEBUG_NO_RBC
)) ||
488 (res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)) &&
489 isl_surf_get_ccs_surf(&screen
->isl_dev
, &res
->surf
, &res
->aux
.surf
,
490 &res
->aux
.extra_aux
.surf
, 0);
492 /* Having both HIZ and MCS is impossible. */
493 assert(!has_mcs
|| !has_hiz
);
495 /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */
496 if (has_ccs
&& (has_mcs
|| has_hiz
)) {
497 assert(res
->aux
.extra_aux
.surf
.size_B
> 0 &&
498 res
->aux
.extra_aux
.surf
.usage
& ISL_SURF_USAGE_CCS_BIT
);
499 assert(res
->aux
.surf
.size_B
> 0 &&
500 res
->aux
.surf
.usage
&
501 (ISL_SURF_USAGE_HIZ_BIT
| ISL_SURF_USAGE_MCS_BIT
));
504 if (res
->mod_info
&& has_ccs
) {
505 /* Only allow a CCS modifier if the aux was created successfully. */
506 res
->aux
.possible_usages
|= 1 << res
->mod_info
->aux_usage
;
507 } else if (has_mcs
) {
508 res
->aux
.possible_usages
|=
509 1 << (has_ccs
? ISL_AUX_USAGE_MCS_CCS
: ISL_AUX_USAGE_MCS
);
510 } else if (has_hiz
) {
512 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ
;
513 } else if (res
->surf
.samples
== 1 &&
514 (res
->surf
.usage
& ISL_SURF_USAGE_TEXTURE_BIT
)) {
515 /* If this resource is single-sampled and will be used as a texture,
516 * put the HiZ surface in write-through mode so that we can sample
519 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS_WT
;
521 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_HIZ_CCS
;
523 } else if (has_ccs
&& isl_surf_usage_is_stencil(res
->surf
.usage
)) {
524 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_STC_CCS
;
525 } else if (has_ccs
) {
526 if (want_ccs_e_for_format(devinfo
, res
->surf
.format
)) {
527 res
->aux
.possible_usages
|= devinfo
->gen
< 12 ?
528 1 << ISL_AUX_USAGE_CCS_E
: 1 << ISL_AUX_USAGE_GEN12_CCS_E
;
529 } else if (isl_format_supports_ccs_d(devinfo
, res
->surf
.format
)) {
530 res
->aux
.possible_usages
|= 1 << ISL_AUX_USAGE_CCS_D
;
534 res
->aux
.usage
= util_last_bit(res
->aux
.possible_usages
) - 1;
536 res
->aux
.sampler_usages
= res
->aux
.possible_usages
;
538 /* We don't always support sampling with hiz. But when we do, it must be
541 if (!devinfo
->has_sample_with_hiz
|| res
->surf
.samples
> 1)
542 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ
);
544 /* ISL_AUX_USAGE_HIZ_CCS doesn't support sampling at all */
545 res
->aux
.sampler_usages
&= ~(1 << ISL_AUX_USAGE_HIZ_CCS
);
547 enum isl_aux_state initial_state
;
550 assert(!res
->aux
.bo
);
552 switch (res
->aux
.usage
) {
553 case ISL_AUX_USAGE_NONE
:
554 /* Having no aux buffer is only okay if there's no modifier with aux. */
555 return !res
->mod_info
|| res
->mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
;
556 case ISL_AUX_USAGE_HIZ
:
557 case ISL_AUX_USAGE_HIZ_CCS
:
558 case ISL_AUX_USAGE_HIZ_CCS_WT
:
559 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
561 case ISL_AUX_USAGE_MCS
:
562 case ISL_AUX_USAGE_MCS_CCS
:
563 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
565 * "When MCS buffer is enabled and bound to MSRT, it is required
566 * that it is cleared prior to any rendering."
568 * Since we only use the MCS buffer for rendering, we just clear it
569 * immediately on allocation. The clear value for MCS buffers is all
570 * 1's, so we simply memset it to 0xff.
572 initial_state
= ISL_AUX_STATE_CLEAR
;
574 case ISL_AUX_USAGE_CCS_D
:
575 case ISL_AUX_USAGE_CCS_E
:
576 case ISL_AUX_USAGE_GEN12_CCS_E
:
577 case ISL_AUX_USAGE_STC_CCS
:
578 /* When CCS_E is used, we need to ensure that the CCS starts off in
579 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
582 * "If Software wants to enable Color Compression without Fast
583 * clear, Software needs to initialize MCS with zeros."
585 * A CCS value of 0 indicates that the corresponding block is in the
586 * pass-through state which is what we want.
588 * For CCS_D, do the same thing. On Gen9+, this avoids having any
589 * undefined bits in the aux buffer.
592 assert(res
->aux
.usage
!= ISL_AUX_USAGE_STC_CCS
);
594 isl_drm_modifier_get_default_aux_state(res
->mod_info
->modifier
);
596 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
598 *alloc_flags
|= BO_ALLOC_ZEROED
;
600 case ISL_AUX_USAGE_MC
:
601 unreachable("Unsupported aux mode");
604 /* Create the aux_state for the auxiliary buffer. */
605 res
->aux
.state
= create_aux_state_map(res
, initial_state
);
609 /* Increase the aux offset if the main and aux surfaces will share a BO. */
611 !res
->mod_info
|| res
->mod_info
->aux_usage
== res
->aux
.usage
?
612 ALIGN(res
->surf
.size_B
, res
->aux
.surf
.alignment_B
) : 0;
613 uint64_t size
= res
->aux
.surf
.size_B
;
615 /* Allocate space in the buffer for storing the CCS. */
616 if (res
->aux
.extra_aux
.surf
.size_B
> 0) {
617 const uint64_t padded_aux_size
=
618 ALIGN(size
, res
->aux
.extra_aux
.surf
.alignment_B
);
619 res
->aux
.extra_aux
.offset
= res
->aux
.offset
+ padded_aux_size
;
620 size
= padded_aux_size
+ res
->aux
.extra_aux
.surf
.size_B
;
623 /* Allocate space in the buffer for storing the clear color. On modern
624 * platforms (gen > 9), we can read it directly from such buffer.
626 * On gen <= 9, we are going to store the clear color on the buffer
627 * anyways, and copy it back to the surface state during state emission.
629 * Also add some padding to make sure the fast clear color state buffer
630 * starts at a 4K alignment. We believe that 256B might be enough, but due
631 * to lack of testing we will leave this as 4K for now.
633 size
= ALIGN(size
, 4096);
634 res
->aux
.clear_color_offset
= res
->aux
.offset
+ size
;
635 size
+= iris_get_aux_clear_color_state_size(screen
);
638 if (isl_aux_usage_has_hiz(res
->aux
.usage
)) {
639 for (unsigned level
= 0; level
< res
->surf
.levels
; ++level
) {
640 uint32_t width
= u_minify(res
->surf
.phys_level0_sa
.width
, level
);
641 uint32_t height
= u_minify(res
->surf
.phys_level0_sa
.height
, level
);
643 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
644 * For LOD == 0, we can grow the dimensions to make it work.
646 if (level
== 0 || ((width
& 7) == 0 && (height
& 3) == 0))
647 res
->aux
.has_hiz
|= 1 << level
;
655 * Initialize the aux buffer contents.
657 * Returns false on unexpected error (e.g. mapping a BO failed).
660 iris_resource_init_aux_buf(struct iris_resource
*res
, uint32_t alloc_flags
,
661 unsigned clear_color_state_size
)
663 if (!(alloc_flags
& BO_ALLOC_ZEROED
)) {
664 void *map
= iris_bo_map(NULL
, res
->aux
.bo
, MAP_WRITE
| MAP_RAW
);
669 if (iris_resource_get_aux_state(res
, 0, 0) != ISL_AUX_STATE_AUX_INVALID
) {
670 uint8_t memset_value
= isl_aux_usage_has_mcs(res
->aux
.usage
) ? 0xFF : 0;
671 memset((char*)map
+ res
->aux
.offset
, memset_value
,
672 res
->aux
.surf
.size_B
);
675 memset((char*)map
+ res
->aux
.extra_aux
.offset
,
676 0, res
->aux
.extra_aux
.surf
.size_B
);
678 /* Zero the indirect clear color to match ::fast_clear_color. */
679 memset((char *)map
+ res
->aux
.clear_color_offset
, 0,
680 clear_color_state_size
);
682 iris_bo_unmap(res
->aux
.bo
);
685 if (clear_color_state_size
> 0) {
686 res
->aux
.clear_color_bo
= res
->aux
.bo
;
687 iris_bo_reference(res
->aux
.clear_color_bo
);
694 * Allocate the initial aux surface for a resource based on aux.usage
696 * Returns false on unexpected error (e.g. allocation failed, or invalid
697 * configuration result).
700 iris_resource_alloc_separate_aux(struct iris_screen
*screen
,
701 struct iris_resource
*res
)
703 uint32_t alloc_flags
;
705 if (!iris_resource_configure_aux(screen
, res
, false, &size
, &alloc_flags
))
711 /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
712 * the drm allocator. Therefore, one can pass the ISL dimensions in terms
713 * of bytes instead of trying to recalculate based on different format
716 res
->aux
.bo
= iris_bo_alloc_tiled(screen
->bufmgr
, "aux buffer", size
, 4096,
718 isl_tiling_to_i915_tiling(res
->aux
.surf
.tiling
),
719 res
->aux
.surf
.row_pitch_B
, alloc_flags
);
724 if (!iris_resource_init_aux_buf(res
, alloc_flags
,
725 iris_get_aux_clear_color_state_size(screen
)))
728 map_aux_addresses(screen
, res
);
734 iris_resource_finish_aux_import(struct pipe_screen
*pscreen
,
735 struct iris_resource
*res
)
737 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
738 assert(iris_resource_unfinished_aux_import(res
));
739 assert(!res
->mod_info
->supports_clear_color
);
741 struct iris_resource
*aux_res
= (void *) res
->base
.next
;
742 assert(aux_res
->aux
.surf
.row_pitch_B
&& aux_res
->aux
.offset
&&
745 assert(res
->bo
== aux_res
->aux
.bo
);
746 iris_bo_reference(aux_res
->aux
.bo
);
747 res
->aux
.bo
= aux_res
->aux
.bo
;
749 res
->aux
.offset
= aux_res
->aux
.offset
;
751 assert(res
->bo
->size
>= (res
->aux
.offset
+ res
->aux
.surf
.size_B
));
752 assert(res
->aux
.clear_color_bo
== NULL
);
753 res
->aux
.clear_color_offset
= 0;
755 assert(aux_res
->aux
.surf
.row_pitch_B
== res
->aux
.surf
.row_pitch_B
);
757 unsigned clear_color_state_size
=
758 iris_get_aux_clear_color_state_size(screen
);
760 if (clear_color_state_size
> 0) {
761 res
->aux
.clear_color_bo
=
762 iris_bo_alloc(screen
->bufmgr
, "clear color buffer",
763 clear_color_state_size
, IRIS_MEMZONE_OTHER
);
764 res
->aux
.clear_color_offset
= 0;
767 iris_resource_destroy(&screen
->base
, res
->base
.next
);
768 res
->base
.next
= NULL
;
770 map_aux_addresses(screen
, res
);
773 static struct pipe_resource
*
774 iris_resource_create_for_buffer(struct pipe_screen
*pscreen
,
775 const struct pipe_resource
*templ
)
777 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
778 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
780 assert(templ
->target
== PIPE_BUFFER
);
781 assert(templ
->height0
<= 1);
782 assert(templ
->depth0
<= 1);
783 assert(templ
->format
== PIPE_FORMAT_NONE
||
784 util_format_get_blocksize(templ
->format
) == 1);
786 res
->internal_format
= templ
->format
;
787 res
->surf
.tiling
= ISL_TILING_LINEAR
;
789 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
790 const char *name
= templ
->target
== PIPE_BUFFER
? "buffer" : "miptree";
791 if (templ
->flags
& IRIS_RESOURCE_FLAG_SHADER_MEMZONE
) {
792 memzone
= IRIS_MEMZONE_SHADER
;
793 name
= "shader kernels";
794 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
) {
795 memzone
= IRIS_MEMZONE_SURFACE
;
796 name
= "surface state";
797 } else if (templ
->flags
& IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
) {
798 memzone
= IRIS_MEMZONE_DYNAMIC
;
799 name
= "dynamic state";
802 res
->bo
= iris_bo_alloc(screen
->bufmgr
, name
, templ
->width0
, memzone
);
804 iris_resource_destroy(pscreen
, &res
->base
);
808 if (templ
->bind
& PIPE_BIND_SHARED
)
809 iris_bo_make_external(res
->bo
);
814 static struct pipe_resource
*
815 iris_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
816 const struct pipe_resource
*templ
,
817 const uint64_t *modifiers
,
820 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
821 struct gen_device_info
*devinfo
= &screen
->devinfo
;
822 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
827 const struct util_format_description
*format_desc
=
828 util_format_description(templ
->format
);
829 const bool has_depth
= util_format_has_depth(format_desc
);
831 select_best_modifier(devinfo
, templ
->format
, modifiers
, modifiers_count
);
833 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
835 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
836 res
->mod_info
= isl_drm_modifier_get_info(modifier
);
838 tiling_flags
= 1 << res
->mod_info
->tiling
;
840 if (modifiers_count
> 0) {
841 fprintf(stderr
, "Unsupported modifier, resource creation failed.\n");
845 /* Use linear for staging buffers */
846 if (templ
->usage
== PIPE_USAGE_STAGING
||
847 templ
->bind
& (PIPE_BIND_LINEAR
| PIPE_BIND_CURSOR
) )
848 tiling_flags
= ISL_TILING_LINEAR_BIT
;
849 else if (templ
->bind
& PIPE_BIND_SCANOUT
)
850 tiling_flags
= ISL_TILING_X_BIT
;
853 isl_surf_usage_flags_t usage
= pipe_bind_to_isl_usage(templ
->bind
);
855 if (templ
->target
== PIPE_TEXTURE_CUBE
||
856 templ
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
857 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
859 if (templ
->usage
!= PIPE_USAGE_STAGING
) {
860 if (templ
->format
== PIPE_FORMAT_S8_UINT
)
861 usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
863 usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
866 enum pipe_format pfmt
= templ
->format
;
867 res
->internal_format
= pfmt
;
869 /* Should be handled by u_transfer_helper */
870 assert(!util_format_is_depth_and_stencil(pfmt
));
872 struct iris_format_info fmt
= iris_format_for_usage(devinfo
, pfmt
, usage
);
873 assert(fmt
.fmt
!= ISL_FORMAT_UNSUPPORTED
);
875 UNUSED
const bool isl_surf_created_successfully
=
876 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
877 .dim
= target_to_isl_surf_dim(templ
->target
),
879 .width
= templ
->width0
,
880 .height
= templ
->height0
,
881 .depth
= templ
->depth0
,
882 .levels
= templ
->last_level
+ 1,
883 .array_len
= templ
->array_size
,
884 .samples
= MAX2(templ
->nr_samples
, 1),
885 .min_alignment_B
= 0,
888 .tiling_flags
= tiling_flags
);
889 assert(isl_surf_created_successfully
);
891 const char *name
= "miptree";
892 enum iris_memory_zone memzone
= IRIS_MEMZONE_OTHER
;
894 unsigned int flags
= 0;
895 if (templ
->usage
== PIPE_USAGE_STAGING
)
896 flags
|= BO_ALLOC_COHERENT
;
898 /* These are for u_upload_mgr buffers only */
899 assert(!(templ
->flags
& (IRIS_RESOURCE_FLAG_SHADER_MEMZONE
|
900 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE
|
901 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE
)));
903 uint32_t aux_preferred_alloc_flags
;
904 uint64_t aux_size
= 0;
905 if (!iris_resource_configure_aux(screen
, res
, false, &aux_size
,
906 &aux_preferred_alloc_flags
)) {
910 /* Modifiers require the aux data to be in the same buffer as the main
911 * surface, but we combine them even when a modifiers is not being used.
913 const uint64_t bo_size
=
914 MAX2(res
->surf
.size_B
, res
->aux
.offset
+ aux_size
);
915 uint32_t alignment
= MAX2(4096, res
->surf
.alignment_B
);
916 res
->bo
= iris_bo_alloc_tiled(screen
->bufmgr
, name
, bo_size
, alignment
,
918 isl_tiling_to_i915_tiling(res
->surf
.tiling
),
919 res
->surf
.row_pitch_B
, flags
);
925 res
->aux
.bo
= res
->bo
;
926 iris_bo_reference(res
->aux
.bo
);
927 unsigned clear_color_state_size
=
928 iris_get_aux_clear_color_state_size(screen
);
929 if (!iris_resource_init_aux_buf(res
, flags
, clear_color_state_size
))
931 map_aux_addresses(screen
, res
);
934 if (templ
->bind
& PIPE_BIND_SHARED
)
935 iris_bo_make_external(res
->bo
);
940 fprintf(stderr
, "XXX: resource creation failed\n");
941 iris_resource_destroy(pscreen
, &res
->base
);
946 static struct pipe_resource
*
947 iris_resource_create(struct pipe_screen
*pscreen
,
948 const struct pipe_resource
*templ
)
950 if (templ
->target
== PIPE_BUFFER
)
951 return iris_resource_create_for_buffer(pscreen
, templ
);
953 return iris_resource_create_with_modifiers(pscreen
, templ
, NULL
, 0);
957 tiling_to_modifier(uint32_t tiling
)
959 static const uint64_t map
[] = {
960 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
961 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
962 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
965 assert(tiling
< ARRAY_SIZE(map
));
970 static struct pipe_resource
*
971 iris_resource_from_user_memory(struct pipe_screen
*pscreen
,
972 const struct pipe_resource
*templ
,
975 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
976 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
977 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
981 assert(templ
->target
== PIPE_BUFFER
);
983 res
->internal_format
= templ
->format
;
984 res
->bo
= iris_bo_create_userptr(bufmgr
, "user",
985 user_memory
, templ
->width0
,
988 iris_resource_destroy(pscreen
, &res
->base
);
992 util_range_add(&res
->base
, &res
->valid_buffer_range
, 0, templ
->width0
);
997 static struct pipe_resource
*
998 iris_resource_from_handle(struct pipe_screen
*pscreen
,
999 const struct pipe_resource
*templ
,
1000 struct winsys_handle
*whandle
,
1003 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
1004 struct gen_device_info
*devinfo
= &screen
->devinfo
;
1005 struct iris_bufmgr
*bufmgr
= screen
->bufmgr
;
1006 struct iris_resource
*res
= iris_alloc_resource(pscreen
, templ
);
1007 const struct isl_drm_modifier_info
*mod_inf
=
1008 isl_drm_modifier_get_info(whandle
->modifier
);
1014 switch (whandle
->type
) {
1015 case WINSYS_HANDLE_TYPE_FD
:
1017 tiling
= isl_tiling_to_i915_tiling(mod_inf
->tiling
);
1019 tiling
= I915_TILING_LAST
+ 1;
1020 res
->bo
= iris_bo_import_dmabuf(bufmgr
, whandle
->handle
,
1021 tiling
, whandle
->stride
);
1023 case WINSYS_HANDLE_TYPE_SHARED
:
1024 res
->bo
= iris_bo_gem_create_from_name(bufmgr
, "winsys image",
1028 unreachable("invalid winsys handle type");
1033 res
->offset
= whandle
->offset
;
1035 if (mod_inf
== NULL
) {
1037 isl_drm_modifier_get_info(tiling_to_modifier(res
->bo
->tiling_mode
));
1041 res
->external_format
= whandle
->format
;
1042 res
->mod_info
= mod_inf
;
1044 isl_surf_usage_flags_t isl_usage
= pipe_bind_to_isl_usage(templ
->bind
);
1046 const struct iris_format_info fmt
=
1047 iris_format_for_usage(devinfo
, templ
->format
, isl_usage
);
1048 res
->internal_format
= templ
->format
;
1050 if (templ
->target
== PIPE_BUFFER
) {
1051 res
->surf
.tiling
= ISL_TILING_LINEAR
;
1053 /* Create a surface for each plane specified by the external format. */
1054 if (whandle
->plane
< util_format_get_num_planes(whandle
->format
)) {
1055 UNUSED
const bool isl_surf_created_successfully
=
1056 isl_surf_init(&screen
->isl_dev
, &res
->surf
,
1057 .dim
= target_to_isl_surf_dim(templ
->target
),
1059 .width
= templ
->width0
,
1060 .height
= templ
->height0
,
1061 .depth
= templ
->depth0
,
1062 .levels
= templ
->last_level
+ 1,
1063 .array_len
= templ
->array_size
,
1064 .samples
= MAX2(templ
->nr_samples
, 1),
1065 .min_alignment_B
= 0,
1066 .row_pitch_B
= whandle
->stride
,
1068 .tiling_flags
= 1 << res
->mod_info
->tiling
);
1069 assert(isl_surf_created_successfully
);
1070 assert(res
->bo
->tiling_mode
==
1071 isl_tiling_to_i915_tiling(res
->surf
.tiling
));
1073 // XXX: create_ccs_buf_for_image?
1074 if (whandle
->modifier
== DRM_FORMAT_MOD_INVALID
) {
1075 if (!iris_resource_alloc_separate_aux(screen
, res
))
1078 if (res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1079 uint32_t alloc_flags
;
1081 bool ok
= iris_resource_configure_aux(screen
, res
, true, &size
,
1084 /* The gallium dri layer will create a separate plane resource
1085 * for the aux image. iris_resource_finish_aux_import will
1086 * merge the separate aux parameters back into a single
1092 /* Save modifier import information to reconstruct later. After
1093 * import, this will be available under a second image accessible
1094 * from the main image with res->base.next. See
1095 * iris_resource_finish_aux_import.
1097 res
->aux
.surf
.row_pitch_B
= whandle
->stride
;
1098 res
->aux
.offset
= whandle
->offset
;
1099 res
->aux
.bo
= res
->bo
;
1107 iris_resource_destroy(pscreen
, &res
->base
);
1112 iris_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*resource
)
1114 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1115 struct iris_resource
*res
= (void *) resource
;
1116 const struct isl_drm_modifier_info
*mod
= res
->mod_info
;
1118 iris_resource_prepare_access(ice
, res
,
1119 0, INTEL_REMAINING_LEVELS
,
1120 0, INTEL_REMAINING_LAYERS
,
1121 mod
? mod
->aux_usage
: ISL_AUX_USAGE_NONE
,
1122 mod
? mod
->supports_clear_color
: false);
1126 iris_resource_disable_aux_on_first_query(struct pipe_resource
*resource
,
1129 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1131 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1133 /* Disable aux usage if explicit flush not set and this is the first time
1134 * we are dealing with this resource and the resource was not created with
1135 * a modifier with aux.
1137 if (!mod_with_aux
&&
1138 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && res
->aux
.usage
!= 0) &&
1139 p_atomic_read(&resource
->reference
.count
) == 1) {
1140 iris_resource_disable_aux(res
);
1145 iris_resource_get_param(struct pipe_screen
*pscreen
,
1146 struct pipe_context
*context
,
1147 struct pipe_resource
*resource
,
1150 enum pipe_resource_param param
,
1151 unsigned handle_usage
,
1154 struct iris_screen
*screen
= (struct iris_screen
*)pscreen
;
1155 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1157 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1158 bool wants_aux
= mod_with_aux
&& plane
> 0;
1162 if (iris_resource_unfinished_aux_import(res
))
1163 iris_resource_finish_aux_import(pscreen
, res
);
1165 struct iris_bo
*bo
= wants_aux
? res
->aux
.bo
: res
->bo
;
1167 iris_resource_disable_aux_on_first_query(resource
, handle_usage
);
1170 case PIPE_RESOURCE_PARAM_NPLANES
:
1175 for (struct pipe_resource
*cur
= resource
; cur
; cur
= cur
->next
)
1180 case PIPE_RESOURCE_PARAM_STRIDE
:
1181 *value
= wants_aux
? res
->aux
.surf
.row_pitch_B
: res
->surf
.row_pitch_B
;
1183 case PIPE_RESOURCE_PARAM_OFFSET
:
1184 *value
= wants_aux
? res
->aux
.offset
: 0;
1186 case PIPE_RESOURCE_PARAM_MODIFIER
:
1187 *value
= res
->mod_info
? res
->mod_info
->modifier
:
1188 tiling_to_modifier(res
->bo
->tiling_mode
);
1190 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
1191 result
= iris_bo_flink(bo
, &handle
) == 0;
1195 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
: {
1196 /* Because we share the same drm file across multiple iris_screen, when
1197 * we export a GEM handle we must make sure it is valid in the DRM file
1198 * descriptor the caller is using (this is the FD given at screen
1202 if (iris_bo_export_gem_handle_for_device(bo
, screen
->winsys_fd
, &handle
))
1208 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
1209 result
= iris_bo_export_dmabuf(bo
, (int *) &handle
) == 0;
1219 iris_resource_get_handle(struct pipe_screen
*pscreen
,
1220 struct pipe_context
*ctx
,
1221 struct pipe_resource
*resource
,
1222 struct winsys_handle
*whandle
,
1225 struct iris_screen
*screen
= (struct iris_screen
*) pscreen
;
1226 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1228 res
->mod_info
&& res
->mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
;
1230 iris_resource_disable_aux_on_first_query(resource
, usage
);
1233 if (mod_with_aux
&& whandle
->plane
> 0) {
1234 assert(res
->aux
.bo
);
1236 whandle
->stride
= res
->aux
.surf
.row_pitch_B
;
1237 whandle
->offset
= res
->aux
.offset
;
1239 /* If this is a buffer, stride should be 0 - no need to special case */
1240 whandle
->stride
= res
->surf
.row_pitch_B
;
1244 whandle
->format
= res
->external_format
;
1246 res
->mod_info
? res
->mod_info
->modifier
1247 : tiling_to_modifier(res
->bo
->tiling_mode
);
1250 enum isl_aux_usage allowed_usage
=
1251 res
->mod_info
? res
->mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
1253 if (res
->aux
.usage
!= allowed_usage
) {
1254 enum isl_aux_state aux_state
= iris_resource_get_aux_state(res
, 0, 0);
1255 assert(aux_state
== ISL_AUX_STATE_RESOLVED
||
1256 aux_state
== ISL_AUX_STATE_PASS_THROUGH
);
1260 switch (whandle
->type
) {
1261 case WINSYS_HANDLE_TYPE_SHARED
:
1262 return iris_bo_flink(bo
, &whandle
->handle
) == 0;
1263 case WINSYS_HANDLE_TYPE_KMS
: {
1264 /* Because we share the same drm file across multiple iris_screen, when
1265 * we export a GEM handle we must make sure it is valid in the DRM file
1266 * descriptor the caller is using (this is the FD given at screen
1270 if (iris_bo_export_gem_handle_for_device(bo
, screen
->winsys_fd
, &handle
))
1272 whandle
->handle
= handle
;
1275 case WINSYS_HANDLE_TYPE_FD
:
1276 return iris_bo_export_dmabuf(bo
, (int *) &whandle
->handle
) == 0;
1283 resource_is_busy(struct iris_context
*ice
,
1284 struct iris_resource
*res
)
1286 bool busy
= iris_bo_busy(res
->bo
);
1288 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++)
1289 busy
|= iris_batch_references(&ice
->batches
[i
], res
->bo
);
1295 iris_invalidate_resource(struct pipe_context
*ctx
,
1296 struct pipe_resource
*resource
)
1298 struct iris_screen
*screen
= (void *) ctx
->screen
;
1299 struct iris_context
*ice
= (void *) ctx
;
1300 struct iris_resource
*res
= (void *) resource
;
1302 if (resource
->target
!= PIPE_BUFFER
)
1305 /* If it's already invalidated, don't bother doing anything. */
1306 if (res
->valid_buffer_range
.start
> res
->valid_buffer_range
.end
)
1309 if (!resource_is_busy(ice
, res
)) {
1310 /* The resource is idle, so just mark that it contains no data and
1311 * keep using the same underlying buffer object.
1313 util_range_set_empty(&res
->valid_buffer_range
);
1317 /* Otherwise, try and replace the backing storage with a new BO. */
1319 /* We can't reallocate memory we didn't allocate in the first place. */
1320 if (res
->bo
->userptr
)
1323 // XXX: We should support this.
1324 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
)
1327 struct iris_bo
*old_bo
= res
->bo
;
1328 struct iris_bo
*new_bo
=
1329 iris_bo_alloc(screen
->bufmgr
, res
->bo
->name
, resource
->width0
,
1330 iris_memzone_for_address(old_bo
->gtt_offset
));
1334 /* Swap out the backing storage */
1337 /* Rebind the buffer, replacing any state referring to the old BO's
1338 * address, and marking state dirty so it's reemitted.
1340 screen
->vtbl
.rebind_buffer(ice
, res
);
1342 util_range_set_empty(&res
->valid_buffer_range
);
1344 iris_bo_unreference(old_bo
);
1348 iris_flush_staging_region(struct pipe_transfer
*xfer
,
1349 const struct pipe_box
*flush_box
)
1351 if (!(xfer
->usage
& PIPE_TRANSFER_WRITE
))
1354 struct iris_transfer
*map
= (void *) xfer
;
1356 struct pipe_box src_box
= *flush_box
;
1358 /* Account for extra alignment padding in staging buffer */
1359 if (xfer
->resource
->target
== PIPE_BUFFER
)
1360 src_box
.x
+= xfer
->box
.x
% IRIS_MAP_BUFFER_ALIGNMENT
;
1362 struct pipe_box dst_box
= (struct pipe_box
) {
1363 .x
= xfer
->box
.x
+ flush_box
->x
,
1364 .y
= xfer
->box
.y
+ flush_box
->y
,
1365 .z
= xfer
->box
.z
+ flush_box
->z
,
1366 .width
= flush_box
->width
,
1367 .height
= flush_box
->height
,
1368 .depth
= flush_box
->depth
,
1371 iris_copy_region(map
->blorp
, map
->batch
, xfer
->resource
, xfer
->level
,
1372 dst_box
.x
, dst_box
.y
, dst_box
.z
, map
->staging
, 0,
1377 iris_unmap_copy_region(struct iris_transfer
*map
)
1379 iris_resource_destroy(map
->staging
->screen
, map
->staging
);
1385 iris_map_copy_region(struct iris_transfer
*map
)
1387 struct pipe_screen
*pscreen
= &map
->batch
->screen
->base
;
1388 struct pipe_transfer
*xfer
= &map
->base
;
1389 struct pipe_box
*box
= &xfer
->box
;
1390 struct iris_resource
*res
= (void *) xfer
->resource
;
1392 unsigned extra
= xfer
->resource
->target
== PIPE_BUFFER
?
1393 box
->x
% IRIS_MAP_BUFFER_ALIGNMENT
: 0;
1395 struct pipe_resource templ
= (struct pipe_resource
) {
1396 .usage
= PIPE_USAGE_STAGING
,
1397 .width0
= box
->width
+ extra
,
1398 .height0
= box
->height
,
1400 .nr_samples
= xfer
->resource
->nr_samples
,
1401 .nr_storage_samples
= xfer
->resource
->nr_storage_samples
,
1402 .array_size
= box
->depth
,
1403 .format
= res
->internal_format
,
1406 if (xfer
->resource
->target
== PIPE_BUFFER
)
1407 templ
.target
= PIPE_BUFFER
;
1408 else if (templ
.array_size
> 1)
1409 templ
.target
= PIPE_TEXTURE_2D_ARRAY
;
1411 templ
.target
= PIPE_TEXTURE_2D
;
1413 map
->staging
= iris_resource_create(pscreen
, &templ
);
1414 assert(map
->staging
);
1416 if (templ
.target
!= PIPE_BUFFER
) {
1417 struct isl_surf
*surf
= &((struct iris_resource
*) map
->staging
)->surf
;
1418 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1419 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1422 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1423 iris_copy_region(map
->blorp
, map
->batch
, map
->staging
, 0, extra
, 0, 0,
1424 xfer
->resource
, xfer
->level
, box
);
1425 /* Ensure writes to the staging BO land before we map it below. */
1426 iris_emit_pipe_control_flush(map
->batch
,
1427 "transfer read: flush before mapping",
1428 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
1429 PIPE_CONTROL_CS_STALL
);
1432 struct iris_bo
*staging_bo
= iris_resource_bo(map
->staging
);
1434 if (iris_batch_references(map
->batch
, staging_bo
))
1435 iris_batch_flush(map
->batch
);
1438 iris_bo_map(map
->dbg
, staging_bo
, xfer
->usage
& MAP_FLAGS
) + extra
;
1440 map
->unmap
= iris_unmap_copy_region
;
1444 get_image_offset_el(const struct isl_surf
*surf
, unsigned level
, unsigned z
,
1445 unsigned *out_x0_el
, unsigned *out_y0_el
)
1447 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1448 isl_surf_get_image_offset_el(surf
, level
, 0, z
, out_x0_el
, out_y0_el
);
1450 isl_surf_get_image_offset_el(surf
, level
, z
, 0, out_x0_el
, out_y0_el
);
1455 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1456 * different tiling patterns.
1459 iris_resource_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1460 uint32_t *tile_w
, uint32_t *tile_h
)
1471 case ISL_TILING_LINEAR
:
1476 unreachable("not reached");
1482 * This function computes masks that may be used to select the bits of the X
1483 * and Y coordinates that indicate the offset within a tile. If the BO is
1484 * untiled, the masks are set to 0.
1487 iris_resource_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1488 uint32_t *mask_x
, uint32_t *mask_y
)
1490 uint32_t tile_w_bytes
, tile_h
;
1492 iris_resource_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1494 *mask_x
= tile_w_bytes
/ cpp
- 1;
1495 *mask_y
= tile_h
- 1;
1499 * Compute the offset (in bytes) from the start of the BO to the given x
1500 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1501 * multiples of the tile size.
1504 iris_resource_get_aligned_offset(const struct iris_resource
*res
,
1505 uint32_t x
, uint32_t y
)
1507 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1508 unsigned cpp
= fmtl
->bpb
/ 8;
1509 uint32_t pitch
= res
->surf
.row_pitch_B
;
1511 switch (res
->surf
.tiling
) {
1513 unreachable("not reached");
1514 case ISL_TILING_LINEAR
:
1515 return y
* pitch
+ x
* cpp
;
1517 assert((x
% (512 / cpp
)) == 0);
1518 assert((y
% 8) == 0);
1519 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1521 assert((x
% (128 / cpp
)) == 0);
1522 assert((y
% 32) == 0);
1523 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1528 * Rendering with tiled buffers requires that the base address of the buffer
1529 * be aligned to a page boundary. For renderbuffers, and sometimes with
1530 * textures, we may want the surface to point at a texture image level that
1531 * isn't at a page boundary.
1533 * This function returns an appropriately-aligned base offset
1534 * according to the tiling restrictions, plus any required x/y offset
1538 iris_resource_get_tile_offsets(const struct iris_resource
*res
,
1539 uint32_t level
, uint32_t z
,
1540 uint32_t *tile_x
, uint32_t *tile_y
)
1543 uint32_t mask_x
, mask_y
;
1545 const struct isl_format_layout
*fmtl
= isl_format_get_layout(res
->surf
.format
);
1546 const unsigned cpp
= fmtl
->bpb
/ 8;
1548 iris_resource_get_tile_masks(res
->surf
.tiling
, cpp
, &mask_x
, &mask_y
);
1549 get_image_offset_el(&res
->surf
, level
, z
, &x
, &y
);
1551 *tile_x
= x
& mask_x
;
1552 *tile_y
= y
& mask_y
;
1554 return iris_resource_get_aligned_offset(res
, x
& ~mask_x
, y
& ~mask_y
);
1558 * Get pointer offset into stencil buffer.
1560 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1561 * must decode the tile's layout in software.
1564 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1566 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1568 * Even though the returned offset is always positive, the return type is
1570 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1571 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1574 s8_offset(uint32_t stride
, uint32_t x
, uint32_t y
)
1576 uint32_t tile_size
= 4096;
1577 uint32_t tile_width
= 64;
1578 uint32_t tile_height
= 64;
1579 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
1581 uint32_t tile_x
= x
/ tile_width
;
1582 uint32_t tile_y
= y
/ tile_height
;
1584 /* The byte's address relative to the tile's base addres. */
1585 uint32_t byte_x
= x
% tile_width
;
1586 uint32_t byte_y
= y
% tile_height
;
1588 uintptr_t u
= tile_y
* row_size
1589 + tile_x
* tile_size
1590 + 512 * (byte_x
/ 8)
1592 + 32 * ((byte_y
/ 4) % 2)
1593 + 16 * ((byte_x
/ 4) % 2)
1594 + 8 * ((byte_y
/ 2) % 2)
1595 + 4 * ((byte_x
/ 2) % 2)
1603 iris_unmap_s8(struct iris_transfer
*map
)
1605 struct pipe_transfer
*xfer
= &map
->base
;
1606 const struct pipe_box
*box
= &xfer
->box
;
1607 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1608 struct isl_surf
*surf
= &res
->surf
;
1610 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1611 uint8_t *untiled_s8_map
= map
->ptr
;
1612 uint8_t *tiled_s8_map
=
1613 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1615 for (int s
= 0; s
< box
->depth
; s
++) {
1616 unsigned x0_el
, y0_el
;
1617 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1619 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1620 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1621 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1623 y0_el
+ box
->y
+ y
);
1624 tiled_s8_map
[offset
] =
1625 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
];
1635 iris_map_s8(struct iris_transfer
*map
)
1637 struct pipe_transfer
*xfer
= &map
->base
;
1638 const struct pipe_box
*box
= &xfer
->box
;
1639 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1640 struct isl_surf
*surf
= &res
->surf
;
1642 xfer
->stride
= surf
->row_pitch_B
;
1643 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1645 /* The tiling and detiling functions require that the linear buffer has
1646 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1647 * over-allocate the linear buffer to get the proper alignment.
1649 map
->buffer
= map
->ptr
= malloc(xfer
->layer_stride
* box
->depth
);
1650 assert(map
->buffer
);
1652 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1653 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1654 * invalidate is set, since we'll be writing the whole rectangle from our
1655 * temporary buffer back out.
1657 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1658 uint8_t *untiled_s8_map
= map
->ptr
;
1659 uint8_t *tiled_s8_map
=
1660 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1662 for (int s
= 0; s
< box
->depth
; s
++) {
1663 unsigned x0_el
, y0_el
;
1664 get_image_offset_el(surf
, xfer
->level
, box
->z
+ s
, &x0_el
, &y0_el
);
1666 for (uint32_t y
= 0; y
< box
->height
; y
++) {
1667 for (uint32_t x
= 0; x
< box
->width
; x
++) {
1668 ptrdiff_t offset
= s8_offset(surf
->row_pitch_B
,
1670 y0_el
+ box
->y
+ y
);
1671 untiled_s8_map
[s
* xfer
->layer_stride
+ y
* xfer
->stride
+ x
] =
1672 tiled_s8_map
[offset
];
1678 map
->unmap
= iris_unmap_s8
;
1681 /* Compute extent parameters for use with tiled_memcpy functions.
1682 * xs are in units of bytes and ys are in units of strides.
1685 tile_extents(const struct isl_surf
*surf
,
1686 const struct pipe_box
*box
,
1687 unsigned level
, int z
,
1688 unsigned *x1_B
, unsigned *x2_B
,
1689 unsigned *y1_el
, unsigned *y2_el
)
1691 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1692 const unsigned cpp
= fmtl
->bpb
/ 8;
1694 assert(box
->x
% fmtl
->bw
== 0);
1695 assert(box
->y
% fmtl
->bh
== 0);
1697 unsigned x0_el
, y0_el
;
1698 get_image_offset_el(surf
, level
, box
->z
+ z
, &x0_el
, &y0_el
);
1700 *x1_B
= (box
->x
/ fmtl
->bw
+ x0_el
) * cpp
;
1701 *y1_el
= box
->y
/ fmtl
->bh
+ y0_el
;
1702 *x2_B
= (DIV_ROUND_UP(box
->x
+ box
->width
, fmtl
->bw
) + x0_el
) * cpp
;
1703 *y2_el
= DIV_ROUND_UP(box
->y
+ box
->height
, fmtl
->bh
) + y0_el
;
1707 iris_unmap_tiled_memcpy(struct iris_transfer
*map
)
1709 struct pipe_transfer
*xfer
= &map
->base
;
1710 const struct pipe_box
*box
= &xfer
->box
;
1711 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1712 struct isl_surf
*surf
= &res
->surf
;
1714 const bool has_swizzling
= false;
1716 if (xfer
->usage
& PIPE_TRANSFER_WRITE
) {
1718 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1720 for (int s
= 0; s
< box
->depth
; s
++) {
1721 unsigned x1
, x2
, y1
, y2
;
1722 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1724 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1726 isl_memcpy_linear_to_tiled(x1
, x2
, y1
, y2
, dst
, ptr
,
1727 surf
->row_pitch_B
, xfer
->stride
,
1728 has_swizzling
, surf
->tiling
, ISL_MEMCPY
);
1731 os_free_aligned(map
->buffer
);
1732 map
->buffer
= map
->ptr
= NULL
;
1736 iris_map_tiled_memcpy(struct iris_transfer
*map
)
1738 struct pipe_transfer
*xfer
= &map
->base
;
1739 const struct pipe_box
*box
= &xfer
->box
;
1740 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1741 struct isl_surf
*surf
= &res
->surf
;
1743 xfer
->stride
= ALIGN(surf
->row_pitch_B
, 16);
1744 xfer
->layer_stride
= xfer
->stride
* box
->height
;
1746 unsigned x1
, x2
, y1
, y2
;
1747 tile_extents(surf
, box
, xfer
->level
, 0, &x1
, &x2
, &y1
, &y2
);
1749 /* The tiling and detiling functions require that the linear buffer has
1750 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1751 * over-allocate the linear buffer to get the proper alignment.
1754 os_malloc_aligned(xfer
->layer_stride
* box
->depth
, 16);
1755 assert(map
->buffer
);
1756 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
1758 const bool has_swizzling
= false;
1760 if (!(xfer
->usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
1762 iris_bo_map(map
->dbg
, res
->bo
, (xfer
->usage
| MAP_RAW
) & MAP_FLAGS
);
1764 for (int s
= 0; s
< box
->depth
; s
++) {
1765 unsigned x1
, x2
, y1
, y2
;
1766 tile_extents(surf
, box
, xfer
->level
, s
, &x1
, &x2
, &y1
, &y2
);
1768 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1769 void *ptr
= map
->ptr
+ s
* xfer
->layer_stride
;
1771 isl_memcpy_tiled_to_linear(x1
, x2
, y1
, y2
, ptr
, src
, xfer
->stride
,
1772 surf
->row_pitch_B
, has_swizzling
,
1773 surf
->tiling
, ISL_MEMCPY_STREAMING_LOAD
);
1777 map
->unmap
= iris_unmap_tiled_memcpy
;
1781 iris_map_direct(struct iris_transfer
*map
)
1783 struct pipe_transfer
*xfer
= &map
->base
;
1784 struct pipe_box
*box
= &xfer
->box
;
1785 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1787 void *ptr
= iris_bo_map(map
->dbg
, res
->bo
, xfer
->usage
& MAP_FLAGS
);
1789 if (res
->base
.target
== PIPE_BUFFER
) {
1791 xfer
->layer_stride
= 0;
1793 map
->ptr
= ptr
+ box
->x
;
1795 struct isl_surf
*surf
= &res
->surf
;
1796 const struct isl_format_layout
*fmtl
=
1797 isl_format_get_layout(surf
->format
);
1798 const unsigned cpp
= fmtl
->bpb
/ 8;
1799 unsigned x0_el
, y0_el
;
1801 get_image_offset_el(surf
, xfer
->level
, box
->z
, &x0_el
, &y0_el
);
1803 xfer
->stride
= isl_surf_get_row_pitch_B(surf
);
1804 xfer
->layer_stride
= isl_surf_get_array_pitch(surf
);
1806 map
->ptr
= ptr
+ (y0_el
+ box
->y
) * xfer
->stride
+ (x0_el
+ box
->x
) * cpp
;
1811 can_promote_to_async(const struct iris_resource
*res
,
1812 const struct pipe_box
*box
,
1813 enum pipe_transfer_usage usage
)
1815 /* If we're writing to a section of the buffer that hasn't even been
1816 * initialized with useful data, then we can safely promote this write
1817 * to be unsynchronized. This helps the common pattern of appending data.
1819 return res
->base
.target
== PIPE_BUFFER
&& (usage
& PIPE_TRANSFER_WRITE
) &&
1820 !(usage
& TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED
) &&
1821 !util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1822 box
->x
+ box
->width
);
1826 iris_transfer_map(struct pipe_context
*ctx
,
1827 struct pipe_resource
*resource
,
1829 enum pipe_transfer_usage usage
,
1830 const struct pipe_box
*box
,
1831 struct pipe_transfer
**ptransfer
)
1833 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1834 struct iris_resource
*res
= (struct iris_resource
*)resource
;
1835 struct isl_surf
*surf
= &res
->surf
;
1837 if (iris_resource_unfinished_aux_import(res
))
1838 iris_resource_finish_aux_import(ctx
->screen
, res
);
1840 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
1841 /* Replace the backing storage with a fresh buffer for non-async maps */
1842 if (!(usage
& (PIPE_TRANSFER_UNSYNCHRONIZED
|
1843 TC_TRANSFER_MAP_NO_INVALIDATE
)))
1844 iris_invalidate_resource(ctx
, resource
);
1846 /* If we can discard the whole resource, we can discard the range. */
1847 usage
|= PIPE_TRANSFER_DISCARD_RANGE
;
1850 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
1851 can_promote_to_async(res
, box
, usage
)) {
1852 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1855 bool need_resolve
= false;
1856 bool need_color_resolve
= false;
1858 if (resource
->target
!= PIPE_BUFFER
) {
1859 bool need_hiz_resolve
= iris_resource_level_has_hiz(res
, level
);
1860 bool need_stencil_resolve
= res
->aux
.usage
== ISL_AUX_USAGE_STC_CCS
;
1862 need_color_resolve
=
1863 (res
->aux
.usage
== ISL_AUX_USAGE_CCS_D
||
1864 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
||
1865 res
->aux
.usage
== ISL_AUX_USAGE_GEN12_CCS_E
) &&
1866 iris_has_color_unresolved(res
, level
, 1, box
->z
, box
->depth
);
1868 need_resolve
= need_color_resolve
||
1870 need_stencil_resolve
;
1873 bool map_would_stall
= false;
1875 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1876 map_would_stall
= need_resolve
|| resource_is_busy(ice
, res
);
1878 if (map_would_stall
&& (usage
& PIPE_TRANSFER_DONTBLOCK
) &&
1879 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1883 if (surf
->tiling
!= ISL_TILING_LINEAR
&&
1884 (usage
& PIPE_TRANSFER_MAP_DIRECTLY
))
1887 struct iris_transfer
*map
= slab_alloc(&ice
->transfer_pool
);
1888 struct pipe_transfer
*xfer
= &map
->base
;
1893 memset(map
, 0, sizeof(*map
));
1894 map
->dbg
= &ice
->dbg
;
1896 pipe_resource_reference(&xfer
->resource
, resource
);
1897 xfer
->level
= level
;
1898 xfer
->usage
= usage
;
1902 map
->dest_had_defined_contents
=
1903 util_ranges_intersect(&res
->valid_buffer_range
, box
->x
,
1904 box
->x
+ box
->width
);
1906 if (usage
& PIPE_TRANSFER_WRITE
)
1907 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1909 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1910 * there is to access them simultaneously on the CPU & GPU. This also
1911 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1912 * contain state we're constructing for a GPU draw call, which would
1913 * kill us with infinite stack recursion.
1915 bool no_gpu
= usage
& (PIPE_TRANSFER_PERSISTENT
|
1916 PIPE_TRANSFER_COHERENT
|
1917 PIPE_TRANSFER_MAP_DIRECTLY
);
1919 /* GPU copies are not useful for buffer reads. Instead of stalling to
1920 * read from the original buffer, we'd simply copy it to a temporary...
1921 * then stall (a bit longer) to read from that buffer.
1923 * Images are less clear-cut. Color resolves are destructive, removing
1924 * the underlying compression, so we'd rather blit the data to a linear
1925 * temporary and map that, to avoid the resolve. (It might be better to
1926 * a tiled temporary and use the tiled_memcpy paths...)
1928 if (!(usage
& PIPE_TRANSFER_DISCARD_RANGE
) && !need_color_resolve
)
1931 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1932 if (fmtl
->txc
== ISL_TXC_ASTC
)
1935 if ((map_would_stall
||
1936 res
->aux
.usage
== ISL_AUX_USAGE_CCS_E
||
1937 res
->aux
.usage
== ISL_AUX_USAGE_GEN12_CCS_E
) && !no_gpu
) {
1938 /* If we need a synchronous mapping and the resource is busy, or needs
1939 * resolving, we copy to/from a linear temporary buffer using the GPU.
1941 map
->batch
= &ice
->batches
[IRIS_BATCH_RENDER
];
1942 map
->blorp
= &ice
->blorp
;
1943 iris_map_copy_region(map
);
1945 /* Otherwise we're free to map on the CPU. */
1948 iris_resource_access_raw(ice
, res
, level
, box
->z
, box
->depth
,
1949 usage
& PIPE_TRANSFER_WRITE
);
1952 if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
1953 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1954 if (iris_batch_references(&ice
->batches
[i
], res
->bo
))
1955 iris_batch_flush(&ice
->batches
[i
]);
1959 if (surf
->tiling
== ISL_TILING_W
) {
1960 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1962 } else if (surf
->tiling
!= ISL_TILING_LINEAR
) {
1963 iris_map_tiled_memcpy(map
);
1965 iris_map_direct(map
);
1973 iris_transfer_flush_region(struct pipe_context
*ctx
,
1974 struct pipe_transfer
*xfer
,
1975 const struct pipe_box
*box
)
1977 struct iris_context
*ice
= (struct iris_context
*)ctx
;
1978 struct iris_resource
*res
= (struct iris_resource
*) xfer
->resource
;
1979 struct iris_transfer
*map
= (void *) xfer
;
1982 iris_flush_staging_region(xfer
, box
);
1984 uint32_t history_flush
= 0;
1986 if (res
->base
.target
== PIPE_BUFFER
) {
1988 history_flush
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
1990 if (map
->dest_had_defined_contents
)
1991 history_flush
|= iris_flush_bits_for_history(res
);
1993 util_range_add(&res
->base
, &res
->valid_buffer_range
, box
->x
, box
->x
+ box
->width
);
1996 if (history_flush
& ~PIPE_CONTROL_CS_STALL
) {
1997 for (int i
= 0; i
< IRIS_BATCH_COUNT
; i
++) {
1998 struct iris_batch
*batch
= &ice
->batches
[i
];
1999 if (batch
->contains_draw
|| batch
->cache
.render
->entries
) {
2000 iris_batch_maybe_flush(batch
, 24);
2001 iris_emit_pipe_control_flush(batch
,
2002 "cache history: transfer flush",
2008 /* Make sure we flag constants dirty even if there's no need to emit
2009 * any PIPE_CONTROLs to a batch.
2011 iris_dirty_for_history(ice
, res
);
2015 iris_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*xfer
)
2017 struct iris_context
*ice
= (struct iris_context
*)ctx
;
2018 struct iris_transfer
*map
= (void *) xfer
;
2020 if (!(xfer
->usage
& (PIPE_TRANSFER_FLUSH_EXPLICIT
|
2021 PIPE_TRANSFER_COHERENT
))) {
2022 struct pipe_box flush_box
= {
2023 .x
= 0, .y
= 0, .z
= 0,
2024 .width
= xfer
->box
.width
,
2025 .height
= xfer
->box
.height
,
2026 .depth
= xfer
->box
.depth
,
2028 iris_transfer_flush_region(ctx
, xfer
, &flush_box
);
2034 pipe_resource_reference(&xfer
->resource
, NULL
);
2035 slab_free(&ice
->transfer_pool
, map
);
2039 * Mark state dirty that needs to be re-emitted when a resource is written.
2042 iris_dirty_for_history(struct iris_context
*ice
,
2043 struct iris_resource
*res
)
2045 uint64_t stage_dirty
= 0ull;
2047 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
2048 stage_dirty
|= ((uint64_t)res
->bind_stages
)
2049 << IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS
;
2052 ice
->state
.stage_dirty
|= stage_dirty
;
2056 * Produce a set of PIPE_CONTROL bits which ensure data written to a
2057 * resource becomes visible, and any stale read cache data is invalidated.
2060 iris_flush_bits_for_history(struct iris_resource
*res
)
2062 uint32_t flush
= PIPE_CONTROL_CS_STALL
;
2064 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
2065 flush
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
2066 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2069 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
)
2070 flush
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
2072 if (res
->bind_history
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
))
2073 flush
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
2075 if (res
->bind_history
& (PIPE_BIND_SHADER_BUFFER
| PIPE_BIND_SHADER_IMAGE
))
2076 flush
|= PIPE_CONTROL_DATA_CACHE_FLUSH
;
2082 iris_flush_and_dirty_for_history(struct iris_context
*ice
,
2083 struct iris_batch
*batch
,
2084 struct iris_resource
*res
,
2085 uint32_t extra_flags
,
2088 if (res
->base
.target
!= PIPE_BUFFER
)
2091 uint32_t flush
= iris_flush_bits_for_history(res
) | extra_flags
;
2093 iris_emit_pipe_control_flush(batch
, reason
, flush
);
2095 iris_dirty_for_history(ice
, res
);
2099 iris_resource_set_clear_color(struct iris_context
*ice
,
2100 struct iris_resource
*res
,
2101 union isl_color_value color
)
2103 if (memcmp(&res
->aux
.clear_color
, &color
, sizeof(color
)) != 0) {
2104 res
->aux
.clear_color
= color
;
2111 union isl_color_value
2112 iris_resource_get_clear_color(const struct iris_resource
*res
,
2113 struct iris_bo
**clear_color_bo
,
2114 uint64_t *clear_color_offset
)
2116 assert(res
->aux
.bo
);
2119 *clear_color_bo
= res
->aux
.clear_color_bo
;
2120 if (clear_color_offset
)
2121 *clear_color_offset
= res
->aux
.clear_color_offset
;
2122 return res
->aux
.clear_color
;
2125 static enum pipe_format
2126 iris_resource_get_internal_format(struct pipe_resource
*p_res
)
2128 struct iris_resource
*res
= (void *) p_res
;
2129 return res
->internal_format
;
2132 static const struct u_transfer_vtbl transfer_vtbl
= {
2133 .resource_create
= iris_resource_create
,
2134 .resource_destroy
= iris_resource_destroy
,
2135 .transfer_map
= iris_transfer_map
,
2136 .transfer_unmap
= iris_transfer_unmap
,
2137 .transfer_flush_region
= iris_transfer_flush_region
,
2138 .get_internal_format
= iris_resource_get_internal_format
,
2139 .set_stencil
= iris_resource_set_separate_stencil
,
2140 .get_stencil
= iris_resource_get_separate_stencil
,
2144 iris_init_screen_resource_functions(struct pipe_screen
*pscreen
)
2146 pscreen
->query_dmabuf_modifiers
= iris_query_dmabuf_modifiers
;
2147 pscreen
->resource_create_with_modifiers
=
2148 iris_resource_create_with_modifiers
;
2149 pscreen
->resource_create
= u_transfer_helper_resource_create
;
2150 pscreen
->resource_from_user_memory
= iris_resource_from_user_memory
;
2151 pscreen
->resource_from_handle
= iris_resource_from_handle
;
2152 pscreen
->resource_get_handle
= iris_resource_get_handle
;
2153 pscreen
->resource_get_param
= iris_resource_get_param
;
2154 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
2155 pscreen
->transfer_helper
=
2156 u_transfer_helper_create(&transfer_vtbl
, true, true, false, true);
2160 iris_init_resource_functions(struct pipe_context
*ctx
)
2162 ctx
->flush_resource
= iris_flush_resource
;
2163 ctx
->invalidate_resource
= iris_invalidate_resource
;
2164 ctx
->transfer_map
= u_transfer_helper_transfer_map
;
2165 ctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
2166 ctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
2167 ctx
->buffer_subdata
= u_default_buffer_subdata
;
2168 ctx
->texture_subdata
= u_default_texture_subdata
;