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26 * ============================= GENXML CODE =============================
27 * [This file is compiled once per generation.]
28 * =======================================================================
30 * This is the main state upload code.
32 * Gallium uses Constant State Objects, or CSOs, for most state. Large,
33 * complex, or highly reusable state can be created once, and bound and
34 * rebound multiple times. This is modeled with the pipe->create_*_state()
35 * and pipe->bind_*_state() hooks. Highly dynamic or inexpensive state is
36 * streamed out on the fly, via pipe->set_*_state() hooks.
38 * OpenGL involves frequently mutating context state, which is mirrored in
39 * core Mesa by highly mutable data structures. However, most applications
40 * typically draw the same things over and over - from frame to frame, most
41 * of the same objects are still visible and need to be redrawn. So, rather
42 * than inventing new state all the time, applications usually mutate to swap
43 * between known states that we've seen before.
45 * Gallium isolates us from this mutation by tracking API state, and
46 * distilling it into a set of Constant State Objects, or CSOs. Large,
47 * complex, or typically reusable state can be created once, then reused
48 * multiple times. Drivers can create and store their own associated data.
49 * This create/bind model corresponds to the pipe->create_*_state() and
50 * pipe->bind_*_state() driver hooks.
52 * Some state is cheap to create, or expected to be highly dynamic. Rather
53 * than creating and caching piles of CSOs for these, Gallium simply streams
54 * them out, via the pipe->set_*_state() driver hooks.
56 * To reduce draw time overhead, we try to compute as much state at create
57 * time as possible. Wherever possible, we translate the Gallium pipe state
58 * to 3DSTATE commands, and store those commands in the CSO. At draw time,
59 * we can simply memcpy them into a batch buffer.
61 * No hardware matches the abstraction perfectly, so some commands require
62 * information from multiple CSOs. In this case, we can store two copies
63 * of the packet (one in each CSO), and simply | together their DWords at
64 * draw time. Sometimes the second set is trivial (one or two fields), so
65 * we simply pack it at draw time.
67 * There are two main components in the file below. First, the CSO hooks
68 * create/bind/track state. The second are the draw-time upload functions,
69 * iris_upload_render_state() and iris_upload_compute_state(), which read
70 * the context state and emit the commands into the actual batch.
81 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
87 #include "pipe/p_defines.h"
88 #include "pipe/p_state.h"
89 #include "pipe/p_context.h"
90 #include "pipe/p_screen.h"
91 #include "util/u_dual_blend.h"
92 #include "util/u_inlines.h"
93 #include "util/u_format.h"
94 #include "util/u_framebuffer.h"
95 #include "util/u_transfer.h"
96 #include "util/u_upload_mgr.h"
97 #include "util/u_viewport.h"
98 #include "drm-uapi/i915_drm.h"
100 #include "intel/compiler/brw_compiler.h"
101 #include "intel/common/gen_l3_config.h"
102 #include "intel/common/gen_sample_positions.h"
103 #include "iris_batch.h"
104 #include "iris_context.h"
105 #include "iris_defines.h"
106 #include "iris_pipe.h"
107 #include "iris_resource.h"
109 #define __gen_address_type struct iris_address
110 #define __gen_user_data struct iris_batch
112 #define ARRAY_BYTES(x) (sizeof(uint32_t) * ARRAY_SIZE(x))
115 __gen_combine_address(struct iris_batch
*batch
, void *location
,
116 struct iris_address addr
, uint32_t delta
)
118 uint64_t result
= addr
.offset
+ delta
;
121 iris_use_pinned_bo(batch
, addr
.bo
, addr
.write
);
122 /* Assume this is a general address, not relative to a base. */
123 result
+= addr
.bo
->gtt_offset
;
129 #define __genxml_cmd_length(cmd) cmd ## _length
130 #define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
131 #define __genxml_cmd_header(cmd) cmd ## _header
132 #define __genxml_cmd_pack(cmd) cmd ## _pack
134 #define _iris_pack_command(batch, cmd, dst, name) \
135 for (struct cmd name = { __genxml_cmd_header(cmd) }, \
136 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
137 ({ __genxml_cmd_pack(cmd)(batch, (void *)_dst, &name); \
141 #define iris_pack_command(cmd, dst, name) \
142 _iris_pack_command(NULL, cmd, dst, name)
144 #define iris_pack_state(cmd, dst, name) \
145 for (struct cmd name = {}, \
146 *_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
147 __genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
150 #define iris_emit_cmd(batch, cmd, name) \
151 _iris_pack_command(batch, cmd, iris_get_command_space(batch, 4 * __genxml_cmd_length(cmd)), name)
153 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \
155 uint32_t *dw = iris_get_command_space(batch, 4 * num_dwords); \
156 for (uint32_t i = 0; i < num_dwords; i++) \
157 dw[i] = (dwords0)[i] | (dwords1)[i]; \
158 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
161 #include "genxml/genX_pack.h"
162 #include "genxml/gen_macros.h"
163 #include "genxml/genX_bits.h"
166 #define MOCS_PTE 0x18
169 #define MOCS_PTE (1 << 1)
170 #define MOCS_WB (2 << 1)
174 mocs(const struct iris_bo
*bo
)
176 return bo
&& bo
->external
? MOCS_PTE
: MOCS_WB
;
180 * Statically assert that PIPE_* enums match the hardware packets.
181 * (As long as they match, we don't need to translate them.)
183 UNUSED
static void pipe_asserts()
185 #define PIPE_ASSERT(x) STATIC_ASSERT((int)x)
187 /* pipe_logicop happens to match the hardware. */
188 PIPE_ASSERT(PIPE_LOGICOP_CLEAR
== LOGICOP_CLEAR
);
189 PIPE_ASSERT(PIPE_LOGICOP_NOR
== LOGICOP_NOR
);
190 PIPE_ASSERT(PIPE_LOGICOP_AND_INVERTED
== LOGICOP_AND_INVERTED
);
191 PIPE_ASSERT(PIPE_LOGICOP_COPY_INVERTED
== LOGICOP_COPY_INVERTED
);
192 PIPE_ASSERT(PIPE_LOGICOP_AND_REVERSE
== LOGICOP_AND_REVERSE
);
193 PIPE_ASSERT(PIPE_LOGICOP_INVERT
== LOGICOP_INVERT
);
194 PIPE_ASSERT(PIPE_LOGICOP_XOR
== LOGICOP_XOR
);
195 PIPE_ASSERT(PIPE_LOGICOP_NAND
== LOGICOP_NAND
);
196 PIPE_ASSERT(PIPE_LOGICOP_AND
== LOGICOP_AND
);
197 PIPE_ASSERT(PIPE_LOGICOP_EQUIV
== LOGICOP_EQUIV
);
198 PIPE_ASSERT(PIPE_LOGICOP_NOOP
== LOGICOP_NOOP
);
199 PIPE_ASSERT(PIPE_LOGICOP_OR_INVERTED
== LOGICOP_OR_INVERTED
);
200 PIPE_ASSERT(PIPE_LOGICOP_COPY
== LOGICOP_COPY
);
201 PIPE_ASSERT(PIPE_LOGICOP_OR_REVERSE
== LOGICOP_OR_REVERSE
);
202 PIPE_ASSERT(PIPE_LOGICOP_OR
== LOGICOP_OR
);
203 PIPE_ASSERT(PIPE_LOGICOP_SET
== LOGICOP_SET
);
205 /* pipe_blend_func happens to match the hardware. */
206 PIPE_ASSERT(PIPE_BLENDFACTOR_ONE
== BLENDFACTOR_ONE
);
207 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_COLOR
== BLENDFACTOR_SRC_COLOR
);
208 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA
== BLENDFACTOR_SRC_ALPHA
);
209 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_ALPHA
== BLENDFACTOR_DST_ALPHA
);
210 PIPE_ASSERT(PIPE_BLENDFACTOR_DST_COLOR
== BLENDFACTOR_DST_COLOR
);
211 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
== BLENDFACTOR_SRC_ALPHA_SATURATE
);
212 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_COLOR
== BLENDFACTOR_CONST_COLOR
);
213 PIPE_ASSERT(PIPE_BLENDFACTOR_CONST_ALPHA
== BLENDFACTOR_CONST_ALPHA
);
214 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_COLOR
== BLENDFACTOR_SRC1_COLOR
);
215 PIPE_ASSERT(PIPE_BLENDFACTOR_SRC1_ALPHA
== BLENDFACTOR_SRC1_ALPHA
);
216 PIPE_ASSERT(PIPE_BLENDFACTOR_ZERO
== BLENDFACTOR_ZERO
);
217 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_COLOR
== BLENDFACTOR_INV_SRC_COLOR
);
218 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC_ALPHA
== BLENDFACTOR_INV_SRC_ALPHA
);
219 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_ALPHA
== BLENDFACTOR_INV_DST_ALPHA
);
220 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_DST_COLOR
== BLENDFACTOR_INV_DST_COLOR
);
221 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_COLOR
== BLENDFACTOR_INV_CONST_COLOR
);
222 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_CONST_ALPHA
== BLENDFACTOR_INV_CONST_ALPHA
);
223 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_COLOR
== BLENDFACTOR_INV_SRC1_COLOR
);
224 PIPE_ASSERT(PIPE_BLENDFACTOR_INV_SRC1_ALPHA
== BLENDFACTOR_INV_SRC1_ALPHA
);
226 /* pipe_blend_func happens to match the hardware. */
227 PIPE_ASSERT(PIPE_BLEND_ADD
== BLENDFUNCTION_ADD
);
228 PIPE_ASSERT(PIPE_BLEND_SUBTRACT
== BLENDFUNCTION_SUBTRACT
);
229 PIPE_ASSERT(PIPE_BLEND_REVERSE_SUBTRACT
== BLENDFUNCTION_REVERSE_SUBTRACT
);
230 PIPE_ASSERT(PIPE_BLEND_MIN
== BLENDFUNCTION_MIN
);
231 PIPE_ASSERT(PIPE_BLEND_MAX
== BLENDFUNCTION_MAX
);
233 /* pipe_stencil_op happens to match the hardware. */
234 PIPE_ASSERT(PIPE_STENCIL_OP_KEEP
== STENCILOP_KEEP
);
235 PIPE_ASSERT(PIPE_STENCIL_OP_ZERO
== STENCILOP_ZERO
);
236 PIPE_ASSERT(PIPE_STENCIL_OP_REPLACE
== STENCILOP_REPLACE
);
237 PIPE_ASSERT(PIPE_STENCIL_OP_INCR
== STENCILOP_INCRSAT
);
238 PIPE_ASSERT(PIPE_STENCIL_OP_DECR
== STENCILOP_DECRSAT
);
239 PIPE_ASSERT(PIPE_STENCIL_OP_INCR_WRAP
== STENCILOP_INCR
);
240 PIPE_ASSERT(PIPE_STENCIL_OP_DECR_WRAP
== STENCILOP_DECR
);
241 PIPE_ASSERT(PIPE_STENCIL_OP_INVERT
== STENCILOP_INVERT
);
243 /* pipe_sprite_coord_mode happens to match 3DSTATE_SBE */
244 PIPE_ASSERT(PIPE_SPRITE_COORD_UPPER_LEFT
== UPPERLEFT
);
245 PIPE_ASSERT(PIPE_SPRITE_COORD_LOWER_LEFT
== LOWERLEFT
);
250 translate_prim_type(enum pipe_prim_type prim
, uint8_t verts_per_patch
)
252 static const unsigned map
[] = {
253 [PIPE_PRIM_POINTS
] = _3DPRIM_POINTLIST
,
254 [PIPE_PRIM_LINES
] = _3DPRIM_LINELIST
,
255 [PIPE_PRIM_LINE_LOOP
] = _3DPRIM_LINELOOP
,
256 [PIPE_PRIM_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
257 [PIPE_PRIM_TRIANGLES
] = _3DPRIM_TRILIST
,
258 [PIPE_PRIM_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
259 [PIPE_PRIM_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
260 [PIPE_PRIM_QUADS
] = _3DPRIM_QUADLIST
,
261 [PIPE_PRIM_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
262 [PIPE_PRIM_POLYGON
] = _3DPRIM_POLYGON
,
263 [PIPE_PRIM_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
264 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
265 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
266 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
267 [PIPE_PRIM_PATCHES
] = _3DPRIM_PATCHLIST_1
- 1,
270 return map
[prim
] + (prim
== PIPE_PRIM_PATCHES
? verts_per_patch
: 0);
274 translate_compare_func(enum pipe_compare_func pipe_func
)
276 static const unsigned map
[] = {
277 [PIPE_FUNC_NEVER
] = COMPAREFUNCTION_NEVER
,
278 [PIPE_FUNC_LESS
] = COMPAREFUNCTION_LESS
,
279 [PIPE_FUNC_EQUAL
] = COMPAREFUNCTION_EQUAL
,
280 [PIPE_FUNC_LEQUAL
] = COMPAREFUNCTION_LEQUAL
,
281 [PIPE_FUNC_GREATER
] = COMPAREFUNCTION_GREATER
,
282 [PIPE_FUNC_NOTEQUAL
] = COMPAREFUNCTION_NOTEQUAL
,
283 [PIPE_FUNC_GEQUAL
] = COMPAREFUNCTION_GEQUAL
,
284 [PIPE_FUNC_ALWAYS
] = COMPAREFUNCTION_ALWAYS
,
286 return map
[pipe_func
];
290 translate_shadow_func(enum pipe_compare_func pipe_func
)
292 /* Gallium specifies the result of shadow comparisons as:
294 * 1 if ref <op> texel,
299 * 0 if texel <op> ref,
302 * So we need to flip the operator and also negate.
304 static const unsigned map
[] = {
305 [PIPE_FUNC_NEVER
] = PREFILTEROPALWAYS
,
306 [PIPE_FUNC_LESS
] = PREFILTEROPLEQUAL
,
307 [PIPE_FUNC_EQUAL
] = PREFILTEROPNOTEQUAL
,
308 [PIPE_FUNC_LEQUAL
] = PREFILTEROPLESS
,
309 [PIPE_FUNC_GREATER
] = PREFILTEROPGEQUAL
,
310 [PIPE_FUNC_NOTEQUAL
] = PREFILTEROPEQUAL
,
311 [PIPE_FUNC_GEQUAL
] = PREFILTEROPGREATER
,
312 [PIPE_FUNC_ALWAYS
] = PREFILTEROPNEVER
,
314 return map
[pipe_func
];
318 translate_cull_mode(unsigned pipe_face
)
320 static const unsigned map
[4] = {
321 [PIPE_FACE_NONE
] = CULLMODE_NONE
,
322 [PIPE_FACE_FRONT
] = CULLMODE_FRONT
,
323 [PIPE_FACE_BACK
] = CULLMODE_BACK
,
324 [PIPE_FACE_FRONT_AND_BACK
] = CULLMODE_BOTH
,
326 return map
[pipe_face
];
330 translate_fill_mode(unsigned pipe_polymode
)
332 static const unsigned map
[4] = {
333 [PIPE_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
334 [PIPE_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
335 [PIPE_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
336 [PIPE_POLYGON_MODE_FILL_RECTANGLE
] = FILL_MODE_SOLID
,
338 return map
[pipe_polymode
];
342 translate_mip_filter(enum pipe_tex_mipfilter pipe_mip
)
344 static const unsigned map
[] = {
345 [PIPE_TEX_MIPFILTER_NEAREST
] = MIPFILTER_NEAREST
,
346 [PIPE_TEX_MIPFILTER_LINEAR
] = MIPFILTER_LINEAR
,
347 [PIPE_TEX_MIPFILTER_NONE
] = MIPFILTER_NONE
,
349 return map
[pipe_mip
];
353 translate_wrap(unsigned pipe_wrap
)
355 static const unsigned map
[] = {
356 [PIPE_TEX_WRAP_REPEAT
] = TCM_WRAP
,
357 [PIPE_TEX_WRAP_CLAMP
] = TCM_HALF_BORDER
,
358 [PIPE_TEX_WRAP_CLAMP_TO_EDGE
] = TCM_CLAMP
,
359 [PIPE_TEX_WRAP_CLAMP_TO_BORDER
] = TCM_CLAMP_BORDER
,
360 [PIPE_TEX_WRAP_MIRROR_REPEAT
] = TCM_MIRROR
,
361 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
] = TCM_MIRROR_ONCE
,
363 /* These are unsupported. */
364 [PIPE_TEX_WRAP_MIRROR_CLAMP
] = -1,
365 [PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
] = -1,
367 return map
[pipe_wrap
];
370 static struct iris_address
371 ro_bo(struct iris_bo
*bo
, uint64_t offset
)
373 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
374 * validation list at CSO creation time, instead of draw time.
376 return (struct iris_address
) { .bo
= bo
, .offset
= offset
};
379 static struct iris_address
380 rw_bo(struct iris_bo
*bo
, uint64_t offset
)
382 /* CSOs must pass NULL for bo! Otherwise it will add the BO to the
383 * validation list at CSO creation time, instead of draw time.
385 return (struct iris_address
) { .bo
= bo
, .offset
= offset
, .write
= true };
389 * Allocate space for some indirect state.
391 * Return a pointer to the map (to fill it out) and a state ref (for
392 * referring to the state in GPU commands).
395 upload_state(struct u_upload_mgr
*uploader
,
396 struct iris_state_ref
*ref
,
401 u_upload_alloc(uploader
, 0, size
, alignment
, &ref
->offset
, &ref
->res
, &p
);
406 * Stream out temporary/short-lived state.
408 * This allocates space, pins the BO, and includes the BO address in the
409 * returned offset (which works because all state lives in 32-bit memory
413 stream_state(struct iris_batch
*batch
,
414 struct u_upload_mgr
*uploader
,
415 struct pipe_resource
**out_res
,
418 uint32_t *out_offset
)
422 u_upload_alloc(uploader
, 0, size
, alignment
, out_offset
, out_res
, &ptr
);
424 struct iris_bo
*bo
= iris_resource_bo(*out_res
);
425 iris_use_pinned_bo(batch
, bo
, false);
427 *out_offset
+= iris_bo_offset_from_base_address(bo
);
433 * stream_state() + memcpy.
436 emit_state(struct iris_batch
*batch
,
437 struct u_upload_mgr
*uploader
,
438 struct pipe_resource
**out_res
,
445 stream_state(batch
, uploader
, out_res
, size
, alignment
, &offset
);
448 memcpy(map
, data
, size
);
454 * Did field 'x' change between 'old_cso' and 'new_cso'?
456 * (If so, we may want to set some dirty flags.)
458 #define cso_changed(x) (!old_cso || (old_cso->x != new_cso->x))
459 #define cso_changed_memcmp(x) \
460 (!old_cso || memcmp(old_cso->x, new_cso->x, sizeof(old_cso->x)) != 0)
463 flush_for_state_base_change(struct iris_batch
*batch
)
465 /* Flush before emitting STATE_BASE_ADDRESS.
467 * This isn't documented anywhere in the PRM. However, it seems to be
468 * necessary prior to changing the surface state base adress. We've
469 * seen issues in Vulkan where we get GPU hangs when using multi-level
470 * command buffers which clear depth, reset state base address, and then
473 * Normally, in GL, we would trust the kernel to do sufficient stalls
474 * and flushes prior to executing our batch. However, it doesn't seem
475 * as if the kernel's flushing is always sufficient and we don't want to
478 * We make this an end-of-pipe sync instead of a normal flush because we
479 * do not know the current status of the GPU. On Haswell at least,
480 * having a fast-clear operation in flight at the same time as a normal
481 * rendering operation can cause hangs. Since the kernel's flushing is
482 * insufficient, we need to ensure that any rendering operations from
483 * other processes are definitely complete before we try to do our own
484 * rendering. It's a bit of a big hammer but it appears to work.
486 iris_emit_end_of_pipe_sync(batch
,
487 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
488 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
489 PIPE_CONTROL_DATA_CACHE_FLUSH
);
493 _iris_emit_lri(struct iris_batch
*batch
, uint32_t reg
, uint32_t val
)
495 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
496 lri
.RegisterOffset
= reg
;
500 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
503 _iris_emit_lrr(struct iris_batch
*batch
, uint32_t dst
, uint32_t src
)
505 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
506 lrr
.SourceRegisterAddress
= src
;
507 lrr
.DestinationRegisterAddress
= dst
;
512 emit_pipeline_select(struct iris_batch
*batch
, uint32_t pipeline
)
514 #if GEN_GEN >= 8 && GEN_GEN < 10
515 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
517 * Software must clear the COLOR_CALC_STATE Valid field in
518 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
519 * with Pipeline Select set to GPGPU.
521 * The internal hardware docs recommend the same workaround for Gen9
524 if (pipeline
== GPGPU
)
525 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
529 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
530 * PIPELINE_SELECT [DevBWR+]":
534 * Software must ensure all the write caches are flushed through a
535 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
536 * command to invalidate read only caches prior to programming
537 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode."
539 iris_emit_pipe_control_flush(batch
,
540 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
541 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
542 PIPE_CONTROL_DATA_CACHE_FLUSH
|
543 PIPE_CONTROL_CS_STALL
);
545 iris_emit_pipe_control_flush(batch
,
546 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
547 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
548 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
549 PIPE_CONTROL_INSTRUCTION_INVALIDATE
);
551 iris_emit_cmd(batch
, GENX(PIPELINE_SELECT
), sel
) {
555 sel
.PipelineSelection
= pipeline
;
560 init_glk_barrier_mode(struct iris_batch
*batch
, uint32_t value
)
565 * "This chicken bit works around a hardware issue with barrier
566 * logic encountered when switching between GPGPU and 3D pipelines.
567 * To workaround the issue, this mode bit should be set after a
568 * pipeline is selected."
571 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
572 reg
.GLKBarrierMode
= value
;
573 reg
.GLKBarrierModeMask
= 1;
575 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
580 init_state_base_address(struct iris_batch
*batch
)
582 flush_for_state_base_change(batch
);
584 /* We program most base addresses once at context initialization time.
585 * Each base address points at a 4GB memory zone, and never needs to
586 * change. See iris_bufmgr.h for a description of the memory zones.
588 * The one exception is Surface State Base Address, which needs to be
589 * updated occasionally. See iris_binder.c for the details there.
591 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
592 sba
.GeneralStateMOCS
= MOCS_WB
;
593 sba
.StatelessDataPortAccessMOCS
= MOCS_WB
;
594 sba
.DynamicStateMOCS
= MOCS_WB
;
595 sba
.IndirectObjectMOCS
= MOCS_WB
;
596 sba
.InstructionMOCS
= MOCS_WB
;
598 sba
.GeneralStateBaseAddressModifyEnable
= true;
599 sba
.DynamicStateBaseAddressModifyEnable
= true;
600 sba
.IndirectObjectBaseAddressModifyEnable
= true;
601 sba
.InstructionBaseAddressModifyEnable
= true;
602 sba
.GeneralStateBufferSizeModifyEnable
= true;
603 sba
.DynamicStateBufferSizeModifyEnable
= true;
605 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
606 sba
.BindlessSurfaceStateMOCS
= MOCS_WB
;
608 sba
.IndirectObjectBufferSizeModifyEnable
= true;
609 sba
.InstructionBuffersizeModifyEnable
= true;
611 sba
.InstructionBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_SHADER_START
);
612 sba
.DynamicStateBaseAddress
= ro_bo(NULL
, IRIS_MEMZONE_DYNAMIC_START
);
614 sba
.GeneralStateBufferSize
= 0xfffff;
615 sba
.IndirectObjectBufferSize
= 0xfffff;
616 sba
.InstructionBufferSize
= 0xfffff;
617 sba
.DynamicStateBufferSize
= 0xfffff;
622 iris_emit_l3_config(struct iris_batch
*batch
, const struct gen_l3_config
*cfg
,
623 bool has_slm
, bool wants_dc_cache
)
626 iris_pack_state(GENX(L3CNTLREG
), ®_val
, reg
) {
627 reg
.SLMEnable
= has_slm
;
629 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
630 * in L3CNTLREG register. The default setting of the bit is not the
631 * desirable behavior.
633 reg
.ErrorDetectionBehaviorControl
= true;
635 reg
.URBAllocation
= cfg
->n
[GEN_L3P_URB
];
636 reg
.ROAllocation
= cfg
->n
[GEN_L3P_RO
];
637 reg
.DCAllocation
= cfg
->n
[GEN_L3P_DC
];
638 reg
.AllAllocation
= cfg
->n
[GEN_L3P_ALL
];
640 iris_emit_lri(batch
, L3CNTLREG
, reg_val
);
644 iris_emit_default_l3_config(struct iris_batch
*batch
,
645 const struct gen_device_info
*devinfo
,
648 bool wants_dc_cache
= true;
649 bool has_slm
= compute
;
650 const struct gen_l3_weights w
=
651 gen_get_default_l3_weights(devinfo
, wants_dc_cache
, has_slm
);
652 const struct gen_l3_config
*cfg
= gen_get_l3_config(devinfo
, w
);
653 iris_emit_l3_config(batch
, cfg
, has_slm
, wants_dc_cache
);
658 iris_enable_obj_preemption(struct iris_batch
*batch
, bool enable
)
662 /* A fixed function pipe flush is required before modifying this field */
663 iris_emit_end_of_pipe_sync(batch
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
665 /* enable object level preemption */
666 iris_pack_state(GENX(CS_CHICKEN1
), ®_val
, reg
) {
667 reg
.ReplayMode
= enable
;
668 reg
.ReplayModeMask
= true;
670 iris_emit_lri(batch
, CS_CHICKEN1
, reg_val
);
675 * Upload the initial GPU state for a render context.
677 * This sets some invariant state that needs to be programmed a particular
678 * way, but we never actually change.
681 iris_init_render_context(struct iris_screen
*screen
,
682 struct iris_batch
*batch
,
683 struct iris_vtable
*vtbl
,
684 struct pipe_debug_callback
*dbg
)
686 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
689 emit_pipeline_select(batch
, _3D
);
691 iris_emit_default_l3_config(batch
, devinfo
, false);
693 init_state_base_address(batch
);
696 iris_pack_state(GENX(CS_DEBUG_MODE2
), ®_val
, reg
) {
697 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
698 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
700 iris_emit_lri(batch
, CS_DEBUG_MODE2
, reg_val
);
702 iris_pack_state(GENX(INSTPM
), ®_val
, reg
) {
703 reg
.CONSTANT_BUFFERAddressOffsetDisable
= true;
704 reg
.CONSTANT_BUFFERAddressOffsetDisableMask
= true;
706 iris_emit_lri(batch
, INSTPM
, reg_val
);
710 iris_pack_state(GENX(CACHE_MODE_1
), ®_val
, reg
) {
711 reg
.FloatBlendOptimizationEnable
= true;
712 reg
.FloatBlendOptimizationEnableMask
= true;
713 reg
.PartialResolveDisableInVC
= true;
714 reg
.PartialResolveDisableInVCMask
= true;
716 iris_emit_lri(batch
, CACHE_MODE_1
, reg_val
);
718 if (devinfo
->is_geminilake
)
719 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_3D_HULL
);
723 iris_pack_state(GENX(SAMPLER_MODE
), ®_val
, reg
) {
724 reg
.HeaderlessMessageforPreemptableContexts
= 1;
725 reg
.HeaderlessMessageforPreemptableContextsMask
= 1;
727 iris_emit_lri(batch
, SAMPLER_MODE
, reg_val
);
729 /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
730 iris_pack_state(GENX(HALF_SLICE_CHICKEN7
), ®_val
, reg
) {
731 reg
.EnabledTexelOffsetPrecisionFix
= 1;
732 reg
.EnabledTexelOffsetPrecisionFixMask
= 1;
734 iris_emit_lri(batch
, HALF_SLICE_CHICKEN7
, reg_val
);
736 /* WA_2204188704: Pixel Shader Panic dispatch must be disabled. */
737 iris_pack_state(GENX(COMMON_SLICE_CHICKEN3
), ®_val
, reg
) {
738 reg
.PSThreadPanicDispatch
= 0x3;
739 reg
.PSThreadPanicDispatchMask
= 0x3;
741 iris_emit_lri(batch
, COMMON_SLICE_CHICKEN3
, reg_val
);
743 iris_pack_state(GENX(SLICE_COMMON_ECO_CHICKEN1
), ®_val
, reg
) {
744 reg
.StateCacheRedirectToCSSectionEnable
= true;
745 reg
.StateCacheRedirectToCSSectionEnableMask
= true;
747 iris_emit_lri(batch
, SLICE_COMMON_ECO_CHICKEN1
, reg_val
);
753 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
754 * changing it dynamically. We set it to the maximum size here, and
755 * instead include the render target dimensions in the viewport, so
756 * viewport extents clipping takes care of pruning stray geometry.
758 iris_emit_cmd(batch
, GENX(3DSTATE_DRAWING_RECTANGLE
), rect
) {
759 rect
.ClippedDrawingRectangleXMax
= UINT16_MAX
;
760 rect
.ClippedDrawingRectangleYMax
= UINT16_MAX
;
763 /* Set the initial MSAA sample positions. */
764 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_PATTERN
), pat
) {
765 GEN_SAMPLE_POS_1X(pat
._1xSample
);
766 GEN_SAMPLE_POS_2X(pat
._2xSample
);
767 GEN_SAMPLE_POS_4X(pat
._4xSample
);
768 GEN_SAMPLE_POS_8X(pat
._8xSample
);
770 GEN_SAMPLE_POS_16X(pat
._16xSample
);
774 /* Use the legacy AA line coverage computation. */
775 iris_emit_cmd(batch
, GENX(3DSTATE_AA_LINE_PARAMETERS
), foo
);
777 /* Disable chromakeying (it's for media) */
778 iris_emit_cmd(batch
, GENX(3DSTATE_WM_CHROMAKEY
), foo
);
780 /* We want regular rendering, not special HiZ operations. */
781 iris_emit_cmd(batch
, GENX(3DSTATE_WM_HZ_OP
), foo
);
783 /* No polygon stippling offsets are necessary. */
784 /* TODO: may need to set an offset for origin-UL framebuffers */
785 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_OFFSET
), foo
);
787 /* Set a static partitioning of the push constant area. */
788 /* TODO: this may be a bad idea...could starve the push ringbuffers... */
789 for (int i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
790 iris_emit_cmd(batch
, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
791 alloc
._3DCommandSubOpcode
= 18 + i
;
792 alloc
.ConstantBufferOffset
= 6 * i
;
793 alloc
.ConstantBufferSize
= i
== MESA_SHADER_FRAGMENT
? 8 : 6;
798 /* Gen11+ is enabled for us by the kernel. */
799 iris_enable_obj_preemption(batch
, true);
804 iris_init_compute_context(struct iris_screen
*screen
,
805 struct iris_batch
*batch
,
806 struct iris_vtable
*vtbl
,
807 struct pipe_debug_callback
*dbg
)
809 UNUSED
const struct gen_device_info
*devinfo
= &screen
->devinfo
;
811 emit_pipeline_select(batch
, GPGPU
);
813 iris_emit_default_l3_config(batch
, devinfo
, true);
815 init_state_base_address(batch
);
818 if (devinfo
->is_geminilake
)
819 init_glk_barrier_mode(batch
, GLK_BARRIER_MODE_GPGPU
);
823 struct iris_vertex_buffer_state
{
824 /** The VERTEX_BUFFER_STATE hardware structure. */
825 uint32_t state
[GENX(VERTEX_BUFFER_STATE_length
)];
827 /** The resource to source vertex data from. */
828 struct pipe_resource
*resource
;
831 struct iris_depth_buffer_state
{
832 /* Depth/HiZ/Stencil related hardware packets. */
833 uint32_t packets
[GENX(3DSTATE_DEPTH_BUFFER_length
) +
834 GENX(3DSTATE_STENCIL_BUFFER_length
) +
835 GENX(3DSTATE_HIER_DEPTH_BUFFER_length
) +
836 GENX(3DSTATE_CLEAR_PARAMS_length
)];
840 * Generation-specific context state (ice->state.genx->...).
842 * Most state can go in iris_context directly, but these encode hardware
843 * packets which vary by generation.
845 struct iris_genx_state
{
846 struct iris_vertex_buffer_state vertex_buffers
[33];
848 struct iris_depth_buffer_state depth_buffer
;
850 uint32_t so_buffers
[4 * GENX(3DSTATE_SO_BUFFER_length
)];
853 /* Is object level preemption enabled? */
854 bool object_preemption
;
859 struct brw_image_param image_param
[PIPE_MAX_SHADER_IMAGES
];
861 } shaders
[MESA_SHADER_STAGES
];
865 * The pipe->set_blend_color() driver hook.
867 * This corresponds to our COLOR_CALC_STATE.
870 iris_set_blend_color(struct pipe_context
*ctx
,
871 const struct pipe_blend_color
*state
)
873 struct iris_context
*ice
= (struct iris_context
*) ctx
;
875 /* Our COLOR_CALC_STATE is exactly pipe_blend_color, so just memcpy */
876 memcpy(&ice
->state
.blend_color
, state
, sizeof(struct pipe_blend_color
));
877 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
881 * Gallium CSO for blend state (see pipe_blend_state).
883 struct iris_blend_state
{
884 /** Partial 3DSTATE_PS_BLEND */
885 uint32_t ps_blend
[GENX(3DSTATE_PS_BLEND_length
)];
887 /** Partial BLEND_STATE */
888 uint32_t blend_state
[GENX(BLEND_STATE_length
) +
889 BRW_MAX_DRAW_BUFFERS
* GENX(BLEND_STATE_ENTRY_length
)];
891 bool alpha_to_coverage
; /* for shader key */
893 /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
894 uint8_t blend_enables
;
896 /** Bitfield of whether color writes are enabled for RT[i] */
897 uint8_t color_write_enables
;
899 /** Does RT[0] use dual color blending? */
900 bool dual_color_blending
;
903 static enum pipe_blendfactor
904 fix_blendfactor(enum pipe_blendfactor f
, bool alpha_to_one
)
907 if (f
== PIPE_BLENDFACTOR_SRC1_ALPHA
)
908 return PIPE_BLENDFACTOR_ONE
;
910 if (f
== PIPE_BLENDFACTOR_INV_SRC1_ALPHA
)
911 return PIPE_BLENDFACTOR_ZERO
;
918 * The pipe->create_blend_state() driver hook.
920 * Translates a pipe_blend_state into iris_blend_state.
923 iris_create_blend_state(struct pipe_context
*ctx
,
924 const struct pipe_blend_state
*state
)
926 struct iris_blend_state
*cso
= malloc(sizeof(struct iris_blend_state
));
927 uint32_t *blend_entry
= cso
->blend_state
+ GENX(BLEND_STATE_length
);
929 cso
->blend_enables
= 0;
930 cso
->color_write_enables
= 0;
931 STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS
<= 8);
933 cso
->alpha_to_coverage
= state
->alpha_to_coverage
;
935 bool indep_alpha_blend
= false;
937 for (int i
= 0; i
< BRW_MAX_DRAW_BUFFERS
; i
++) {
938 const struct pipe_rt_blend_state
*rt
=
939 &state
->rt
[state
->independent_blend_enable
? i
: 0];
941 enum pipe_blendfactor src_rgb
=
942 fix_blendfactor(rt
->rgb_src_factor
, state
->alpha_to_one
);
943 enum pipe_blendfactor src_alpha
=
944 fix_blendfactor(rt
->alpha_src_factor
, state
->alpha_to_one
);
945 enum pipe_blendfactor dst_rgb
=
946 fix_blendfactor(rt
->rgb_dst_factor
, state
->alpha_to_one
);
947 enum pipe_blendfactor dst_alpha
=
948 fix_blendfactor(rt
->alpha_dst_factor
, state
->alpha_to_one
);
950 if (rt
->rgb_func
!= rt
->alpha_func
||
951 src_rgb
!= src_alpha
|| dst_rgb
!= dst_alpha
)
952 indep_alpha_blend
= true;
954 if (rt
->blend_enable
)
955 cso
->blend_enables
|= 1u << i
;
958 cso
->color_write_enables
|= 1u << i
;
960 iris_pack_state(GENX(BLEND_STATE_ENTRY
), blend_entry
, be
) {
961 be
.LogicOpEnable
= state
->logicop_enable
;
962 be
.LogicOpFunction
= state
->logicop_func
;
964 be
.PreBlendSourceOnlyClampEnable
= false;
965 be
.ColorClampRange
= COLORCLAMP_RTFORMAT
;
966 be
.PreBlendColorClampEnable
= true;
967 be
.PostBlendColorClampEnable
= true;
969 be
.ColorBufferBlendEnable
= rt
->blend_enable
;
971 be
.ColorBlendFunction
= rt
->rgb_func
;
972 be
.AlphaBlendFunction
= rt
->alpha_func
;
973 be
.SourceBlendFactor
= src_rgb
;
974 be
.SourceAlphaBlendFactor
= src_alpha
;
975 be
.DestinationBlendFactor
= dst_rgb
;
976 be
.DestinationAlphaBlendFactor
= dst_alpha
;
978 be
.WriteDisableRed
= !(rt
->colormask
& PIPE_MASK_R
);
979 be
.WriteDisableGreen
= !(rt
->colormask
& PIPE_MASK_G
);
980 be
.WriteDisableBlue
= !(rt
->colormask
& PIPE_MASK_B
);
981 be
.WriteDisableAlpha
= !(rt
->colormask
& PIPE_MASK_A
);
983 blend_entry
+= GENX(BLEND_STATE_ENTRY_length
);
986 iris_pack_command(GENX(3DSTATE_PS_BLEND
), cso
->ps_blend
, pb
) {
987 /* pb.HasWriteableRT is filled in at draw time. */
988 /* pb.AlphaTestEnable is filled in at draw time. */
989 pb
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
990 pb
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
992 pb
.ColorBufferBlendEnable
= state
->rt
[0].blend_enable
;
994 pb
.SourceBlendFactor
=
995 fix_blendfactor(state
->rt
[0].rgb_src_factor
, state
->alpha_to_one
);
996 pb
.SourceAlphaBlendFactor
=
997 fix_blendfactor(state
->rt
[0].alpha_src_factor
, state
->alpha_to_one
);
998 pb
.DestinationBlendFactor
=
999 fix_blendfactor(state
->rt
[0].rgb_dst_factor
, state
->alpha_to_one
);
1000 pb
.DestinationAlphaBlendFactor
=
1001 fix_blendfactor(state
->rt
[0].alpha_dst_factor
, state
->alpha_to_one
);
1004 iris_pack_state(GENX(BLEND_STATE
), cso
->blend_state
, bs
) {
1005 bs
.AlphaToCoverageEnable
= state
->alpha_to_coverage
;
1006 bs
.IndependentAlphaBlendEnable
= indep_alpha_blend
;
1007 bs
.AlphaToOneEnable
= state
->alpha_to_one
;
1008 bs
.AlphaToCoverageDitherEnable
= state
->alpha_to_coverage
;
1009 bs
.ColorDitherEnable
= state
->dither
;
1010 /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
1013 cso
->dual_color_blending
= util_blend_state_is_dual(state
, 0);
1019 * The pipe->bind_blend_state() driver hook.
1021 * Bind a blending CSO and flag related dirty bits.
1024 iris_bind_blend_state(struct pipe_context
*ctx
, void *state
)
1026 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1027 struct iris_blend_state
*cso
= state
;
1029 ice
->state
.cso_blend
= cso
;
1030 ice
->state
.blend_enables
= cso
? cso
->blend_enables
: 0;
1032 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
;
1033 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1034 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1035 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_BLEND
];
1039 * Return true if the FS writes to any color outputs which are not disabled
1040 * via color masking.
1043 has_writeable_rt(const struct iris_blend_state
*cso_blend
,
1044 const struct shader_info
*fs_info
)
1049 unsigned rt_outputs
= fs_info
->outputs_written
>> FRAG_RESULT_DATA0
;
1051 if (fs_info
->outputs_written
& BITFIELD64_BIT(FRAG_RESULT_COLOR
))
1052 rt_outputs
= (1 << BRW_MAX_DRAW_BUFFERS
) - 1;
1054 return cso_blend
->color_write_enables
& rt_outputs
;
1058 * Gallium CSO for depth, stencil, and alpha testing state.
1060 struct iris_depth_stencil_alpha_state
{
1061 /** Partial 3DSTATE_WM_DEPTH_STENCIL. */
1062 uint32_t wmds
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
1064 /** Outbound to BLEND_STATE, 3DSTATE_PS_BLEND, COLOR_CALC_STATE. */
1065 struct pipe_alpha_state alpha
;
1067 /** Outbound to resolve and cache set tracking. */
1068 bool depth_writes_enabled
;
1069 bool stencil_writes_enabled
;
1073 * The pipe->create_depth_stencil_alpha_state() driver hook.
1075 * We encode most of 3DSTATE_WM_DEPTH_STENCIL, and just save off the alpha
1076 * testing state since we need pieces of it in a variety of places.
1079 iris_create_zsa_state(struct pipe_context
*ctx
,
1080 const struct pipe_depth_stencil_alpha_state
*state
)
1082 struct iris_depth_stencil_alpha_state
*cso
=
1083 malloc(sizeof(struct iris_depth_stencil_alpha_state
));
1085 bool two_sided_stencil
= state
->stencil
[1].enabled
;
1087 cso
->alpha
= state
->alpha
;
1088 cso
->depth_writes_enabled
= state
->depth
.writemask
;
1089 cso
->stencil_writes_enabled
=
1090 state
->stencil
[0].writemask
!= 0 ||
1091 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1093 /* The state tracker needs to optimize away EQUAL writes for us. */
1094 assert(!(state
->depth
.func
== PIPE_FUNC_EQUAL
&& state
->depth
.writemask
));
1096 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), cso
->wmds
, wmds
) {
1097 wmds
.StencilFailOp
= state
->stencil
[0].fail_op
;
1098 wmds
.StencilPassDepthFailOp
= state
->stencil
[0].zfail_op
;
1099 wmds
.StencilPassDepthPassOp
= state
->stencil
[0].zpass_op
;
1100 wmds
.StencilTestFunction
=
1101 translate_compare_func(state
->stencil
[0].func
);
1102 wmds
.BackfaceStencilFailOp
= state
->stencil
[1].fail_op
;
1103 wmds
.BackfaceStencilPassDepthFailOp
= state
->stencil
[1].zfail_op
;
1104 wmds
.BackfaceStencilPassDepthPassOp
= state
->stencil
[1].zpass_op
;
1105 wmds
.BackfaceStencilTestFunction
=
1106 translate_compare_func(state
->stencil
[1].func
);
1107 wmds
.DepthTestFunction
= translate_compare_func(state
->depth
.func
);
1108 wmds
.DoubleSidedStencilEnable
= two_sided_stencil
;
1109 wmds
.StencilTestEnable
= state
->stencil
[0].enabled
;
1110 wmds
.StencilBufferWriteEnable
=
1111 state
->stencil
[0].writemask
!= 0 ||
1112 (two_sided_stencil
&& state
->stencil
[1].writemask
!= 0);
1113 wmds
.DepthTestEnable
= state
->depth
.enabled
;
1114 wmds
.DepthBufferWriteEnable
= state
->depth
.writemask
;
1115 wmds
.StencilTestMask
= state
->stencil
[0].valuemask
;
1116 wmds
.StencilWriteMask
= state
->stencil
[0].writemask
;
1117 wmds
.BackfaceStencilTestMask
= state
->stencil
[1].valuemask
;
1118 wmds
.BackfaceStencilWriteMask
= state
->stencil
[1].writemask
;
1119 /* wmds.[Backface]StencilReferenceValue are merged later */
1126 * The pipe->bind_depth_stencil_alpha_state() driver hook.
1128 * Bind a depth/stencil/alpha CSO and flag related dirty bits.
1131 iris_bind_zsa_state(struct pipe_context
*ctx
, void *state
)
1133 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1134 struct iris_depth_stencil_alpha_state
*old_cso
= ice
->state
.cso_zsa
;
1135 struct iris_depth_stencil_alpha_state
*new_cso
= state
;
1138 if (cso_changed(alpha
.ref_value
))
1139 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
1141 if (cso_changed(alpha
.enabled
))
1142 ice
->state
.dirty
|= IRIS_DIRTY_PS_BLEND
| IRIS_DIRTY_BLEND_STATE
;
1144 if (cso_changed(alpha
.func
))
1145 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
1147 if (cso_changed(depth_writes_enabled
))
1148 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
1150 ice
->state
.depth_writes_enabled
= new_cso
->depth_writes_enabled
;
1151 ice
->state
.stencil_writes_enabled
= new_cso
->stencil_writes_enabled
;
1154 ice
->state
.cso_zsa
= new_cso
;
1155 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1156 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
1157 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_DEPTH_STENCIL_ALPHA
];
1161 * Gallium CSO for rasterizer state.
1163 struct iris_rasterizer_state
{
1164 uint32_t sf
[GENX(3DSTATE_SF_length
)];
1165 uint32_t clip
[GENX(3DSTATE_CLIP_length
)];
1166 uint32_t raster
[GENX(3DSTATE_RASTER_length
)];
1167 uint32_t wm
[GENX(3DSTATE_WM_length
)];
1168 uint32_t line_stipple
[GENX(3DSTATE_LINE_STIPPLE_length
)];
1170 uint8_t num_clip_plane_consts
;
1171 bool clip_halfz
; /* for CC_VIEWPORT */
1172 bool depth_clip_near
; /* for CC_VIEWPORT */
1173 bool depth_clip_far
; /* for CC_VIEWPORT */
1174 bool flatshade
; /* for shader state */
1175 bool flatshade_first
; /* for stream output */
1176 bool clamp_fragment_color
; /* for shader state */
1177 bool light_twoside
; /* for shader state */
1178 bool rasterizer_discard
; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
1179 bool half_pixel_center
; /* for 3DSTATE_MULTISAMPLE */
1180 bool line_stipple_enable
;
1181 bool poly_stipple_enable
;
1183 bool force_persample_interp
;
1184 bool conservative_rasterization
;
1185 enum pipe_sprite_coord_mode sprite_coord_mode
; /* PIPE_SPRITE_* */
1186 uint16_t sprite_coord_enable
;
1190 get_line_width(const struct pipe_rasterizer_state
*state
)
1192 float line_width
= state
->line_width
;
1194 /* From the OpenGL 4.4 spec:
1196 * "The actual width of non-antialiased lines is determined by rounding
1197 * the supplied width to the nearest integer, then clamping it to the
1198 * implementation-dependent maximum non-antialiased line width."
1200 if (!state
->multisample
&& !state
->line_smooth
)
1201 line_width
= roundf(state
->line_width
);
1203 if (!state
->multisample
&& state
->line_smooth
&& line_width
< 1.5f
) {
1204 /* For 1 pixel line thickness or less, the general anti-aliasing
1205 * algorithm gives up, and a garbage line is generated. Setting a
1206 * Line Width of 0.0 specifies the rasterization of the "thinnest"
1207 * (one-pixel-wide), non-antialiased lines.
1209 * Lines rendered with zero Line Width are rasterized using the
1210 * "Grid Intersection Quantization" rules as specified by the
1211 * "Zero-Width (Cosmetic) Line Rasterization" section of the docs.
1220 * The pipe->create_rasterizer_state() driver hook.
1223 iris_create_rasterizer_state(struct pipe_context
*ctx
,
1224 const struct pipe_rasterizer_state
*state
)
1226 struct iris_rasterizer_state
*cso
=
1227 malloc(sizeof(struct iris_rasterizer_state
));
1229 cso
->multisample
= state
->multisample
;
1230 cso
->force_persample_interp
= state
->force_persample_interp
;
1231 cso
->clip_halfz
= state
->clip_halfz
;
1232 cso
->depth_clip_near
= state
->depth_clip_near
;
1233 cso
->depth_clip_far
= state
->depth_clip_far
;
1234 cso
->flatshade
= state
->flatshade
;
1235 cso
->flatshade_first
= state
->flatshade_first
;
1236 cso
->clamp_fragment_color
= state
->clamp_fragment_color
;
1237 cso
->light_twoside
= state
->light_twoside
;
1238 cso
->rasterizer_discard
= state
->rasterizer_discard
;
1239 cso
->half_pixel_center
= state
->half_pixel_center
;
1240 cso
->sprite_coord_mode
= state
->sprite_coord_mode
;
1241 cso
->sprite_coord_enable
= state
->sprite_coord_enable
;
1242 cso
->line_stipple_enable
= state
->line_stipple_enable
;
1243 cso
->poly_stipple_enable
= state
->poly_stipple_enable
;
1244 cso
->conservative_rasterization
=
1245 state
->conservative_raster_mode
== PIPE_CONSERVATIVE_RASTER_POST_SNAP
;
1247 if (state
->clip_plane_enable
!= 0)
1248 cso
->num_clip_plane_consts
= util_logbase2(state
->clip_plane_enable
) + 1;
1250 cso
->num_clip_plane_consts
= 0;
1252 float line_width
= get_line_width(state
);
1254 iris_pack_command(GENX(3DSTATE_SF
), cso
->sf
, sf
) {
1255 sf
.StatisticsEnable
= true;
1256 sf
.ViewportTransformEnable
= true;
1257 sf
.AALineDistanceMode
= AALINEDISTANCE_TRUE
;
1258 sf
.LineEndCapAntialiasingRegionWidth
=
1259 state
->line_smooth
? _10pixels
: _05pixels
;
1260 sf
.LastPixelEnable
= state
->line_last_pixel
;
1261 sf
.LineWidth
= line_width
;
1262 sf
.SmoothPointEnable
= (state
->point_smooth
|| state
->multisample
) &&
1263 !state
->point_quad_rasterization
;
1264 sf
.PointWidthSource
= state
->point_size_per_vertex
? Vertex
: State
;
1265 sf
.PointWidth
= state
->point_size
;
1267 if (state
->flatshade_first
) {
1268 sf
.TriangleFanProvokingVertexSelect
= 1;
1270 sf
.TriangleStripListProvokingVertexSelect
= 2;
1271 sf
.TriangleFanProvokingVertexSelect
= 2;
1272 sf
.LineStripListProvokingVertexSelect
= 1;
1276 iris_pack_command(GENX(3DSTATE_RASTER
), cso
->raster
, rr
) {
1277 rr
.FrontWinding
= state
->front_ccw
? CounterClockwise
: Clockwise
;
1278 rr
.CullMode
= translate_cull_mode(state
->cull_face
);
1279 rr
.FrontFaceFillMode
= translate_fill_mode(state
->fill_front
);
1280 rr
.BackFaceFillMode
= translate_fill_mode(state
->fill_back
);
1281 rr
.DXMultisampleRasterizationEnable
= state
->multisample
;
1282 rr
.GlobalDepthOffsetEnableSolid
= state
->offset_tri
;
1283 rr
.GlobalDepthOffsetEnableWireframe
= state
->offset_line
;
1284 rr
.GlobalDepthOffsetEnablePoint
= state
->offset_point
;
1285 rr
.GlobalDepthOffsetConstant
= state
->offset_units
* 2;
1286 rr
.GlobalDepthOffsetScale
= state
->offset_scale
;
1287 rr
.GlobalDepthOffsetClamp
= state
->offset_clamp
;
1288 rr
.SmoothPointEnable
= state
->point_smooth
;
1289 rr
.AntialiasingEnable
= state
->line_smooth
;
1290 rr
.ScissorRectangleEnable
= state
->scissor
;
1292 rr
.ViewportZNearClipTestEnable
= state
->depth_clip_near
;
1293 rr
.ViewportZFarClipTestEnable
= state
->depth_clip_far
;
1294 rr
.ConservativeRasterizationEnable
=
1295 cso
->conservative_rasterization
;
1297 rr
.ViewportZClipTestEnable
= (state
->depth_clip_near
|| state
->depth_clip_far
);
1301 iris_pack_command(GENX(3DSTATE_CLIP
), cso
->clip
, cl
) {
1302 /* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
1303 * the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
1305 cl
.EarlyCullEnable
= true;
1306 cl
.UserClipDistanceClipTestEnableBitmask
= state
->clip_plane_enable
;
1307 cl
.ForceUserClipDistanceClipTestEnableBitmask
= true;
1308 cl
.APIMode
= state
->clip_halfz
? APIMODE_D3D
: APIMODE_OGL
;
1309 cl
.GuardbandClipTestEnable
= true;
1310 cl
.ClipEnable
= true;
1311 cl
.ViewportXYClipTestEnable
= state
->point_tri_clip
;
1312 cl
.MinimumPointWidth
= 0.125;
1313 cl
.MaximumPointWidth
= 255.875;
1315 if (state
->flatshade_first
) {
1316 cl
.TriangleFanProvokingVertexSelect
= 1;
1318 cl
.TriangleStripListProvokingVertexSelect
= 2;
1319 cl
.TriangleFanProvokingVertexSelect
= 2;
1320 cl
.LineStripListProvokingVertexSelect
= 1;
1324 iris_pack_command(GENX(3DSTATE_WM
), cso
->wm
, wm
) {
1325 /* wm.BarycentricInterpolationMode and wm.EarlyDepthStencilControl are
1326 * filled in at draw time from the FS program.
1328 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1329 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1330 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1331 wm
.LineStippleEnable
= state
->line_stipple_enable
;
1332 wm
.PolygonStippleEnable
= state
->poly_stipple_enable
;
1335 /* Remap from 0..255 back to 1..256 */
1336 const unsigned line_stipple_factor
= state
->line_stipple_factor
+ 1;
1338 iris_pack_command(GENX(3DSTATE_LINE_STIPPLE
), cso
->line_stipple
, line
) {
1339 line
.LineStipplePattern
= state
->line_stipple_pattern
;
1340 line
.LineStippleInverseRepeatCount
= 1.0f
/ line_stipple_factor
;
1341 line
.LineStippleRepeatCount
= line_stipple_factor
;
1348 * The pipe->bind_rasterizer_state() driver hook.
1350 * Bind a rasterizer CSO and flag related dirty bits.
1353 iris_bind_rasterizer_state(struct pipe_context
*ctx
, void *state
)
1355 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1356 struct iris_rasterizer_state
*old_cso
= ice
->state
.cso_rast
;
1357 struct iris_rasterizer_state
*new_cso
= state
;
1360 /* Try to avoid re-emitting 3DSTATE_LINE_STIPPLE, it's non-pipelined */
1361 if (cso_changed_memcmp(line_stipple
))
1362 ice
->state
.dirty
|= IRIS_DIRTY_LINE_STIPPLE
;
1364 if (cso_changed(half_pixel_center
))
1365 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
1367 if (cso_changed(line_stipple_enable
) || cso_changed(poly_stipple_enable
))
1368 ice
->state
.dirty
|= IRIS_DIRTY_WM
;
1370 if (cso_changed(rasterizer_discard
))
1371 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
| IRIS_DIRTY_CLIP
;
1373 if (cso_changed(flatshade_first
))
1374 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
1376 if (cso_changed(depth_clip_near
) || cso_changed(depth_clip_far
) ||
1377 cso_changed(clip_halfz
))
1378 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
1380 if (cso_changed(sprite_coord_enable
) ||
1381 cso_changed(sprite_coord_mode
) ||
1382 cso_changed(light_twoside
))
1383 ice
->state
.dirty
|= IRIS_DIRTY_SBE
;
1385 if (cso_changed(conservative_rasterization
))
1386 ice
->state
.dirty
|= IRIS_DIRTY_FS
;
1389 ice
->state
.cso_rast
= new_cso
;
1390 ice
->state
.dirty
|= IRIS_DIRTY_RASTER
;
1391 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
1392 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_RASTERIZER
];
1396 * Return true if the given wrap mode requires the border color to exist.
1398 * (We can skip uploading it if the sampler isn't going to use it.)
1401 wrap_mode_needs_border_color(unsigned wrap_mode
)
1403 return wrap_mode
== TCM_CLAMP_BORDER
|| wrap_mode
== TCM_HALF_BORDER
;
1407 * Gallium CSO for sampler state.
1409 struct iris_sampler_state
{
1410 union pipe_color_union border_color
;
1411 bool needs_border_color
;
1413 uint32_t sampler_state
[GENX(SAMPLER_STATE_length
)];
1417 * The pipe->create_sampler_state() driver hook.
1419 * We fill out SAMPLER_STATE (except for the border color pointer), and
1420 * store that on the CPU. It doesn't make sense to upload it to a GPU
1421 * buffer object yet, because 3DSTATE_SAMPLER_STATE_POINTERS requires
1422 * all bound sampler states to be in contiguous memor.
1425 iris_create_sampler_state(struct pipe_context
*ctx
,
1426 const struct pipe_sampler_state
*state
)
1428 struct iris_sampler_state
*cso
= CALLOC_STRUCT(iris_sampler_state
);
1433 STATIC_ASSERT(PIPE_TEX_FILTER_NEAREST
== MAPFILTER_NEAREST
);
1434 STATIC_ASSERT(PIPE_TEX_FILTER_LINEAR
== MAPFILTER_LINEAR
);
1436 unsigned wrap_s
= translate_wrap(state
->wrap_s
);
1437 unsigned wrap_t
= translate_wrap(state
->wrap_t
);
1438 unsigned wrap_r
= translate_wrap(state
->wrap_r
);
1440 memcpy(&cso
->border_color
, &state
->border_color
, sizeof(cso
->border_color
));
1442 cso
->needs_border_color
= wrap_mode_needs_border_color(wrap_s
) ||
1443 wrap_mode_needs_border_color(wrap_t
) ||
1444 wrap_mode_needs_border_color(wrap_r
);
1446 float min_lod
= state
->min_lod
;
1447 unsigned mag_img_filter
= state
->mag_img_filter
;
1449 // XXX: explain this code ported from ilo...I don't get it at all...
1450 if (state
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
&&
1451 state
->min_lod
> 0.0f
) {
1453 mag_img_filter
= state
->min_img_filter
;
1456 iris_pack_state(GENX(SAMPLER_STATE
), cso
->sampler_state
, samp
) {
1457 samp
.TCXAddressControlMode
= wrap_s
;
1458 samp
.TCYAddressControlMode
= wrap_t
;
1459 samp
.TCZAddressControlMode
= wrap_r
;
1460 samp
.CubeSurfaceControlMode
= state
->seamless_cube_map
;
1461 samp
.NonnormalizedCoordinateEnable
= !state
->normalized_coords
;
1462 samp
.MinModeFilter
= state
->min_img_filter
;
1463 samp
.MagModeFilter
= mag_img_filter
;
1464 samp
.MipModeFilter
= translate_mip_filter(state
->min_mip_filter
);
1465 samp
.MaximumAnisotropy
= RATIO21
;
1467 if (state
->max_anisotropy
>= 2) {
1468 if (state
->min_img_filter
== PIPE_TEX_FILTER_LINEAR
) {
1469 samp
.MinModeFilter
= MAPFILTER_ANISOTROPIC
;
1470 samp
.AnisotropicAlgorithm
= EWAApproximation
;
1473 if (state
->mag_img_filter
== PIPE_TEX_FILTER_LINEAR
)
1474 samp
.MagModeFilter
= MAPFILTER_ANISOTROPIC
;
1476 samp
.MaximumAnisotropy
=
1477 MIN2((state
->max_anisotropy
- 2) / 2, RATIO161
);
1480 /* Set address rounding bits if not using nearest filtering. */
1481 if (state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1482 samp
.UAddressMinFilterRoundingEnable
= true;
1483 samp
.VAddressMinFilterRoundingEnable
= true;
1484 samp
.RAddressMinFilterRoundingEnable
= true;
1487 if (state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
1488 samp
.UAddressMagFilterRoundingEnable
= true;
1489 samp
.VAddressMagFilterRoundingEnable
= true;
1490 samp
.RAddressMagFilterRoundingEnable
= true;
1493 if (state
->compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
1494 samp
.ShadowFunction
= translate_shadow_func(state
->compare_func
);
1496 const float hw_max_lod
= GEN_GEN
>= 7 ? 14 : 13;
1498 samp
.LODPreClampMode
= CLAMP_MODE_OGL
;
1499 samp
.MinLOD
= CLAMP(min_lod
, 0, hw_max_lod
);
1500 samp
.MaxLOD
= CLAMP(state
->max_lod
, 0, hw_max_lod
);
1501 samp
.TextureLODBias
= CLAMP(state
->lod_bias
, -16, 15);
1503 /* .BorderColorPointer is filled in by iris_bind_sampler_states. */
1510 * The pipe->bind_sampler_states() driver hook.
1513 iris_bind_sampler_states(struct pipe_context
*ctx
,
1514 enum pipe_shader_type p_stage
,
1515 unsigned start
, unsigned count
,
1518 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1519 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1520 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1522 assert(start
+ count
<= IRIS_MAX_TEXTURE_SAMPLERS
);
1524 for (int i
= 0; i
< count
; i
++) {
1525 shs
->samplers
[start
+ i
] = states
[i
];
1528 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
;
1532 * Upload the sampler states into a contiguous area of GPU memory, for
1533 * for 3DSTATE_SAMPLER_STATE_POINTERS_*.
1535 * Also fill out the border color state pointers.
1538 iris_upload_sampler_states(struct iris_context
*ice
, gl_shader_stage stage
)
1540 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1541 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
1543 /* We assume the state tracker will call pipe->bind_sampler_states()
1544 * if the program's number of textures changes.
1546 unsigned count
= info
? util_last_bit(info
->textures_used
) : 0;
1551 /* Assemble the SAMPLER_STATEs into a contiguous table that lives
1552 * in the dynamic state memory zone, so we can point to it via the
1553 * 3DSTATE_SAMPLER_STATE_POINTERS_* commands.
1556 upload_state(ice
->state
.dynamic_uploader
, &shs
->sampler_table
,
1557 count
* 4 * GENX(SAMPLER_STATE_length
), 32);
1561 struct pipe_resource
*res
= shs
->sampler_table
.res
;
1562 shs
->sampler_table
.offset
+=
1563 iris_bo_offset_from_base_address(iris_resource_bo(res
));
1565 /* Make sure all land in the same BO */
1566 iris_border_color_pool_reserve(ice
, IRIS_MAX_TEXTURE_SAMPLERS
);
1568 ice
->state
.need_border_colors
&= ~(1 << stage
);
1570 for (int i
= 0; i
< count
; i
++) {
1571 struct iris_sampler_state
*state
= shs
->samplers
[i
];
1572 struct iris_sampler_view
*tex
= shs
->textures
[i
];
1575 memset(map
, 0, 4 * GENX(SAMPLER_STATE_length
));
1576 } else if (!state
->needs_border_color
) {
1577 memcpy(map
, state
->sampler_state
, 4 * GENX(SAMPLER_STATE_length
));
1579 ice
->state
.need_border_colors
|= 1 << stage
;
1581 /* We may need to swizzle the border color for format faking.
1582 * A/LA formats are faked as R/RG with 000R or R00G swizzles.
1583 * This means we need to move the border color's A channel into
1584 * the R or G channels so that those read swizzles will move it
1587 union pipe_color_union
*color
= &state
->border_color
;
1588 union pipe_color_union tmp
;
1590 enum pipe_format internal_format
= tex
->res
->internal_format
;
1592 if (util_format_is_alpha(internal_format
)) {
1593 unsigned char swz
[4] = {
1594 PIPE_SWIZZLE_W
, PIPE_SWIZZLE_0
,
1595 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1597 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1599 } else if (util_format_is_luminance_alpha(internal_format
) &&
1600 internal_format
!= PIPE_FORMAT_L8A8_SRGB
) {
1601 unsigned char swz
[4] = {
1602 PIPE_SWIZZLE_X
, PIPE_SWIZZLE_W
,
1603 PIPE_SWIZZLE_0
, PIPE_SWIZZLE_0
1605 util_format_apply_color_swizzle(&tmp
, color
, swz
, true);
1610 /* Stream out the border color and merge the pointer. */
1611 uint32_t offset
= iris_upload_border_color(ice
, color
);
1613 uint32_t dynamic
[GENX(SAMPLER_STATE_length
)];
1614 iris_pack_state(GENX(SAMPLER_STATE
), dynamic
, dyns
) {
1615 dyns
.BorderColorPointer
= offset
;
1618 for (uint32_t j
= 0; j
< GENX(SAMPLER_STATE_length
); j
++)
1619 map
[j
] = state
->sampler_state
[j
] | dynamic
[j
];
1622 map
+= GENX(SAMPLER_STATE_length
);
1626 static enum isl_channel_select
1627 fmt_swizzle(const struct iris_format_info
*fmt
, enum pipe_swizzle swz
)
1630 case PIPE_SWIZZLE_X
: return fmt
->swizzle
.r
;
1631 case PIPE_SWIZZLE_Y
: return fmt
->swizzle
.g
;
1632 case PIPE_SWIZZLE_Z
: return fmt
->swizzle
.b
;
1633 case PIPE_SWIZZLE_W
: return fmt
->swizzle
.a
;
1634 case PIPE_SWIZZLE_1
: return SCS_ONE
;
1635 case PIPE_SWIZZLE_0
: return SCS_ZERO
;
1636 default: unreachable("invalid swizzle");
1641 fill_buffer_surface_state(struct isl_device
*isl_dev
,
1644 enum isl_format format
,
1645 struct isl_swizzle swizzle
,
1649 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1650 const unsigned cpp
= format
== ISL_FORMAT_RAW
? 1 : fmtl
->bpb
/ 8;
1652 /* The ARB_texture_buffer_specification says:
1654 * "The number of texels in the buffer texture's texel array is given by
1656 * floor(<buffer_size> / (<components> * sizeof(<base_type>)),
1658 * where <buffer_size> is the size of the buffer object, in basic
1659 * machine units and <components> and <base_type> are the element count
1660 * and base data type for elements, as specified in Table X.1. The
1661 * number of texels in the texel array is then clamped to the
1662 * implementation-dependent limit MAX_TEXTURE_BUFFER_SIZE_ARB."
1664 * We need to clamp the size in bytes to MAX_TEXTURE_BUFFER_SIZE * stride,
1665 * so that when ISL divides by stride to obtain the number of texels, that
1666 * texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
1668 unsigned final_size
=
1669 MIN3(size
, bo
->size
- offset
, IRIS_MAX_TEXTURE_BUFFER_SIZE
* cpp
);
1671 isl_buffer_fill_state(isl_dev
, map
,
1672 .address
= bo
->gtt_offset
+ offset
,
1673 .size_B
= final_size
,
1680 #define SURFACE_STATE_ALIGNMENT 64
1683 * Allocate several contiguous SURFACE_STATE structures, one for each
1684 * supported auxiliary surface mode.
1687 alloc_surface_states(struct u_upload_mgr
*mgr
,
1688 struct iris_state_ref
*ref
,
1689 unsigned aux_usages
)
1691 const unsigned surf_size
= 4 * GENX(RENDER_SURFACE_STATE_length
);
1693 /* If this changes, update this to explicitly align pointers */
1694 STATIC_ASSERT(surf_size
== SURFACE_STATE_ALIGNMENT
);
1696 assert(aux_usages
!= 0);
1699 upload_state(mgr
, ref
, util_bitcount(aux_usages
) * surf_size
,
1700 SURFACE_STATE_ALIGNMENT
);
1702 ref
->offset
+= iris_bo_offset_from_base_address(iris_resource_bo(ref
->res
));
1708 fill_surface_state(struct isl_device
*isl_dev
,
1710 struct iris_resource
*res
,
1711 struct isl_view
*view
,
1714 struct isl_surf_fill_state_info f
= {
1717 .mocs
= mocs(res
->bo
),
1718 .address
= res
->bo
->gtt_offset
,
1721 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1722 f
.aux_surf
= &res
->aux
.surf
;
1723 f
.aux_usage
= aux_usage
;
1724 f
.aux_address
= res
->aux
.bo
->gtt_offset
+ res
->aux
.offset
;
1725 f
.clear_color
= res
->aux
.clear_color
;
1728 isl_surf_fill_state_s(isl_dev
, map
, &f
);
1732 * The pipe->create_sampler_view() driver hook.
1734 static struct pipe_sampler_view
*
1735 iris_create_sampler_view(struct pipe_context
*ctx
,
1736 struct pipe_resource
*tex
,
1737 const struct pipe_sampler_view
*tmpl
)
1739 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1740 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1741 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1742 struct iris_sampler_view
*isv
= calloc(1, sizeof(struct iris_sampler_view
));
1747 /* initialize base object */
1749 isv
->base
.context
= ctx
;
1750 isv
->base
.texture
= NULL
;
1751 pipe_reference_init(&isv
->base
.reference
, 1);
1752 pipe_resource_reference(&isv
->base
.texture
, tex
);
1754 if (util_format_is_depth_or_stencil(tmpl
->format
)) {
1755 struct iris_resource
*zres
, *sres
;
1756 const struct util_format_description
*desc
=
1757 util_format_description(tmpl
->format
);
1759 iris_get_depth_stencil_resources(tex
, &zres
, &sres
);
1761 tex
= util_format_has_depth(desc
) ? &zres
->base
: &sres
->base
;
1764 isv
->res
= (struct iris_resource
*) tex
;
1766 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1767 &isv
->surface_state
,
1768 isv
->res
->aux
.sampler_usages
);
1772 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
1774 if (isv
->base
.target
== PIPE_TEXTURE_CUBE
||
1775 isv
->base
.target
== PIPE_TEXTURE_CUBE_ARRAY
)
1776 usage
|= ISL_SURF_USAGE_CUBE_BIT
;
1778 const struct iris_format_info fmt
=
1779 iris_format_for_usage(devinfo
, tmpl
->format
, usage
);
1781 isv
->clear_color
= isv
->res
->aux
.clear_color
;
1783 isv
->view
= (struct isl_view
) {
1785 .swizzle
= (struct isl_swizzle
) {
1786 .r
= fmt_swizzle(&fmt
, tmpl
->swizzle_r
),
1787 .g
= fmt_swizzle(&fmt
, tmpl
->swizzle_g
),
1788 .b
= fmt_swizzle(&fmt
, tmpl
->swizzle_b
),
1789 .a
= fmt_swizzle(&fmt
, tmpl
->swizzle_a
),
1794 /* Fill out SURFACE_STATE for this view. */
1795 if (tmpl
->target
!= PIPE_BUFFER
) {
1796 isv
->view
.base_level
= tmpl
->u
.tex
.first_level
;
1797 isv
->view
.levels
= tmpl
->u
.tex
.last_level
- tmpl
->u
.tex
.first_level
+ 1;
1798 // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
1799 isv
->view
.base_array_layer
= tmpl
->u
.tex
.first_layer
;
1800 isv
->view
.array_len
=
1801 tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1;
1803 unsigned aux_modes
= isv
->res
->aux
.sampler_usages
;
1805 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1807 /* If we have a multisampled depth buffer, do not create a sampler
1808 * surface state with HiZ.
1810 fill_surface_state(&screen
->isl_dev
, map
, isv
->res
, &isv
->view
,
1813 map
+= SURFACE_STATE_ALIGNMENT
;
1816 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
->bo
, map
,
1817 isv
->view
.format
, isv
->view
.swizzle
,
1818 tmpl
->u
.buf
.offset
, tmpl
->u
.buf
.size
);
1825 iris_sampler_view_destroy(struct pipe_context
*ctx
,
1826 struct pipe_sampler_view
*state
)
1828 struct iris_sampler_view
*isv
= (void *) state
;
1829 pipe_resource_reference(&state
->texture
, NULL
);
1830 pipe_resource_reference(&isv
->surface_state
.res
, NULL
);
1835 * The pipe->create_surface() driver hook.
1837 * In Gallium nomenclature, "surfaces" are a view of a resource that
1838 * can be bound as a render target or depth/stencil buffer.
1840 static struct pipe_surface
*
1841 iris_create_surface(struct pipe_context
*ctx
,
1842 struct pipe_resource
*tex
,
1843 const struct pipe_surface
*tmpl
)
1845 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1846 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1847 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1848 struct iris_surface
*surf
= calloc(1, sizeof(struct iris_surface
));
1849 struct pipe_surface
*psurf
= &surf
->base
;
1850 struct iris_resource
*res
= (struct iris_resource
*) tex
;
1855 pipe_reference_init(&psurf
->reference
, 1);
1856 pipe_resource_reference(&psurf
->texture
, tex
);
1857 psurf
->context
= ctx
;
1858 psurf
->format
= tmpl
->format
;
1859 psurf
->width
= tex
->width0
;
1860 psurf
->height
= tex
->height0
;
1861 psurf
->texture
= tex
;
1862 psurf
->u
.tex
.first_layer
= tmpl
->u
.tex
.first_layer
;
1863 psurf
->u
.tex
.last_layer
= tmpl
->u
.tex
.last_layer
;
1864 psurf
->u
.tex
.level
= tmpl
->u
.tex
.level
;
1866 isl_surf_usage_flags_t usage
= 0;
1868 usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1869 else if (util_format_is_depth_or_stencil(tmpl
->format
))
1870 usage
= ISL_SURF_USAGE_DEPTH_BIT
;
1872 usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
1874 const struct iris_format_info fmt
=
1875 iris_format_for_usage(devinfo
, psurf
->format
, usage
);
1877 if ((usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
1878 !isl_format_supports_rendering(devinfo
, fmt
.fmt
)) {
1879 /* Framebuffer validation will reject this invalid case, but it
1880 * hasn't had the opportunity yet. In the meantime, we need to
1881 * avoid hitting ISL asserts about unsupported formats below.
1887 surf
->view
= (struct isl_view
) {
1889 .base_level
= tmpl
->u
.tex
.level
,
1891 .base_array_layer
= tmpl
->u
.tex
.first_layer
,
1892 .array_len
= tmpl
->u
.tex
.last_layer
- tmpl
->u
.tex
.first_layer
+ 1,
1893 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1897 surf
->clear_color
= res
->aux
.clear_color
;
1899 /* Bail early for depth/stencil - we don't want SURFACE_STATE for them. */
1900 if (res
->surf
.usage
& (ISL_SURF_USAGE_DEPTH_BIT
|
1901 ISL_SURF_USAGE_STENCIL_BIT
))
1905 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
1906 &surf
->surface_state
,
1907 res
->aux
.possible_usages
);
1911 unsigned aux_modes
= res
->aux
.possible_usages
;
1913 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
1915 fill_surface_state(&screen
->isl_dev
, map
, res
, &surf
->view
, aux_usage
);
1917 map
+= SURFACE_STATE_ALIGNMENT
;
1925 fill_default_image_param(struct brw_image_param
*param
)
1927 memset(param
, 0, sizeof(*param
));
1928 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
1929 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
1930 * detailed explanation of these parameters.
1932 param
->swizzling
[0] = 0xff;
1933 param
->swizzling
[1] = 0xff;
1937 fill_buffer_image_param(struct brw_image_param
*param
,
1938 enum pipe_format pfmt
,
1941 const unsigned cpp
= util_format_get_blocksize(pfmt
);
1943 fill_default_image_param(param
);
1944 param
->size
[0] = size
/ cpp
;
1945 param
->stride
[0] = cpp
;
1948 #define isl_surf_fill_image_param(x, ...)
1949 #define fill_default_image_param(x, ...)
1950 #define fill_buffer_image_param(x, ...)
1954 * The pipe->set_shader_images() driver hook.
1957 iris_set_shader_images(struct pipe_context
*ctx
,
1958 enum pipe_shader_type p_stage
,
1959 unsigned start_slot
, unsigned count
,
1960 const struct pipe_image_view
*p_images
)
1962 struct iris_context
*ice
= (struct iris_context
*) ctx
;
1963 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
1964 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1965 gl_shader_stage stage
= stage_from_pipe(p_stage
);
1966 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
1968 struct iris_genx_state
*genx
= ice
->state
.genx
;
1969 struct brw_image_param
*image_params
= genx
->shaders
[stage
].image_param
;
1972 shs
->bound_image_views
&= ~u_bit_consecutive(start_slot
, count
);
1974 for (unsigned i
= 0; i
< count
; i
++) {
1975 struct iris_image_view
*iv
= &shs
->image
[start_slot
+ i
];
1977 if (p_images
&& p_images
[i
].resource
) {
1978 const struct pipe_image_view
*img
= &p_images
[i
];
1979 struct iris_resource
*res
= (void *) img
->resource
;
1981 // XXX: these are not retained forever, use a separate uploader?
1983 alloc_surface_states(ice
->state
.surface_uploader
,
1984 &iv
->surface_state
, 1 << ISL_AUX_USAGE_NONE
);
1989 iv
->base
.resource
= NULL
;
1990 pipe_resource_reference(&iv
->base
.resource
, &res
->base
);
1992 shs
->bound_image_views
|= 1 << (start_slot
+ i
);
1994 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
1996 isl_surf_usage_flags_t usage
= ISL_SURF_USAGE_STORAGE_BIT
;
1997 enum isl_format isl_fmt
=
1998 iris_format_for_usage(devinfo
, img
->format
, usage
).fmt
;
2000 bool untyped_fallback
= false;
2002 if (img
->shader_access
& PIPE_IMAGE_ACCESS_READ
) {
2003 /* On Gen8, try to use typed surfaces reads (which support a
2004 * limited number of formats), and if not possible, fall back
2007 untyped_fallback
= GEN_GEN
== 8 &&
2008 !isl_has_matching_typed_storage_image_format(devinfo
, isl_fmt
);
2010 if (untyped_fallback
)
2011 isl_fmt
= ISL_FORMAT_RAW
;
2013 isl_fmt
= isl_lower_storage_image_format(devinfo
, isl_fmt
);
2016 if (res
->base
.target
!= PIPE_BUFFER
) {
2017 struct isl_view view
= {
2019 .base_level
= img
->u
.tex
.level
,
2021 .base_array_layer
= img
->u
.tex
.first_layer
,
2022 .array_len
= img
->u
.tex
.last_layer
- img
->u
.tex
.first_layer
+ 1,
2023 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2027 if (untyped_fallback
) {
2028 fill_buffer_surface_state(&screen
->isl_dev
, res
->bo
, map
,
2029 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2032 /* Images don't support compression */
2033 unsigned aux_modes
= 1 << ISL_AUX_USAGE_NONE
;
2035 enum isl_aux_usage usage
= u_bit_scan(&aux_modes
);
2037 fill_surface_state(&screen
->isl_dev
, map
, res
, &view
, usage
);
2039 map
+= SURFACE_STATE_ALIGNMENT
;
2043 isl_surf_fill_image_param(&screen
->isl_dev
,
2044 &image_params
[start_slot
+ i
],
2047 util_range_add(&res
->valid_buffer_range
, img
->u
.buf
.offset
,
2048 img
->u
.buf
.offset
+ img
->u
.buf
.size
);
2050 fill_buffer_surface_state(&screen
->isl_dev
, res
->bo
, map
,
2051 isl_fmt
, ISL_SWIZZLE_IDENTITY
,
2052 img
->u
.buf
.offset
, img
->u
.buf
.size
);
2053 fill_buffer_image_param(&image_params
[start_slot
+ i
],
2054 img
->format
, img
->u
.buf
.size
);
2057 pipe_resource_reference(&iv
->base
.resource
, NULL
);
2058 pipe_resource_reference(&iv
->surface_state
.res
, NULL
);
2059 fill_default_image_param(&image_params
[start_slot
+ i
]);
2063 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2065 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2066 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2068 /* Broadwell also needs brw_image_params re-uploaded */
2070 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2071 shs
->cbuf0_needs_upload
= true;
2077 * The pipe->set_sampler_views() driver hook.
2080 iris_set_sampler_views(struct pipe_context
*ctx
,
2081 enum pipe_shader_type p_stage
,
2082 unsigned start
, unsigned count
,
2083 struct pipe_sampler_view
**views
)
2085 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2086 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2087 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2089 shs
->bound_sampler_views
&= ~u_bit_consecutive(start
, count
);
2091 for (unsigned i
= 0; i
< count
; i
++) {
2092 struct pipe_sampler_view
*pview
= views
? views
[i
] : NULL
;
2093 pipe_sampler_view_reference((struct pipe_sampler_view
**)
2094 &shs
->textures
[start
+ i
], pview
);
2095 struct iris_sampler_view
*view
= (void *) pview
;
2097 view
->res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
2098 shs
->bound_sampler_views
|= 1 << (start
+ i
);
2102 ice
->state
.dirty
|= (IRIS_DIRTY_BINDINGS_VS
<< stage
);
2104 stage
== MESA_SHADER_COMPUTE
? IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES
2105 : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2109 * The pipe->set_tess_state() driver hook.
2112 iris_set_tess_state(struct pipe_context
*ctx
,
2113 const float default_outer_level
[4],
2114 const float default_inner_level
[2])
2116 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2117 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_TESS_CTRL
];
2119 memcpy(&ice
->state
.default_outer_level
[0], &default_outer_level
[0], 4 * sizeof(float));
2120 memcpy(&ice
->state
.default_inner_level
[0], &default_inner_level
[0], 2 * sizeof(float));
2122 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_TCS
;
2123 shs
->cbuf0_needs_upload
= true;
2127 iris_surface_destroy(struct pipe_context
*ctx
, struct pipe_surface
*p_surf
)
2129 struct iris_surface
*surf
= (void *) p_surf
;
2130 pipe_resource_reference(&p_surf
->texture
, NULL
);
2131 pipe_resource_reference(&surf
->surface_state
.res
, NULL
);
2136 iris_set_clip_state(struct pipe_context
*ctx
,
2137 const struct pipe_clip_state
*state
)
2139 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2140 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_VERTEX
];
2142 memcpy(&ice
->state
.clip_planes
, state
, sizeof(*state
));
2144 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
;
2145 shs
->cbuf0_needs_upload
= true;
2149 * The pipe->set_polygon_stipple() driver hook.
2152 iris_set_polygon_stipple(struct pipe_context
*ctx
,
2153 const struct pipe_poly_stipple
*state
)
2155 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2156 memcpy(&ice
->state
.poly_stipple
, state
, sizeof(*state
));
2157 ice
->state
.dirty
|= IRIS_DIRTY_POLYGON_STIPPLE
;
2161 * The pipe->set_sample_mask() driver hook.
2164 iris_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2166 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2168 /* We only support 16x MSAA, so we have 16 bits of sample maks.
2169 * st/mesa may pass us 0xffffffff though, meaning "enable all samples".
2171 ice
->state
.sample_mask
= sample_mask
& 0xffff;
2172 ice
->state
.dirty
|= IRIS_DIRTY_SAMPLE_MASK
;
2176 * The pipe->set_scissor_states() driver hook.
2178 * This corresponds to our SCISSOR_RECT state structures. It's an
2179 * exact match, so we just store them, and memcpy them out later.
2182 iris_set_scissor_states(struct pipe_context
*ctx
,
2183 unsigned start_slot
,
2184 unsigned num_scissors
,
2185 const struct pipe_scissor_state
*rects
)
2187 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2189 for (unsigned i
= 0; i
< num_scissors
; i
++) {
2190 if (rects
[i
].minx
== rects
[i
].maxx
|| rects
[i
].miny
== rects
[i
].maxy
) {
2191 /* If the scissor was out of bounds and got clamped to 0 width/height
2192 * at the bounds, the subtraction of 1 from maximums could produce a
2193 * negative number and thus not clip anything. Instead, just provide
2194 * a min > max scissor inside the bounds, which produces the expected
2197 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2198 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,
2201 ice
->state
.scissors
[start_slot
+ i
] = (struct pipe_scissor_state
) {
2202 .minx
= rects
[i
].minx
, .miny
= rects
[i
].miny
,
2203 .maxx
= rects
[i
].maxx
- 1, .maxy
= rects
[i
].maxy
- 1,
2208 ice
->state
.dirty
|= IRIS_DIRTY_SCISSOR_RECT
;
2212 * The pipe->set_stencil_ref() driver hook.
2214 * This is added to 3DSTATE_WM_DEPTH_STENCIL dynamically at draw time.
2217 iris_set_stencil_ref(struct pipe_context
*ctx
,
2218 const struct pipe_stencil_ref
*state
)
2220 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2221 memcpy(&ice
->state
.stencil_ref
, state
, sizeof(*state
));
2223 ice
->state
.dirty
|= IRIS_DIRTY_COLOR_CALC_STATE
;
2225 ice
->state
.dirty
|= IRIS_DIRTY_WM_DEPTH_STENCIL
;
2229 viewport_extent(const struct pipe_viewport_state
*state
, int axis
, float sign
)
2231 return copysignf(state
->scale
[axis
], sign
) + state
->translate
[axis
];
2235 calculate_guardband_size(uint32_t fb_width
, uint32_t fb_height
,
2236 float m00
, float m11
, float m30
, float m31
,
2237 float *xmin
, float *xmax
,
2238 float *ymin
, float *ymax
)
2240 /* According to the "Vertex X,Y Clamping and Quantization" section of the
2241 * Strips and Fans documentation:
2243 * "The vertex X and Y screen-space coordinates are also /clamped/ to the
2244 * fixed-point "guardband" range supported by the rasterization hardware"
2248 * "In almost all circumstances, if an object’s vertices are actually
2249 * modified by this clamping (i.e., had X or Y coordinates outside of
2250 * the guardband extent the rendered object will not match the intended
2251 * result. Therefore software should take steps to ensure that this does
2252 * not happen - e.g., by clipping objects such that they do not exceed
2253 * these limits after the Drawing Rectangle is applied."
2255 * I believe the fundamental restriction is that the rasterizer (in
2256 * the SF/WM stages) have a limit on the number of pixels that can be
2257 * rasterized. We need to ensure any coordinates beyond the rasterizer
2258 * limit are handled by the clipper. So effectively that limit becomes
2259 * the clipper's guardband size.
2261 * It goes on to say:
2263 * "In addition, in order to be correctly rendered, objects must have a
2264 * screenspace bounding box not exceeding 8K in the X or Y direction.
2265 * This additional restriction must also be comprehended by software,
2266 * i.e., enforced by use of clipping."
2268 * This makes no sense. Gen7+ hardware supports 16K render targets,
2269 * and you definitely need to be able to draw polygons that fill the
2270 * surface. Our assumption is that the rasterizer was limited to 8K
2271 * on Sandybridge, which only supports 8K surfaces, and it was actually
2272 * increased to 16K on Ivybridge and later.
2274 * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge.
2276 const float gb_size
= GEN_GEN
>= 7 ? 16384.0f
: 8192.0f
;
2278 if (m00
!= 0 && m11
!= 0) {
2279 /* First, we compute the screen-space render area */
2280 const float ss_ra_xmin
= MIN3( 0, m30
+ m00
, m30
- m00
);
2281 const float ss_ra_xmax
= MAX3( fb_width
, m30
+ m00
, m30
- m00
);
2282 const float ss_ra_ymin
= MIN3( 0, m31
+ m11
, m31
- m11
);
2283 const float ss_ra_ymax
= MAX3(fb_height
, m31
+ m11
, m31
- m11
);
2285 /* We want the guardband to be centered on that */
2286 const float ss_gb_xmin
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 - gb_size
;
2287 const float ss_gb_xmax
= (ss_ra_xmin
+ ss_ra_xmax
) / 2 + gb_size
;
2288 const float ss_gb_ymin
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 - gb_size
;
2289 const float ss_gb_ymax
= (ss_ra_ymin
+ ss_ra_ymax
) / 2 + gb_size
;
2291 /* Now we need it in native device coordinates */
2292 const float ndc_gb_xmin
= (ss_gb_xmin
- m30
) / m00
;
2293 const float ndc_gb_xmax
= (ss_gb_xmax
- m30
) / m00
;
2294 const float ndc_gb_ymin
= (ss_gb_ymin
- m31
) / m11
;
2295 const float ndc_gb_ymax
= (ss_gb_ymax
- m31
) / m11
;
2297 /* Thanks to Y-flipping and ORIGIN_UPPER_LEFT, the Y coordinates may be
2298 * flipped upside-down. X should be fine though.
2300 assert(ndc_gb_xmin
<= ndc_gb_xmax
);
2301 *xmin
= ndc_gb_xmin
;
2302 *xmax
= ndc_gb_xmax
;
2303 *ymin
= MIN2(ndc_gb_ymin
, ndc_gb_ymax
);
2304 *ymax
= MAX2(ndc_gb_ymin
, ndc_gb_ymax
);
2306 /* The viewport scales to 0, so nothing will be rendered. */
2315 * The pipe->set_viewport_states() driver hook.
2317 * This corresponds to our SF_CLIP_VIEWPORT states. We can't calculate
2318 * the guardband yet, as we need the framebuffer dimensions, but we can
2319 * at least fill out the rest.
2322 iris_set_viewport_states(struct pipe_context
*ctx
,
2323 unsigned start_slot
,
2325 const struct pipe_viewport_state
*states
)
2327 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2329 memcpy(&ice
->state
.viewports
[start_slot
], states
, sizeof(*states
) * count
);
2331 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2333 if (ice
->state
.cso_rast
&& (!ice
->state
.cso_rast
->depth_clip_near
||
2334 !ice
->state
.cso_rast
->depth_clip_far
))
2335 ice
->state
.dirty
|= IRIS_DIRTY_CC_VIEWPORT
;
2339 * The pipe->set_framebuffer_state() driver hook.
2341 * Sets the current draw FBO, including color render targets, depth,
2342 * and stencil buffers.
2345 iris_set_framebuffer_state(struct pipe_context
*ctx
,
2346 const struct pipe_framebuffer_state
*state
)
2348 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2349 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2350 struct isl_device
*isl_dev
= &screen
->isl_dev
;
2351 struct pipe_framebuffer_state
*cso
= &ice
->state
.framebuffer
;
2352 struct iris_resource
*zres
;
2353 struct iris_resource
*stencil_res
;
2355 unsigned samples
= util_framebuffer_get_num_samples(state
);
2356 unsigned layers
= util_framebuffer_get_num_layers(state
);
2358 if (cso
->samples
!= samples
) {
2359 ice
->state
.dirty
|= IRIS_DIRTY_MULTISAMPLE
;
2362 if (cso
->nr_cbufs
!= state
->nr_cbufs
) {
2363 ice
->state
.dirty
|= IRIS_DIRTY_BLEND_STATE
;
2366 if ((cso
->layers
== 0) != (layers
== 0)) {
2367 ice
->state
.dirty
|= IRIS_DIRTY_CLIP
;
2370 if (cso
->width
!= state
->width
|| cso
->height
!= state
->height
) {
2371 ice
->state
.dirty
|= IRIS_DIRTY_SF_CL_VIEWPORT
;
2374 util_copy_framebuffer_state(cso
, state
);
2375 cso
->samples
= samples
;
2376 cso
->layers
= layers
;
2378 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
2380 struct isl_view view
= {
2383 .base_array_layer
= 0,
2385 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2388 struct isl_depth_stencil_hiz_emit_info info
= { .view
= &view
};
2391 iris_get_depth_stencil_resources(cso
->zsbuf
->texture
, &zres
,
2394 view
.base_level
= cso
->zsbuf
->u
.tex
.level
;
2395 view
.base_array_layer
= cso
->zsbuf
->u
.tex
.first_layer
;
2397 cso
->zsbuf
->u
.tex
.last_layer
- cso
->zsbuf
->u
.tex
.first_layer
+ 1;
2400 view
.usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
2402 info
.depth_surf
= &zres
->surf
;
2403 info
.depth_address
= zres
->bo
->gtt_offset
;
2404 info
.mocs
= mocs(zres
->bo
);
2406 view
.format
= zres
->surf
.format
;
2408 if (iris_resource_level_has_hiz(zres
, view
.base_level
)) {
2409 info
.hiz_usage
= ISL_AUX_USAGE_HIZ
;
2410 info
.hiz_surf
= &zres
->aux
.surf
;
2411 info
.hiz_address
= zres
->aux
.bo
->gtt_offset
;
2416 view
.usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
2417 info
.stencil_surf
= &stencil_res
->surf
;
2418 info
.stencil_address
= stencil_res
->bo
->gtt_offset
;
2420 view
.format
= stencil_res
->surf
.format
;
2421 info
.mocs
= mocs(stencil_res
->bo
);
2426 isl_emit_depth_stencil_hiz_s(isl_dev
, cso_z
->packets
, &info
);
2428 /* Make a null surface for unbound buffers */
2429 void *null_surf_map
=
2430 upload_state(ice
->state
.surface_uploader
, &ice
->state
.null_fb
,
2431 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2432 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
,
2433 isl_extent3d(MAX2(cso
->width
, 1),
2434 MAX2(cso
->height
, 1),
2435 cso
->layers
? cso
->layers
: 1));
2436 ice
->state
.null_fb
.offset
+=
2437 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.null_fb
.res
));
2439 ice
->state
.dirty
|= IRIS_DIRTY_DEPTH_BUFFER
;
2441 /* Render target change */
2442 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_FS
;
2444 ice
->state
.dirty
|= IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES
;
2446 ice
->state
.dirty
|= ice
->state
.dirty_for_nos
[IRIS_NOS_FRAMEBUFFER
];
2449 // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?)
2450 // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6
2452 /* The PIPE_CONTROL command description says:
2454 * "Whenever a Binding Table Index (BTI) used by a Render Target Message
2455 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2456 * Target Cache Flush by enabling this bit. When render target flush
2457 * is set due to new association of BTI, PS Scoreboard Stall bit must
2458 * be set in this packet."
2460 // XXX: does this need to happen at 3DSTATE_BTP_PS time?
2461 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
],
2462 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
2463 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
2468 upload_ubo_ssbo_surf_state(struct iris_context
*ice
,
2469 struct pipe_shader_buffer
*buf
,
2470 struct iris_state_ref
*surf_state
,
2473 struct pipe_context
*ctx
= &ice
->ctx
;
2474 struct iris_screen
*screen
= (struct iris_screen
*) ctx
->screen
;
2476 // XXX: these are not retained forever, use a separate uploader?
2478 upload_state(ice
->state
.surface_uploader
, surf_state
,
2479 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
2480 if (!unlikely(map
)) {
2481 surf_state
->res
= NULL
;
2485 struct iris_resource
*res
= (void *) buf
->buffer
;
2486 struct iris_bo
*surf_bo
= iris_resource_bo(surf_state
->res
);
2487 surf_state
->offset
+= iris_bo_offset_from_base_address(surf_bo
);
2489 isl_buffer_fill_state(&screen
->isl_dev
, map
,
2490 .address
= res
->bo
->gtt_offset
+ buf
->buffer_offset
,
2491 .size_B
= buf
->buffer_size
,
2492 .format
= ssbo
? ISL_FORMAT_RAW
2493 : ISL_FORMAT_R32G32B32A32_FLOAT
,
2494 .swizzle
= ISL_SWIZZLE_IDENTITY
,
2496 .mocs
= mocs(res
->bo
))
2501 * The pipe->set_constant_buffer() driver hook.
2503 * This uploads any constant data in user buffers, and references
2504 * any UBO resources containing constant data.
2507 iris_set_constant_buffer(struct pipe_context
*ctx
,
2508 enum pipe_shader_type p_stage
, unsigned index
,
2509 const struct pipe_constant_buffer
*input
)
2511 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2512 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2513 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2514 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[index
];
2516 if (input
&& input
->buffer
) {
2517 shs
->bound_cbufs
|= 1u << index
;
2521 pipe_resource_reference(&cbuf
->buffer
, input
->buffer
);
2522 cbuf
->buffer_offset
= input
->buffer_offset
;
2524 MIN2(input
->buffer_size
,
2525 iris_resource_bo(input
->buffer
)->size
- cbuf
->buffer_offset
);
2527 struct iris_resource
*res
= (void *) cbuf
->buffer
;
2528 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
2530 upload_ubo_ssbo_surf_state(ice
, cbuf
, &shs
->constbuf_surf_state
[index
],
2533 shs
->bound_cbufs
&= ~(1u << index
);
2534 pipe_resource_reference(&cbuf
->buffer
, NULL
);
2535 pipe_resource_reference(&shs
->constbuf_surf_state
[index
].res
, NULL
);
2540 memcpy(&shs
->cbuf0
, input
, sizeof(shs
->cbuf0
));
2542 memset(&shs
->cbuf0
, 0, sizeof(shs
->cbuf0
));
2544 shs
->cbuf0_needs_upload
= true;
2547 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< stage
;
2548 // XXX: maybe not necessary all the time...?
2549 // XXX: we need 3DS_BTP to commit these changes, and if we fell back to
2550 // XXX: pull model we may need actual new bindings...
2551 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2555 upload_uniforms(struct iris_context
*ice
,
2556 gl_shader_stage stage
)
2558 UNUSED
struct iris_genx_state
*genx
= ice
->state
.genx
;
2559 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2560 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[0];
2561 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
2563 unsigned upload_size
= shader
->num_system_values
* sizeof(uint32_t) +
2564 shs
->cbuf0
.buffer_size
;
2566 if (upload_size
== 0)
2569 uint32_t *map
= NULL
;
2570 u_upload_alloc(ice
->ctx
.const_uploader
, 0, upload_size
, 64,
2571 &cbuf
->buffer_offset
, &cbuf
->buffer
, (void **) &map
);
2573 for (int i
= 0; i
< shader
->num_system_values
; i
++) {
2574 uint32_t sysval
= shader
->system_values
[i
];
2577 if (BRW_PARAM_DOMAIN(sysval
) == BRW_PARAM_DOMAIN_IMAGE
) {
2579 unsigned img
= BRW_PARAM_IMAGE_IDX(sysval
);
2580 unsigned offset
= BRW_PARAM_IMAGE_OFFSET(sysval
);
2581 struct brw_image_param
*param
=
2582 &genx
->shaders
[stage
].image_param
[img
];
2584 assert(offset
< sizeof(struct brw_image_param
));
2585 value
= ((uint32_t *) param
)[offset
];
2587 } else if (sysval
== BRW_PARAM_BUILTIN_ZERO
) {
2589 } else if (BRW_PARAM_BUILTIN_IS_CLIP_PLANE(sysval
)) {
2590 int plane
= BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval
);
2591 int comp
= BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval
);
2592 value
= fui(ice
->state
.clip_planes
.ucp
[plane
][comp
]);
2593 } else if (sysval
== BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
) {
2594 if (stage
== MESA_SHADER_TESS_CTRL
) {
2595 value
= ice
->state
.vertices_per_patch
;
2597 assert(stage
== MESA_SHADER_TESS_EVAL
);
2598 const struct shader_info
*tcs_info
=
2599 iris_get_shader_info(ice
, MESA_SHADER_TESS_CTRL
);
2601 value
= tcs_info
->tess
.tcs_vertices_out
;
2603 value
= ice
->state
.vertices_per_patch
;
2605 } else if (sysval
>= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
&&
2606 sysval
<= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
) {
2607 unsigned i
= sysval
- BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
;
2608 value
= fui(ice
->state
.default_outer_level
[i
]);
2609 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
) {
2610 value
= fui(ice
->state
.default_inner_level
[0]);
2611 } else if (sysval
== BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
) {
2612 value
= fui(ice
->state
.default_inner_level
[1]);
2614 assert(!"unhandled system value");
2620 if (shs
->cbuf0
.user_buffer
) {
2621 memcpy(map
, shs
->cbuf0
.user_buffer
, shs
->cbuf0
.buffer_size
);
2624 cbuf
->buffer_size
= upload_size
;
2625 upload_ubo_ssbo_surf_state(ice
, cbuf
, &shs
->constbuf_surf_state
[0], false);
2629 * The pipe->set_shader_buffers() driver hook.
2631 * This binds SSBOs and ABOs. Unfortunately, we need to stream out
2632 * SURFACE_STATE here, as the buffer offset may change each time.
2635 iris_set_shader_buffers(struct pipe_context
*ctx
,
2636 enum pipe_shader_type p_stage
,
2637 unsigned start_slot
, unsigned count
,
2638 const struct pipe_shader_buffer
*buffers
,
2639 unsigned writable_bitmask
)
2641 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2642 gl_shader_stage stage
= stage_from_pipe(p_stage
);
2643 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
2645 unsigned modified_bits
= u_bit_consecutive(start_slot
, count
);
2647 shs
->bound_ssbos
&= ~modified_bits
;
2648 shs
->writable_ssbos
&= ~modified_bits
;
2649 shs
->writable_ssbos
|= writable_bitmask
<< start_slot
;
2651 for (unsigned i
= 0; i
< count
; i
++) {
2652 if (buffers
&& buffers
[i
].buffer
) {
2653 struct iris_resource
*res
= (void *) buffers
[i
].buffer
;
2654 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[start_slot
+ i
];
2655 struct iris_state_ref
*surf_state
=
2656 &shs
->ssbo_surf_state
[start_slot
+ i
];
2657 pipe_resource_reference(&ssbo
->buffer
, &res
->base
);
2658 ssbo
->buffer_offset
= buffers
[i
].buffer_offset
;
2660 MIN2(buffers
[i
].buffer_size
, res
->bo
->size
- ssbo
->buffer_offset
);
2662 shs
->bound_ssbos
|= 1 << (start_slot
+ i
);
2664 upload_ubo_ssbo_surf_state(ice
, ssbo
, surf_state
, true);
2666 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
2668 util_range_add(&res
->valid_buffer_range
, ssbo
->buffer_offset
,
2669 ssbo
->buffer_offset
+ ssbo
->buffer_size
);
2671 pipe_resource_reference(&shs
->ssbo
[start_slot
+ i
].buffer
, NULL
);
2672 pipe_resource_reference(&shs
->ssbo_surf_state
[start_slot
+ i
].res
,
2677 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< stage
;
2681 iris_delete_state(struct pipe_context
*ctx
, void *state
)
2687 * The pipe->set_vertex_buffers() driver hook.
2689 * This translates pipe_vertex_buffer to our 3DSTATE_VERTEX_BUFFERS packet.
2692 iris_set_vertex_buffers(struct pipe_context
*ctx
,
2693 unsigned start_slot
, unsigned count
,
2694 const struct pipe_vertex_buffer
*buffers
)
2696 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2697 struct iris_genx_state
*genx
= ice
->state
.genx
;
2699 ice
->state
.bound_vertex_buffers
&= ~u_bit_consecutive64(start_slot
, count
);
2701 for (unsigned i
= 0; i
< count
; i
++) {
2702 const struct pipe_vertex_buffer
*buffer
= buffers
? &buffers
[i
] : NULL
;
2703 struct iris_vertex_buffer_state
*state
=
2704 &genx
->vertex_buffers
[start_slot
+ i
];
2707 pipe_resource_reference(&state
->resource
, NULL
);
2711 /* We may see user buffers that are NULL bindings. */
2712 assert(!(buffer
->is_user_buffer
&& buffer
->buffer
.user
!= NULL
));
2714 pipe_resource_reference(&state
->resource
, buffer
->buffer
.resource
);
2715 struct iris_resource
*res
= (void *) state
->resource
;
2718 ice
->state
.bound_vertex_buffers
|= 1ull << (start_slot
+ i
);
2719 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
2722 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
2723 vb
.VertexBufferIndex
= start_slot
+ i
;
2724 vb
.AddressModifyEnable
= true;
2725 vb
.BufferPitch
= buffer
->stride
;
2727 vb
.BufferSize
= res
->bo
->size
- (int) buffer
->buffer_offset
;
2728 vb
.BufferStartingAddress
=
2729 ro_bo(NULL
, res
->bo
->gtt_offset
+ (int) buffer
->buffer_offset
);
2730 vb
.MOCS
= mocs(res
->bo
);
2732 vb
.NullVertexBuffer
= true;
2737 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
2741 * Gallium CSO for vertex elements.
2743 struct iris_vertex_element_state
{
2744 uint32_t vertex_elements
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
2745 uint32_t vf_instancing
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
2746 uint32_t edgeflag_ve
[GENX(VERTEX_ELEMENT_STATE_length
)];
2747 uint32_t edgeflag_vfi
[GENX(3DSTATE_VF_INSTANCING_length
)];
2752 * The pipe->create_vertex_elements() driver hook.
2754 * This translates pipe_vertex_element to our 3DSTATE_VERTEX_ELEMENTS
2755 * and 3DSTATE_VF_INSTANCING commands. The vertex_elements and vf_instancing
2756 * arrays are ready to be emitted at draw time if no EdgeFlag or SGVs are
2757 * needed. In these cases we will need information available at draw time.
2758 * We setup edgeflag_ve and edgeflag_vfi as alternatives last
2759 * 3DSTATE_VERTEX_ELEMENT and 3DSTATE_VF_INSTANCING that can be used at
2760 * draw time if we detect that EdgeFlag is needed by the Vertex Shader.
2763 iris_create_vertex_elements(struct pipe_context
*ctx
,
2765 const struct pipe_vertex_element
*state
)
2767 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
2768 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2769 struct iris_vertex_element_state
*cso
=
2770 malloc(sizeof(struct iris_vertex_element_state
));
2774 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
), cso
->vertex_elements
, ve
) {
2776 1 + GENX(VERTEX_ELEMENT_STATE_length
) * MAX2(count
, 1) - 2;
2779 uint32_t *ve_pack_dest
= &cso
->vertex_elements
[1];
2780 uint32_t *vfi_pack_dest
= cso
->vf_instancing
;
2783 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2785 ve
.SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
2786 ve
.Component0Control
= VFCOMP_STORE_0
;
2787 ve
.Component1Control
= VFCOMP_STORE_0
;
2788 ve
.Component2Control
= VFCOMP_STORE_0
;
2789 ve
.Component3Control
= VFCOMP_STORE_1_FP
;
2792 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2796 for (int i
= 0; i
< count
; i
++) {
2797 const struct iris_format_info fmt
=
2798 iris_format_for_usage(devinfo
, state
[i
].src_format
, 0);
2799 unsigned comp
[4] = { VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
,
2800 VFCOMP_STORE_SRC
, VFCOMP_STORE_SRC
};
2802 switch (isl_format_get_num_channels(fmt
.fmt
)) {
2803 case 0: comp
[0] = VFCOMP_STORE_0
; /* fallthrough */
2804 case 1: comp
[1] = VFCOMP_STORE_0
; /* fallthrough */
2805 case 2: comp
[2] = VFCOMP_STORE_0
; /* fallthrough */
2807 comp
[3] = isl_format_has_int_channel(fmt
.fmt
) ? VFCOMP_STORE_1_INT
2808 : VFCOMP_STORE_1_FP
;
2811 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
2812 ve
.EdgeFlagEnable
= false;
2813 ve
.VertexBufferIndex
= state
[i
].vertex_buffer_index
;
2815 ve
.SourceElementOffset
= state
[i
].src_offset
;
2816 ve
.SourceElementFormat
= fmt
.fmt
;
2817 ve
.Component0Control
= comp
[0];
2818 ve
.Component1Control
= comp
[1];
2819 ve
.Component2Control
= comp
[2];
2820 ve
.Component3Control
= comp
[3];
2823 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
2824 vi
.VertexElementIndex
= i
;
2825 vi
.InstancingEnable
= state
[i
].instance_divisor
> 0;
2826 vi
.InstanceDataStepRate
= state
[i
].instance_divisor
;
2829 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
2830 vfi_pack_dest
+= GENX(3DSTATE_VF_INSTANCING_length
);
2833 /* An alternative version of the last VE and VFI is stored so it
2834 * can be used at draw time in case Vertex Shader uses EdgeFlag
2837 const unsigned edgeflag_index
= count
- 1;
2838 const struct iris_format_info fmt
=
2839 iris_format_for_usage(devinfo
, state
[edgeflag_index
].src_format
, 0);
2840 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), cso
->edgeflag_ve
, ve
) {
2841 ve
.EdgeFlagEnable
= true ;
2842 ve
.VertexBufferIndex
= state
[edgeflag_index
].vertex_buffer_index
;
2844 ve
.SourceElementOffset
= state
[edgeflag_index
].src_offset
;
2845 ve
.SourceElementFormat
= fmt
.fmt
;
2846 ve
.Component0Control
= VFCOMP_STORE_SRC
;
2847 ve
.Component1Control
= VFCOMP_STORE_0
;
2848 ve
.Component2Control
= VFCOMP_STORE_0
;
2849 ve
.Component3Control
= VFCOMP_STORE_0
;
2851 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), cso
->edgeflag_vfi
, vi
) {
2852 /* The vi.VertexElementIndex of the EdgeFlag Vertex Element is filled
2853 * at draw time, as it should change if SGVs are emitted.
2855 vi
.InstancingEnable
= state
[edgeflag_index
].instance_divisor
> 0;
2856 vi
.InstanceDataStepRate
= state
[edgeflag_index
].instance_divisor
;
2864 * The pipe->bind_vertex_elements_state() driver hook.
2867 iris_bind_vertex_elements_state(struct pipe_context
*ctx
, void *state
)
2869 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2870 struct iris_vertex_element_state
*old_cso
= ice
->state
.cso_vertex_elements
;
2871 struct iris_vertex_element_state
*new_cso
= state
;
2873 /* 3DSTATE_VF_SGVs overrides the last VE, so if the count is changing,
2874 * we need to re-emit it to ensure we're overriding the right one.
2876 if (new_cso
&& cso_changed(count
))
2877 ice
->state
.dirty
|= IRIS_DIRTY_VF_SGVS
;
2879 ice
->state
.cso_vertex_elements
= state
;
2880 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_ELEMENTS
;
2884 * The pipe->create_stream_output_target() driver hook.
2886 * "Target" here refers to a destination buffer. We translate this into
2887 * a 3DSTATE_SO_BUFFER packet. We can handle most fields, but don't yet
2888 * know which buffer this represents, or whether we ought to zero the
2889 * write-offsets, or append. Those are handled in the set() hook.
2891 static struct pipe_stream_output_target
*
2892 iris_create_stream_output_target(struct pipe_context
*ctx
,
2893 struct pipe_resource
*p_res
,
2894 unsigned buffer_offset
,
2895 unsigned buffer_size
)
2897 struct iris_resource
*res
= (void *) p_res
;
2898 struct iris_stream_output_target
*cso
= calloc(1, sizeof(*cso
));
2902 res
->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
2904 pipe_reference_init(&cso
->base
.reference
, 1);
2905 pipe_resource_reference(&cso
->base
.buffer
, p_res
);
2906 cso
->base
.buffer_offset
= buffer_offset
;
2907 cso
->base
.buffer_size
= buffer_size
;
2908 cso
->base
.context
= ctx
;
2910 util_range_add(&res
->valid_buffer_range
, buffer_offset
,
2911 buffer_offset
+ buffer_size
);
2913 upload_state(ctx
->stream_uploader
, &cso
->offset
, sizeof(uint32_t), 4);
2919 iris_stream_output_target_destroy(struct pipe_context
*ctx
,
2920 struct pipe_stream_output_target
*state
)
2922 struct iris_stream_output_target
*cso
= (void *) state
;
2924 pipe_resource_reference(&cso
->base
.buffer
, NULL
);
2925 pipe_resource_reference(&cso
->offset
.res
, NULL
);
2931 * The pipe->set_stream_output_targets() driver hook.
2933 * At this point, we know which targets are bound to a particular index,
2934 * and also whether we want to append or start over. We can finish the
2935 * 3DSTATE_SO_BUFFER packets we started earlier.
2938 iris_set_stream_output_targets(struct pipe_context
*ctx
,
2939 unsigned num_targets
,
2940 struct pipe_stream_output_target
**targets
,
2941 const unsigned *offsets
)
2943 struct iris_context
*ice
= (struct iris_context
*) ctx
;
2944 struct iris_genx_state
*genx
= ice
->state
.genx
;
2945 uint32_t *so_buffers
= genx
->so_buffers
;
2947 const bool active
= num_targets
> 0;
2948 if (ice
->state
.streamout_active
!= active
) {
2949 ice
->state
.streamout_active
= active
;
2950 ice
->state
.dirty
|= IRIS_DIRTY_STREAMOUT
;
2952 /* We only emit 3DSTATE_SO_DECL_LIST when streamout is active, because
2953 * it's a non-pipelined command. If we're switching streamout on, we
2954 * may have missed emitting it earlier, so do so now. (We're already
2955 * taking a stall to update 3DSTATE_SO_BUFFERS anyway...)
2958 ice
->state
.dirty
|= IRIS_DIRTY_SO_DECL_LIST
;
2961 for (int i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
2962 struct iris_stream_output_target
*tgt
=
2963 (void *) ice
->state
.so_target
[i
];
2965 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
2967 flush
|= iris_flush_bits_for_history(res
);
2968 iris_dirty_for_history(ice
, res
);
2971 iris_emit_pipe_control_flush(&ice
->batches
[IRIS_BATCH_RENDER
], flush
);
2975 for (int i
= 0; i
< 4; i
++) {
2976 pipe_so_target_reference(&ice
->state
.so_target
[i
],
2977 i
< num_targets
? targets
[i
] : NULL
);
2980 /* No need to update 3DSTATE_SO_BUFFER unless SOL is active. */
2984 for (unsigned i
= 0; i
< 4; i
++,
2985 so_buffers
+= GENX(3DSTATE_SO_BUFFER_length
)) {
2987 if (i
>= num_targets
|| !targets
[i
]) {
2988 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
)
2989 sob
.SOBufferIndex
= i
;
2993 struct iris_stream_output_target
*tgt
= (void *) targets
[i
];
2994 struct iris_resource
*res
= (void *) tgt
->base
.buffer
;
2996 /* Note that offsets[i] will either be 0, causing us to zero
2997 * the value in the buffer, or 0xFFFFFFFF, which happens to mean
2998 * "continue appending at the existing offset."
3000 assert(offsets
[i
] == 0 || offsets
[i
] == 0xFFFFFFFF);
3002 iris_pack_command(GENX(3DSTATE_SO_BUFFER
), so_buffers
, sob
) {
3003 sob
.SurfaceBaseAddress
=
3004 rw_bo(NULL
, res
->bo
->gtt_offset
+ tgt
->base
.buffer_offset
);
3005 sob
.SOBufferEnable
= true;
3006 sob
.StreamOffsetWriteEnable
= true;
3007 sob
.StreamOutputBufferOffsetAddressEnable
= true;
3008 sob
.MOCS
= mocs(res
->bo
);
3010 sob
.SurfaceSize
= MAX2(tgt
->base
.buffer_size
/ 4, 1) - 1;
3012 sob
.SOBufferIndex
= i
;
3013 sob
.StreamOffset
= offsets
[i
];
3014 sob
.StreamOutputBufferOffsetAddress
=
3015 rw_bo(NULL
, iris_resource_bo(tgt
->offset
.res
)->gtt_offset
+
3016 tgt
->offset
.offset
);
3020 ice
->state
.dirty
|= IRIS_DIRTY_SO_BUFFERS
;
3024 * An iris-vtable helper for encoding the 3DSTATE_SO_DECL_LIST and
3025 * 3DSTATE_STREAMOUT packets.
3027 * 3DSTATE_SO_DECL_LIST is a list of shader outputs we want the streamout
3028 * hardware to record. We can create it entirely based on the shader, with
3029 * no dynamic state dependencies.
3031 * 3DSTATE_STREAMOUT is an annoying mix of shader-based information and
3032 * state-based settings. We capture the shader-related ones here, and merge
3033 * the rest in at draw time.
3036 iris_create_so_decl_list(const struct pipe_stream_output_info
*info
,
3037 const struct brw_vue_map
*vue_map
)
3039 struct GENX(SO_DECL
) so_decl
[MAX_VERTEX_STREAMS
][128];
3040 int buffer_mask
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3041 int next_offset
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3042 int decls
[MAX_VERTEX_STREAMS
] = {0, 0, 0, 0};
3044 STATIC_ASSERT(ARRAY_SIZE(so_decl
[0]) >= MAX_PROGRAM_OUTPUTS
);
3046 memset(so_decl
, 0, sizeof(so_decl
));
3048 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3049 * command feels strange -- each dword pair contains a SO_DECL per stream.
3051 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
3052 const struct pipe_stream_output
*output
= &info
->output
[i
];
3053 const int buffer
= output
->output_buffer
;
3054 const int varying
= output
->register_index
;
3055 const unsigned stream_id
= output
->stream
;
3056 assert(stream_id
< MAX_VERTEX_STREAMS
);
3058 buffer_mask
[stream_id
] |= 1 << buffer
;
3060 assert(vue_map
->varying_to_slot
[varying
] >= 0);
3062 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3063 * array. Instead, it simply increments DstOffset for the following
3064 * input by the number of components that should be skipped.
3066 * Our hardware is unusual in that it requires us to program SO_DECLs
3067 * for fake "hole" components, rather than simply taking the offset
3068 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3069 * program as many size = 4 holes as we can, then a final hole to
3070 * accommodate the final 1, 2, or 3 remaining.
3072 int skip_components
= output
->dst_offset
- next_offset
[buffer
];
3074 while (skip_components
> 0) {
3075 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3077 .OutputBufferSlot
= output
->output_buffer
,
3078 .ComponentMask
= (1 << MIN2(skip_components
, 4)) - 1,
3080 skip_components
-= 4;
3083 next_offset
[buffer
] = output
->dst_offset
+ output
->num_components
;
3085 so_decl
[stream_id
][decls
[stream_id
]++] = (struct GENX(SO_DECL
)) {
3086 .OutputBufferSlot
= output
->output_buffer
,
3087 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
3089 ((1 << output
->num_components
) - 1) << output
->start_component
,
3092 if (decls
[stream_id
] > max_decls
)
3093 max_decls
= decls
[stream_id
];
3096 unsigned dwords
= GENX(3DSTATE_STREAMOUT_length
) + (3 + 2 * max_decls
);
3097 uint32_t *map
= ralloc_size(NULL
, sizeof(uint32_t) * dwords
);
3098 uint32_t *so_decl_map
= map
+ GENX(3DSTATE_STREAMOUT_length
);
3100 iris_pack_command(GENX(3DSTATE_STREAMOUT
), map
, sol
) {
3101 int urb_entry_read_offset
= 0;
3102 int urb_entry_read_length
= (vue_map
->num_slots
+ 1) / 2 -
3103 urb_entry_read_offset
;
3105 /* We always read the whole vertex. This could be reduced at some
3106 * point by reading less and offsetting the register index in the
3109 sol
.Stream0VertexReadOffset
= urb_entry_read_offset
;
3110 sol
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
3111 sol
.Stream1VertexReadOffset
= urb_entry_read_offset
;
3112 sol
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
3113 sol
.Stream2VertexReadOffset
= urb_entry_read_offset
;
3114 sol
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
3115 sol
.Stream3VertexReadOffset
= urb_entry_read_offset
;
3116 sol
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
3118 /* Set buffer pitches; 0 means unbound. */
3119 sol
.Buffer0SurfacePitch
= 4 * info
->stride
[0];
3120 sol
.Buffer1SurfacePitch
= 4 * info
->stride
[1];
3121 sol
.Buffer2SurfacePitch
= 4 * info
->stride
[2];
3122 sol
.Buffer3SurfacePitch
= 4 * info
->stride
[3];
3125 iris_pack_command(GENX(3DSTATE_SO_DECL_LIST
), so_decl_map
, list
) {
3126 list
.DWordLength
= 3 + 2 * max_decls
- 2;
3127 list
.StreamtoBufferSelects0
= buffer_mask
[0];
3128 list
.StreamtoBufferSelects1
= buffer_mask
[1];
3129 list
.StreamtoBufferSelects2
= buffer_mask
[2];
3130 list
.StreamtoBufferSelects3
= buffer_mask
[3];
3131 list
.NumEntries0
= decls
[0];
3132 list
.NumEntries1
= decls
[1];
3133 list
.NumEntries2
= decls
[2];
3134 list
.NumEntries3
= decls
[3];
3137 for (int i
= 0; i
< max_decls
; i
++) {
3138 iris_pack_state(GENX(SO_DECL_ENTRY
), so_decl_map
+ 3 + i
* 2, entry
) {
3139 entry
.Stream0Decl
= so_decl
[0][i
];
3140 entry
.Stream1Decl
= so_decl
[1][i
];
3141 entry
.Stream2Decl
= so_decl
[2][i
];
3142 entry
.Stream3Decl
= so_decl
[3][i
];
3150 iris_compute_sbe_urb_read_interval(uint64_t fs_input_slots
,
3151 const struct brw_vue_map
*last_vue_map
,
3152 bool two_sided_color
,
3153 unsigned *out_offset
,
3154 unsigned *out_length
)
3156 /* The compiler computes the first URB slot without considering COL/BFC
3157 * swizzling (because it doesn't know whether it's enabled), so we need
3158 * to do that here too. This may result in a smaller offset, which
3161 const unsigned first_slot
=
3162 brw_compute_first_urb_slot_required(fs_input_slots
, last_vue_map
);
3164 /* This becomes the URB read offset (counted in pairs of slots). */
3165 assert(first_slot
% 2 == 0);
3166 *out_offset
= first_slot
/ 2;
3168 /* We need to adjust the inputs read to account for front/back color
3169 * swizzling, as it can make the URB length longer.
3171 for (int c
= 0; c
<= 1; c
++) {
3172 if (fs_input_slots
& (VARYING_BIT_COL0
<< c
)) {
3173 /* If two sided color is enabled, the fragment shader's gl_Color
3174 * (COL0) input comes from either the gl_FrontColor (COL0) or
3175 * gl_BackColor (BFC0) input varyings. Mark BFC as used, too.
3177 if (two_sided_color
)
3178 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3180 /* If front color isn't written, we opt to give them back color
3181 * instead of an undefined value. Switch from COL to BFC.
3183 if (last_vue_map
->varying_to_slot
[VARYING_SLOT_COL0
+ c
] == -1) {
3184 fs_input_slots
&= ~(VARYING_BIT_COL0
<< c
);
3185 fs_input_slots
|= (VARYING_BIT_BFC0
<< c
);
3190 /* Compute the minimum URB Read Length necessary for the FS inputs.
3192 * From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
3193 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
3195 * "This field should be set to the minimum length required to read the
3196 * maximum source attribute. The maximum source attribute is indicated
3197 * by the maximum value of the enabled Attribute # Source Attribute if
3198 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
3199 * enable is not set.
3200 * read_length = ceiling((max_source_attr + 1) / 2)
3202 * [errata] Corruption/Hang possible if length programmed larger than
3205 * Similar text exists for Ivy Bridge.
3207 * We find the last URB slot that's actually read by the FS.
3209 unsigned last_read_slot
= last_vue_map
->num_slots
- 1;
3210 while (last_read_slot
> first_slot
&& !(fs_input_slots
&
3211 (1ull << last_vue_map
->slot_to_varying
[last_read_slot
])))
3214 /* The URB read length is the difference of the two, counted in pairs. */
3215 *out_length
= DIV_ROUND_UP(last_read_slot
- first_slot
+ 1, 2);
3219 iris_emit_sbe_swiz(struct iris_batch
*batch
,
3220 const struct iris_context
*ice
,
3221 unsigned urb_read_offset
,
3222 unsigned sprite_coord_enables
)
3224 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) attr_overrides
[16] = {};
3225 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3226 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3227 const struct brw_vue_map
*vue_map
= ice
->shaders
.last_vue_map
;
3228 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3230 /* XXX: this should be generated when putting programs in place */
3232 for (int fs_attr
= 0; fs_attr
< VARYING_SLOT_MAX
; fs_attr
++) {
3233 const int input_index
= wm_prog_data
->urb_setup
[fs_attr
];
3234 if (input_index
< 0 || input_index
>= 16)
3237 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL
) *attr
=
3238 &attr_overrides
[input_index
];
3239 int slot
= vue_map
->varying_to_slot
[fs_attr
];
3241 /* Viewport and Layer are stored in the VUE header. We need to override
3242 * them to zero if earlier stages didn't write them, as GL requires that
3243 * they read back as zero when not explicitly set.
3246 case VARYING_SLOT_VIEWPORT
:
3247 case VARYING_SLOT_LAYER
:
3248 attr
->ComponentOverrideX
= true;
3249 attr
->ComponentOverrideW
= true;
3250 attr
->ConstantSource
= CONST_0000
;
3252 if (!(vue_map
->slots_valid
& VARYING_BIT_LAYER
))
3253 attr
->ComponentOverrideY
= true;
3254 if (!(vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
))
3255 attr
->ComponentOverrideZ
= true;
3258 case VARYING_SLOT_PRIMITIVE_ID
:
3259 /* Override if the previous shader stage didn't write gl_PrimitiveID. */
3261 attr
->ComponentOverrideX
= true;
3262 attr
->ComponentOverrideY
= true;
3263 attr
->ComponentOverrideZ
= true;
3264 attr
->ComponentOverrideW
= true;
3265 attr
->ConstantSource
= PRIM_ID
;
3273 if (sprite_coord_enables
& (1 << input_index
))
3276 /* If there was only a back color written but not front, use back
3277 * as the color instead of undefined.
3279 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL0
)
3280 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC0
];
3281 if (slot
== -1 && fs_attr
== VARYING_SLOT_COL1
)
3282 slot
= vue_map
->varying_to_slot
[VARYING_SLOT_BFC1
];
3284 /* Not written by the previous stage - undefined. */
3286 attr
->ComponentOverrideX
= true;
3287 attr
->ComponentOverrideY
= true;
3288 attr
->ComponentOverrideZ
= true;
3289 attr
->ComponentOverrideW
= true;
3290 attr
->ConstantSource
= CONST_0001_FLOAT
;
3294 /* Compute the location of the attribute relative to the read offset,
3295 * which is counted in 256-bit increments (two 128-bit VUE slots).
3297 const int source_attr
= slot
- 2 * urb_read_offset
;
3298 assert(source_attr
>= 0 && source_attr
<= 32);
3299 attr
->SourceAttribute
= source_attr
;
3301 /* If we are doing two-sided color, and the VUE slot following this one
3302 * represents a back-facing color, then we need to instruct the SF unit
3303 * to do back-facing swizzling.
3305 if (cso_rast
->light_twoside
&&
3306 ((vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL0
&&
3307 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC0
) ||
3308 (vue_map
->slot_to_varying
[slot
] == VARYING_SLOT_COL1
&&
3309 vue_map
->slot_to_varying
[slot
+1] == VARYING_SLOT_BFC1
)))
3310 attr
->SwizzleSelect
= INPUTATTR_FACING
;
3313 iris_emit_cmd(batch
, GENX(3DSTATE_SBE_SWIZ
), sbes
) {
3314 for (int i
= 0; i
< 16; i
++)
3315 sbes
.Attribute
[i
] = attr_overrides
[i
];
3320 iris_calculate_point_sprite_overrides(const struct brw_wm_prog_data
*prog_data
,
3321 const struct iris_rasterizer_state
*cso
)
3323 unsigned overrides
= 0;
3325 if (prog_data
->urb_setup
[VARYING_SLOT_PNTC
] != -1)
3326 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_PNTC
];
3328 for (int i
= 0; i
< 8; i
++) {
3329 if ((cso
->sprite_coord_enable
& (1 << i
)) &&
3330 prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
] != -1)
3331 overrides
|= 1 << prog_data
->urb_setup
[VARYING_SLOT_TEX0
+ i
];
3338 iris_emit_sbe(struct iris_batch
*batch
, const struct iris_context
*ice
)
3340 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3341 const struct brw_wm_prog_data
*wm_prog_data
= (void *)
3342 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
3343 const struct shader_info
*fs_info
=
3344 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
3346 unsigned urb_read_offset
, urb_read_length
;
3347 iris_compute_sbe_urb_read_interval(fs_info
->inputs_read
,
3348 ice
->shaders
.last_vue_map
,
3349 cso_rast
->light_twoside
,
3350 &urb_read_offset
, &urb_read_length
);
3352 unsigned sprite_coord_overrides
=
3353 iris_calculate_point_sprite_overrides(wm_prog_data
, cso_rast
);
3355 iris_emit_cmd(batch
, GENX(3DSTATE_SBE
), sbe
) {
3356 sbe
.AttributeSwizzleEnable
= true;
3357 sbe
.NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
;
3358 sbe
.PointSpriteTextureCoordinateOrigin
= cso_rast
->sprite_coord_mode
;
3359 sbe
.VertexURBEntryReadOffset
= urb_read_offset
;
3360 sbe
.VertexURBEntryReadLength
= urb_read_length
;
3361 sbe
.ForceVertexURBEntryReadOffset
= true;
3362 sbe
.ForceVertexURBEntryReadLength
= true;
3363 sbe
.ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
;
3364 sbe
.PointSpriteTextureCoordinateEnable
= sprite_coord_overrides
;
3366 for (int i
= 0; i
< 32; i
++) {
3367 sbe
.AttributeActiveComponentFormat
[i
] = ACTIVE_COMPONENT_XYZW
;
3372 iris_emit_sbe_swiz(batch
, ice
, urb_read_offset
, sprite_coord_overrides
);
3375 /* ------------------------------------------------------------------- */
3378 * Populate VS program key fields based on the current state.
3381 iris_populate_vs_key(const struct iris_context
*ice
,
3382 const struct shader_info
*info
,
3383 struct brw_vs_prog_key
*key
)
3385 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
3387 if (info
->clip_distance_array_size
== 0 &&
3388 (info
->outputs_written
& (VARYING_BIT_POS
| VARYING_BIT_CLIP_VERTEX
)))
3389 key
->nr_userclip_plane_consts
= cso_rast
->num_clip_plane_consts
;
3393 * Populate TCS program key fields based on the current state.
3396 iris_populate_tcs_key(const struct iris_context
*ice
,
3397 struct brw_tcs_prog_key
*key
)
3402 * Populate TES program key fields based on the current state.
3405 iris_populate_tes_key(const struct iris_context
*ice
,
3406 struct brw_tes_prog_key
*key
)
3411 * Populate GS program key fields based on the current state.
3414 iris_populate_gs_key(const struct iris_context
*ice
,
3415 struct brw_gs_prog_key
*key
)
3420 * Populate FS program key fields based on the current state.
3423 iris_populate_fs_key(const struct iris_context
*ice
,
3424 struct brw_wm_prog_key
*key
)
3426 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3427 const struct pipe_framebuffer_state
*fb
= &ice
->state
.framebuffer
;
3428 const struct iris_depth_stencil_alpha_state
*zsa
= ice
->state
.cso_zsa
;
3429 const struct iris_rasterizer_state
*rast
= ice
->state
.cso_rast
;
3430 const struct iris_blend_state
*blend
= ice
->state
.cso_blend
;
3432 key
->nr_color_regions
= fb
->nr_cbufs
;
3434 key
->clamp_fragment_color
= rast
->clamp_fragment_color
;
3436 key
->alpha_to_coverage
= blend
->alpha_to_coverage
;
3438 key
->alpha_test_replicate_alpha
= fb
->nr_cbufs
> 1 && zsa
->alpha
.enabled
;
3440 /* XXX: only bother if COL0/1 are read */
3441 key
->flat_shade
= rast
->flatshade
;
3443 key
->persample_interp
= rast
->force_persample_interp
;
3444 key
->multisample_fbo
= rast
->multisample
&& fb
->samples
> 1;
3446 key
->coherent_fb_fetch
= true;
3448 key
->force_dual_color_blend
=
3449 screen
->driconf
.dual_color_blend_by_location
&&
3450 (blend
->blend_enables
& 1) && blend
->dual_color_blending
;
3452 /* TODO: support key->force_dual_color_blend for Unigine */
3453 /* TODO: Respect glHint for key->high_quality_derivatives */
3457 iris_populate_cs_key(const struct iris_context
*ice
,
3458 struct brw_cs_prog_key
*key
)
3463 KSP(const struct iris_compiled_shader
*shader
)
3465 struct iris_resource
*res
= (void *) shader
->assembly
.res
;
3466 return iris_bo_offset_from_base_address(res
->bo
) + shader
->assembly
.offset
;
3469 /* Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
3470 * prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
3471 * this WA on C0 stepping.
3473 * TODO: Fill out SamplerCount for prefetching?
3476 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
3477 pkt.KernelStartPointer = KSP(shader); \
3478 pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
3479 prog_data->binding_table.size_bytes / 4; \
3480 pkt.FloatingPointMode = prog_data->use_alt_mode; \
3482 pkt.DispatchGRFStartRegisterForURBData = \
3483 prog_data->dispatch_grf_start_reg; \
3484 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
3485 pkt.prefix##URBEntryReadOffset = 0; \
3487 pkt.StatisticsEnable = true; \
3488 pkt.Enable = true; \
3490 if (prog_data->total_scratch) { \
3491 struct iris_bo *bo = \
3492 iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
3493 uint32_t scratch_addr = bo->gtt_offset; \
3494 pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
3495 pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
3499 * Encode most of 3DSTATE_VS based on the compiled shader.
3502 iris_store_vs_state(struct iris_context
*ice
,
3503 const struct gen_device_info
*devinfo
,
3504 struct iris_compiled_shader
*shader
)
3506 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3507 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3509 iris_pack_command(GENX(3DSTATE_VS
), shader
->derived_data
, vs
) {
3510 INIT_THREAD_DISPATCH_FIELDS(vs
, Vertex
, MESA_SHADER_VERTEX
);
3511 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
3512 vs
.SIMD8DispatchEnable
= true;
3513 vs
.UserClipDistanceCullTestEnableBitmask
=
3514 vue_prog_data
->cull_distance_mask
;
3519 * Encode most of 3DSTATE_HS based on the compiled shader.
3522 iris_store_tcs_state(struct iris_context
*ice
,
3523 const struct gen_device_info
*devinfo
,
3524 struct iris_compiled_shader
*shader
)
3526 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3527 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3528 struct brw_tcs_prog_data
*tcs_prog_data
= (void *) prog_data
;
3530 iris_pack_command(GENX(3DSTATE_HS
), shader
->derived_data
, hs
) {
3531 INIT_THREAD_DISPATCH_FIELDS(hs
, Vertex
, MESA_SHADER_TESS_CTRL
);
3533 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
3534 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
3535 hs
.IncludeVertexHandles
= true;
3540 * Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
3543 iris_store_tes_state(struct iris_context
*ice
,
3544 const struct gen_device_info
*devinfo
,
3545 struct iris_compiled_shader
*shader
)
3547 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3548 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3549 struct brw_tes_prog_data
*tes_prog_data
= (void *) prog_data
;
3551 uint32_t *te_state
= (void *) shader
->derived_data
;
3552 uint32_t *ds_state
= te_state
+ GENX(3DSTATE_TE_length
);
3554 iris_pack_command(GENX(3DSTATE_TE
), te_state
, te
) {
3555 te
.Partitioning
= tes_prog_data
->partitioning
;
3556 te
.OutputTopology
= tes_prog_data
->output_topology
;
3557 te
.TEDomain
= tes_prog_data
->domain
;
3559 te
.MaximumTessellationFactorOdd
= 63.0;
3560 te
.MaximumTessellationFactorNotOdd
= 64.0;
3563 iris_pack_command(GENX(3DSTATE_DS
), ds_state
, ds
) {
3564 INIT_THREAD_DISPATCH_FIELDS(ds
, Patch
, MESA_SHADER_TESS_EVAL
);
3566 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
3567 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
3568 ds
.ComputeWCoordinateEnable
=
3569 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
3571 ds
.UserClipDistanceCullTestEnableBitmask
=
3572 vue_prog_data
->cull_distance_mask
;
3578 * Encode most of 3DSTATE_GS based on the compiled shader.
3581 iris_store_gs_state(struct iris_context
*ice
,
3582 const struct gen_device_info
*devinfo
,
3583 struct iris_compiled_shader
*shader
)
3585 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3586 struct brw_vue_prog_data
*vue_prog_data
= (void *) prog_data
;
3587 struct brw_gs_prog_data
*gs_prog_data
= (void *) prog_data
;
3589 iris_pack_command(GENX(3DSTATE_GS
), shader
->derived_data
, gs
) {
3590 INIT_THREAD_DISPATCH_FIELDS(gs
, Vertex
, MESA_SHADER_GEOMETRY
);
3592 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
3593 gs
.OutputTopology
= gs_prog_data
->output_topology
;
3594 gs
.ControlDataHeaderSize
=
3595 gs_prog_data
->control_data_header_size_hwords
;
3596 gs
.InstanceControl
= gs_prog_data
->invocations
- 1;
3597 gs
.DispatchMode
= DISPATCH_MODE_SIMD8
;
3598 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
3599 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
3600 gs
.ReorderMode
= TRAILING
;
3601 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
3602 gs
.MaximumNumberofThreads
=
3603 GEN_GEN
== 8 ? (devinfo
->max_gs_threads
/ 2 - 1)
3604 : (devinfo
->max_gs_threads
- 1);
3606 if (gs_prog_data
->static_vertex_count
!= -1) {
3607 gs
.StaticOutput
= true;
3608 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
;
3610 gs
.IncludeVertexHandles
= vue_prog_data
->include_vue_handles
;
3612 gs
.UserClipDistanceCullTestEnableBitmask
=
3613 vue_prog_data
->cull_distance_mask
;
3615 const int urb_entry_write_offset
= 1;
3616 const uint32_t urb_entry_output_length
=
3617 DIV_ROUND_UP(vue_prog_data
->vue_map
.num_slots
, 2) -
3618 urb_entry_write_offset
;
3620 gs
.VertexURBEntryOutputReadOffset
= urb_entry_write_offset
;
3621 gs
.VertexURBEntryOutputLength
= MAX2(urb_entry_output_length
, 1);
3626 * Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
3629 iris_store_fs_state(struct iris_context
*ice
,
3630 const struct gen_device_info
*devinfo
,
3631 struct iris_compiled_shader
*shader
)
3633 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3634 struct brw_wm_prog_data
*wm_prog_data
= (void *) shader
->prog_data
;
3636 uint32_t *ps_state
= (void *) shader
->derived_data
;
3637 uint32_t *psx_state
= ps_state
+ GENX(3DSTATE_PS_length
);
3639 iris_pack_command(GENX(3DSTATE_PS
), ps_state
, ps
) {
3640 ps
.VectorMaskEnable
= true;
3641 // XXX: WABTPPrefetchDisable, see above, drop at C0
3642 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 :
3643 prog_data
->binding_table
.size_bytes
/ 4;
3644 ps
.FloatingPointMode
= prog_data
->use_alt_mode
;
3645 ps
.MaximumNumberofThreadsPerPSD
= 64 - (GEN_GEN
== 8 ? 2 : 1);
3647 ps
.PushConstantEnable
= prog_data
->ubo_ranges
[0].length
> 0;
3649 /* From the documentation for this packet:
3650 * "If the PS kernel does not need the Position XY Offsets to
3651 * compute a Position Value, then this field should be programmed
3652 * to POSOFFSET_NONE."
3654 * "SW Recommendation: If the PS kernel needs the Position Offsets
3655 * to compute a Position XY value, this field should match Position
3656 * ZW Interpolation Mode to ensure a consistent position.xyzw
3659 * We only require XY sample offsets. So, this recommendation doesn't
3660 * look useful at the moment. We might need this in future.
3662 ps
.PositionXYOffsetSelect
=
3663 wm_prog_data
->uses_pos_offset
? POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
3664 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
3665 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
3666 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
3668 // XXX: Disable SIMD32 with 16x MSAA
3670 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
3671 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
3672 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
3673 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
3674 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
3675 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
3677 ps
.KernelStartPointer0
=
3678 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
3679 ps
.KernelStartPointer1
=
3680 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
3681 ps
.KernelStartPointer2
=
3682 KSP(shader
) + brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
3684 if (prog_data
->total_scratch
) {
3685 struct iris_bo
*bo
=
3686 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
3687 MESA_SHADER_FRAGMENT
);
3688 uint32_t scratch_addr
= bo
->gtt_offset
;
3689 ps
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
3690 ps
.ScratchSpaceBasePointer
= rw_bo(NULL
, scratch_addr
);
3694 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), psx_state
, psx
) {
3695 psx
.PixelShaderValid
= true;
3696 psx
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
3697 psx
.PixelShaderKillsPixel
= wm_prog_data
->uses_kill
;
3698 psx
.AttributeEnable
= wm_prog_data
->num_varying_inputs
!= 0;
3699 psx
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
3700 psx
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
3701 psx
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
3702 psx
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
3705 psx
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
3706 psx
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
3708 psx
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
3715 * Compute the size of the derived data (shader command packets).
3717 * This must match the data written by the iris_store_xs_state() functions.
3720 iris_store_cs_state(struct iris_context
*ice
,
3721 const struct gen_device_info
*devinfo
,
3722 struct iris_compiled_shader
*shader
)
3724 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
3725 struct brw_cs_prog_data
*cs_prog_data
= (void *) shader
->prog_data
;
3726 void *map
= shader
->derived_data
;
3728 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), map
, desc
) {
3729 desc
.KernelStartPointer
= KSP(shader
);
3730 desc
.ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
;
3731 desc
.NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
;
3732 desc
.SharedLocalMemorySize
=
3733 encode_slm_size(GEN_GEN
, prog_data
->total_shared
);
3734 desc
.BarrierEnable
= cs_prog_data
->uses_barrier
;
3735 desc
.CrossThreadConstantDataReadLength
=
3736 cs_prog_data
->push
.cross_thread
.regs
;
3741 iris_derived_program_state_size(enum iris_program_cache_id cache_id
)
3743 assert(cache_id
<= IRIS_CACHE_BLORP
);
3745 static const unsigned dwords
[] = {
3746 [IRIS_CACHE_VS
] = GENX(3DSTATE_VS_length
),
3747 [IRIS_CACHE_TCS
] = GENX(3DSTATE_HS_length
),
3748 [IRIS_CACHE_TES
] = GENX(3DSTATE_TE_length
) + GENX(3DSTATE_DS_length
),
3749 [IRIS_CACHE_GS
] = GENX(3DSTATE_GS_length
),
3751 GENX(3DSTATE_PS_length
) + GENX(3DSTATE_PS_EXTRA_length
),
3752 [IRIS_CACHE_CS
] = GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3753 [IRIS_CACHE_BLORP
] = 0,
3756 return sizeof(uint32_t) * dwords
[cache_id
];
3760 * Create any state packets corresponding to the given shader stage
3761 * (i.e. 3DSTATE_VS) and save them as "derived data" in the shader variant.
3762 * This means that we can look up a program in the in-memory cache and
3763 * get most of the state packet without having to reconstruct it.
3766 iris_store_derived_program_state(struct iris_context
*ice
,
3767 enum iris_program_cache_id cache_id
,
3768 struct iris_compiled_shader
*shader
)
3770 struct iris_screen
*screen
= (void *) ice
->ctx
.screen
;
3771 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3775 iris_store_vs_state(ice
, devinfo
, shader
);
3777 case IRIS_CACHE_TCS
:
3778 iris_store_tcs_state(ice
, devinfo
, shader
);
3780 case IRIS_CACHE_TES
:
3781 iris_store_tes_state(ice
, devinfo
, shader
);
3784 iris_store_gs_state(ice
, devinfo
, shader
);
3787 iris_store_fs_state(ice
, devinfo
, shader
);
3790 iris_store_cs_state(ice
, devinfo
, shader
);
3791 case IRIS_CACHE_BLORP
:
3798 /* ------------------------------------------------------------------- */
3800 static const uint32_t push_constant_opcodes
[] = {
3801 [MESA_SHADER_VERTEX
] = 21,
3802 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3803 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3804 [MESA_SHADER_GEOMETRY
] = 22,
3805 [MESA_SHADER_FRAGMENT
] = 23,
3806 [MESA_SHADER_COMPUTE
] = 0,
3810 use_null_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3812 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.unbound_tex
.res
);
3814 iris_use_pinned_bo(batch
, state_bo
, false);
3816 return ice
->state
.unbound_tex
.offset
;
3820 use_null_fb_surface(struct iris_batch
*batch
, struct iris_context
*ice
)
3822 /* If set_framebuffer_state() was never called, fall back to 1x1x1 */
3823 if (!ice
->state
.null_fb
.res
)
3824 return use_null_surface(batch
, ice
);
3826 struct iris_bo
*state_bo
= iris_resource_bo(ice
->state
.null_fb
.res
);
3828 iris_use_pinned_bo(batch
, state_bo
, false);
3830 return ice
->state
.null_fb
.offset
;
3834 surf_state_offset_for_aux(struct iris_resource
*res
,
3836 enum isl_aux_usage aux_usage
)
3838 return SURFACE_STATE_ALIGNMENT
*
3839 util_bitcount(res
->aux
.possible_usages
& ((1 << aux_usage
) - 1));
3843 surf_state_update_clear_value(struct iris_batch
*batch
,
3844 struct iris_resource
*res
,
3845 struct iris_state_ref
*state
,
3847 enum isl_aux_usage aux_usage
)
3849 struct isl_device
*isl_dev
= &batch
->screen
->isl_dev
;
3850 struct iris_bo
*state_bo
= iris_resource_bo(state
->res
);
3851 uint64_t real_offset
= state
->offset
+
3852 IRIS_MEMZONE_BINDER_START
;
3853 uint32_t offset_into_bo
= real_offset
- state_bo
->gtt_offset
;
3854 uint32_t clear_offset
= offset_into_bo
+
3855 isl_dev
->ss
.clear_value_offset
+
3856 surf_state_offset_for_aux(res
, aux_modes
, aux_usage
);
3858 batch
->vtbl
->copy_mem_mem(batch
, state_bo
, clear_offset
,
3859 res
->aux
.clear_color_bo
,
3860 res
->aux
.clear_color_offset
,
3861 isl_dev
->ss
.clear_value_size
);
3865 update_clear_value(struct iris_context
*ice
,
3866 struct iris_batch
*batch
,
3867 struct iris_resource
*res
,
3868 struct iris_state_ref
*state
,
3870 struct isl_view
*view
)
3872 struct iris_screen
*screen
= batch
->screen
;
3873 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
3875 /* We only need to update the clear color in the surface state for gen8 and
3876 * gen9. Newer gens can read it directly from the clear color state buffer.
3878 if (devinfo
->gen
> 9)
3881 if (devinfo
->gen
== 9) {
3882 /* Skip updating the ISL_AUX_USAGE_NONE surface state */
3883 aux_modes
&= ~(1 << ISL_AUX_USAGE_NONE
);
3886 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
3888 surf_state_update_clear_value(batch
, res
, state
, aux_modes
,
3891 } else if (devinfo
->gen
== 8) {
3892 pipe_resource_reference(&state
->res
, NULL
);
3893 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
3894 state
, res
->aux
.possible_usages
);
3896 enum isl_aux_usage aux_usage
= u_bit_scan(&aux_modes
);
3897 fill_surface_state(&screen
->isl_dev
, map
, res
, view
, aux_usage
);
3898 map
+= SURFACE_STATE_ALIGNMENT
;
3904 * Add a surface to the validation list, as well as the buffer containing
3905 * the corresponding SURFACE_STATE.
3907 * Returns the binding table entry (offset to SURFACE_STATE).
3910 use_surface(struct iris_context
*ice
,
3911 struct iris_batch
*batch
,
3912 struct pipe_surface
*p_surf
,
3914 enum isl_aux_usage aux_usage
)
3916 struct iris_surface
*surf
= (void *) p_surf
;
3917 struct iris_resource
*res
= (void *) p_surf
->texture
;
3919 iris_use_pinned_bo(batch
, iris_resource_bo(p_surf
->texture
), writeable
);
3920 iris_use_pinned_bo(batch
, iris_resource_bo(surf
->surface_state
.res
), false);
3923 iris_use_pinned_bo(batch
, res
->aux
.bo
, writeable
);
3924 if (res
->aux
.clear_color_bo
)
3925 iris_use_pinned_bo(batch
, res
->aux
.clear_color_bo
, false);
3927 if (memcmp(&res
->aux
.clear_color
, &surf
->clear_color
,
3928 sizeof(surf
->clear_color
)) != 0) {
3929 update_clear_value(ice
, batch
, res
, &surf
->surface_state
,
3930 res
->aux
.possible_usages
, &surf
->view
);
3931 surf
->clear_color
= res
->aux
.clear_color
;
3935 return surf
->surface_state
.offset
+
3936 surf_state_offset_for_aux(res
, res
->aux
.possible_usages
, aux_usage
);
3940 use_sampler_view(struct iris_context
*ice
,
3941 struct iris_batch
*batch
,
3942 struct iris_sampler_view
*isv
)
3945 enum isl_aux_usage aux_usage
=
3946 iris_resource_texture_aux_usage(ice
, isv
->res
, isv
->view
.format
, 0);
3948 iris_use_pinned_bo(batch
, isv
->res
->bo
, false);
3949 iris_use_pinned_bo(batch
, iris_resource_bo(isv
->surface_state
.res
), false);
3951 if (isv
->res
->aux
.bo
) {
3952 iris_use_pinned_bo(batch
, isv
->res
->aux
.bo
, false);
3953 if (isv
->res
->aux
.clear_color_bo
)
3954 iris_use_pinned_bo(batch
, isv
->res
->aux
.clear_color_bo
, false);
3955 if (memcmp(&isv
->res
->aux
.clear_color
, &isv
->clear_color
,
3956 sizeof(isv
->clear_color
)) != 0) {
3957 update_clear_value(ice
, batch
, isv
->res
, &isv
->surface_state
,
3958 isv
->res
->aux
.sampler_usages
, &isv
->view
);
3959 isv
->clear_color
= isv
->res
->aux
.clear_color
;
3963 return isv
->surface_state
.offset
+
3964 surf_state_offset_for_aux(isv
->res
, isv
->res
->aux
.sampler_usages
,
3969 use_ubo_ssbo(struct iris_batch
*batch
,
3970 struct iris_context
*ice
,
3971 struct pipe_shader_buffer
*buf
,
3972 struct iris_state_ref
*surf_state
,
3976 return use_null_surface(batch
, ice
);
3978 iris_use_pinned_bo(batch
, iris_resource_bo(buf
->buffer
), writable
);
3979 iris_use_pinned_bo(batch
, iris_resource_bo(surf_state
->res
), false);
3981 return surf_state
->offset
;
3985 use_image(struct iris_batch
*batch
, struct iris_context
*ice
,
3986 struct iris_shader_state
*shs
, int i
)
3988 struct iris_image_view
*iv
= &shs
->image
[i
];
3989 struct iris_resource
*res
= (void *) iv
->base
.resource
;
3992 return use_null_surface(batch
, ice
);
3994 bool write
= iv
->base
.shader_access
& PIPE_IMAGE_ACCESS_WRITE
;
3996 iris_use_pinned_bo(batch
, res
->bo
, write
);
3997 iris_use_pinned_bo(batch
, iris_resource_bo(iv
->surface_state
.res
), false);
4000 iris_use_pinned_bo(batch
, res
->aux
.bo
, write
);
4002 return iv
->surface_state
.offset
;
4005 #define push_bt_entry(addr) \
4006 assert(addr >= binder_addr); \
4007 assert(s < prog_data->binding_table.size_bytes / sizeof(uint32_t)); \
4008 if (!pin_only) bt_map[s++] = (addr) - binder_addr;
4010 #define bt_assert(section, exists) \
4011 if (!pin_only) assert(prog_data->binding_table.section == \
4012 (exists) ? s : 0xd0d0d0d0)
4015 * Populate the binding table for a given shader stage.
4017 * This fills out the table of pointers to surfaces required by the shader,
4018 * and also adds those buffers to the validation list so the kernel can make
4019 * resident before running our batch.
4022 iris_populate_binding_table(struct iris_context
*ice
,
4023 struct iris_batch
*batch
,
4024 gl_shader_stage stage
,
4027 const struct iris_binder
*binder
= &ice
->state
.binder
;
4028 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4032 UNUSED
struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4033 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4034 uint32_t binder_addr
= binder
->bo
->gtt_offset
;
4036 //struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
4037 uint32_t *bt_map
= binder
->map
+ binder
->bt_offset
[stage
];
4040 const struct shader_info
*info
= iris_get_shader_info(ice
, stage
);
4042 /* TCS passthrough doesn't need a binding table. */
4043 assert(stage
== MESA_SHADER_TESS_CTRL
);
4047 if (stage
== MESA_SHADER_COMPUTE
) {
4048 /* surface for gl_NumWorkGroups */
4049 struct iris_state_ref
*grid_data
= &ice
->state
.grid_size
;
4050 struct iris_state_ref
*grid_state
= &ice
->state
.grid_surf_state
;
4051 iris_use_pinned_bo(batch
, iris_resource_bo(grid_data
->res
), false);
4052 iris_use_pinned_bo(batch
, iris_resource_bo(grid_state
->res
), false);
4053 push_bt_entry(grid_state
->offset
);
4056 if (stage
== MESA_SHADER_FRAGMENT
) {
4057 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4058 /* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
4059 if (cso_fb
->nr_cbufs
) {
4060 for (unsigned i
= 0; i
< cso_fb
->nr_cbufs
; i
++) {
4062 if (cso_fb
->cbufs
[i
]) {
4063 addr
= use_surface(ice
, batch
, cso_fb
->cbufs
[i
], true,
4064 ice
->state
.draw_aux_usage
[i
]);
4066 addr
= use_null_fb_surface(batch
, ice
);
4068 push_bt_entry(addr
);
4071 uint32_t addr
= use_null_fb_surface(batch
, ice
);
4072 push_bt_entry(addr
);
4076 unsigned num_textures
= util_last_bit(info
->textures_used
);
4078 bt_assert(texture_start
, num_textures
> 0);
4080 for (int i
= 0; i
< num_textures
; i
++) {
4081 struct iris_sampler_view
*view
= shs
->textures
[i
];
4082 uint32_t addr
= view
? use_sampler_view(ice
, batch
, view
)
4083 : use_null_surface(batch
, ice
);
4084 push_bt_entry(addr
);
4087 bt_assert(image_start
, info
->num_images
> 0);
4089 for (int i
= 0; i
< info
->num_images
; i
++) {
4090 uint32_t addr
= use_image(batch
, ice
, shs
, i
);
4091 push_bt_entry(addr
);
4094 bt_assert(ubo_start
, shader
->num_cbufs
> 0);
4096 for (int i
= 0; i
< shader
->num_cbufs
; i
++) {
4097 uint32_t addr
= use_ubo_ssbo(batch
, ice
, &shs
->constbuf
[i
],
4098 &shs
->constbuf_surf_state
[i
], false);
4099 push_bt_entry(addr
);
4102 bt_assert(ssbo_start
, info
->num_abos
+ info
->num_ssbos
> 0);
4104 /* XXX: st is wasting 16 binding table slots for ABOs. Should add a cap
4105 * for changing nir_lower_atomics_to_ssbos setting and buffer_base offset
4106 * in st_atom_storagebuf.c so it'll compact them into one range, with
4107 * SSBOs starting at info->num_abos. Ideally it'd reset num_abos to 0 too
4109 if (info
->num_abos
+ info
->num_ssbos
> 0) {
4110 for (int i
= 0; i
< IRIS_MAX_ABOS
+ info
->num_ssbos
; i
++) {
4112 use_ubo_ssbo(batch
, ice
, &shs
->ssbo
[i
], &shs
->ssbo_surf_state
[i
],
4113 shs
->writable_ssbos
& (1u << i
));
4114 push_bt_entry(addr
);
4119 /* XXX: YUV surfaces not implemented yet */
4120 bt_assert(plane_start
[1], ...);
4121 bt_assert(plane_start
[2], ...);
4126 iris_use_optional_res(struct iris_batch
*batch
,
4127 struct pipe_resource
*res
,
4131 struct iris_bo
*bo
= iris_resource_bo(res
);
4132 iris_use_pinned_bo(batch
, bo
, writeable
);
4137 pin_depth_and_stencil_buffers(struct iris_batch
*batch
,
4138 struct pipe_surface
*zsbuf
,
4139 struct iris_depth_stencil_alpha_state
*cso_zsa
)
4144 struct iris_resource
*zres
, *sres
;
4145 iris_get_depth_stencil_resources(zsbuf
->texture
, &zres
, &sres
);
4148 iris_use_pinned_bo(batch
, zres
->bo
, cso_zsa
->depth_writes_enabled
);
4150 iris_use_pinned_bo(batch
, zres
->aux
.bo
,
4151 cso_zsa
->depth_writes_enabled
);
4156 iris_use_pinned_bo(batch
, sres
->bo
, cso_zsa
->stencil_writes_enabled
);
4160 /* ------------------------------------------------------------------- */
4163 * Pin any BOs which were installed by a previous batch, and restored
4164 * via the hardware logical context mechanism.
4166 * We don't need to re-emit all state every batch - the hardware context
4167 * mechanism will save and restore it for us. This includes pointers to
4168 * various BOs...which won't exist unless we ask the kernel to pin them
4169 * by adding them to the validation list.
4171 * We can skip buffers if we've re-emitted those packets, as we're
4172 * overwriting those stale pointers with new ones, and don't actually
4173 * refer to the old BOs.
4176 iris_restore_render_saved_bos(struct iris_context
*ice
,
4177 struct iris_batch
*batch
,
4178 const struct pipe_draw_info
*draw
)
4180 struct iris_genx_state
*genx
= ice
->state
.genx
;
4182 const uint64_t clean
= ~ice
->state
.dirty
;
4184 if (clean
& IRIS_DIRTY_CC_VIEWPORT
) {
4185 iris_use_optional_res(batch
, ice
->state
.last_res
.cc_vp
, false);
4188 if (clean
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4189 iris_use_optional_res(batch
, ice
->state
.last_res
.sf_cl_vp
, false);
4192 if (clean
& IRIS_DIRTY_BLEND_STATE
) {
4193 iris_use_optional_res(batch
, ice
->state
.last_res
.blend
, false);
4196 if (clean
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4197 iris_use_optional_res(batch
, ice
->state
.last_res
.color_calc
, false);
4200 if (clean
& IRIS_DIRTY_SCISSOR_RECT
) {
4201 iris_use_optional_res(batch
, ice
->state
.last_res
.scissor
, false);
4204 if (ice
->state
.streamout_active
&& (clean
& IRIS_DIRTY_SO_BUFFERS
)) {
4205 for (int i
= 0; i
< 4; i
++) {
4206 struct iris_stream_output_target
*tgt
=
4207 (void *) ice
->state
.so_target
[i
];
4209 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4211 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4217 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4218 if (!(clean
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4221 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4222 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4227 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4229 for (int i
= 0; i
< 4; i
++) {
4230 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4232 if (range
->length
== 0)
4235 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4236 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4239 iris_use_pinned_bo(batch
, res
->bo
, false);
4241 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4245 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4246 if (clean
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4247 /* Re-pin any buffers referred to by the binding table. */
4248 iris_populate_binding_table(ice
, batch
, stage
, true);
4252 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4253 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4254 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4256 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4259 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4260 if (clean
& (IRIS_DIRTY_VS
<< stage
)) {
4261 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4264 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4265 iris_use_pinned_bo(batch
, bo
, false);
4267 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4269 if (prog_data
->total_scratch
> 0) {
4270 struct iris_bo
*bo
=
4271 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4272 iris_use_pinned_bo(batch
, bo
, true);
4278 if ((clean
& IRIS_DIRTY_DEPTH_BUFFER
) &&
4279 (clean
& IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
4280 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4281 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
4284 if (draw
->index_size
== 0 && ice
->state
.last_res
.index_buffer
) {
4285 /* This draw didn't emit a new index buffer, so we are inheriting the
4286 * older index buffer. This draw didn't need it, but future ones may.
4288 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
4289 iris_use_pinned_bo(batch
, bo
, false);
4292 if (clean
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4293 uint64_t bound
= ice
->state
.bound_vertex_buffers
;
4295 const int i
= u_bit_scan64(&bound
);
4296 struct pipe_resource
*res
= genx
->vertex_buffers
[i
].resource
;
4297 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4303 iris_restore_compute_saved_bos(struct iris_context
*ice
,
4304 struct iris_batch
*batch
,
4305 const struct pipe_grid_info
*grid
)
4307 const uint64_t clean
= ~ice
->state
.dirty
;
4309 const int stage
= MESA_SHADER_COMPUTE
;
4310 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4312 if (clean
& IRIS_DIRTY_CONSTANTS_CS
) {
4313 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4316 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4317 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[0];
4319 if (range
->length
> 0) {
4320 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4321 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4324 iris_use_pinned_bo(batch
, res
->bo
, false);
4326 iris_use_pinned_bo(batch
, batch
->screen
->workaround_bo
, false);
4331 if (clean
& IRIS_DIRTY_BINDINGS_CS
) {
4332 /* Re-pin any buffers referred to by the binding table. */
4333 iris_populate_binding_table(ice
, batch
, stage
, true);
4336 struct pipe_resource
*sampler_res
= shs
->sampler_table
.res
;
4338 iris_use_pinned_bo(batch
, iris_resource_bo(sampler_res
), false);
4340 if (clean
& IRIS_DIRTY_CS
) {
4341 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4344 struct iris_bo
*bo
= iris_resource_bo(shader
->assembly
.res
);
4345 iris_use_pinned_bo(batch
, bo
, false);
4347 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4349 if (prog_data
->total_scratch
> 0) {
4350 struct iris_bo
*bo
=
4351 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4352 iris_use_pinned_bo(batch
, bo
, true);
4359 * Possibly emit STATE_BASE_ADDRESS to update Surface State Base Address.
4362 iris_update_surface_base_address(struct iris_batch
*batch
,
4363 struct iris_binder
*binder
)
4365 if (batch
->last_surface_base_address
== binder
->bo
->gtt_offset
)
4368 flush_for_state_base_change(batch
);
4370 iris_emit_cmd(batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
4371 sba
.SurfaceStateMOCS
= MOCS_WB
;
4372 sba
.SurfaceStateBaseAddressModifyEnable
= true;
4373 sba
.SurfaceStateBaseAddress
= ro_bo(binder
->bo
, 0);
4376 batch
->last_surface_base_address
= binder
->bo
->gtt_offset
;
4380 iris_upload_dirty_render_state(struct iris_context
*ice
,
4381 struct iris_batch
*batch
,
4382 const struct pipe_draw_info
*draw
)
4384 const uint64_t dirty
= ice
->state
.dirty
;
4386 if (!(dirty
& IRIS_ALL_DIRTY_FOR_RENDER
))
4389 struct iris_genx_state
*genx
= ice
->state
.genx
;
4390 struct iris_binder
*binder
= &ice
->state
.binder
;
4391 struct brw_wm_prog_data
*wm_prog_data
= (void *)
4392 ice
->shaders
.prog
[MESA_SHADER_FRAGMENT
]->prog_data
;
4394 if (dirty
& IRIS_DIRTY_CC_VIEWPORT
) {
4395 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4396 uint32_t cc_vp_address
;
4398 /* XXX: could avoid streaming for depth_clip [0,1] case. */
4399 uint32_t *cc_vp_map
=
4400 stream_state(batch
, ice
->state
.dynamic_uploader
,
4401 &ice
->state
.last_res
.cc_vp
,
4402 4 * ice
->state
.num_viewports
*
4403 GENX(CC_VIEWPORT_length
), 32, &cc_vp_address
);
4404 for (int i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4406 util_viewport_zmin_zmax(&ice
->state
.viewports
[i
],
4407 cso_rast
->clip_halfz
, &zmin
, &zmax
);
4408 if (cso_rast
->depth_clip_near
)
4410 if (cso_rast
->depth_clip_far
)
4413 iris_pack_state(GENX(CC_VIEWPORT
), cc_vp_map
, ccv
) {
4414 ccv
.MinimumDepth
= zmin
;
4415 ccv
.MaximumDepth
= zmax
;
4418 cc_vp_map
+= GENX(CC_VIEWPORT_length
);
4421 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), ptr
) {
4422 ptr
.CCViewportPointer
= cc_vp_address
;
4426 if (dirty
& IRIS_DIRTY_SF_CL_VIEWPORT
) {
4427 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4428 uint32_t sf_cl_vp_address
;
4430 stream_state(batch
, ice
->state
.dynamic_uploader
,
4431 &ice
->state
.last_res
.sf_cl_vp
,
4432 4 * ice
->state
.num_viewports
*
4433 GENX(SF_CLIP_VIEWPORT_length
), 64, &sf_cl_vp_address
);
4435 for (unsigned i
= 0; i
< ice
->state
.num_viewports
; i
++) {
4436 const struct pipe_viewport_state
*state
= &ice
->state
.viewports
[i
];
4437 float gb_xmin
, gb_xmax
, gb_ymin
, gb_ymax
;
4439 float vp_xmin
= viewport_extent(state
, 0, -1.0f
);
4440 float vp_xmax
= viewport_extent(state
, 0, 1.0f
);
4441 float vp_ymin
= viewport_extent(state
, 1, -1.0f
);
4442 float vp_ymax
= viewport_extent(state
, 1, 1.0f
);
4444 calculate_guardband_size(cso_fb
->width
, cso_fb
->height
,
4445 state
->scale
[0], state
->scale
[1],
4446 state
->translate
[0], state
->translate
[1],
4447 &gb_xmin
, &gb_xmax
, &gb_ymin
, &gb_ymax
);
4449 iris_pack_state(GENX(SF_CLIP_VIEWPORT
), vp_map
, vp
) {
4450 vp
.ViewportMatrixElementm00
= state
->scale
[0];
4451 vp
.ViewportMatrixElementm11
= state
->scale
[1];
4452 vp
.ViewportMatrixElementm22
= state
->scale
[2];
4453 vp
.ViewportMatrixElementm30
= state
->translate
[0];
4454 vp
.ViewportMatrixElementm31
= state
->translate
[1];
4455 vp
.ViewportMatrixElementm32
= state
->translate
[2];
4456 vp
.XMinClipGuardband
= gb_xmin
;
4457 vp
.XMaxClipGuardband
= gb_xmax
;
4458 vp
.YMinClipGuardband
= gb_ymin
;
4459 vp
.YMaxClipGuardband
= gb_ymax
;
4460 vp
.XMinViewPort
= MAX2(vp_xmin
, 0);
4461 vp
.XMaxViewPort
= MIN2(vp_xmax
, cso_fb
->width
) - 1;
4462 vp
.YMinViewPort
= MAX2(vp_ymin
, 0);
4463 vp
.YMaxViewPort
= MIN2(vp_ymax
, cso_fb
->height
) - 1;
4466 vp_map
+= GENX(SF_CLIP_VIEWPORT_length
);
4469 iris_emit_cmd(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), ptr
) {
4470 ptr
.SFClipViewportPointer
= sf_cl_vp_address
;
4474 if (dirty
& IRIS_DIRTY_URB
) {
4477 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
4478 if (!ice
->shaders
.prog
[i
]) {
4481 struct brw_vue_prog_data
*vue_prog_data
=
4482 (void *) ice
->shaders
.prog
[i
]->prog_data
;
4483 size
[i
] = vue_prog_data
->urb_entry_size
;
4485 assert(size
[i
] != 0);
4488 genX(emit_urb_setup
)(ice
, batch
, size
,
4489 ice
->shaders
.prog
[MESA_SHADER_TESS_EVAL
] != NULL
,
4490 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
] != NULL
);
4493 if (dirty
& IRIS_DIRTY_BLEND_STATE
) {
4494 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4495 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4496 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4497 const int header_dwords
= GENX(BLEND_STATE_length
);
4499 /* Always write at least one BLEND_STATE - the final RT message will
4500 * reference BLEND_STATE[0] even if there aren't color writes. There
4501 * may still be alpha testing, computed depth, and so on.
4503 const int rt_dwords
=
4504 MAX2(cso_fb
->nr_cbufs
, 1) * GENX(BLEND_STATE_ENTRY_length
);
4506 uint32_t blend_offset
;
4507 uint32_t *blend_map
=
4508 stream_state(batch
, ice
->state
.dynamic_uploader
,
4509 &ice
->state
.last_res
.blend
,
4510 4 * (header_dwords
+ rt_dwords
), 64, &blend_offset
);
4512 uint32_t blend_state_header
;
4513 iris_pack_state(GENX(BLEND_STATE
), &blend_state_header
, bs
) {
4514 bs
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4515 bs
.AlphaTestFunction
= translate_compare_func(cso_zsa
->alpha
.func
);
4518 blend_map
[0] = blend_state_header
| cso_blend
->blend_state
[0];
4519 memcpy(&blend_map
[1], &cso_blend
->blend_state
[1], 4 * rt_dwords
);
4521 iris_emit_cmd(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), ptr
) {
4522 ptr
.BlendStatePointer
= blend_offset
;
4523 ptr
.BlendStatePointerValid
= true;
4527 if (dirty
& IRIS_DIRTY_COLOR_CALC_STATE
) {
4528 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4530 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4534 stream_state(batch
, ice
->state
.dynamic_uploader
,
4535 &ice
->state
.last_res
.color_calc
,
4536 sizeof(uint32_t) * GENX(COLOR_CALC_STATE_length
),
4538 iris_pack_state(GENX(COLOR_CALC_STATE
), cc_map
, cc
) {
4539 cc
.AlphaTestFormat
= ALPHATEST_FLOAT32
;
4540 cc
.AlphaReferenceValueAsFLOAT32
= cso
->alpha
.ref_value
;
4541 cc
.BlendConstantColorRed
= ice
->state
.blend_color
.color
[0];
4542 cc
.BlendConstantColorGreen
= ice
->state
.blend_color
.color
[1];
4543 cc
.BlendConstantColorBlue
= ice
->state
.blend_color
.color
[2];
4544 cc
.BlendConstantColorAlpha
= ice
->state
.blend_color
.color
[3];
4546 cc
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4547 cc
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4550 iris_emit_cmd(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ptr
) {
4551 ptr
.ColorCalcStatePointer
= cc_offset
;
4552 ptr
.ColorCalcStatePointerValid
= true;
4556 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4557 if (!(dirty
& (IRIS_DIRTY_CONSTANTS_VS
<< stage
)))
4560 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4561 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4566 if (shs
->cbuf0_needs_upload
)
4567 upload_uniforms(ice
, stage
);
4569 struct brw_stage_prog_data
*prog_data
= (void *) shader
->prog_data
;
4571 iris_emit_cmd(batch
, GENX(3DSTATE_CONSTANT_VS
), pkt
) {
4572 pkt
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
4574 /* The Skylake PRM contains the following restriction:
4576 * "The driver must ensure The following case does not occur
4577 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
4578 * buffer 3 read length equal to zero committed followed by a
4579 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
4582 * To avoid this, we program the buffers in the highest slots.
4583 * This way, slot 0 is only used if slot 3 is also used.
4587 for (int i
= 3; i
>= 0; i
--) {
4588 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4590 if (range
->length
== 0)
4593 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[range
->block
];
4594 struct iris_resource
*res
= (void *) cbuf
->buffer
;
4596 assert(cbuf
->buffer_offset
% 32 == 0);
4598 pkt
.ConstantBody
.ReadLength
[n
] = range
->length
;
4599 pkt
.ConstantBody
.Buffer
[n
] =
4600 res
? ro_bo(res
->bo
, range
->start
* 32 + cbuf
->buffer_offset
)
4601 : ro_bo(batch
->screen
->workaround_bo
, 0);
4608 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4609 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4610 iris_emit_cmd(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), ptr
) {
4611 ptr
._3DCommandSubOpcode
= 38 + stage
;
4612 ptr
.PointertoVSBindingTable
= binder
->bt_offset
[stage
];
4617 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4618 if (dirty
& (IRIS_DIRTY_BINDINGS_VS
<< stage
)) {
4619 iris_populate_binding_table(ice
, batch
, stage
, false);
4623 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4624 if (!(dirty
& (IRIS_DIRTY_SAMPLER_STATES_VS
<< stage
)) ||
4625 !ice
->shaders
.prog
[stage
])
4628 iris_upload_sampler_states(ice
, stage
);
4630 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
4631 struct pipe_resource
*res
= shs
->sampler_table
.res
;
4633 iris_use_pinned_bo(batch
, iris_resource_bo(res
), false);
4635 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ptr
) {
4636 ptr
._3DCommandSubOpcode
= 43 + stage
;
4637 ptr
.PointertoVSSamplerState
= shs
->sampler_table
.offset
;
4641 if (ice
->state
.need_border_colors
)
4642 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
4644 if (dirty
& IRIS_DIRTY_MULTISAMPLE
) {
4645 iris_emit_cmd(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
4647 ice
->state
.cso_rast
->half_pixel_center
? CENTER
: UL_CORNER
;
4648 if (ice
->state
.framebuffer
.samples
> 0)
4649 ms
.NumberofMultisamples
= ffs(ice
->state
.framebuffer
.samples
) - 1;
4653 if (dirty
& IRIS_DIRTY_SAMPLE_MASK
) {
4654 iris_emit_cmd(batch
, GENX(3DSTATE_SAMPLE_MASK
), ms
) {
4655 ms
.SampleMask
= ice
->state
.sample_mask
;
4659 for (int stage
= 0; stage
<= MESA_SHADER_FRAGMENT
; stage
++) {
4660 if (!(dirty
& (IRIS_DIRTY_VS
<< stage
)))
4663 struct iris_compiled_shader
*shader
= ice
->shaders
.prog
[stage
];
4666 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
4667 struct iris_resource
*cache
= (void *) shader
->assembly
.res
;
4668 iris_use_pinned_bo(batch
, cache
->bo
, false);
4670 if (prog_data
->total_scratch
> 0) {
4671 struct iris_bo
*bo
=
4672 iris_get_scratch_space(ice
, prog_data
->total_scratch
, stage
);
4673 iris_use_pinned_bo(batch
, bo
, true);
4676 if (stage
== MESA_SHADER_FRAGMENT
&& wm_prog_data
->uses_sample_mask
) {
4677 uint32_t psx_state
[GENX(3DSTATE_PS_EXTRA_length
)] = {0};
4678 uint32_t *shader_psx
= ((uint32_t*)shader
->derived_data
) +
4679 GENX(3DSTATE_PS_length
);
4680 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4682 iris_pack_command(GENX(3DSTATE_PS_EXTRA
), &psx_state
, psx
) {
4683 if (wm_prog_data
->post_depth_coverage
)
4684 psx
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
4685 else if (wm_prog_data
->inner_coverage
&& cso
->conservative_rasterization
)
4686 psx
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
4688 psx
.InputCoverageMaskState
= ICMS_NORMAL
;
4691 iris_batch_emit(batch
, shader
->derived_data
,
4692 sizeof(uint32_t) * GENX(3DSTATE_PS_length
));
4693 iris_emit_merge(batch
,
4696 GENX(3DSTATE_PS_EXTRA_length
));
4699 iris_batch_emit(batch
, shader
->derived_data
,
4700 iris_derived_program_state_size(stage
));
4702 if (stage
== MESA_SHADER_TESS_EVAL
) {
4703 iris_emit_cmd(batch
, GENX(3DSTATE_HS
), hs
);
4704 iris_emit_cmd(batch
, GENX(3DSTATE_TE
), te
);
4705 iris_emit_cmd(batch
, GENX(3DSTATE_DS
), ds
);
4706 } else if (stage
== MESA_SHADER_GEOMETRY
) {
4707 iris_emit_cmd(batch
, GENX(3DSTATE_GS
), gs
);
4712 if (ice
->state
.streamout_active
) {
4713 if (dirty
& IRIS_DIRTY_SO_BUFFERS
) {
4714 iris_batch_emit(batch
, genx
->so_buffers
,
4715 4 * 4 * GENX(3DSTATE_SO_BUFFER_length
));
4716 for (int i
= 0; i
< 4; i
++) {
4717 struct iris_stream_output_target
*tgt
=
4718 (void *) ice
->state
.so_target
[i
];
4720 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->base
.buffer
),
4722 iris_use_pinned_bo(batch
, iris_resource_bo(tgt
->offset
.res
),
4728 if ((dirty
& IRIS_DIRTY_SO_DECL_LIST
) && ice
->state
.streamout
) {
4729 uint32_t *decl_list
=
4730 ice
->state
.streamout
+ GENX(3DSTATE_STREAMOUT_length
);
4731 iris_batch_emit(batch
, decl_list
, 4 * ((decl_list
[0] & 0xff) + 2));
4734 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4735 const struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4737 uint32_t dynamic_sol
[GENX(3DSTATE_STREAMOUT_length
)];
4738 iris_pack_command(GENX(3DSTATE_STREAMOUT
), dynamic_sol
, sol
) {
4739 sol
.SOFunctionEnable
= true;
4740 sol
.SOStatisticsEnable
= true;
4742 sol
.RenderingDisable
= cso_rast
->rasterizer_discard
&&
4743 !ice
->state
.prims_generated_query_active
;
4744 sol
.ReorderMode
= cso_rast
->flatshade_first
? LEADING
: TRAILING
;
4747 assert(ice
->state
.streamout
);
4749 iris_emit_merge(batch
, ice
->state
.streamout
, dynamic_sol
,
4750 GENX(3DSTATE_STREAMOUT_length
));
4753 if (dirty
& IRIS_DIRTY_STREAMOUT
) {
4754 iris_emit_cmd(batch
, GENX(3DSTATE_STREAMOUT
), sol
);
4758 if (dirty
& IRIS_DIRTY_CLIP
) {
4759 struct iris_rasterizer_state
*cso_rast
= ice
->state
.cso_rast
;
4760 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4762 uint32_t dynamic_clip
[GENX(3DSTATE_CLIP_length
)];
4763 iris_pack_command(GENX(3DSTATE_CLIP
), &dynamic_clip
, cl
) {
4764 cl
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4765 cl
.ClipMode
= cso_rast
->rasterizer_discard
? CLIPMODE_REJECT_ALL
4767 if (wm_prog_data
->barycentric_interp_modes
&
4768 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
)
4769 cl
.NonPerspectiveBarycentricEnable
= true;
4771 cl
.ForceZeroRTAIndexEnable
= cso_fb
->layers
== 0;
4772 cl
.MaximumVPIndex
= ice
->state
.num_viewports
- 1;
4774 iris_emit_merge(batch
, cso_rast
->clip
, dynamic_clip
,
4775 ARRAY_SIZE(cso_rast
->clip
));
4778 if (dirty
& IRIS_DIRTY_RASTER
) {
4779 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4780 iris_batch_emit(batch
, cso
->raster
, sizeof(cso
->raster
));
4781 iris_batch_emit(batch
, cso
->sf
, sizeof(cso
->sf
));
4785 if (dirty
& IRIS_DIRTY_WM
) {
4786 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4787 uint32_t dynamic_wm
[GENX(3DSTATE_WM_length
)];
4789 iris_pack_command(GENX(3DSTATE_WM
), &dynamic_wm
, wm
) {
4790 wm
.StatisticsEnable
= ice
->state
.statistics_counters_enabled
;
4792 wm
.BarycentricInterpolationMode
=
4793 wm_prog_data
->barycentric_interp_modes
;
4795 if (wm_prog_data
->early_fragment_tests
)
4796 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
4797 else if (wm_prog_data
->has_side_effects
)
4798 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
4800 /* We could skip this bit if color writes are enabled. */
4801 if (wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
)
4802 wm
.ForceThreadDispatchEnable
= ForceON
;
4804 iris_emit_merge(batch
, cso
->wm
, dynamic_wm
, ARRAY_SIZE(cso
->wm
));
4807 if (dirty
& IRIS_DIRTY_SBE
) {
4808 iris_emit_sbe(batch
, ice
);
4811 if (dirty
& IRIS_DIRTY_PS_BLEND
) {
4812 struct iris_blend_state
*cso_blend
= ice
->state
.cso_blend
;
4813 struct iris_depth_stencil_alpha_state
*cso_zsa
= ice
->state
.cso_zsa
;
4814 const struct shader_info
*fs_info
=
4815 iris_get_shader_info(ice
, MESA_SHADER_FRAGMENT
);
4817 uint32_t dynamic_pb
[GENX(3DSTATE_PS_BLEND_length
)];
4818 iris_pack_command(GENX(3DSTATE_PS_BLEND
), &dynamic_pb
, pb
) {
4819 pb
.HasWriteableRT
= has_writeable_rt(cso_blend
, fs_info
);
4820 pb
.AlphaTestEnable
= cso_zsa
->alpha
.enabled
;
4823 iris_emit_merge(batch
, cso_blend
->ps_blend
, dynamic_pb
,
4824 ARRAY_SIZE(cso_blend
->ps_blend
));
4827 if (dirty
& IRIS_DIRTY_WM_DEPTH_STENCIL
) {
4828 struct iris_depth_stencil_alpha_state
*cso
= ice
->state
.cso_zsa
;
4830 struct pipe_stencil_ref
*p_stencil_refs
= &ice
->state
.stencil_ref
;
4831 uint32_t stencil_refs
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
4832 iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL
), &stencil_refs
, wmds
) {
4833 wmds
.StencilReferenceValue
= p_stencil_refs
->ref_value
[0];
4834 wmds
.BackfaceStencilReferenceValue
= p_stencil_refs
->ref_value
[1];
4836 iris_emit_merge(batch
, cso
->wmds
, stencil_refs
, ARRAY_SIZE(cso
->wmds
));
4838 iris_batch_emit(batch
, cso
->wmds
, sizeof(cso
->wmds
));
4842 if (dirty
& IRIS_DIRTY_SCISSOR_RECT
) {
4843 uint32_t scissor_offset
=
4844 emit_state(batch
, ice
->state
.dynamic_uploader
,
4845 &ice
->state
.last_res
.scissor
,
4846 ice
->state
.scissors
,
4847 sizeof(struct pipe_scissor_state
) *
4848 ice
->state
.num_viewports
, 32);
4850 iris_emit_cmd(batch
, GENX(3DSTATE_SCISSOR_STATE_POINTERS
), ptr
) {
4851 ptr
.ScissorRectPointer
= scissor_offset
;
4855 if (dirty
& IRIS_DIRTY_DEPTH_BUFFER
) {
4856 struct iris_depth_buffer_state
*cso_z
= &ice
->state
.genx
->depth_buffer
;
4858 /* Do not emit the clear params yets. We need to update the clear value
4861 uint32_t clear_length
= GENX(3DSTATE_CLEAR_PARAMS_length
) * 4;
4862 uint32_t cso_z_size
= sizeof(cso_z
->packets
) - clear_length
;
4863 iris_batch_emit(batch
, cso_z
->packets
, cso_z_size
);
4865 union isl_color_value clear_value
= { .f32
= { 0, } };
4867 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4868 if (cso_fb
->zsbuf
) {
4869 struct iris_resource
*zres
, *sres
;
4870 iris_get_depth_stencil_resources(cso_fb
->zsbuf
->texture
,
4872 if (zres
&& zres
->aux
.bo
)
4873 clear_value
= iris_resource_get_clear_color(zres
, NULL
, NULL
);
4876 uint32_t clear_params
[GENX(3DSTATE_CLEAR_PARAMS_length
)];
4877 iris_pack_command(GENX(3DSTATE_CLEAR_PARAMS
), clear_params
, clear
) {
4878 clear
.DepthClearValueValid
= true;
4879 clear
.DepthClearValue
= clear_value
.f32
[0];
4881 iris_batch_emit(batch
, clear_params
, clear_length
);
4884 if (dirty
& (IRIS_DIRTY_DEPTH_BUFFER
| IRIS_DIRTY_WM_DEPTH_STENCIL
)) {
4885 /* Listen for buffer changes, and also write enable changes. */
4886 struct pipe_framebuffer_state
*cso_fb
= &ice
->state
.framebuffer
;
4887 pin_depth_and_stencil_buffers(batch
, cso_fb
->zsbuf
, ice
->state
.cso_zsa
);
4890 if (dirty
& IRIS_DIRTY_POLYGON_STIPPLE
) {
4891 iris_emit_cmd(batch
, GENX(3DSTATE_POLY_STIPPLE_PATTERN
), poly
) {
4892 for (int i
= 0; i
< 32; i
++) {
4893 poly
.PatternRow
[i
] = ice
->state
.poly_stipple
.stipple
[i
];
4898 if (dirty
& IRIS_DIRTY_LINE_STIPPLE
) {
4899 struct iris_rasterizer_state
*cso
= ice
->state
.cso_rast
;
4900 iris_batch_emit(batch
, cso
->line_stipple
, sizeof(cso
->line_stipple
));
4903 if (dirty
& IRIS_DIRTY_VF_TOPOLOGY
) {
4904 iris_emit_cmd(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
4905 topo
.PrimitiveTopologyType
=
4906 translate_prim_type(draw
->mode
, draw
->vertices_per_patch
);
4910 if (dirty
& IRIS_DIRTY_VERTEX_BUFFERS
) {
4911 int count
= util_bitcount64(ice
->state
.bound_vertex_buffers
);
4912 int dynamic_bound
= ice
->state
.bound_vertex_buffers
;
4914 if (ice
->state
.vs_uses_draw_params
) {
4915 if (ice
->draw
.draw_params_offset
== 0) {
4916 u_upload_data(ice
->state
.dynamic_uploader
, 0, sizeof(ice
->draw
.params
),
4917 4, &ice
->draw
.params
, &ice
->draw
.draw_params_offset
,
4918 &ice
->draw
.draw_params_res
);
4920 assert(ice
->draw
.draw_params_res
);
4922 struct iris_vertex_buffer_state
*state
=
4923 &(ice
->state
.genx
->vertex_buffers
[count
]);
4924 pipe_resource_reference(&state
->resource
, ice
->draw
.draw_params_res
);
4925 struct iris_resource
*res
= (void *) state
->resource
;
4927 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
4928 vb
.VertexBufferIndex
= count
;
4929 vb
.AddressModifyEnable
= true;
4931 vb
.BufferSize
= res
->bo
->size
- ice
->draw
.draw_params_offset
;
4932 vb
.BufferStartingAddress
=
4933 ro_bo(NULL
, res
->bo
->gtt_offset
+
4934 (int) ice
->draw
.draw_params_offset
);
4935 vb
.MOCS
= mocs(res
->bo
);
4937 dynamic_bound
|= 1ull << count
;
4941 if (ice
->state
.vs_uses_derived_draw_params
) {
4942 u_upload_data(ice
->state
.dynamic_uploader
, 0,
4943 sizeof(ice
->draw
.derived_params
), 4,
4944 &ice
->draw
.derived_params
,
4945 &ice
->draw
.derived_draw_params_offset
,
4946 &ice
->draw
.derived_draw_params_res
);
4948 struct iris_vertex_buffer_state
*state
=
4949 &(ice
->state
.genx
->vertex_buffers
[count
]);
4950 pipe_resource_reference(&state
->resource
,
4951 ice
->draw
.derived_draw_params_res
);
4952 struct iris_resource
*res
= (void *) ice
->draw
.derived_draw_params_res
;
4954 iris_pack_state(GENX(VERTEX_BUFFER_STATE
), state
->state
, vb
) {
4955 vb
.VertexBufferIndex
= count
;
4956 vb
.AddressModifyEnable
= true;
4959 res
->bo
->size
- ice
->draw
.derived_draw_params_offset
;
4960 vb
.BufferStartingAddress
=
4961 ro_bo(NULL
, res
->bo
->gtt_offset
+
4962 (int) ice
->draw
.derived_draw_params_offset
);
4963 vb
.MOCS
= mocs(res
->bo
);
4965 dynamic_bound
|= 1ull << count
;
4970 /* The VF cache designers cut corners, and made the cache key's
4971 * <VertexBufferIndex, Memory Address> tuple only consider the bottom
4972 * 32 bits of the address. If you have two vertex buffers which get
4973 * placed exactly 4 GiB apart and use them in back-to-back draw calls,
4974 * you can get collisions (even within a single batch).
4976 * So, we need to do a VF cache invalidate if the buffer for a VB
4977 * slot slot changes [48:32] address bits from the previous time.
4979 unsigned flush_flags
= 0;
4981 uint64_t bound
= dynamic_bound
;
4983 const int i
= u_bit_scan64(&bound
);
4984 uint16_t high_bits
= 0;
4986 struct iris_resource
*res
=
4987 (void *) genx
->vertex_buffers
[i
].resource
;
4989 iris_use_pinned_bo(batch
, res
->bo
, false);
4991 high_bits
= res
->bo
->gtt_offset
>> 32ull;
4992 if (high_bits
!= ice
->state
.last_vbo_high_bits
[i
]) {
4993 flush_flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
|
4994 PIPE_CONTROL_CS_STALL
;
4995 ice
->state
.last_vbo_high_bits
[i
] = high_bits
;
5001 iris_emit_pipe_control_flush(batch
, flush_flags
);
5003 const unsigned vb_dwords
= GENX(VERTEX_BUFFER_STATE_length
);
5006 iris_get_command_space(batch
, 4 * (1 + vb_dwords
* count
));
5007 _iris_pack_command(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), map
, vb
) {
5008 vb
.DWordLength
= (vb_dwords
* count
+ 1) - 2;
5012 bound
= dynamic_bound
;
5014 const int i
= u_bit_scan64(&bound
);
5015 memcpy(map
, genx
->vertex_buffers
[i
].state
,
5016 sizeof(uint32_t) * vb_dwords
);
5022 if (dirty
& IRIS_DIRTY_VERTEX_ELEMENTS
) {
5023 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5024 const unsigned entries
= MAX2(cso
->count
, 1);
5025 if (!(ice
->state
.vs_needs_sgvs_element
||
5026 ice
->state
.vs_uses_derived_draw_params
||
5027 ice
->state
.vs_needs_edge_flag
)) {
5028 iris_batch_emit(batch
, cso
->vertex_elements
, sizeof(uint32_t) *
5029 (1 + entries
* GENX(VERTEX_ELEMENT_STATE_length
)));
5031 uint32_t dynamic_ves
[1 + 33 * GENX(VERTEX_ELEMENT_STATE_length
)];
5032 const unsigned dyn_count
= cso
->count
+
5033 ice
->state
.vs_needs_sgvs_element
+
5034 ice
->state
.vs_uses_derived_draw_params
;
5036 iris_pack_command(GENX(3DSTATE_VERTEX_ELEMENTS
),
5039 1 + GENX(VERTEX_ELEMENT_STATE_length
) * dyn_count
- 2;
5041 memcpy(&dynamic_ves
[1], &cso
->vertex_elements
[1],
5042 (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5043 GENX(VERTEX_ELEMENT_STATE_length
) * sizeof(uint32_t));
5044 uint32_t *ve_pack_dest
=
5045 &dynamic_ves
[1 + (cso
->count
- ice
->state
.vs_needs_edge_flag
) *
5046 GENX(VERTEX_ELEMENT_STATE_length
)];
5048 if (ice
->state
.vs_needs_sgvs_element
) {
5049 uint32_t base_ctrl
= ice
->state
.vs_uses_draw_params
?
5050 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
5051 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5053 ve
.VertexBufferIndex
=
5054 util_bitcount64(ice
->state
.bound_vertex_buffers
);
5055 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5056 ve
.Component0Control
= base_ctrl
;
5057 ve
.Component1Control
= base_ctrl
;
5058 ve
.Component2Control
= VFCOMP_STORE_0
;
5059 ve
.Component3Control
= VFCOMP_STORE_0
;
5061 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5063 if (ice
->state
.vs_uses_derived_draw_params
) {
5064 iris_pack_state(GENX(VERTEX_ELEMENT_STATE
), ve_pack_dest
, ve
) {
5066 ve
.VertexBufferIndex
=
5067 util_bitcount64(ice
->state
.bound_vertex_buffers
) +
5068 ice
->state
.vs_uses_draw_params
;
5069 ve
.SourceElementFormat
= ISL_FORMAT_R32G32_UINT
;
5070 ve
.Component0Control
= VFCOMP_STORE_SRC
;
5071 ve
.Component1Control
= VFCOMP_STORE_SRC
;
5072 ve
.Component2Control
= VFCOMP_STORE_0
;
5073 ve
.Component3Control
= VFCOMP_STORE_0
;
5075 ve_pack_dest
+= GENX(VERTEX_ELEMENT_STATE_length
);
5077 if (ice
->state
.vs_needs_edge_flag
) {
5078 for (int i
= 0; i
< GENX(VERTEX_ELEMENT_STATE_length
); i
++)
5079 ve_pack_dest
[i
] = cso
->edgeflag_ve
[i
];
5082 iris_batch_emit(batch
, &dynamic_ves
, sizeof(uint32_t) *
5083 (1 + dyn_count
* GENX(VERTEX_ELEMENT_STATE_length
)));
5086 if (!ice
->state
.vs_needs_edge_flag
) {
5087 iris_batch_emit(batch
, cso
->vf_instancing
, sizeof(uint32_t) *
5088 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5090 assert(cso
->count
> 0);
5091 const unsigned edgeflag_index
= cso
->count
- 1;
5092 uint32_t dynamic_vfi
[33 * GENX(3DSTATE_VF_INSTANCING_length
)];
5093 memcpy(&dynamic_vfi
[0], cso
->vf_instancing
, edgeflag_index
*
5094 GENX(3DSTATE_VF_INSTANCING_length
) * sizeof(uint32_t));
5096 uint32_t *vfi_pack_dest
= &dynamic_vfi
[0] +
5097 edgeflag_index
* GENX(3DSTATE_VF_INSTANCING_length
);
5098 iris_pack_command(GENX(3DSTATE_VF_INSTANCING
), vfi_pack_dest
, vi
) {
5099 vi
.VertexElementIndex
= edgeflag_index
+
5100 ice
->state
.vs_needs_sgvs_element
+
5101 ice
->state
.vs_uses_derived_draw_params
;
5103 for (int i
= 0; i
< GENX(3DSTATE_VF_INSTANCING_length
); i
++)
5104 vfi_pack_dest
[i
] |= cso
->edgeflag_vfi
[i
];
5106 iris_batch_emit(batch
, &dynamic_vfi
[0], sizeof(uint32_t) *
5107 entries
* GENX(3DSTATE_VF_INSTANCING_length
));
5111 if (dirty
& IRIS_DIRTY_VF_SGVS
) {
5112 const struct brw_vs_prog_data
*vs_prog_data
= (void *)
5113 ice
->shaders
.prog
[MESA_SHADER_VERTEX
]->prog_data
;
5114 struct iris_vertex_element_state
*cso
= ice
->state
.cso_vertex_elements
;
5116 iris_emit_cmd(batch
, GENX(3DSTATE_VF_SGVS
), sgv
) {
5117 if (vs_prog_data
->uses_vertexid
) {
5118 sgv
.VertexIDEnable
= true;
5119 sgv
.VertexIDComponentNumber
= 2;
5120 sgv
.VertexIDElementOffset
=
5121 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5124 if (vs_prog_data
->uses_instanceid
) {
5125 sgv
.InstanceIDEnable
= true;
5126 sgv
.InstanceIDComponentNumber
= 3;
5127 sgv
.InstanceIDElementOffset
=
5128 cso
->count
- ice
->state
.vs_needs_edge_flag
;
5133 if (dirty
& IRIS_DIRTY_VF
) {
5134 iris_emit_cmd(batch
, GENX(3DSTATE_VF
), vf
) {
5135 if (draw
->primitive_restart
) {
5136 vf
.IndexedDrawCutIndexEnable
= true;
5137 vf
.CutIndex
= draw
->restart_index
;
5142 if (dirty
& IRIS_DIRTY_VF_STATISTICS
) {
5143 iris_emit_cmd(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
5144 vf
.StatisticsEnable
= true;
5148 /* TODO: Gen8 PMA fix */
5152 iris_upload_render_state(struct iris_context
*ice
,
5153 struct iris_batch
*batch
,
5154 const struct pipe_draw_info
*draw
)
5156 /* Always pin the binder. If we're emitting new binding table pointers,
5157 * we need it. If not, we're probably inheriting old tables via the
5158 * context, and need it anyway. Since true zero-bindings cases are
5159 * practically non-existent, just pin it and avoid last_res tracking.
5161 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5163 if (!batch
->contains_draw
) {
5164 iris_restore_render_saved_bos(ice
, batch
, draw
);
5165 batch
->contains_draw
= true;
5168 iris_upload_dirty_render_state(ice
, batch
, draw
);
5170 if (draw
->index_size
> 0) {
5173 if (draw
->has_user_indices
) {
5174 u_upload_data(ice
->ctx
.stream_uploader
, 0,
5175 draw
->count
* draw
->index_size
, 4, draw
->index
.user
,
5176 &offset
, &ice
->state
.last_res
.index_buffer
);
5178 struct iris_resource
*res
= (void *) draw
->index
.resource
;
5179 res
->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
5181 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
,
5182 draw
->index
.resource
);
5186 struct iris_bo
*bo
= iris_resource_bo(ice
->state
.last_res
.index_buffer
);
5188 iris_emit_cmd(batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
5189 ib
.IndexFormat
= draw
->index_size
>> 1;
5191 ib
.BufferSize
= bo
->size
- offset
;
5192 ib
.BufferStartingAddress
= ro_bo(bo
, offset
);
5195 /* The VF cache key only uses 32-bits, see vertex buffer comment above */
5196 uint16_t high_bits
= bo
->gtt_offset
>> 32ull;
5197 if (high_bits
!= ice
->state
.last_index_bo_high_bits
) {
5198 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_VF_CACHE_INVALIDATE
|
5199 PIPE_CONTROL_CS_STALL
);
5200 ice
->state
.last_index_bo_high_bits
= high_bits
;
5204 #define _3DPRIM_END_OFFSET 0x2420
5205 #define _3DPRIM_START_VERTEX 0x2430
5206 #define _3DPRIM_VERTEX_COUNT 0x2434
5207 #define _3DPRIM_INSTANCE_COUNT 0x2438
5208 #define _3DPRIM_START_INSTANCE 0x243C
5209 #define _3DPRIM_BASE_VERTEX 0x2440
5211 if (draw
->indirect
) {
5212 /* We don't support this MultidrawIndirect. */
5213 assert(!draw
->indirect
->indirect_draw_count
);
5215 struct iris_bo
*bo
= iris_resource_bo(draw
->indirect
->buffer
);
5218 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5219 lrm
.RegisterAddress
= _3DPRIM_VERTEX_COUNT
;
5220 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 0);
5222 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5223 lrm
.RegisterAddress
= _3DPRIM_INSTANCE_COUNT
;
5224 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 4);
5226 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5227 lrm
.RegisterAddress
= _3DPRIM_START_VERTEX
;
5228 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 8);
5230 if (draw
->index_size
) {
5231 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5232 lrm
.RegisterAddress
= _3DPRIM_BASE_VERTEX
;
5233 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5235 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5236 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5237 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 16);
5240 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5241 lrm
.RegisterAddress
= _3DPRIM_START_INSTANCE
;
5242 lrm
.MemoryAddress
= ro_bo(bo
, draw
->indirect
->offset
+ 12);
5244 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
5245 lri
.RegisterOffset
= _3DPRIM_BASE_VERTEX
;
5249 } else if (draw
->count_from_stream_output
) {
5250 struct iris_stream_output_target
*so
=
5251 (void *) draw
->count_from_stream_output
;
5253 /* XXX: Replace with actual cache tracking */
5254 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
5256 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5257 lrm
.RegisterAddress
= CS_GPR(0);
5259 ro_bo(iris_resource_bo(so
->offset
.res
), so
->offset
.offset
);
5261 if (so
->base
.buffer_offset
)
5262 iris_math_add32_gpr0(ice
, batch
, -so
->base
.buffer_offset
);
5263 iris_math_div32_gpr0(ice
, batch
, so
->stride
);
5264 _iris_emit_lrr(batch
, _3DPRIM_VERTEX_COUNT
, CS_GPR(0));
5266 _iris_emit_lri(batch
, _3DPRIM_START_VERTEX
, 0);
5267 _iris_emit_lri(batch
, _3DPRIM_BASE_VERTEX
, 0);
5268 _iris_emit_lri(batch
, _3DPRIM_START_INSTANCE
, 0);
5269 _iris_emit_lri(batch
, _3DPRIM_INSTANCE_COUNT
, draw
->instance_count
);
5272 iris_emit_cmd(batch
, GENX(3DPRIMITIVE
), prim
) {
5273 prim
.VertexAccessType
= draw
->index_size
> 0 ? RANDOM
: SEQUENTIAL
;
5274 prim
.PredicateEnable
=
5275 ice
->state
.predicate
== IRIS_PREDICATE_STATE_USE_BIT
;
5277 if (draw
->indirect
|| draw
->count_from_stream_output
) {
5278 prim
.IndirectParameterEnable
= true;
5280 prim
.StartInstanceLocation
= draw
->start_instance
;
5281 prim
.InstanceCount
= draw
->instance_count
;
5282 prim
.VertexCountPerInstance
= draw
->count
;
5284 // XXX: this is probably bonkers.
5285 prim
.StartVertexLocation
= draw
->start
;
5287 if (draw
->index_size
) {
5288 prim
.BaseVertexLocation
+= draw
->index_bias
;
5290 prim
.StartVertexLocation
+= draw
->index_bias
;
5293 //prim.BaseVertexLocation = ...;
5299 iris_upload_compute_state(struct iris_context
*ice
,
5300 struct iris_batch
*batch
,
5301 const struct pipe_grid_info
*grid
)
5303 const uint64_t dirty
= ice
->state
.dirty
;
5304 struct iris_screen
*screen
= batch
->screen
;
5305 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
5306 struct iris_binder
*binder
= &ice
->state
.binder
;
5307 struct iris_shader_state
*shs
= &ice
->state
.shaders
[MESA_SHADER_COMPUTE
];
5308 struct iris_compiled_shader
*shader
=
5309 ice
->shaders
.prog
[MESA_SHADER_COMPUTE
];
5310 struct brw_stage_prog_data
*prog_data
= shader
->prog_data
;
5311 struct brw_cs_prog_data
*cs_prog_data
= (void *) prog_data
;
5313 /* Always pin the binder. If we're emitting new binding table pointers,
5314 * we need it. If not, we're probably inheriting old tables via the
5315 * context, and need it anyway. Since true zero-bindings cases are
5316 * practically non-existent, just pin it and avoid last_res tracking.
5318 iris_use_pinned_bo(batch
, ice
->state
.binder
.bo
, false);
5320 if ((dirty
& IRIS_DIRTY_CONSTANTS_CS
) && shs
->cbuf0_needs_upload
)
5321 upload_uniforms(ice
, MESA_SHADER_COMPUTE
);
5323 if (dirty
& IRIS_DIRTY_BINDINGS_CS
)
5324 iris_populate_binding_table(ice
, batch
, MESA_SHADER_COMPUTE
, false);
5326 if (dirty
& IRIS_DIRTY_SAMPLER_STATES_CS
)
5327 iris_upload_sampler_states(ice
, MESA_SHADER_COMPUTE
);
5329 iris_use_optional_res(batch
, shs
->sampler_table
.res
, false);
5330 iris_use_pinned_bo(batch
, iris_resource_bo(shader
->assembly
.res
), false);
5332 if (ice
->state
.need_border_colors
)
5333 iris_use_pinned_bo(batch
, ice
->state
.border_color_pool
.bo
, false);
5335 if (dirty
& IRIS_DIRTY_CS
) {
5336 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
5338 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
5339 * the only bits that are changed are scoreboard related: Scoreboard
5340 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard Delta. For
5341 * these scoreboard related states, a MEDIA_STATE_FLUSH is
5344 iris_emit_pipe_control_flush(batch
, PIPE_CONTROL_CS_STALL
);
5346 iris_emit_cmd(batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
5347 if (prog_data
->total_scratch
) {
5348 struct iris_bo
*bo
=
5349 iris_get_scratch_space(ice
, prog_data
->total_scratch
,
5350 MESA_SHADER_COMPUTE
);
5351 vfe
.PerThreadScratchSpace
= ffs(prog_data
->total_scratch
) - 11;
5352 vfe
.ScratchSpaceBasePointer
= rw_bo(bo
, 0);
5355 vfe
.MaximumNumberofThreads
=
5356 devinfo
->max_cs_threads
* screen
->subslice_total
- 1;
5358 vfe
.ResetGatewayTimer
=
5359 Resettingrelativetimerandlatchingtheglobaltimestamp
;
5362 vfe
.BypassGatewayControl
= true;
5364 vfe
.NumberofURBEntries
= 2;
5365 vfe
.URBEntryAllocationSize
= 2;
5367 vfe
.CURBEAllocationSize
=
5368 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
5369 cs_prog_data
->push
.cross_thread
.regs
, 2);
5373 /* TODO: Combine subgroup-id with cbuf0 so we can push regular uniforms */
5374 uint32_t curbe_data_offset
= 0;
5375 assert(cs_prog_data
->push
.cross_thread
.dwords
== 0 &&
5376 cs_prog_data
->push
.per_thread
.dwords
== 1 &&
5377 cs_prog_data
->base
.param
[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID
);
5378 struct pipe_resource
*curbe_data_res
= NULL
;
5379 uint32_t *curbe_data_map
=
5380 stream_state(batch
, ice
->state
.dynamic_uploader
, &curbe_data_res
,
5381 ALIGN(cs_prog_data
->push
.total
.size
, 64), 64,
5382 &curbe_data_offset
);
5383 assert(curbe_data_map
);
5384 memset(curbe_data_map
, 0x5a, ALIGN(cs_prog_data
->push
.total
.size
, 64));
5385 iris_fill_cs_push_const_buffer(cs_prog_data
, curbe_data_map
);
5387 if (dirty
& IRIS_DIRTY_CONSTANTS_CS
) {
5388 iris_emit_cmd(batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
5389 curbe
.CURBETotalDataLength
=
5390 ALIGN(cs_prog_data
->push
.total
.size
, 64);
5391 curbe
.CURBEDataStartAddress
= curbe_data_offset
;
5395 if (dirty
& (IRIS_DIRTY_SAMPLER_STATES_CS
|
5396 IRIS_DIRTY_BINDINGS_CS
|
5397 IRIS_DIRTY_CONSTANTS_CS
|
5399 struct pipe_resource
*desc_res
= NULL
;
5400 uint32_t desc
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
5402 iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA
), desc
, idd
) {
5403 idd
.SamplerStatePointer
= shs
->sampler_table
.offset
;
5404 idd
.BindingTablePointer
= binder
->bt_offset
[MESA_SHADER_COMPUTE
];
5407 for (int i
= 0; i
< GENX(INTERFACE_DESCRIPTOR_DATA_length
); i
++)
5408 desc
[i
] |= ((uint32_t *) shader
->derived_data
)[i
];
5410 iris_emit_cmd(batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), load
) {
5411 load
.InterfaceDescriptorTotalLength
=
5412 GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
5413 load
.InterfaceDescriptorDataStartAddress
=
5414 emit_state(batch
, ice
->state
.dynamic_uploader
,
5415 &desc_res
, desc
, sizeof(desc
), 32);
5418 pipe_resource_reference(&desc_res
, NULL
);
5421 uint32_t group_size
= grid
->block
[0] * grid
->block
[1] * grid
->block
[2];
5422 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
5423 uint32_t right_mask
;
5426 right_mask
= ~0u >> (32 - remainder
);
5428 right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
5430 #define GPGPU_DISPATCHDIMX 0x2500
5431 #define GPGPU_DISPATCHDIMY 0x2504
5432 #define GPGPU_DISPATCHDIMZ 0x2508
5434 if (grid
->indirect
) {
5435 struct iris_state_ref
*grid_size
= &ice
->state
.grid_size
;
5436 struct iris_bo
*bo
= iris_resource_bo(grid_size
->res
);
5437 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5438 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMX
;
5439 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 0);
5441 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5442 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMY
;
5443 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 4);
5445 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5446 lrm
.RegisterAddress
= GPGPU_DISPATCHDIMZ
;
5447 lrm
.MemoryAddress
= ro_bo(bo
, grid_size
->offset
+ 8);
5451 iris_emit_cmd(batch
, GENX(GPGPU_WALKER
), ggw
) {
5452 ggw
.IndirectParameterEnable
= grid
->indirect
!= NULL
;
5453 ggw
.SIMDSize
= cs_prog_data
->simd_size
/ 16;
5454 ggw
.ThreadDepthCounterMaximum
= 0;
5455 ggw
.ThreadHeightCounterMaximum
= 0;
5456 ggw
.ThreadWidthCounterMaximum
= cs_prog_data
->threads
- 1;
5457 ggw
.ThreadGroupIDXDimension
= grid
->grid
[0];
5458 ggw
.ThreadGroupIDYDimension
= grid
->grid
[1];
5459 ggw
.ThreadGroupIDZDimension
= grid
->grid
[2];
5460 ggw
.RightExecutionMask
= right_mask
;
5461 ggw
.BottomExecutionMask
= 0xffffffff;
5464 iris_emit_cmd(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
5466 if (!batch
->contains_draw
) {
5467 iris_restore_compute_saved_bos(ice
, batch
, grid
);
5468 batch
->contains_draw
= true;
5473 * State module teardown.
5476 iris_destroy_state(struct iris_context
*ice
)
5478 struct iris_genx_state
*genx
= ice
->state
.genx
;
5480 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5482 const int i
= u_bit_scan64(&bound_vbs
);
5483 pipe_resource_reference(&genx
->vertex_buffers
[i
].resource
, NULL
);
5485 free(ice
->state
.genx
);
5487 for (unsigned i
= 0; i
< ice
->state
.framebuffer
.nr_cbufs
; i
++) {
5488 pipe_surface_reference(&ice
->state
.framebuffer
.cbufs
[i
], NULL
);
5490 pipe_surface_reference(&ice
->state
.framebuffer
.zsbuf
, NULL
);
5492 for (int stage
= 0; stage
< MESA_SHADER_STAGES
; stage
++) {
5493 struct iris_shader_state
*shs
= &ice
->state
.shaders
[stage
];
5494 pipe_resource_reference(&shs
->sampler_table
.res
, NULL
);
5495 for (int i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
5496 pipe_resource_reference(&shs
->constbuf
[i
].buffer
, NULL
);
5497 pipe_resource_reference(&shs
->constbuf_surf_state
[i
].res
, NULL
);
5499 for (int i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
5500 pipe_resource_reference(&shs
->image
[i
].base
.resource
, NULL
);
5501 pipe_resource_reference(&shs
->image
[i
].surface_state
.res
, NULL
);
5503 for (int i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
5504 pipe_resource_reference(&shs
->ssbo
[i
].buffer
, NULL
);
5505 pipe_resource_reference(&shs
->ssbo_surf_state
[i
].res
, NULL
);
5507 for (int i
= 0; i
< IRIS_MAX_TEXTURE_SAMPLERS
; i
++) {
5508 pipe_sampler_view_reference((struct pipe_sampler_view
**)
5509 &shs
->textures
[i
], NULL
);
5513 pipe_resource_reference(&ice
->state
.grid_size
.res
, NULL
);
5514 pipe_resource_reference(&ice
->state
.grid_surf_state
.res
, NULL
);
5516 pipe_resource_reference(&ice
->state
.null_fb
.res
, NULL
);
5517 pipe_resource_reference(&ice
->state
.unbound_tex
.res
, NULL
);
5519 pipe_resource_reference(&ice
->state
.last_res
.cc_vp
, NULL
);
5520 pipe_resource_reference(&ice
->state
.last_res
.sf_cl_vp
, NULL
);
5521 pipe_resource_reference(&ice
->state
.last_res
.color_calc
, NULL
);
5522 pipe_resource_reference(&ice
->state
.last_res
.scissor
, NULL
);
5523 pipe_resource_reference(&ice
->state
.last_res
.blend
, NULL
);
5524 pipe_resource_reference(&ice
->state
.last_res
.index_buffer
, NULL
);
5527 /* ------------------------------------------------------------------- */
5530 iris_rebind_buffer(struct iris_context
*ice
,
5531 struct iris_resource
*res
,
5532 uint64_t old_address
)
5534 struct pipe_context
*ctx
= &ice
->ctx
;
5535 struct iris_screen
*screen
= (void *) ctx
->screen
;
5536 struct iris_genx_state
*genx
= ice
->state
.genx
;
5538 assert(res
->base
.target
== PIPE_BUFFER
);
5540 /* Buffers can't be framebuffer attachments, nor display related,
5541 * and we don't have upstream Clover support.
5543 assert(!(res
->bind_history
& (PIPE_BIND_DEPTH_STENCIL
|
5544 PIPE_BIND_RENDER_TARGET
|
5545 PIPE_BIND_BLENDABLE
|
5546 PIPE_BIND_DISPLAY_TARGET
|
5548 PIPE_BIND_COMPUTE_RESOURCE
|
5549 PIPE_BIND_GLOBAL
)));
5551 if (res
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
5552 uint64_t bound_vbs
= ice
->state
.bound_vertex_buffers
;
5554 const int i
= u_bit_scan64(&bound_vbs
);
5555 struct iris_vertex_buffer_state
*state
= &genx
->vertex_buffers
[i
];
5557 /* Update the CPU struct */
5558 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_start
) == 32);
5559 STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits
) == 64);
5560 uint64_t *addr
= (uint64_t *) &state
->state
[1];
5562 if (*addr
== old_address
) {
5563 *addr
= res
->bo
->gtt_offset
;
5564 ice
->state
.dirty
|= IRIS_DIRTY_VERTEX_BUFFERS
;
5569 /* No need to handle these:
5570 * - PIPE_BIND_INDEX_BUFFER (emitted for every indexed draw)
5571 * - PIPE_BIND_COMMAND_ARGS_BUFFER (emitted for every indirect draw)
5572 * - PIPE_BIND_QUERY_BUFFER (no persistent state references)
5575 if (res
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
5576 /* XXX: be careful about resetting vs appending... */
5580 for (int s
= MESA_SHADER_VERTEX
; s
< MESA_SHADER_STAGES
; s
++) {
5581 struct iris_shader_state
*shs
= &ice
->state
.shaders
[s
];
5582 enum pipe_shader_type p_stage
= stage_to_pipe(s
);
5584 if (res
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
5585 /* Skip constant buffer 0, it's for regular uniforms, not UBOs */
5586 uint32_t bound_cbufs
= shs
->bound_cbufs
& ~1u;
5587 while (bound_cbufs
) {
5588 const int i
= u_bit_scan(&bound_cbufs
);
5589 struct pipe_shader_buffer
*cbuf
= &shs
->constbuf
[i
];
5590 struct iris_state_ref
*surf_state
= &shs
->constbuf_surf_state
[i
];
5592 if (res
->bo
== iris_resource_bo(cbuf
->buffer
)) {
5593 upload_ubo_ssbo_surf_state(ice
, cbuf
, surf_state
, false);
5594 ice
->state
.dirty
|= IRIS_DIRTY_CONSTANTS_VS
<< s
;
5599 if (res
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
5600 uint32_t bound_ssbos
= shs
->bound_ssbos
;
5601 while (bound_ssbos
) {
5602 const int i
= u_bit_scan(&bound_ssbos
);
5603 struct pipe_shader_buffer
*ssbo
= &shs
->ssbo
[i
];
5605 if (res
->bo
== iris_resource_bo(ssbo
->buffer
)) {
5606 struct pipe_shader_buffer buf
= {
5607 .buffer
= &res
->base
,
5608 .buffer_offset
= ssbo
->buffer_offset
,
5609 .buffer_size
= ssbo
->buffer_size
,
5611 iris_set_shader_buffers(ctx
, p_stage
, i
, 1, &buf
,
5612 (shs
->writable_ssbos
>> i
) & 1);
5617 if (res
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
5618 uint32_t bound_sampler_views
= shs
->bound_sampler_views
;
5619 while (bound_sampler_views
) {
5620 const int i
= u_bit_scan(&bound_sampler_views
);
5621 struct iris_sampler_view
*isv
= shs
->textures
[i
];
5623 if (res
->bo
== iris_resource_bo(isv
->base
.texture
)) {
5624 void *map
= alloc_surface_states(ice
->state
.surface_uploader
,
5625 &isv
->surface_state
,
5626 isv
->res
->aux
.sampler_usages
);
5628 fill_buffer_surface_state(&screen
->isl_dev
, isv
->res
->bo
, map
,
5629 isv
->view
.format
, isv
->view
.swizzle
,
5630 isv
->base
.u
.buf
.offset
,
5631 isv
->base
.u
.buf
.size
);
5632 ice
->state
.dirty
|= IRIS_DIRTY_BINDINGS_VS
<< s
;
5637 if (res
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
5638 uint32_t bound_image_views
= shs
->bound_image_views
;
5639 while (bound_image_views
) {
5640 const int i
= u_bit_scan(&bound_image_views
);
5641 struct iris_image_view
*iv
= &shs
->image
[i
];
5643 if (res
->bo
== iris_resource_bo(iv
->base
.resource
)) {
5644 iris_set_shader_images(ctx
, p_stage
, i
, 1, &iv
->base
);
5651 /* ------------------------------------------------------------------- */
5654 iris_load_register_reg32(struct iris_batch
*batch
, uint32_t dst
,
5657 _iris_emit_lrr(batch
, dst
, src
);
5661 iris_load_register_reg64(struct iris_batch
*batch
, uint32_t dst
,
5664 _iris_emit_lrr(batch
, dst
, src
);
5665 _iris_emit_lrr(batch
, dst
+ 4, src
+ 4);
5669 iris_load_register_imm32(struct iris_batch
*batch
, uint32_t reg
,
5672 _iris_emit_lri(batch
, reg
, val
);
5676 iris_load_register_imm64(struct iris_batch
*batch
, uint32_t reg
,
5679 _iris_emit_lri(batch
, reg
+ 0, val
& 0xffffffff);
5680 _iris_emit_lri(batch
, reg
+ 4, val
>> 32);
5684 * Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
5687 iris_load_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
5688 struct iris_bo
*bo
, uint32_t offset
)
5690 iris_emit_cmd(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
5691 lrm
.RegisterAddress
= reg
;
5692 lrm
.MemoryAddress
= ro_bo(bo
, offset
);
5697 * Load a 64-bit value from a buffer into a MMIO register via
5698 * two MI_LOAD_REGISTER_MEM commands.
5701 iris_load_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
5702 struct iris_bo
*bo
, uint32_t offset
)
5704 iris_load_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0);
5705 iris_load_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4);
5709 iris_store_register_mem32(struct iris_batch
*batch
, uint32_t reg
,
5710 struct iris_bo
*bo
, uint32_t offset
,
5713 iris_emit_cmd(batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
5714 srm
.RegisterAddress
= reg
;
5715 srm
.MemoryAddress
= rw_bo(bo
, offset
);
5716 srm
.PredicateEnable
= predicated
;
5721 iris_store_register_mem64(struct iris_batch
*batch
, uint32_t reg
,
5722 struct iris_bo
*bo
, uint32_t offset
,
5725 iris_store_register_mem32(batch
, reg
+ 0, bo
, offset
+ 0, predicated
);
5726 iris_store_register_mem32(batch
, reg
+ 4, bo
, offset
+ 4, predicated
);
5730 iris_store_data_imm32(struct iris_batch
*batch
,
5731 struct iris_bo
*bo
, uint32_t offset
,
5734 iris_emit_cmd(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
5735 sdi
.Address
= rw_bo(bo
, offset
);
5736 sdi
.ImmediateData
= imm
;
5741 iris_store_data_imm64(struct iris_batch
*batch
,
5742 struct iris_bo
*bo
, uint32_t offset
,
5745 /* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
5746 * 2 in genxml but it's actually variable length and we need 5 DWords.
5748 void *map
= iris_get_command_space(batch
, 4 * 5);
5749 _iris_pack_command(batch
, GENX(MI_STORE_DATA_IMM
), map
, sdi
) {
5750 sdi
.DWordLength
= 5 - 2;
5751 sdi
.Address
= rw_bo(bo
, offset
);
5752 sdi
.ImmediateData
= imm
;
5757 iris_copy_mem_mem(struct iris_batch
*batch
,
5758 struct iris_bo
*dst_bo
, uint32_t dst_offset
,
5759 struct iris_bo
*src_bo
, uint32_t src_offset
,
5762 /* MI_COPY_MEM_MEM operates on DWords. */
5763 assert(bytes
% 4 == 0);
5764 assert(dst_offset
% 4 == 0);
5765 assert(src_offset
% 4 == 0);
5767 for (unsigned i
= 0; i
< bytes
; i
+= 4) {
5768 iris_emit_cmd(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
5769 cp
.DestinationMemoryAddress
= rw_bo(dst_bo
, dst_offset
+ i
);
5770 cp
.SourceMemoryAddress
= ro_bo(src_bo
, src_offset
+ i
);
5775 /* ------------------------------------------------------------------- */
5778 flags_to_post_sync_op(uint32_t flags
)
5780 if (flags
& PIPE_CONTROL_WRITE_IMMEDIATE
)
5781 return WriteImmediateData
;
5783 if (flags
& PIPE_CONTROL_WRITE_DEPTH_COUNT
)
5784 return WritePSDepthCount
;
5786 if (flags
& PIPE_CONTROL_WRITE_TIMESTAMP
)
5787 return WriteTimestamp
;
5793 * Do the given flags have a Post Sync or LRI Post Sync operation?
5795 static enum pipe_control_flags
5796 get_post_sync_flags(enum pipe_control_flags flags
)
5798 flags
&= PIPE_CONTROL_WRITE_IMMEDIATE
|
5799 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5800 PIPE_CONTROL_WRITE_TIMESTAMP
|
5801 PIPE_CONTROL_LRI_POST_SYNC_OP
;
5803 /* Only one "Post Sync Op" is allowed, and it's mutually exclusive with
5804 * "LRI Post Sync Operation". So more than one bit set would be illegal.
5806 assert(util_bitcount(flags
) <= 1);
5811 #define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
5814 * Emit a series of PIPE_CONTROL commands, taking into account any
5815 * workarounds necessary to actually accomplish the caller's request.
5817 * Unless otherwise noted, spec quotations in this function come from:
5819 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
5820 * Restrictions for PIPE_CONTROL.
5822 * You should not use this function directly. Use the helpers in
5823 * iris_pipe_control.c instead, which may split the pipe control further.
5826 iris_emit_raw_pipe_control(struct iris_batch
*batch
, uint32_t flags
,
5827 struct iris_bo
*bo
, uint32_t offset
, uint64_t imm
)
5829 UNUSED
const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
5830 enum pipe_control_flags post_sync_flags
= get_post_sync_flags(flags
);
5831 enum pipe_control_flags non_lri_post_sync_flags
=
5832 post_sync_flags
& ~PIPE_CONTROL_LRI_POST_SYNC_OP
;
5834 /* Recursive PIPE_CONTROL workarounds --------------------------------
5835 * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
5837 * We do these first because we want to look at the original operation,
5838 * rather than any workarounds we set.
5840 if (GEN_GEN
== 9 && (flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
)) {
5841 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
5842 * lists several workarounds:
5844 * "Project: SKL, KBL, BXT
5846 * If the VF Cache Invalidation Enable is set to a 1 in a
5847 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
5848 * sets to 0, with the VF Cache Invalidation Enable set to 0
5849 * needs to be sent prior to the PIPE_CONTROL with VF Cache
5850 * Invalidation Enable set to a 1."
5852 iris_emit_raw_pipe_control(batch
, 0, NULL
, 0, 0);
5855 if (GEN_GEN
== 9 && IS_COMPUTE_PIPELINE(batch
) && post_sync_flags
) {
5856 /* Project: SKL / Argument: LRI Post Sync Operation [23]
5858 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
5859 * programmed prior to programming a PIPECONTROL command with "LRI
5860 * Post Sync Operation" in GPGPU mode of operation (i.e when
5861 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
5863 * The same text exists a few rows below for Post Sync Op.
5865 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_CS_STALL
, bo
, offset
, imm
);
5868 if (GEN_GEN
== 10 && (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
)) {
5870 * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
5871 * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
5872 * = 0 and Pipe Control Flush Enable (bit 7) = 1"
5874 iris_emit_raw_pipe_control(batch
, PIPE_CONTROL_FLUSH_ENABLE
, bo
,
5878 /* "Flush Types" workarounds ---------------------------------------------
5879 * We do these now because they may add post-sync operations or CS stalls.
5882 if (GEN_GEN
< 11 && flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
) {
5883 /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
5885 * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or
5886 * 'Write PS Depth Count' or 'Write Timestamp'."
5889 flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5890 post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5891 non_lri_post_sync_flags
|= PIPE_CONTROL_WRITE_IMMEDIATE
;
5892 bo
= batch
->screen
->workaround_bo
;
5896 /* #1130 from Gen10 workarounds page:
5898 * "Enable Depth Stall on every Post Sync Op if Render target Cache
5899 * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
5900 * board stall if Render target cache flush is enabled."
5902 * Applicable to CNL B0 and C0 steppings only.
5904 * The wording here is unclear, and this workaround doesn't look anything
5905 * like the internal bug report recommendations, but leave it be for now...
5907 if (GEN_GEN
== 10) {
5908 if (flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
) {
5909 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
5910 } else if (flags
& non_lri_post_sync_flags
) {
5911 flags
|= PIPE_CONTROL_DEPTH_STALL
;
5915 if (flags
& PIPE_CONTROL_DEPTH_STALL
) {
5916 /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
5918 * "This bit must be DISABLED for operations other than writing
5921 * This seems like nonsense. An Ivybridge workaround requires us to
5922 * emit a PIPE_CONTROL with a depth stall and write immediate post-sync
5923 * operation. Gen8+ requires us to emit depth stalls and depth cache
5924 * flushes together. So, it's hard to imagine this means anything other
5925 * than "we originally intended this to be used for PS_DEPTH_COUNT".
5927 * We ignore the supposed restriction and do nothing.
5931 if (flags
& (PIPE_CONTROL_RENDER_TARGET_FLUSH
|
5932 PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5933 /* From the PIPE_CONTROL instruction table, bit 12 and bit 1:
5935 * "This bit must be DISABLED for End-of-pipe (Read) fences,
5936 * PS_DEPTH_COUNT or TIMESTAMP queries."
5938 * TODO: Implement end-of-pipe checking.
5940 assert(!(post_sync_flags
& (PIPE_CONTROL_WRITE_DEPTH_COUNT
|
5941 PIPE_CONTROL_WRITE_TIMESTAMP
)));
5944 if (GEN_GEN
< 11 && (flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
)) {
5945 /* From the PIPE_CONTROL instruction table, bit 1:
5947 * "This bit is ignored if Depth Stall Enable is set.
5948 * Further, the render cache is not flushed even if Write Cache
5949 * Flush Enable bit is set."
5951 * We assert that the caller doesn't do this combination, to try and
5952 * prevent mistakes. It shouldn't hurt the GPU, though.
5954 * We skip this check on Gen11+ as the "Stall at Pixel Scoreboard"
5955 * and "Render Target Flush" combo is explicitly required for BTI
5956 * update workarounds.
5958 assert(!(flags
& (PIPE_CONTROL_DEPTH_STALL
|
5959 PIPE_CONTROL_RENDER_TARGET_FLUSH
)));
5962 /* PIPE_CONTROL page workarounds ------------------------------------- */
5964 if (GEN_GEN
<= 8 && (flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
)) {
5965 /* From the PIPE_CONTROL page itself:
5968 * Restriction: Pipe_control with CS-stall bit set must be issued
5969 * before a pipe-control command that has the State Cache
5970 * Invalidate bit set."
5972 flags
|= PIPE_CONTROL_CS_STALL
;
5975 if (flags
& PIPE_CONTROL_FLUSH_LLC
) {
5976 /* From the PIPE_CONTROL instruction table, bit 26 (Flush LLC):
5979 * SW must always program Post-Sync Operation to "Write Immediate
5980 * Data" when Flush LLC is set."
5982 * For now, we just require the caller to do it.
5984 assert(flags
& PIPE_CONTROL_WRITE_IMMEDIATE
);
5987 /* "Post-Sync Operation" workarounds -------------------------------- */
5989 /* Project: All / Argument: Global Snapshot Count Reset [19]
5991 * "This bit must not be exercised on any product.
5992 * Requires stall bit ([20] of DW1) set."
5994 * We don't use this, so we just assert that it isn't used. The
5995 * PIPE_CONTROL instruction page indicates that they intended this
5996 * as a debug feature and don't think it is useful in production,
5997 * but it may actually be usable, should we ever want to.
5999 assert((flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
) == 0);
6001 if (flags
& (PIPE_CONTROL_MEDIA_STATE_CLEAR
|
6002 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
)) {
6003 /* Project: All / Arguments:
6005 * - Generic Media State Clear [16]
6006 * - Indirect State Pointers Disable [16]
6008 * "Requires stall bit ([20] of DW1) set."
6010 * Also, the PIPE_CONTROL instruction table, bit 16 (Generic Media
6011 * State Clear) says:
6013 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
6014 * programmed prior to programming a PIPECONTROL command with "Media
6015 * State Clear" set in GPGPU mode of operation"
6017 * This is a subset of the earlier rule, so there's nothing to do.
6019 flags
|= PIPE_CONTROL_CS_STALL
;
6022 if (flags
& PIPE_CONTROL_STORE_DATA_INDEX
) {
6023 /* Project: All / Argument: Store Data Index
6025 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6028 * For now, we just assert that the caller does this. We might want to
6029 * automatically add a write to the workaround BO...
6031 assert(non_lri_post_sync_flags
!= 0);
6034 if (flags
& PIPE_CONTROL_SYNC_GFDT
) {
6035 /* Project: All / Argument: Sync GFDT
6037 * "Post-Sync Operation ([15:14] of DW1) must be set to something other
6038 * than '0' or 0x2520[13] must be set."
6040 * For now, we just assert that the caller does this.
6042 assert(non_lri_post_sync_flags
!= 0);
6045 if (flags
& PIPE_CONTROL_TLB_INVALIDATE
) {
6046 /* Project: IVB+ / Argument: TLB inv
6048 * "Requires stall bit ([20] of DW1) set."
6050 * Also, from the PIPE_CONTROL instruction table:
6053 * Post Sync Operation or CS stall must be set to ensure a TLB
6054 * invalidation occurs. Otherwise no cycle will occur to the TLB
6055 * cache to invalidate."
6057 * This is not a subset of the earlier rule, so there's nothing to do.
6059 flags
|= PIPE_CONTROL_CS_STALL
;
6062 if (GEN_GEN
== 9 && devinfo
->gt
== 4) {
6063 /* TODO: The big Skylake GT4 post sync op workaround */
6066 /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
6068 if (IS_COMPUTE_PIPELINE(batch
)) {
6069 if (GEN_GEN
>= 9 && (flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
)) {
6070 /* Project: SKL+ / Argument: Tex Invalidate
6071 * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
6073 flags
|= PIPE_CONTROL_CS_STALL
;
6076 if (GEN_GEN
== 8 && (post_sync_flags
||
6077 (flags
& (PIPE_CONTROL_NOTIFY_ENABLE
|
6078 PIPE_CONTROL_DEPTH_STALL
|
6079 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6080 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6081 PIPE_CONTROL_DATA_CACHE_FLUSH
)))) {
6082 /* Project: BDW / Arguments:
6084 * - LRI Post Sync Operation [23]
6085 * - Post Sync Op [15:14]
6087 * - Depth Stall [13]
6088 * - Render Target Cache Flush [12]
6089 * - Depth Cache Flush [0]
6090 * - DC Flush Enable [5]
6092 * "Requires stall bit ([20] of DW) set for all GPGPU and Media
6095 flags
|= PIPE_CONTROL_CS_STALL
;
6097 /* Also, from the PIPE_CONTROL instruction table, bit 20:
6100 * This bit must be always set when PIPE_CONTROL command is
6101 * programmed by GPGPU and MEDIA workloads, except for the cases
6102 * when only Read Only Cache Invalidation bits are set (State
6103 * Cache Invalidation Enable, Instruction cache Invalidation
6104 * Enable, Texture Cache Invalidation Enable, Constant Cache
6105 * Invalidation Enable). This is to WA FFDOP CG issue, this WA
6106 * need not implemented when FF_DOP_CG is disable via "Fixed
6107 * Function DOP Clock Gate Disable" bit in RC_PSMI_CTRL register."
6109 * It sounds like we could avoid CS stalls in some cases, but we
6110 * don't currently bother. This list isn't exactly the list above,
6116 /* "Stall" workarounds ----------------------------------------------
6117 * These have to come after the earlier ones because we may have added
6118 * some additional CS stalls above.
6121 if (GEN_GEN
< 9 && (flags
& PIPE_CONTROL_CS_STALL
)) {
6122 /* Project: PRE-SKL, VLV, CHV
6124 * "[All Stepping][All SKUs]:
6126 * One of the following must also be set:
6128 * - Render Target Cache Flush Enable ([12] of DW1)
6129 * - Depth Cache Flush Enable ([0] of DW1)
6130 * - Stall at Pixel Scoreboard ([1] of DW1)
6131 * - Depth Stall ([13] of DW1)
6132 * - Post-Sync Operation ([13] of DW1)
6133 * - DC Flush Enable ([5] of DW1)"
6135 * If we don't already have one of those bits set, we choose to add
6136 * "Stall at Pixel Scoreboard". Some of the other bits require a
6137 * CS stall as a workaround (see above), which would send us into
6138 * an infinite recursion of PIPE_CONTROLs. "Stall at Pixel Scoreboard"
6139 * appears to be safe, so we choose that.
6141 const uint32_t wa_bits
= PIPE_CONTROL_RENDER_TARGET_FLUSH
|
6142 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
6143 PIPE_CONTROL_WRITE_IMMEDIATE
|
6144 PIPE_CONTROL_WRITE_DEPTH_COUNT
|
6145 PIPE_CONTROL_WRITE_TIMESTAMP
|
6146 PIPE_CONTROL_STALL_AT_SCOREBOARD
|
6147 PIPE_CONTROL_DEPTH_STALL
|
6148 PIPE_CONTROL_DATA_CACHE_FLUSH
;
6149 if (!(flags
& wa_bits
))
6150 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6153 /* Emit --------------------------------------------------------------- */
6155 iris_emit_cmd(batch
, GENX(PIPE_CONTROL
), pc
) {
6156 pc
.LRIPostSyncOperation
= NoLRIOperation
;
6157 pc
.PipeControlFlushEnable
= flags
& PIPE_CONTROL_FLUSH_ENABLE
;
6158 pc
.DCFlushEnable
= flags
& PIPE_CONTROL_DATA_CACHE_FLUSH
;
6159 pc
.StoreDataIndex
= 0;
6160 pc
.CommandStreamerStallEnable
= flags
& PIPE_CONTROL_CS_STALL
;
6161 pc
.GlobalSnapshotCountReset
=
6162 flags
& PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET
;
6163 pc
.TLBInvalidate
= flags
& PIPE_CONTROL_TLB_INVALIDATE
;
6164 pc
.GenericMediaStateClear
= flags
& PIPE_CONTROL_MEDIA_STATE_CLEAR
;
6165 pc
.StallAtPixelScoreboard
= flags
& PIPE_CONTROL_STALL_AT_SCOREBOARD
;
6166 pc
.RenderTargetCacheFlushEnable
=
6167 flags
& PIPE_CONTROL_RENDER_TARGET_FLUSH
;
6168 pc
.DepthCacheFlushEnable
= flags
& PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
6169 pc
.StateCacheInvalidationEnable
=
6170 flags
& PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
6171 pc
.VFCacheInvalidationEnable
= flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
6172 pc
.ConstantCacheInvalidationEnable
=
6173 flags
& PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
6174 pc
.PostSyncOperation
= flags_to_post_sync_op(flags
);
6175 pc
.DepthStallEnable
= flags
& PIPE_CONTROL_DEPTH_STALL
;
6176 pc
.InstructionCacheInvalidateEnable
=
6177 flags
& PIPE_CONTROL_INSTRUCTION_INVALIDATE
;
6178 pc
.NotifyEnable
= flags
& PIPE_CONTROL_NOTIFY_ENABLE
;
6179 pc
.IndirectStatePointersDisable
=
6180 flags
& PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE
;
6181 pc
.TextureCacheInvalidationEnable
=
6182 flags
& PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
6183 pc
.Address
= rw_bo(bo
, offset
);
6184 pc
.ImmediateData
= imm
;
6189 genX(emit_urb_setup
)(struct iris_context
*ice
,
6190 struct iris_batch
*batch
,
6191 const unsigned size
[4],
6192 bool tess_present
, bool gs_present
)
6194 const struct gen_device_info
*devinfo
= &batch
->screen
->devinfo
;
6195 const unsigned push_size_kB
= 32;
6196 unsigned entries
[4];
6199 ice
->shaders
.last_vs_entry_size
= size
[MESA_SHADER_VERTEX
];
6201 gen_get_urb_config(devinfo
, 1024 * push_size_kB
,
6202 1024 * ice
->shaders
.urb_size
,
6203 tess_present
, gs_present
,
6204 size
, entries
, start
);
6206 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
6207 iris_emit_cmd(batch
, GENX(3DSTATE_URB_VS
), urb
) {
6208 urb
._3DCommandSubOpcode
+= i
;
6209 urb
.VSURBStartingAddress
= start
[i
];
6210 urb
.VSURBEntryAllocationSize
= size
[i
] - 1;
6211 urb
.VSNumberofURBEntries
= entries
[i
];
6218 * Preemption on Gen9 has to be enabled or disabled in various cases.
6220 * See these workarounds for preemption:
6221 * - WaDisableMidObjectPreemptionForGSLineStripAdj
6222 * - WaDisableMidObjectPreemptionForTrifanOrPolygon
6223 * - WaDisableMidObjectPreemptionForLineLoop
6226 * We don't put this in the vtable because it's only used on Gen9.
6229 gen9_toggle_preemption(struct iris_context
*ice
,
6230 struct iris_batch
*batch
,
6231 const struct pipe_draw_info
*draw
)
6233 struct iris_genx_state
*genx
= ice
->state
.genx
;
6234 bool object_preemption
= true;
6236 /* WaDisableMidObjectPreemptionForGSLineStripAdj
6238 * "WA: Disable mid-draw preemption when draw-call is a linestrip_adj
6239 * and GS is enabled."
6241 if (draw
->mode
== PIPE_PRIM_LINE_STRIP_ADJACENCY
&&
6242 ice
->shaders
.prog
[MESA_SHADER_GEOMETRY
])
6243 object_preemption
= false;
6245 /* WaDisableMidObjectPreemptionForTrifanOrPolygon
6247 * "TriFan miscompare in Execlist Preemption test. Cut index that is
6248 * on a previous context. End the previous, the resume another context
6249 * with a tri-fan or polygon, and the vertex count is corrupted. If we
6250 * prempt again we will cause corruption.
6252 * WA: Disable mid-draw preemption when draw-call has a tri-fan."
6254 if (draw
->mode
== PIPE_PRIM_TRIANGLE_FAN
)
6255 object_preemption
= false;
6257 /* WaDisableMidObjectPreemptionForLineLoop
6259 * "VF Stats Counters Missing a vertex when preemption enabled.
6261 * WA: Disable mid-draw preemption when the draw uses a lineloop
6264 if (draw
->mode
== PIPE_PRIM_LINE_LOOP
)
6265 object_preemption
= false;
6269 * "VF is corrupting GAFS data when preempted on an instance boundary
6270 * and replayed with instancing enabled.
6272 * WA: Disable preemption when using instanceing."
6274 if (draw
->instance_count
> 1)
6275 object_preemption
= false;
6277 if (genx
->object_preemption
!= object_preemption
) {
6278 iris_enable_obj_preemption(batch
, object_preemption
);
6279 genx
->object_preemption
= object_preemption
;
6285 genX(init_state
)(struct iris_context
*ice
)
6287 struct pipe_context
*ctx
= &ice
->ctx
;
6288 struct iris_screen
*screen
= (struct iris_screen
*)ctx
->screen
;
6290 ctx
->create_blend_state
= iris_create_blend_state
;
6291 ctx
->create_depth_stencil_alpha_state
= iris_create_zsa_state
;
6292 ctx
->create_rasterizer_state
= iris_create_rasterizer_state
;
6293 ctx
->create_sampler_state
= iris_create_sampler_state
;
6294 ctx
->create_sampler_view
= iris_create_sampler_view
;
6295 ctx
->create_surface
= iris_create_surface
;
6296 ctx
->create_vertex_elements_state
= iris_create_vertex_elements
;
6297 ctx
->bind_blend_state
= iris_bind_blend_state
;
6298 ctx
->bind_depth_stencil_alpha_state
= iris_bind_zsa_state
;
6299 ctx
->bind_sampler_states
= iris_bind_sampler_states
;
6300 ctx
->bind_rasterizer_state
= iris_bind_rasterizer_state
;
6301 ctx
->bind_vertex_elements_state
= iris_bind_vertex_elements_state
;
6302 ctx
->delete_blend_state
= iris_delete_state
;
6303 ctx
->delete_depth_stencil_alpha_state
= iris_delete_state
;
6304 ctx
->delete_rasterizer_state
= iris_delete_state
;
6305 ctx
->delete_sampler_state
= iris_delete_state
;
6306 ctx
->delete_vertex_elements_state
= iris_delete_state
;
6307 ctx
->set_blend_color
= iris_set_blend_color
;
6308 ctx
->set_clip_state
= iris_set_clip_state
;
6309 ctx
->set_constant_buffer
= iris_set_constant_buffer
;
6310 ctx
->set_shader_buffers
= iris_set_shader_buffers
;
6311 ctx
->set_shader_images
= iris_set_shader_images
;
6312 ctx
->set_sampler_views
= iris_set_sampler_views
;
6313 ctx
->set_tess_state
= iris_set_tess_state
;
6314 ctx
->set_framebuffer_state
= iris_set_framebuffer_state
;
6315 ctx
->set_polygon_stipple
= iris_set_polygon_stipple
;
6316 ctx
->set_sample_mask
= iris_set_sample_mask
;
6317 ctx
->set_scissor_states
= iris_set_scissor_states
;
6318 ctx
->set_stencil_ref
= iris_set_stencil_ref
;
6319 ctx
->set_vertex_buffers
= iris_set_vertex_buffers
;
6320 ctx
->set_viewport_states
= iris_set_viewport_states
;
6321 ctx
->sampler_view_destroy
= iris_sampler_view_destroy
;
6322 ctx
->surface_destroy
= iris_surface_destroy
;
6323 ctx
->draw_vbo
= iris_draw_vbo
;
6324 ctx
->launch_grid
= iris_launch_grid
;
6325 ctx
->create_stream_output_target
= iris_create_stream_output_target
;
6326 ctx
->stream_output_target_destroy
= iris_stream_output_target_destroy
;
6327 ctx
->set_stream_output_targets
= iris_set_stream_output_targets
;
6329 ice
->vtbl
.destroy_state
= iris_destroy_state
;
6330 ice
->vtbl
.init_render_context
= iris_init_render_context
;
6331 ice
->vtbl
.init_compute_context
= iris_init_compute_context
;
6332 ice
->vtbl
.upload_render_state
= iris_upload_render_state
;
6333 ice
->vtbl
.update_surface_base_address
= iris_update_surface_base_address
;
6334 ice
->vtbl
.upload_compute_state
= iris_upload_compute_state
;
6335 ice
->vtbl
.emit_raw_pipe_control
= iris_emit_raw_pipe_control
;
6336 ice
->vtbl
.rebind_buffer
= iris_rebind_buffer
;
6337 ice
->vtbl
.load_register_reg32
= iris_load_register_reg32
;
6338 ice
->vtbl
.load_register_reg64
= iris_load_register_reg64
;
6339 ice
->vtbl
.load_register_imm32
= iris_load_register_imm32
;
6340 ice
->vtbl
.load_register_imm64
= iris_load_register_imm64
;
6341 ice
->vtbl
.load_register_mem32
= iris_load_register_mem32
;
6342 ice
->vtbl
.load_register_mem64
= iris_load_register_mem64
;
6343 ice
->vtbl
.store_register_mem32
= iris_store_register_mem32
;
6344 ice
->vtbl
.store_register_mem64
= iris_store_register_mem64
;
6345 ice
->vtbl
.store_data_imm32
= iris_store_data_imm32
;
6346 ice
->vtbl
.store_data_imm64
= iris_store_data_imm64
;
6347 ice
->vtbl
.copy_mem_mem
= iris_copy_mem_mem
;
6348 ice
->vtbl
.derived_program_state_size
= iris_derived_program_state_size
;
6349 ice
->vtbl
.store_derived_program_state
= iris_store_derived_program_state
;
6350 ice
->vtbl
.create_so_decl_list
= iris_create_so_decl_list
;
6351 ice
->vtbl
.populate_vs_key
= iris_populate_vs_key
;
6352 ice
->vtbl
.populate_tcs_key
= iris_populate_tcs_key
;
6353 ice
->vtbl
.populate_tes_key
= iris_populate_tes_key
;
6354 ice
->vtbl
.populate_gs_key
= iris_populate_gs_key
;
6355 ice
->vtbl
.populate_fs_key
= iris_populate_fs_key
;
6356 ice
->vtbl
.populate_cs_key
= iris_populate_cs_key
;
6357 ice
->vtbl
.mocs
= mocs
;
6359 ice
->state
.dirty
= ~0ull;
6361 ice
->state
.statistics_counters_enabled
= true;
6363 ice
->state
.sample_mask
= 0xffff;
6364 ice
->state
.num_viewports
= 1;
6365 ice
->state
.genx
= calloc(1, sizeof(struct iris_genx_state
));
6367 /* Make a 1x1x1 null surface for unbound textures */
6368 void *null_surf_map
=
6369 upload_state(ice
->state
.surface_uploader
, &ice
->state
.unbound_tex
,
6370 4 * GENX(RENDER_SURFACE_STATE_length
), 64);
6371 isl_null_fill_state(&screen
->isl_dev
, null_surf_map
, isl_extent3d(1, 1, 1));
6372 ice
->state
.unbound_tex
.offset
+=
6373 iris_bo_offset_from_base_address(iris_resource_bo(ice
->state
.unbound_tex
.res
));
6375 /* Default all scissor rectangles to be empty regions. */
6376 for (int i
= 0; i
< IRIS_MAX_VIEWPORTS
; i
++) {
6377 ice
->state
.scissors
[i
] = (struct pipe_scissor_state
) {
6378 .minx
= 1, .maxx
= 0, .miny
= 1, .maxy
= 0,