src/gallium/drivers/lima/ir/pp/node.c

   1 /*
   2  * Copyright (c) 2017 Lima Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "util/u_math.h"
  26 #include "util/ralloc.h"
  27 #include "util/bitscan.h"
  28
  29 #include "ppir.h"
  30
  31 const ppir_op_info ppir_op_infos[] = {
  32    [ppir_op_mov] = {
  33       .name = "mov",
  34       .slots = (int []) {
  35          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
  36          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
  37          PPIR_INSTR_SLOT_END
  38       },
  39    },
  40    [ppir_op_abs] = {
  41       .name = "abs",
  42    },
  43    [ppir_op_neg] = {
  44       .name = "neg",
  45    },
  46    [ppir_op_sat] = {
  47       .name = "sat",
  48    },
  49    [ppir_op_mul] = {
  50       .name = "mul",
  51       .slots = (int []) {
  52          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
  53          PPIR_INSTR_SLOT_END
  54       },
  55    },
  56    [ppir_op_add] = {
  57       .name = "add",
  58       .slots = (int []) {
  59          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
  60          PPIR_INSTR_SLOT_END
  61       },
  62    },
  63    [ppir_op_dot2] = {
  64       .name = "dot2",
  65    },
  66    [ppir_op_dot3] = {
  67       .name = "dot3",
  68    },
  69    [ppir_op_dot4] = {
  70       .name = "dot4",
  71    },
  72    [ppir_op_sum3] = {
  73       .name = "sum3",
  74       .slots = (int []) {
  75          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_END
  76       },
  77    },
  78    [ppir_op_sum4] = {
  79       .name = "sum4",
  80       .slots = (int []) {
  81          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_END
  82       },
  83    },
  84    [ppir_op_rsqrt] = {
  85       .name = "rsqrt",
  86       .slots = (int []) {
  87          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  88       },
  89    },
  90    [ppir_op_log2] = {
  91       .name = "log2",
  92       .slots = (int []) {
  93          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
  94       },
  95    },
  96    [ppir_op_exp2] = {
  97       .name = "exp2",
  98       .slots = (int []) {
  99          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 100       },
 101    },
 102    [ppir_op_sqrt] = {
 103       .name = "sqrt",
 104       .slots = (int []) {
 105          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 106       },
 107    },
 108    [ppir_op_sin] = {
 109       .name = "sin",
 110       .slots = (int []) {
 111          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 112       },
 113    },
 114    [ppir_op_cos] = {
 115       .name = "cos",
 116       .slots = (int []) {
 117          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 118       },
 119    },
 120    [ppir_op_max] = {
 121       .name = "max",
 122       .slots = (int []) {
 123          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
 124          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 125          PPIR_INSTR_SLOT_END
 126       },
 127    },
 128    [ppir_op_min] = {
 129       .name = "min",
 130       .slots = (int []) {
 131          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_SCL_MUL,
 132          PPIR_INSTR_SLOT_ALU_VEC_ADD, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 133          PPIR_INSTR_SLOT_END
 134       },
 135    },
 136    [ppir_op_floor] = {
 137       .name = "floor",
 138       .slots = (int []) {
 139          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 140          PPIR_INSTR_SLOT_END
 141       },
 142    },
 143    [ppir_op_ceil] = {
 144       .name = "ceil",
 145       .slots = (int []) {
 146          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 147          PPIR_INSTR_SLOT_END
 148       },
 149    },
 150    [ppir_op_fract] = {
 151       .name = "fract",
 152       .slots = (int []) {
 153          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 154          PPIR_INSTR_SLOT_END
 155       },
 156    },
 157    [ppir_op_and] = {
 158       .name = "and",
 159       .slots = (int []) {
 160          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 161          PPIR_INSTR_SLOT_END
 162       },
 163    },
 164    [ppir_op_or] = {
 165       .name = "or",
 166       .slots = (int []) {
 167          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 168          PPIR_INSTR_SLOT_END
 169       },
 170    },
 171    [ppir_op_xor] = {
 172       .name = "xor",
 173       .slots = (int []) {
 174          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 175          PPIR_INSTR_SLOT_END
 176       },
 177    },
 178    [ppir_op_not] = {
 179       .name = "not",
 180       .slots = (int []) {
 181          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_VEC_MUL,
 182          PPIR_INSTR_SLOT_END
 183       },
 184    },
 185    [ppir_op_lt] = {
 186       .name = "lt",
 187    },
 188    [ppir_op_le] = {
 189       .name = "le",
 190    },
 191    [ppir_op_gt] = {
 192       .name = "gt",
 193       .slots = (int []) {
 194          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 195          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 196          PPIR_INSTR_SLOT_END
 197       },
 198    },
 199    [ppir_op_ge] = {
 200       .name = "ge",
 201       .slots = (int []) {
 202          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 203          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 204          PPIR_INSTR_SLOT_END
 205       },
 206    },
 207    [ppir_op_eq] = {
 208       .name = "eq",
 209       .slots = (int []) {
 210          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 211          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 212          PPIR_INSTR_SLOT_END
 213       },
 214    },
 215    [ppir_op_ne] = {
 216       .name = "ne",
 217       .slots = (int []) {
 218          PPIR_INSTR_SLOT_ALU_SCL_MUL, PPIR_INSTR_SLOT_ALU_SCL_ADD,
 219          PPIR_INSTR_SLOT_ALU_VEC_MUL, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 220          PPIR_INSTR_SLOT_END
 221       },
 222    },
 223    [ppir_op_select] = {
 224       .name = "select",
 225       .slots = (int []) {
 226          PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD,
 227          PPIR_INSTR_SLOT_END
 228       },
 229    },
 230    [ppir_op_rcp] = {
 231       .name = "rcp",
 232       .slots = (int []) {
 233          PPIR_INSTR_SLOT_ALU_COMBINE, PPIR_INSTR_SLOT_END
 234       },
 235    },
 236    [ppir_op_load_varying] = {
 237       .name = "ld_var",
 238       .type = ppir_node_type_load,
 239       .slots = (int []) {
 240          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 241       },
 242    },
 243    [ppir_op_load_coords] = {
 244       .name = "ld_coords",
 245       .type = ppir_node_type_load,
 246       .slots = (int []) {
 247          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 248       },
 249    },
 250    [ppir_op_load_fragcoord] = {
 251       .name = "ld_fragcoord",
 252       .type = ppir_node_type_load,
 253       .slots = (int []) {
 254          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 255       },
 256    },
 257    [ppir_op_load_pointcoord] = {
 258       .name = "ld_pointcoord",
 259       .type = ppir_node_type_load,
 260       .slots = (int []) {
 261          PPIR_INSTR_SLOT_VARYING, PPIR_INSTR_SLOT_END
 262       },
 263    },
 264    [ppir_op_load_uniform] = {
 265       .name = "ld_uni",
 266       .type = ppir_node_type_load,
 267       .slots = (int []) {
 268          PPIR_INSTR_SLOT_UNIFORM, PPIR_INSTR_SLOT_END
 269       },
 270    },
 271    [ppir_op_load_texture] = {
 272       .name = "ld_tex",
 273       .type = ppir_node_type_load_texture,
 274       .slots = (int []) {
 275          PPIR_INSTR_SLOT_TEXLD, PPIR_INSTR_SLOT_END
 276       },
 277    },
 278    [ppir_op_load_temp] = {
 279       .name = "ld_temp",
 280       .type = ppir_node_type_load,
 281       .slots = (int []) {
 282          PPIR_INSTR_SLOT_UNIFORM, PPIR_INSTR_SLOT_END
 283       },
 284    },
 285    [ppir_op_const] = {
 286       .name = "const",
 287       .type = ppir_node_type_const,
 288    },
 289    [ppir_op_store_color] = {
 290       .name = "st_col",
 291       .type = ppir_node_type_store,
 292    },
 293    [ppir_op_store_temp] = {
 294       .name = "st_temp",
 295       .type = ppir_node_type_store,
 296       .slots = (int []) {
 297          PPIR_INSTR_SLOT_STORE_TEMP, PPIR_INSTR_SLOT_END
 298       },
 299    },
 300    [ppir_op_discard] = {
 301       .name = "discard",
 302       .type = ppir_node_type_discard,
 303       .slots = (int []) {
 304          PPIR_INSTR_SLOT_BRANCH, PPIR_INSTR_SLOT_END
 305       },
 306    },
 307    [ppir_op_branch] = {
 308       .name = "branch",
 309       .type = ppir_node_type_branch,
 310       .slots = (int []) {
 311          PPIR_INSTR_SLOT_BRANCH, PPIR_INSTR_SLOT_END
 312       },
 313    },
 314 };
 315
 316 void *ppir_node_create(ppir_block *block, ppir_op op, int index, unsigned mask)
 317 {
 318    ppir_compiler *comp = block->comp;
 319    static const int node_size[] = {
 320       [ppir_node_type_alu] = sizeof(ppir_alu_node),
 321       [ppir_node_type_const] = sizeof(ppir_const_node),
 322       [ppir_node_type_load] = sizeof(ppir_load_node),
 323       [ppir_node_type_store] = sizeof(ppir_store_node),
 324       [ppir_node_type_load_texture] = sizeof(ppir_load_texture_node),
 325       [ppir_node_type_discard] = sizeof(ppir_discard_node),
 326       [ppir_node_type_branch] = sizeof(ppir_branch_node),
 327    };
 328
 329    ppir_node_type type = ppir_op_infos[op].type;
 330    int size = node_size[type];
 331    ppir_node *node = rzalloc_size(block, size);
 332    if (!node)
 333       return NULL;
 334
 335    list_inithead(&node->succ_list);
 336    list_inithead(&node->pred_list);
 337
 338    if (index >= 0) {
 339       if (mask) {
 340          /* reg has 4 slots for each componemt write node */
 341          while (mask)
 342             comp->var_nodes[(index << 2) + comp->reg_base + u_bit_scan(&mask)] = node;
 343          snprintf(node->name, sizeof(node->name), "reg%d", index);
 344       } else {
 345          comp->var_nodes[index] = node;
 346          snprintf(node->name, sizeof(node->name), "ssa%d", index);
 347       }
 348    }
 349    else
 350       snprintf(node->name, sizeof(node->name), "new");
 351
 352    node->op = op;
 353    node->type = type;
 354    node->index = comp->cur_index++;
 355    node->block = block;
 356
 357    return node;
 358 }
 359
 360 void ppir_node_add_dep(ppir_node *succ, ppir_node *pred)
 361 {
 362    /* don't add dep for two nodes from different block */
 363    if (succ->block != pred->block)
 364       return;
 365
 366    /* don't add duplicated dep */
 367    ppir_node_foreach_pred(succ, dep) {
 368       if (dep->pred == pred)
 369          return;
 370    }
 371
 372    ppir_dep *dep = ralloc(succ, ppir_dep);
 373    dep->pred = pred;
 374    dep->succ = succ;
 375    list_addtail(&dep->pred_link, &succ->pred_list);
 376    list_addtail(&dep->succ_link, &pred->succ_list);
 377 }
 378
 379 void ppir_node_remove_dep(ppir_dep *dep)
 380 {
 381    list_del(&dep->succ_link);
 382    list_del(&dep->pred_link);
 383    ralloc_free(dep);
 384 }
 385
 386 static void _ppir_node_replace_child(ppir_src *src, ppir_node *old_child, ppir_node *new_child)
 387 {
 388    ppir_dest *od = ppir_node_get_dest(old_child);
 389    if (ppir_node_target_equal(src, od)) {
 390       ppir_dest *nd = ppir_node_get_dest(new_child);
 391       ppir_node_target_assign(src, nd);
 392    }
 393 }
 394
 395 void ppir_node_replace_child(ppir_node *parent, ppir_node *old_child, ppir_node *new_child)
 396 {
 397    if (parent->type == ppir_node_type_alu) {
 398       ppir_alu_node *alu = ppir_node_to_alu(parent);
 399       for (int i = 0; i < alu->num_src; i++)
 400          _ppir_node_replace_child(alu->src + i, old_child, new_child);
 401    }
 402    else if (parent->type == ppir_node_type_store) {
 403       ppir_store_node *store = ppir_node_to_store(parent);
 404       _ppir_node_replace_child(&store->src, old_child, new_child);
 405    }
 406 }
 407
 408 void ppir_node_replace_pred(ppir_dep *dep, ppir_node *new_pred)
 409 {
 410    list_del(&dep->succ_link);
 411    dep->pred = new_pred;
 412    list_addtail(&dep->succ_link, &new_pred->succ_list);
 413 }
 414
 415 void ppir_node_replace_all_succ(ppir_node *dst, ppir_node *src)
 416 {
 417    ppir_node_foreach_succ_safe(src, dep) {
 418       ppir_node_replace_pred(dep, dst);
 419       ppir_node_replace_child(dep->succ, src, dst);
 420    }
 421 }
 422
 423 void ppir_node_delete(ppir_node *node)
 424 {
 425    ppir_node_foreach_succ_safe(node, dep)
 426       ppir_node_remove_dep(dep);
 427
 428    ppir_node_foreach_pred_safe(node, dep)
 429       ppir_node_remove_dep(dep);
 430
 431    list_del(&node->list);
 432    ralloc_free(node);
 433 }
 434
 435 static void ppir_node_print_node(ppir_node *node, int space)
 436 {
 437    for (int i = 0; i < space; i++)
 438       printf(" ");
 439    printf("%s%s %d %s\n", node->printed && !ppir_node_is_leaf(node) ? "+" : "",
 440           ppir_op_infos[node->op].name, node->index, node->name);
 441
 442    if (!node->printed) {
 443       ppir_node_foreach_pred(node, dep) {
 444          ppir_node *pred = dep->pred;
 445          ppir_node_print_node(pred, space + 2);
 446       }
 447
 448       node->printed = true;
 449    }
 450 }
 451
 452 void ppir_node_print_prog(ppir_compiler *comp)
 453 {
 454    if (!(lima_debug & LIMA_DEBUG_PP))
 455       return;
 456
 457    list_for_each_entry(ppir_block, block, &comp->block_list, list) {
 458       list_for_each_entry(ppir_node, node, &block->node_list, list) {
 459          node->printed = false;
 460       }
 461    }
 462
 463    printf("========prog========\n");
 464    list_for_each_entry(ppir_block, block, &comp->block_list, list) {
 465       printf("-------block------\n");
 466       list_for_each_entry(ppir_node, node, &block->node_list, list) {
 467          if (ppir_node_is_root(node))
 468             ppir_node_print_node(node, 0);
 469       }
 470    }
 471    printf("====================\n");
 472 }