6f2ff4090b4f0a320c4d1927770a3d4df4d363ff
[mesa.git] / src / gallium / drivers / lima / ir / pp / ppir.h
1 /*
2 * Copyright (c) 2017 Lima Project
3 * Copyright (c) 2013 Connor Abbott
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 * THE SOFTWARE.
22 *
23 */
24
25 #ifndef LIMA_IR_PP_PPIR_H
26 #define LIMA_IR_PP_PPIR_H
27
28 #include "util/u_math.h"
29 #include "util/list.h"
30 #include "util/set.h"
31
32 #include "ir/lima_ir.h"
33
34 typedef enum {
35 ppir_op_mov,
36 ppir_op_abs,
37 ppir_op_neg,
38 ppir_op_sat,
39 ppir_op_add,
40
41 ppir_op_ddx,
42 ppir_op_ddy,
43
44 ppir_op_mul,
45 ppir_op_rcp,
46
47 ppir_op_sin_lut,
48 ppir_op_cos_lut,
49
50 ppir_op_sum3,
51 ppir_op_sum4,
52
53 ppir_op_normalize2,
54 ppir_op_normalize3,
55 ppir_op_normalize4,
56
57 ppir_op_sel_cond,
58 ppir_op_select,
59
60 ppir_op_sin,
61 ppir_op_cos,
62 ppir_op_tan,
63 ppir_op_asin,
64 ppir_op_acos,
65
66 ppir_op_atan,
67 ppir_op_atan2,
68 ppir_op_atan_pt1,
69 ppir_op_atan2_pt1,
70 ppir_op_atan_pt2,
71
72 ppir_op_exp,
73 ppir_op_log,
74 ppir_op_exp2,
75 ppir_op_log2,
76 ppir_op_sqrt,
77 ppir_op_rsqrt,
78
79 ppir_op_sign,
80 ppir_op_floor,
81 ppir_op_ceil,
82 ppir_op_fract,
83 ppir_op_mod,
84 ppir_op_min,
85 ppir_op_max,
86 ppir_op_trunc,
87
88 ppir_op_and,
89 ppir_op_or,
90 ppir_op_xor,
91
92 ppir_op_lt,
93 ppir_op_gt,
94 ppir_op_le,
95 ppir_op_ge,
96 ppir_op_eq,
97 ppir_op_ne,
98 ppir_op_not,
99
100 ppir_op_load_uniform,
101 ppir_op_load_varying,
102 ppir_op_load_coords,
103 ppir_op_load_coords_reg,
104 ppir_op_load_fragcoord,
105 ppir_op_load_pointcoord,
106 ppir_op_load_frontface,
107 ppir_op_load_texture,
108 ppir_op_load_temp,
109
110 ppir_op_store_temp,
111 ppir_op_store_color,
112
113 ppir_op_const,
114
115 ppir_op_discard,
116 ppir_op_branch,
117
118 ppir_op_undef,
119 ppir_op_dummy,
120
121 ppir_op_num,
122 } ppir_op;
123
124 typedef enum {
125 ppir_node_type_alu,
126 ppir_node_type_const,
127 ppir_node_type_load,
128 ppir_node_type_store,
129 ppir_node_type_load_texture,
130 ppir_node_type_discard,
131 ppir_node_type_branch,
132 } ppir_node_type;
133
134 typedef struct {
135 char *name;
136 ppir_node_type type;
137 int *slots;
138 } ppir_op_info;
139
140 extern const ppir_op_info ppir_op_infos[];
141
142 typedef enum {
143 ppir_dep_src,
144 ppir_dep_write_after_read,
145 ppir_dep_sequence,
146 } ppir_dep_type;
147
148 typedef struct {
149 void *pred, *succ;
150 ppir_dep_type type;
151 struct list_head pred_link;
152 struct list_head succ_link;
153 } ppir_dep;
154
155 typedef struct ppir_node {
156 struct list_head list;
157 ppir_op op;
158 ppir_node_type type;
159 int index;
160 char name[16];
161 bool printed;
162 struct ppir_instr *instr;
163 int instr_pos;
164 struct ppir_block *block;
165
166 /* for scheduler */
167 struct list_head succ_list;
168 struct list_head pred_list;
169 } ppir_node;
170
171 typedef enum {
172 ppir_pipeline_reg_const0,
173 ppir_pipeline_reg_const1,
174 ppir_pipeline_reg_sampler,
175 ppir_pipeline_reg_uniform,
176 ppir_pipeline_reg_vmul,
177 ppir_pipeline_reg_fmul,
178 ppir_pipeline_reg_discard, /* varying load */
179 } ppir_pipeline;
180
181 typedef struct ppir_reg {
182 struct list_head list;
183 int index;
184 int regalloc_index;
185 int num_components;
186
187 /* whether this reg has to start from the x component
188 * of a full physical reg, this is true for reg used
189 * in load/store instr which has no swizzle field */
190 bool is_head;
191 bool spilled;
192 bool undef;
193 } ppir_reg;
194
195 typedef enum {
196 ppir_target_ssa,
197 ppir_target_pipeline,
198 ppir_target_register,
199 } ppir_target;
200
201 typedef struct ppir_src {
202 ppir_target type;
203 ppir_node *node;
204
205 union {
206 ppir_reg *ssa;
207 ppir_reg *reg;
208 ppir_pipeline pipeline;
209 };
210
211 uint8_t swizzle[4];
212 bool absolute, negate;
213 } ppir_src;
214
215 typedef enum {
216 ppir_outmod_none,
217 ppir_outmod_clamp_fraction,
218 ppir_outmod_clamp_positive,
219 ppir_outmod_round,
220 } ppir_outmod;
221
222 typedef struct ppir_dest {
223 ppir_target type;
224
225 union {
226 ppir_reg ssa;
227 ppir_reg *reg;
228 ppir_pipeline pipeline;
229 };
230
231 ppir_outmod modifier;
232 unsigned write_mask : 4;
233 } ppir_dest;
234
235 typedef struct {
236 ppir_node node;
237 ppir_dest dest;
238 ppir_src src[3];
239 int num_src;
240 int shift : 3; /* Only used for ppir_op_mul */
241 } ppir_alu_node;
242
243 typedef struct ppir_const {
244 union fi value[4];
245 int num;
246 } ppir_const;
247
248 typedef struct {
249 ppir_node node;
250 ppir_const constant;
251 ppir_dest dest;
252 } ppir_const_node;
253
254 typedef struct {
255 ppir_node node;
256 int index;
257 int num_components;
258 ppir_dest dest;
259 ppir_src src;
260 int num_src;
261 } ppir_load_node;
262
263 typedef struct {
264 ppir_node node;
265 int index;
266 int num_components;
267 ppir_src src;
268 } ppir_store_node;
269
270 typedef struct {
271 ppir_node node;
272 ppir_dest dest;
273 ppir_src src[2]; /* src[0] temporarily stores src_coords,
274 not to be used after lowering */
275 int num_src;
276 int sampler;
277 int sampler_dim;
278 bool lod_bias_en;
279 bool explicit_lod;
280 } ppir_load_texture_node;
281
282 typedef struct {
283 ppir_node node;
284 } ppir_discard_node;
285
286 enum ppir_instr_slot {
287 PPIR_INSTR_SLOT_VARYING,
288 PPIR_INSTR_SLOT_TEXLD,
289 PPIR_INSTR_SLOT_UNIFORM,
290 PPIR_INSTR_SLOT_ALU_VEC_MUL,
291 PPIR_INSTR_SLOT_ALU_SCL_MUL,
292 PPIR_INSTR_SLOT_ALU_VEC_ADD,
293 PPIR_INSTR_SLOT_ALU_SCL_ADD,
294 PPIR_INSTR_SLOT_ALU_COMBINE,
295 PPIR_INSTR_SLOT_STORE_TEMP,
296 PPIR_INSTR_SLOT_BRANCH,
297 PPIR_INSTR_SLOT_NUM,
298 PPIR_INSTR_SLOT_END,
299 PPIR_INSTR_SLOT_ALU_START = PPIR_INSTR_SLOT_ALU_VEC_MUL,
300 PPIR_INSTR_SLOT_ALU_END = PPIR_INSTR_SLOT_ALU_COMBINE,
301 };
302
303 struct ppir_liveness {
304 ppir_reg *reg;
305 unsigned mask : 4;
306 };
307
308 typedef struct ppir_instr {
309 struct list_head list;
310 int index;
311 bool printed;
312 int seq; /* command sequence after schedule */
313
314 ppir_node *slots[PPIR_INSTR_SLOT_NUM];
315 ppir_const constant[2];
316 bool is_end;
317
318 /* for scheduler */
319 struct list_head succ_list;
320 struct list_head pred_list;
321 float reg_pressure;
322 int est; /* earliest start time */
323 int parent_index;
324 bool scheduled;
325 int offset;
326 int encode_size;
327
328 /* for liveness analysis */
329 struct ppir_liveness *live_in;
330 struct ppir_liveness *live_out;
331 /* live_internal is to mark registers only live within an
332 * instruction, without propagation */
333 struct ppir_liveness *live_internal;
334 struct set *live_in_set;
335 struct set *live_out_set;
336 struct set *live_internal_set;
337 } ppir_instr;
338
339 typedef struct ppir_block {
340 struct list_head list;
341 struct list_head node_list;
342 struct list_head instr_list;
343
344 struct ppir_block *successors[2];
345
346 struct ppir_compiler *comp;
347
348 /* for scheduler */
349 int sched_instr_index;
350 int sched_instr_base;
351 int index;
352
353 /* for liveness analysis */
354 struct ppir_liveness *live_in;
355 struct ppir_liveness *live_out;
356 struct set *live_in_set;
357 struct set *live_out_set;
358 } ppir_block;
359
360 typedef struct {
361 ppir_node node;
362 ppir_src src[2];
363 int num_src;
364 bool cond_gt;
365 bool cond_eq;
366 bool cond_lt;
367 bool negate;
368 ppir_block *target;
369 } ppir_branch_node;
370
371 struct ra_regs;
372 struct lima_fs_shader_state;
373
374 typedef struct ppir_compiler {
375 struct list_head block_list;
376 struct hash_table_u64 *blocks;
377 int cur_index;
378 int cur_instr_index;
379
380 struct list_head reg_list;
381
382 /* array for searching ssa/reg node */
383 ppir_node **var_nodes;
384 unsigned reg_base;
385
386 struct ra_regs *ra;
387 struct lima_fs_shader_state *prog;
388
389 /* for scheduler */
390 int sched_instr_base;
391
392 /* for regalloc spilling debug */
393 int force_spilling;
394
395 /* shaderdb */
396 int num_loops;
397 int num_spills;
398 int num_fills;
399
400 ppir_block *discard_block;
401 ppir_block *current_block;
402 ppir_block *loop_break_block;
403 ppir_block *loop_cont_block;
404 } ppir_compiler;
405
406 void *ppir_node_create(ppir_block *block, ppir_op op, int index, unsigned mask);
407 void ppir_node_add_dep(ppir_node *succ, ppir_node *pred, ppir_dep_type type);
408 void ppir_node_remove_dep(ppir_dep *dep);
409 void ppir_node_delete(ppir_node *node);
410 void ppir_node_print_prog(ppir_compiler *comp);
411 void ppir_node_replace_child(ppir_node *parent, ppir_node *old_child, ppir_node *new_child);
412 void ppir_node_replace_all_succ(ppir_node *dst, ppir_node *src);
413 void ppir_node_replace_pred(ppir_dep *dep, ppir_node *new_pred);
414 void ppir_delete_if_orphan(ppir_block *block, ppir_node *node);
415 ppir_dep *ppir_dep_for_pred(ppir_node *node, ppir_node *pred);
416 ppir_node *ppir_node_clone(ppir_block *block, ppir_node *node);
417 /* Assumes that node successors are in the same block */
418 ppir_node *ppir_node_insert_mov(ppir_node *node);
419 ppir_node *ppir_node_insert_mov_all_blocks(ppir_node *node);
420
421 static inline bool ppir_node_is_root(ppir_node *node)
422 {
423 return list_is_empty(&node->succ_list);
424 }
425
426 static inline bool ppir_node_is_leaf(ppir_node *node)
427 {
428 return list_is_empty(&node->pred_list);
429 }
430
431 static inline bool ppir_node_has_single_succ(ppir_node *node)
432 {
433 return list_is_singular(&node->succ_list);
434 }
435
436 bool ppir_node_has_single_src_succ(ppir_node *node);
437
438 static inline ppir_node *ppir_node_first_succ(ppir_node *node)
439 {
440 return list_first_entry(&node->succ_list, ppir_dep, succ_link)->succ;
441 }
442
443 static inline bool ppir_node_has_single_pred(ppir_node *node)
444 {
445 return list_is_singular(&node->pred_list);
446 }
447
448 static inline ppir_node *ppir_node_first_pred(ppir_node *node)
449 {
450 return list_first_entry(&node->pred_list, ppir_dep, pred_link)->pred;
451 }
452
453 #define ppir_node_foreach_succ(node, dep) \
454 list_for_each_entry(ppir_dep, dep, &node->succ_list, succ_link)
455 #define ppir_node_foreach_succ_safe(node, dep) \
456 list_for_each_entry_safe(ppir_dep, dep, &node->succ_list, succ_link)
457 #define ppir_node_foreach_pred(node, dep) \
458 list_for_each_entry(ppir_dep, dep, &node->pred_list, pred_link)
459 #define ppir_node_foreach_pred_safe(node, dep) \
460 list_for_each_entry_safe(ppir_dep, dep, &node->pred_list, pred_link)
461
462 #define ppir_node_to_alu(node) ((ppir_alu_node *)(node))
463 #define ppir_node_to_const(node) ((ppir_const_node *)(node))
464 #define ppir_node_to_load(node) ((ppir_load_node *)(node))
465 #define ppir_node_to_store(node) ((ppir_store_node *)(node))
466 #define ppir_node_to_load_texture(node) ((ppir_load_texture_node *)(node))
467 #define ppir_node_to_discard(node) ((ppir_discard_node *)(node))
468 #define ppir_node_to_branch(node) ((ppir_branch_node *)(node))
469
470 static inline ppir_dest *ppir_node_get_dest(ppir_node *node)
471 {
472 switch (node->type) {
473 case ppir_node_type_alu:
474 return &ppir_node_to_alu(node)->dest;
475 case ppir_node_type_load:
476 return &ppir_node_to_load(node)->dest;
477 case ppir_node_type_const:
478 return &ppir_node_to_const(node)->dest;
479 case ppir_node_type_load_texture:
480 return &ppir_node_to_load_texture(node)->dest;
481 default:
482 return NULL;
483 }
484 }
485
486 static inline int ppir_node_get_src_num(ppir_node *node)
487 {
488 switch (node->type) {
489 case ppir_node_type_alu:
490 return ppir_node_to_alu(node)->num_src;
491 case ppir_node_type_branch:
492 return ppir_node_to_branch(node)->num_src;
493 case ppir_node_type_load:
494 return ppir_node_to_load(node)->num_src;
495 case ppir_node_type_load_texture:
496 return ppir_node_to_load_texture(node)->num_src;
497 case ppir_node_type_store:
498 return 1;
499 default:
500 return 0;
501 }
502
503 return 0;
504 }
505
506 static inline ppir_src *ppir_node_get_src(ppir_node *node, int idx)
507 {
508 if (idx < 0 || idx >= ppir_node_get_src_num(node))
509 return NULL;
510
511 switch (node->type) {
512 case ppir_node_type_alu:
513 return &ppir_node_to_alu(node)->src[idx];
514 case ppir_node_type_branch:
515 return &ppir_node_to_branch(node)->src[idx];
516 case ppir_node_type_load_texture:
517 return &ppir_node_to_load_texture(node)->src[idx];
518 case ppir_node_type_load:
519 return &ppir_node_to_load(node)->src;
520 case ppir_node_type_store:
521 return &ppir_node_to_store(node)->src;
522 default:
523 break;
524 }
525
526 return NULL;
527 }
528
529 static inline ppir_reg *ppir_src_get_reg(ppir_src *src)
530 {
531 switch (src->type) {
532 case ppir_target_ssa:
533 return src->ssa;
534 case ppir_target_register:
535 return src->reg;
536 default:
537 return NULL;
538 }
539 }
540
541 static inline ppir_reg *ppir_dest_get_reg(ppir_dest *dest)
542 {
543 switch (dest->type) {
544 case ppir_target_ssa:
545 return &dest->ssa;
546 case ppir_target_register:
547 return dest->reg;
548 default:
549 return NULL;
550 }
551 }
552
553 static inline ppir_src *ppir_node_get_src_for_pred(ppir_node *node, ppir_node *pred)
554 {
555 for (int i = 0; i < ppir_node_get_src_num(node); i++) {
556 ppir_src *src = ppir_node_get_src(node, i);
557 if (src && src->node == pred)
558 return src;
559 }
560
561 return NULL;
562 }
563
564 static inline void ppir_node_target_assign(ppir_src *src, ppir_node *node)
565 {
566 ppir_dest *dest = ppir_node_get_dest(node);
567 src->type = dest->type;
568 switch (src->type) {
569 case ppir_target_ssa:
570 src->ssa = &dest->ssa;
571 src->node = node;
572 break;
573 case ppir_target_register:
574 src->reg = dest->reg;
575 /* Registers can be assigned from multiple nodes, so don't keep
576 * pointer to the node here
577 */
578 src->node = NULL;
579 break;
580 case ppir_target_pipeline:
581 src->pipeline = dest->pipeline;
582 src->node = node;
583 break;
584 }
585 }
586
587 static inline bool ppir_node_target_equal(ppir_src *src, ppir_dest *dest)
588 {
589 if (src->type != dest->type ||
590 (src->type == ppir_target_ssa && src->ssa != &dest->ssa) ||
591 (src->type == ppir_target_register && src->reg != dest->reg) ||
592 (src->type == ppir_target_pipeline && src->pipeline != dest->pipeline))
593 return false;
594
595 return true;
596 }
597
598 static inline int ppir_target_get_src_reg_index(ppir_src *src)
599 {
600 switch (src->type) {
601 case ppir_target_ssa:
602 if (src->ssa)
603 return src->ssa->index;
604 break;
605 case ppir_target_register:
606 if (src->reg)
607 return src->reg->index;
608 break;
609 case ppir_target_pipeline:
610 if (src->pipeline == ppir_pipeline_reg_discard)
611 return 15 * 4;
612 return (src->pipeline + 12) * 4;
613 }
614
615 return -1;
616 }
617
618 static inline int ppir_target_get_dest_reg_index(ppir_dest *dest)
619 {
620 switch (dest->type) {
621 case ppir_target_ssa:
622 return dest->ssa.index;
623 case ppir_target_register:
624 return dest->reg->index;
625 case ppir_target_pipeline:
626 if (dest->pipeline == ppir_pipeline_reg_discard)
627 return 15 * 4;
628 return (dest->pipeline + 12) * 4;
629 }
630
631 return -1;
632 }
633
634 static inline int ppir_src_get_mask(ppir_src *src)
635 {
636 ppir_reg *reg = ppir_src_get_reg(src);
637 int mask = 0;
638
639 for (int i = 0; i < reg->num_components; i++)
640 mask |= (1 << src->swizzle[i]);
641
642 return mask;
643 }
644
645 static inline bool ppir_target_is_scaler(ppir_dest *dest)
646 {
647 switch (dest->type) {
648 case ppir_target_ssa:
649 return dest->ssa.num_components == 1;
650 case ppir_target_register:
651 /* only one bit in mask is set */
652 if ((dest->write_mask & 0x3) == 0x3 ||
653 (dest->write_mask & 0x5) == 0x5 ||
654 (dest->write_mask & 0x9) == 0x9 ||
655 (dest->write_mask & 0x6) == 0x6 ||
656 (dest->write_mask & 0xa) == 0xa ||
657 (dest->write_mask & 0xc) == 0xc)
658 return false;
659 else
660 return true;
661 case ppir_target_pipeline:
662 if (dest->pipeline == ppir_pipeline_reg_fmul)
663 return true;
664 else
665 return false;
666 default:
667 return false;
668 }
669 }
670
671 ppir_instr *ppir_instr_create(ppir_block *block);
672 bool ppir_instr_insert_node(ppir_instr *instr, ppir_node *node);
673 void ppir_instr_add_dep(ppir_instr *succ, ppir_instr *pred);
674 void ppir_instr_print_list(ppir_compiler *comp);
675 void ppir_instr_print_dep(ppir_compiler *comp);
676 void ppir_instr_insert_mul_node(ppir_node *add, ppir_node *mul);
677
678 #define ppir_instr_foreach_succ(instr, dep) \
679 list_for_each_entry(ppir_dep, dep, &instr->succ_list, succ_link)
680 #define ppir_instr_foreach_succ_safe(instr, dep) \
681 list_for_each_entry_safe(ppir_dep, dep, &instr->succ_list, succ_link)
682 #define ppir_instr_foreach_pred(instr, dep) \
683 list_for_each_entry(ppir_dep, dep, &instr->pred_list, pred_link)
684 #define ppir_instr_foreach_pred_safe(instr, dep) \
685 list_for_each_entry_safe(ppir_dep, dep, &instr->pred_list, pred_link)
686
687 static inline bool ppir_instr_is_root(ppir_instr *instr)
688 {
689 return list_is_empty(&instr->succ_list);
690 }
691
692 static inline bool ppir_instr_is_leaf(ppir_instr *instr)
693 {
694 return list_is_empty(&instr->pred_list);
695 }
696
697 bool ppir_lower_prog(ppir_compiler *comp);
698 bool ppir_node_to_instr(ppir_compiler *comp);
699 bool ppir_schedule_prog(ppir_compiler *comp);
700 bool ppir_regalloc_prog(ppir_compiler *comp);
701 bool ppir_codegen_prog(ppir_compiler *comp);
702 void ppir_liveness_analysis(ppir_compiler *comp);
703
704 #endif