src/gallium/drivers/lima/lima_screen.c

   1 /*
   2  * Copyright (c) 2017-2019 Lima Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <string.h>
  26
  27 #include "util/ralloc.h"
  28 #include "util/u_debug.h"
  29 #include "util/u_screen.h"
  30 #include "renderonly/renderonly.h"
  31
  32 #include "drm-uapi/drm_fourcc.h"
  33 #include "drm-uapi/lima_drm.h"
  34
  35 #include "lima_screen.h"
  36 #include "lima_context.h"
  37 #include "lima_resource.h"
  38 #include "lima_program.h"
  39 #include "lima_bo.h"
  40 #include "lima_fence.h"
  41 #include "lima_format.h"
  42 #include "lima_util.h"
  43 #include "ir/lima_ir.h"
  44
  45 #include "xf86drm.h"
  46
  47 int lima_plb_max_blk = 0;
  48
  49 static void
  50 lima_screen_destroy(struct pipe_screen *pscreen)
  51 {
  52    struct lima_screen *screen = lima_screen(pscreen);
  53
  54    lima_dump_file_close();
  55
  56    slab_destroy_parent(&screen->transfer_pool);
  57
  58    if (screen->ro)
  59       free(screen->ro);
  60
  61    if (screen->pp_buffer)
  62       lima_bo_unreference(screen->pp_buffer);
  63
  64    lima_bo_cache_fini(screen);
  65    lima_bo_table_fini(screen);
  66    ralloc_free(screen);
  67 }
  68
  69 static const char *
  70 lima_screen_get_name(struct pipe_screen *pscreen)
  71 {
  72    struct lima_screen *screen = lima_screen(pscreen);
  73
  74    switch (screen->gpu_type) {
  75    case DRM_LIMA_PARAM_GPU_ID_MALI400:
  76      return "Mali400";
  77    case DRM_LIMA_PARAM_GPU_ID_MALI450:
  78      return "Mali450";
  79    }
  80
  81    return NULL;
  82 }
  83
  84 static const char *
  85 lima_screen_get_vendor(struct pipe_screen *pscreen)
  86 {
  87    return "lima";
  88 }
  89
  90 static const char *
  91 lima_screen_get_device_vendor(struct pipe_screen *pscreen)
  92 {
  93    return "ARM";
  94 }
  95
  96 static int
  97 lima_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  98 {
  99    switch (param) {
 100    case PIPE_CAP_NPOT_TEXTURES:
 101    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 102    case PIPE_CAP_ACCELERATED:
 103    case PIPE_CAP_UMA:
 104    case PIPE_CAP_NATIVE_FENCE_FD:
 105    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 106       return 1;
 107
 108    /* Unimplemented, but for exporting OpenGL 2.0 */
 109    case PIPE_CAP_OCCLUSION_QUERY:
 110    case PIPE_CAP_POINT_SPRITE:
 111       return 1;
 112
 113    /* not clear supported */
 114    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 115    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 116    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 117    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 118       return 1;
 119
 120    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 121    case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
 122    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 123       return 1;
 124
 125    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 126       return 1 << (LIMA_MAX_MIP_LEVELS - 1);
 127    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 128    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 129       return LIMA_MAX_MIP_LEVELS;
 130
 131    case PIPE_CAP_VENDOR_ID:
 132       return 0x13B5;
 133
 134    case PIPE_CAP_VIDEO_MEMORY:
 135       return 0;
 136
 137    case PIPE_CAP_PCI_GROUP:
 138    case PIPE_CAP_PCI_BUS:
 139    case PIPE_CAP_PCI_DEVICE:
 140    case PIPE_CAP_PCI_FUNCTION:
 141       return 0;
 142
 143    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 144       return 0;
 145
 146    case PIPE_CAP_ALPHA_TEST:
 147    case PIPE_CAP_FLATSHADE:
 148    case PIPE_CAP_TWO_SIDED_COLOR:
 149    case PIPE_CAP_CLIP_PLANES:
 150       return 0;
 151
 152    default:
 153       return u_pipe_screen_get_param_defaults(pscreen, param);
 154    }
 155 }
 156
 157 static float
 158 lima_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 159 {
 160    switch (param) {
 161    case PIPE_CAPF_MAX_LINE_WIDTH:
 162    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 163    case PIPE_CAPF_MAX_POINT_WIDTH:
 164    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 165       return 100.0f;
 166    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 167       return 16.0f;
 168    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 169       return 16.0f;
 170
 171    default:
 172       return 0.0f;
 173    }
 174 }
 175
 176 static int
 177 get_vertex_shader_param(struct lima_screen *screen,
 178                         enum pipe_shader_cap param)
 179 {
 180    switch (param) {
 181    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 182    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 183    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 184    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 185       return 16384; /* need investigate */
 186
 187    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 188       return 1024;
 189
 190    case PIPE_SHADER_CAP_MAX_INPUTS:
 191       return 16; /* attributes */
 192
 193    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 194       return LIMA_MAX_VARYING_NUM; /* varying */
 195
 196    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 197       return 16 * 1024 * sizeof(float);
 198
 199    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 200       return 1;
 201
 202    case PIPE_SHADER_CAP_PREFERRED_IR:
 203       return PIPE_SHADER_IR_NIR;
 204
 205    case PIPE_SHADER_CAP_MAX_TEMPS:
 206       return 256; /* need investigate */
 207
 208    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 209       return 32;
 210
 211    default:
 212       return 0;
 213    }
 214 }
 215
 216 static int
 217 get_fragment_shader_param(struct lima_screen *screen,
 218                           enum pipe_shader_cap param)
 219 {
 220    switch (param) {
 221    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 222    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 223    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 224    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 225       return 16384; /* need investigate */
 226
 227    case PIPE_SHADER_CAP_MAX_INPUTS:
 228       return LIMA_MAX_VARYING_NUM - 1; /* varying, minus gl_Position */
 229
 230    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 231       return 1024;
 232
 233    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 234       return 16 * 1024 * sizeof(float);
 235
 236    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 237       return 1;
 238
 239    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 240       return 16; /* need investigate */
 241
 242    case PIPE_SHADER_CAP_PREFERRED_IR:
 243       return PIPE_SHADER_IR_NIR;
 244
 245    case PIPE_SHADER_CAP_MAX_TEMPS:
 246       return 256; /* need investigate */
 247
 248    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 249    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 250       return 1;
 251
 252    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 253    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 254       return 0;
 255
 256    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 257       return 32;
 258
 259    default:
 260       return 0;
 261    }
 262 }
 263
 264 static int
 265 lima_screen_get_shader_param(struct pipe_screen *pscreen,
 266                              enum pipe_shader_type shader,
 267                              enum pipe_shader_cap param)
 268 {
 269    struct lima_screen *screen = lima_screen(pscreen);
 270
 271    switch (shader) {
 272    case PIPE_SHADER_FRAGMENT:
 273       return get_fragment_shader_param(screen, param);
 274    case PIPE_SHADER_VERTEX:
 275       return get_vertex_shader_param(screen, param);
 276
 277    default:
 278       return 0;
 279    }
 280 }
 281
 282 static bool
 283 lima_screen_is_format_supported(struct pipe_screen *pscreen,
 284                                 enum pipe_format format,
 285                                 enum pipe_texture_target target,
 286                                 unsigned sample_count,
 287                                 unsigned storage_sample_count,
 288                                 unsigned usage)
 289 {
 290    switch (target) {
 291    case PIPE_BUFFER:
 292    case PIPE_TEXTURE_1D:
 293    case PIPE_TEXTURE_2D:
 294    case PIPE_TEXTURE_RECT:
 295    case PIPE_TEXTURE_CUBE:
 296       break;
 297    default:
 298       return false;
 299    }
 300
 301    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
 302       return false;
 303
 304    /* be able to support 16, now limit to 4 */
 305    if (sample_count > 1 && sample_count != 4)
 306       return false;
 307
 308    if (usage & PIPE_BIND_RENDER_TARGET &&
 309        !lima_format_pixel_supported(format))
 310       return false;
 311
 312    if (usage & PIPE_BIND_DEPTH_STENCIL) {
 313       switch (format) {
 314       case PIPE_FORMAT_Z16_UNORM:
 315       case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 316       case PIPE_FORMAT_Z24X8_UNORM:
 317          break;
 318       default:
 319          return false;
 320       }
 321    }
 322
 323    if (usage & PIPE_BIND_VERTEX_BUFFER) {
 324       switch (format) {
 325       case PIPE_FORMAT_R32G32B32_FLOAT:
 326          break;
 327       default:
 328          return false;
 329       }
 330    }
 331
 332    if (usage & PIPE_BIND_INDEX_BUFFER) {
 333       switch (format) {
 334       case PIPE_FORMAT_I8_UINT:
 335       case PIPE_FORMAT_I16_UINT:
 336       case PIPE_FORMAT_I32_UINT:
 337          break;
 338       default:
 339          return false;
 340       }
 341    }
 342
 343    if (usage & PIPE_BIND_SAMPLER_VIEW)
 344       return lima_format_texel_supported(format);
 345
 346    return true;
 347 }
 348
 349 static const void *
 350 lima_screen_get_compiler_options(struct pipe_screen *pscreen,
 351                                  enum pipe_shader_ir ir,
 352                                  enum pipe_shader_type shader)
 353 {
 354    return lima_program_get_compiler_options(shader);
 355 }
 356
 357 static bool
 358 lima_screen_set_plb_max_blk(struct lima_screen *screen)
 359 {
 360    if (lima_plb_max_blk) {
 361       screen->plb_max_blk = lima_plb_max_blk;
 362       return true;
 363    }
 364
 365    if (screen->gpu_type == DRM_LIMA_PARAM_GPU_ID_MALI450)
 366       screen->plb_max_blk = 4096;
 367    else
 368       screen->plb_max_blk = 512;
 369
 370    drmDevicePtr devinfo;
 371
 372    if (drmGetDevice2(screen->fd, 0, &devinfo))
 373       return false;
 374
 375    if (devinfo->bustype == DRM_BUS_PLATFORM && devinfo->deviceinfo.platform) {
 376       char **compatible = devinfo->deviceinfo.platform->compatible;
 377
 378       if (compatible && *compatible)
 379          if (!strcmp("allwinner,sun50i-h5-mali", *compatible))
 380             screen->plb_max_blk = 2048;
 381    }
 382
 383    drmFreeDevice(&devinfo);
 384
 385    return true;
 386 }
 387
 388 static bool
 389 lima_screen_query_info(struct lima_screen *screen)
 390 {
 391    struct drm_lima_get_param param;
 392
 393    memset(&param, 0, sizeof(param));
 394    param.param = DRM_LIMA_PARAM_GPU_ID;
 395    if (drmIoctl(screen->fd, DRM_IOCTL_LIMA_GET_PARAM, &param))
 396       return false;
 397
 398    switch (param.value) {
 399    case DRM_LIMA_PARAM_GPU_ID_MALI400:
 400    case DRM_LIMA_PARAM_GPU_ID_MALI450:
 401       screen->gpu_type = param.value;
 402       break;
 403    default:
 404       return false;
 405    }
 406
 407    memset(&param, 0, sizeof(param));
 408    param.param = DRM_LIMA_PARAM_NUM_PP;
 409    if (drmIoctl(screen->fd, DRM_IOCTL_LIMA_GET_PARAM, &param))
 410       return false;
 411
 412    screen->num_pp = param.value;
 413
 414    lima_screen_set_plb_max_blk(screen);
 415
 416    return true;
 417 }
 418
 419 static void
 420 lima_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
 421                                    enum pipe_format format, int max,
 422                                    uint64_t *modifiers,
 423                                    unsigned int *external_only,
 424                                    int *count)
 425 {
 426    uint64_t available_modifiers[] = {
 427       DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED,
 428       DRM_FORMAT_MOD_LINEAR,
 429    };
 430
 431    if (!modifiers) {
 432       *count = ARRAY_SIZE(available_modifiers);
 433       return;
 434    }
 435
 436    for (int i = 0; i < *count; i++) {
 437       modifiers[i] = available_modifiers[i];
 438       if (external_only)
 439          external_only = false;
 440    }
 441 }
 442
 443 static const struct debug_named_value debug_options[] = {
 444         { "gp",       LIMA_DEBUG_GP,
 445           "print GP shader compiler result of each stage" },
 446         { "pp",       LIMA_DEBUG_PP,
 447           "print PP shader compiler result of each stage" },
 448         { "dump",     LIMA_DEBUG_DUMP,
 449           "dump GPU command stream to $PWD/lima.dump" },
 450         { "shaderdb", LIMA_DEBUG_SHADERDB,
 451           "print shader information for shaderdb" },
 452         { "nobocache", LIMA_DEBUG_NO_BO_CACHE,
 453           "disable BO cache" },
 454         { "bocache", LIMA_DEBUG_BO_CACHE,
 455           "print debug info for BO cache" },
 456         { "notiling", LIMA_DEBUG_NO_TILING,
 457           "don't use tiled buffers" },
 458         { NULL }
 459 };
 460
 461 DEBUG_GET_ONCE_FLAGS_OPTION(lima_debug, "LIMA_DEBUG", debug_options, 0)
 462 uint32_t lima_debug;
 463
 464 static void
 465 lima_screen_parse_env(void)
 466 {
 467    lima_debug = debug_get_option_lima_debug();
 468
 469    if (lima_debug & LIMA_DEBUG_DUMP)
 470       lima_dump_file_open();
 471
 472    lima_ctx_num_plb = debug_get_num_option("LIMA_CTX_NUM_PLB", LIMA_CTX_PLB_DEF_NUM);
 473    if (lima_ctx_num_plb > LIMA_CTX_PLB_MAX_NUM ||
 474        lima_ctx_num_plb < LIMA_CTX_PLB_MIN_NUM) {
 475       fprintf(stderr, "lima: LIMA_CTX_NUM_PLB %d out of range [%d %d], "
 476               "reset to default %d\n", lima_ctx_num_plb, LIMA_CTX_PLB_MIN_NUM,
 477               LIMA_CTX_PLB_MAX_NUM, LIMA_CTX_PLB_DEF_NUM);
 478       lima_ctx_num_plb = LIMA_CTX_PLB_DEF_NUM;
 479    }
 480
 481    lima_plb_max_blk = debug_get_num_option("LIMA_PLB_MAX_BLK", 0);
 482    if (lima_plb_max_blk < 0 || lima_plb_max_blk > 65536) {
 483       fprintf(stderr, "lima: LIMA_PLB_MAX_BLK %d out of range [%d %d], "
 484               "reset to default %d\n", lima_plb_max_blk, 0, 65536, 0);
 485       lima_plb_max_blk = 0;
 486    }
 487
 488    lima_ppir_force_spilling = debug_get_num_option("LIMA_PPIR_FORCE_SPILLING", 0);
 489    if (lima_ppir_force_spilling < 0) {
 490       fprintf(stderr, "lima: LIMA_PPIR_FORCE_SPILLING %d less than 0, "
 491               "reset to default 0\n", lima_ppir_force_spilling);
 492       lima_ppir_force_spilling = 0;
 493    }
 494 }
 495
 496 struct pipe_screen *
 497 lima_screen_create(int fd, struct renderonly *ro)
 498 {
 499    struct lima_screen *screen;
 500
 501    screen = rzalloc(NULL, struct lima_screen);
 502    if (!screen)
 503       return NULL;
 504
 505    screen->fd = fd;
 506
 507    lima_screen_parse_env();
 508
 509    if (!lima_screen_query_info(screen))
 510       goto err_out0;
 511
 512    if (!lima_bo_cache_init(screen))
 513       goto err_out0;
 514
 515    if (!lima_bo_table_init(screen))
 516       goto err_out1;
 517
 518    screen->pp_ra = ppir_regalloc_init(screen);
 519    if (!screen->pp_ra)
 520       goto err_out2;
 521
 522    screen->pp_buffer = lima_bo_create(screen, pp_buffer_size, 0);
 523    if (!screen->pp_buffer)
 524       goto err_out2;
 525    screen->pp_buffer->cacheable = false;
 526
 527    /* fs program for clear buffer?
 528     * const0 1 0 0 -1.67773, mov.v0 $0 ^const0.xxxx, stop
 529     */
 530    static const uint32_t pp_clear_program[] = {
 531       0x00020425, 0x0000000c, 0x01e007cf, 0xb0000000,
 532       0x000005f5, 0x00000000, 0x00000000, 0x00000000,
 533    };
 534    memcpy(lima_bo_map(screen->pp_buffer) + pp_clear_program_offset,
 535           pp_clear_program, sizeof(pp_clear_program));
 536
 537    /* copy texture to framebuffer, used to reload gpu tile buffer
 538     * load.v $1 0.xy, texld_2d 0, mov.v0 $0 ^tex_sampler, sync, stop
 539     */
 540    static const uint32_t pp_reload_program[] = {
 541       0x000005e6, 0xf1003c20, 0x00000000, 0x39001000,
 542       0x00000e4e, 0x000007cf, 0x00000000, 0x00000000,
 543    };
 544    memcpy(lima_bo_map(screen->pp_buffer) + pp_reload_program_offset,
 545           pp_reload_program, sizeof(pp_reload_program));
 546
 547    /* 0/1/2 vertex index for reload/clear draw */
 548    static const uint8_t pp_shared_index[] = { 0, 1, 2 };
 549    memcpy(lima_bo_map(screen->pp_buffer) + pp_shared_index_offset,
 550           pp_shared_index, sizeof(pp_shared_index));
 551
 552    /* 4096x4096 gl pos used for partial clear */
 553    static const float pp_clear_gl_pos[] = {
 554       4096, 0,    1, 1,
 555       0,    0,    1, 1,
 556       0,    4096, 1, 1,
 557    };
 558    memcpy(lima_bo_map(screen->pp_buffer) + pp_clear_gl_pos_offset,
 559           pp_clear_gl_pos, sizeof(pp_clear_gl_pos));
 560
 561    /* is pp frame render state static? */
 562    uint32_t *pp_frame_rsw = lima_bo_map(screen->pp_buffer) + pp_frame_rsw_offset;
 563    memset(pp_frame_rsw, 0, 0x40);
 564    pp_frame_rsw[8] = 0x0000f008;
 565    pp_frame_rsw[9] = screen->pp_buffer->va + pp_clear_program_offset;
 566    pp_frame_rsw[13] = 0x00000100;
 567
 568    if (ro) {
 569       screen->ro = renderonly_dup(ro);
 570       if (!screen->ro) {
 571          fprintf(stderr, "Failed to dup renderonly object\n");
 572          goto err_out3;
 573       }
 574    }
 575
 576    screen->base.destroy = lima_screen_destroy;
 577    screen->base.get_name = lima_screen_get_name;
 578    screen->base.get_vendor = lima_screen_get_vendor;
 579    screen->base.get_device_vendor = lima_screen_get_device_vendor;
 580    screen->base.get_param = lima_screen_get_param;
 581    screen->base.get_paramf = lima_screen_get_paramf;
 582    screen->base.get_shader_param = lima_screen_get_shader_param;
 583    screen->base.context_create = lima_context_create;
 584    screen->base.is_format_supported = lima_screen_is_format_supported;
 585    screen->base.get_compiler_options = lima_screen_get_compiler_options;
 586    screen->base.query_dmabuf_modifiers = lima_screen_query_dmabuf_modifiers;
 587
 588    lima_resource_screen_init(screen);
 589    lima_fence_screen_init(screen);
 590
 591    slab_create_parent(&screen->transfer_pool, sizeof(struct lima_transfer), 16);
 592
 593    screen->refcnt = 1;
 594
 595    return &screen->base;
 596
 597 err_out3:
 598    lima_bo_unreference(screen->pp_buffer);
 599 err_out2:
 600    lima_bo_table_fini(screen);
 601 err_out1:
 602    lima_bo_cache_fini(screen);
 603 err_out0:
 604    ralloc_free(screen);
 605    return NULL;
 606 }