src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h

   1 /*
   2  * Copyright 2011 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #ifndef __NV50_IR_DRIVER_H__
  24 #define __NV50_IR_DRIVER_H__
  25
  26 #include "pipe/p_shader_tokens.h"
  27
  28 #include "util/blob.h"
  29 #include "tgsi/tgsi_util.h"
  30 #include "tgsi/tgsi_parse.h"
  31 #include "tgsi/tgsi_scan.h"
  32
  33 struct nir_shader_compiler_options;
  34
  35 /*
  36  * This struct constitutes linkage information in TGSI terminology.
  37  *
  38  * It is created by the code generator and handed to the pipe driver
  39  * for input/output slot assignment.
  40  */
  41 struct nv50_ir_varying
  42 {
  43    uint8_t slot[4]; /* native slots for xyzw (addresses in 32-bit words) */
  44
  45    unsigned mask     : 4; /* vec4 mask */
  46    unsigned linear   : 1; /* linearly interpolated if true (and not flat) */
  47    unsigned flat     : 1;
  48    unsigned sc       : 1; /* special colour interpolation mode (SHADE_MODEL) */
  49    unsigned centroid : 1;
  50    unsigned patch    : 1; /* patch constant value */
  51    unsigned regular  : 1; /* driver-specific meaning (e.g. input in sreg) */
  52    unsigned input    : 1; /* indicates direction of system values */
  53    unsigned oread    : 1; /* true if output is read from parallel TCP */
  54
  55    ubyte id; /* TGSI register index */
  56    ubyte sn; /* TGSI semantic name */
  57    ubyte si; /* TGSI semantic index */
  58 };
  59
  60 #ifndef NDEBUG
  61 # define NV50_IR_DEBUG_BASIC     (1 << 0)
  62 # define NV50_IR_DEBUG_VERBOSE   (2 << 0)
  63 # define NV50_IR_DEBUG_REG_ALLOC (1 << 2)
  64 #else
  65 # define NV50_IR_DEBUG_BASIC     0
  66 # define NV50_IR_DEBUG_VERBOSE   0
  67 # define NV50_IR_DEBUG_REG_ALLOC 0
  68 #endif
  69
  70 struct nv50_ir_prog_symbol
  71 {
  72    uint32_t label;
  73    uint32_t offset;
  74 };
  75
  76 #define NVISA_GF100_CHIPSET    0xc0
  77 #define NVISA_GK104_CHIPSET    0xe0
  78 #define NVISA_GK20A_CHIPSET    0xea
  79 #define NVISA_GM107_CHIPSET    0x110
  80 #define NVISA_GM200_CHIPSET    0x120
  81 #define NVISA_GV100_CHIPSET    0x140
  82
  83 struct nv50_ir_prog_info_out;
  84
  85 /* used for the input data and assignSlot interface */
  86 struct nv50_ir_prog_info
  87 {
  88    uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */
  89
  90    uint8_t type; /* PIPE_SHADER */
  91
  92    uint8_t optLevel; /* optimization level (0 to 3) */
  93    uint8_t dbgFlags;
  94    bool omitLineNum; /* only used for printing the prog when dbgFlags is set */
  95
  96    struct {
  97       uint32_t smemSize;  /* required shared memory per block */
  98       uint8_t sourceRep;  /* PIPE_SHADER_IR_* */
  99       const void *source;
 100    } bin;
 101
 102    union {
 103       struct {
 104          uint32_t inputOffset; /* base address for user args */
 105          uint32_t gridInfoBase;  /* base address for NTID,NCTAID */
 106          uint16_t numThreads[3]; /* max number of threads */
 107       } cp;
 108    } prop;
 109
 110    struct {
 111       int8_t genUserClip;        /* request user clip planes for ClipVertex */
 112       uint8_t auxCBSlot;         /* driver constant buffer slot */
 113       uint16_t ucpBase;          /* base address for UCPs */
 114       uint16_t drawInfoBase;     /* base address for draw parameters */
 115       uint16_t alphaRefBase;     /* base address for alpha test values */
 116       int8_t viewportId;         /* output index of ViewportIndex */
 117       bool mul_zero_wins;        /* program wants for x*0 = 0 */
 118       bool nv50styleSurfaces;    /* generate gX[] access for raw buffers */
 119       uint16_t texBindBase;      /* base address for tex handles (nve4) */
 120       uint16_t fbtexBindBase;    /* base address for fbtex handle (nve4) */
 121       uint16_t suInfoBase;       /* base address for surface info (nve4) */
 122       uint16_t bindlessBase;     /* base address for bindless image info (nve4) */
 123       uint16_t bufInfoBase;      /* base address for buffer info */
 124       uint16_t sampleInfoBase;   /* base address for sample positions */
 125       uint8_t msInfoCBSlot;      /* cX[] used for multisample info */
 126       uint16_t msInfoBase;       /* base address for multisample info */
 127       uint16_t uboInfoBase;      /* base address for compute UBOs (gk104+) */
 128    } io;
 129
 130    /* driver callback to assign input/output locations */
 131    int (*assignSlots)(struct nv50_ir_prog_info_out *);
 132 };
 133
 134 /* the produced binary with metadata */
 135 struct nv50_ir_prog_info_out
 136 {
 137    uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */
 138
 139    uint8_t type; /* PIPE_SHADER */
 140
 141    struct {
 142       int16_t maxGPR;     /* may be -1 if none used */
 143       uint32_t tlsSpace;  /* required local memory per thread */
 144       uint32_t smemSize;  /* required shared memory per block */
 145       uint32_t *code;
 146       uint32_t codeSize;
 147       uint32_t instructions;
 148       void *relocData;
 149       void *fixupData;
 150    } bin;
 151
 152    struct nv50_ir_varying sv[PIPE_MAX_SHADER_INPUTS];
 153    struct nv50_ir_varying in[PIPE_MAX_SHADER_INPUTS];
 154    struct nv50_ir_varying out[PIPE_MAX_SHADER_OUTPUTS];
 155    uint8_t numInputs;
 156    uint8_t numOutputs;
 157    uint8_t numPatchConstants; /* also included in numInputs/numOutputs */
 158    uint8_t numSysVals;
 159
 160    union {
 161       struct {
 162          bool usesDrawParameters;
 163       } vp;
 164       struct {
 165          uint8_t outputPatchSize;
 166          uint8_t partitioning;    /* PIPE_TESS_PART */
 167          int8_t winding;          /* +1 (clockwise) / -1 (counter-clockwise) */
 168          uint8_t domain;          /* PIPE_PRIM_{QUADS,TRIANGLES,LINES} */
 169          uint8_t outputPrim;      /* PIPE_PRIM_{TRIANGLES,LINES,POINTS} */
 170       } tp;
 171       struct {
 172          uint8_t outputPrim;
 173          unsigned instanceCount;
 174          unsigned maxVertices;
 175       } gp;
 176       struct {
 177          unsigned numColourResults;
 178          bool writesDepth           : 1;
 179          bool earlyFragTests        : 1;
 180          bool postDepthCoverage     : 1;
 181          bool usesDiscard           : 1;
 182          bool usesSampleMaskIn      : 1;
 183          bool readsFramebuffer      : 1;
 184          bool readsSampleLocations  : 1;
 185          bool separateFragData      : 1;
 186       } fp;
 187    } prop;
 188
 189    struct {
 190       uint8_t clipDistances;     /* number of clip distance outputs */
 191       uint8_t cullDistances;     /* number of cull distance outputs */
 192       int8_t genUserClip;        /* request user clip planes for ClipVertex */
 193       uint8_t instanceId;        /* system value index of InstanceID */
 194       uint8_t vertexId;          /* system value index of VertexID */
 195       uint8_t edgeFlagIn;
 196       uint8_t edgeFlagOut;
 197       uint8_t fragDepth;         /* output index of FragDepth */
 198       uint8_t sampleMask;        /* output index of SampleMask */
 199       uint8_t globalAccess;      /* 1 for read, 2 for wr, 3 for rw */
 200       bool fp64;                 /* program uses fp64 math */
 201       bool layer_viewport_relative;
 202    } io;
 203
 204    uint8_t numBarriers;
 205
 206    void *driverPriv;
 207 };
 208
 209 #ifdef __cplusplus
 210 extern "C" {
 211 #endif
 212
 213 const struct nir_shader_compiler_options *
 214 nv50_ir_nir_shader_compiler_options(int chipset);
 215
 216 extern int nv50_ir_generate_code(struct nv50_ir_prog_info *,
 217                                  struct nv50_ir_prog_info_out *);
 218
 219 extern void nv50_ir_relocate_code(void *relocData, uint32_t *code,
 220                                   uint32_t codePos,
 221                                   uint32_t libPos,
 222                                   uint32_t dataPos);
 223
 224 extern void
 225 nv50_ir_apply_fixups(void *fixupData, uint32_t *code,
 226                      bool force_per_sample, bool flatshade,
 227                      uint8_t alphatest);
 228
 229 /* obtain code that will be shared among programs */
 230 extern void nv50_ir_get_target_library(uint32_t chipset,
 231                                        const uint32_t **code, uint32_t *size);
 232
 233
 234 #ifdef __cplusplus
 235 namespace nv50_ir
 236 {
 237    class FixupEntry;
 238    class FixupData;
 239
 240    void
 241    gk110_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code,
 242                      const nv50_ir::FixupData& data);
 243    void
 244    gm107_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code,
 245                      const nv50_ir::FixupData& data);
 246    void
 247    nv50_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code,
 248                     const nv50_ir::FixupData& data);
 249    void
 250    nvc0_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code,
 251                     const nv50_ir::FixupData& data);
 252    void
 253    gv100_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code,
 254                      const nv50_ir::FixupData& data);
 255    void
 256    gk110_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code,
 257                   const nv50_ir::FixupData& data);
 258    void
 259    gm107_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code,
 260                   const nv50_ir::FixupData& data);
 261    void
 262    nvc0_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code,
 263                  const nv50_ir::FixupData& data);
 264    void
 265    gv100_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code,
 266                   const nv50_ir::FixupData& data);
 267 }
 268 #endif
 269
 270 /* Serialize a nv50_ir_prog_info_out structure and save it into blob */
 271 extern bool MUST_CHECK
 272 nv50_ir_prog_info_out_serialize(struct blob *, struct nv50_ir_prog_info_out *);
 273
 274 /* Deserialize from data and save into a nv50_ir_prog_info_out structure
 275  * using a pointer. Size is a total size of the serialized data.
 276  * Offset points to where info_out in data is located. */
 277 extern bool MUST_CHECK
 278 nv50_ir_prog_info_out_deserialize(void *data, size_t size, size_t offset,
 279                                   struct nv50_ir_prog_info_out *);
 280
 281 #ifdef __cplusplus
 282 }
 283 #endif
 284
 285 #endif // __NV50_IR_DRIVER_H__