src/gallium/drivers/nouveau/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28
  29 #include "nv_object.xml.h"
  30 #include "nv_m2mf.xml.h"
  31 #include "nv30/nv30-40_3d.xml.h"
  32 #include "nv30/nv01_2d.xml.h"
  33
  34 #include "nouveau_fence.h"
  35 #include "nv30/nv30_screen.h"
  36 #include "nv30/nv30_context.h"
  37 #include "nv30/nv30_resource.h"
  38 #include "nv30/nv30_format.h"
  39
  40 #define RANKINE_0397_CHIPSET 0x00000003
  41 #define RANKINE_0497_CHIPSET 0x000001e0
  42 #define RANKINE_0697_CHIPSET 0x00000010
  43 #define CURIE_4097_CHIPSET   0x00000baf
  44 #define CURIE_4497_CHIPSET   0x00005450
  45 #define CURIE_4497_CHIPSET6X 0x00000088
  46
  47 static int
  48 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  49 {
  50    struct nv30_screen *screen = nv30_screen(pscreen);
  51    struct nouveau_object *eng3d = screen->eng3d;
  52
  53    switch (param) {
  54    /* non-boolean capabilities */
  55    case PIPE_CAP_MAX_RENDER_TARGETS:
  56       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  57    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  58       return 13;
  59    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  60       return 10;
  61    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  62       return 13;
  63    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  64       return 120;
  65    /* supported capabilities */
  66    case PIPE_CAP_TWO_SIDED_STENCIL:
  67    case PIPE_CAP_ANISOTROPIC_FILTER:
  68    case PIPE_CAP_POINT_SPRITE:
  69    case PIPE_CAP_OCCLUSION_QUERY:
  70    case PIPE_CAP_QUERY_TIME_ELAPSED:
  71    case PIPE_CAP_QUERY_TIMESTAMP:
  72    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  73    case PIPE_CAP_TEXTURE_SWIZZLE:
  74    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  75    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  76    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  77    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  78    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  79    case PIPE_CAP_TGSI_TEXCOORD:
  80    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  81    case PIPE_CAP_USER_INDEX_BUFFERS:
  82       return 1;
  83    case PIPE_CAP_USER_VERTEX_BUFFERS:
  84       return 0;
  85    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  86       return 16;
  87    case PIPE_CAP_MAX_VIEWPORTS:
  88       return 1;
  89    /* nv4x capabilities */
  90    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  91    case PIPE_CAP_NPOT_TEXTURES:
  92    case PIPE_CAP_CONDITIONAL_RENDER:
  93    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  94    case PIPE_CAP_PRIMITIVE_RESTART:
  95       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
  96    /* unsupported */
  97    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  98    case PIPE_CAP_SM3:
  99    case PIPE_CAP_INDEP_BLEND_ENABLE:
 100    case PIPE_CAP_INDEP_BLEND_FUNC:
 101    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 102    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 103    case PIPE_CAP_TGSI_INSTANCEID:
 104    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 105    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 106    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 107    case PIPE_CAP_MIN_TEXEL_OFFSET:
 108    case PIPE_CAP_MAX_TEXEL_OFFSET:
 109    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 110    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 111    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 112    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 113    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 114    case PIPE_CAP_TEXTURE_BARRIER:
 115    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 116    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 117    case PIPE_CAP_CUBE_MAP_ARRAY:
 118    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 119    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 120    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 121    case PIPE_CAP_START_INSTANCE:
 122    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 123    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 124    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 125    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 126    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 127    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 128    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 129    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 130    case PIPE_CAP_TGSI_VS_LAYER:
 131    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 132    case PIPE_CAP_TEXTURE_GATHER_SM5:
 133    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 134    case PIPE_CAP_FAKE_SW_MSAA:
 135       return 0;
 136    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 137    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 138    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 139    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 140       return 1;
 141    case PIPE_CAP_ENDIANNESS:
 142       return PIPE_ENDIAN_LITTLE;
 143    default:
 144       debug_printf("unknown param %d\n", param);
 145       return 0;
 146    }
 147 }
 148
 149 static float
 150 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 151 {
 152    struct nv30_screen *screen = nv30_screen(pscreen);
 153    struct nouveau_object *eng3d = screen->eng3d;
 154
 155    switch (param) {
 156    case PIPE_CAPF_MAX_LINE_WIDTH:
 157    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 158       return 10.0;
 159    case PIPE_CAPF_MAX_POINT_WIDTH:
 160    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 161       return 64.0;
 162    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 163       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 164    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 165       return 15.0;
 166    default:
 167       debug_printf("unknown paramf %d\n", param);
 168       return 0;
 169    }
 170 }
 171
 172 static int
 173 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 174                              enum pipe_shader_cap param)
 175 {
 176    struct nv30_screen *screen = nv30_screen(pscreen);
 177    struct nouveau_object *eng3d = screen->eng3d;
 178
 179    switch (shader) {
 180    case PIPE_SHADER_VERTEX:
 181       switch (param) {
 182       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 183       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 184          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 185       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 186       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 187          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 188       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 189          return 0;
 190       case PIPE_SHADER_CAP_MAX_INPUTS:
 191          return 16;
 192       case PIPE_SHADER_CAP_MAX_CONSTS:
 193          return (eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6);
 194       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 195          return 1;
 196       case PIPE_SHADER_CAP_MAX_TEMPS:
 197          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 198       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 199       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 200          return 0;
 201       case PIPE_SHADER_CAP_MAX_ADDRS:
 202          return 2;
 203       case PIPE_SHADER_CAP_MAX_PREDS:
 204       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 205       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 206       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 207       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 208       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 209       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 210       case PIPE_SHADER_CAP_SUBROUTINES:
 211       case PIPE_SHADER_CAP_INTEGERS:
 212          return 0;
 213       default:
 214          debug_printf("unknown vertex shader param %d\n", param);
 215          return 0;
 216       }
 217       break;
 218    case PIPE_SHADER_FRAGMENT:
 219       switch (param) {
 220       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 221       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 222       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 223       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 224          return 4096;
 225       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 226          return 0;
 227       case PIPE_SHADER_CAP_MAX_INPUTS:
 228          return 8; /* should be possible to do 10 with nv4x */
 229       case PIPE_SHADER_CAP_MAX_CONSTS:
 230          return (eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32;
 231       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 232          return 1;
 233       case PIPE_SHADER_CAP_MAX_TEMPS:
 234          return 32;
 235       case PIPE_SHADER_CAP_MAX_ADDRS:
 236          return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 237       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 238       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 239          return 16;
 240       case PIPE_SHADER_CAP_MAX_PREDS:
 241       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 242       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 243       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 244       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 245       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 246       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 247       case PIPE_SHADER_CAP_SUBROUTINES:
 248          return 0;
 249       default:
 250          debug_printf("unknown fragment shader param %d\n", param);
 251          return 0;
 252       }
 253       break;
 254    default:
 255       return 0;
 256    }
 257 }
 258
 259 static boolean
 260 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 261                                 enum pipe_format format,
 262                                 enum pipe_texture_target target,
 263                                 unsigned sample_count,
 264                                 unsigned bindings)
 265 {
 266    if (sample_count > 4)
 267       return FALSE;
 268    if (!(0x00000017 & (1 << sample_count)))
 269       return FALSE;
 270
 271    if (!util_format_is_supported(format, bindings)) {
 272       return FALSE;
 273    }
 274
 275    /* transfers & shared are always supported */
 276    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 277                  PIPE_BIND_TRANSFER_WRITE |
 278                  PIPE_BIND_SHARED);
 279
 280    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 281 }
 282
 283 static void
 284 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 285 {
 286    struct nv30_screen *screen = nv30_screen(pscreen);
 287    struct nouveau_pushbuf *push = screen->base.pushbuf;
 288
 289    *sequence = ++screen->base.fence.sequence;
 290
 291    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 292    PUSH_DATA (push, 0);
 293    PUSH_DATA (push, *sequence);
 294 }
 295
 296 static uint32_t
 297 nv30_screen_fence_update(struct pipe_screen *pscreen)
 298 {
 299    struct nv30_screen *screen = nv30_screen(pscreen);
 300    struct nv04_notify *fence = screen->fence->data;
 301    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 302 }
 303
 304 static void
 305 nv30_screen_destroy(struct pipe_screen *pscreen)
 306 {
 307    struct nv30_screen *screen = nv30_screen(pscreen);
 308
 309    if (!nouveau_drm_screen_unref(&screen->base))
 310       return;
 311
 312    if (screen->base.fence.current) {
 313       struct nouveau_fence *current = NULL;
 314
 315       /* nouveau_fence_wait will create a new current fence, so wait on the
 316        * _current_ one, and remove both.
 317        */
 318       nouveau_fence_ref(screen->base.fence.current, &current);
 319       nouveau_fence_wait(current);
 320       nouveau_fence_ref(NULL, &current);
 321       nouveau_fence_ref(NULL, &screen->base.fence.current);
 322    }
 323
 324    nouveau_object_del(&screen->query);
 325    nouveau_object_del(&screen->fence);
 326    nouveau_object_del(&screen->ntfy);
 327
 328    nouveau_object_del(&screen->sifm);
 329    nouveau_object_del(&screen->swzsurf);
 330    nouveau_object_del(&screen->surf2d);
 331    nouveau_object_del(&screen->m2mf);
 332    nouveau_object_del(&screen->eng3d);
 333    nouveau_object_del(&screen->null);
 334
 335    nouveau_screen_fini(&screen->base);
 336    FREE(screen);
 337 }
 338
 339 #define FAIL_SCREEN_INIT(str, err)                    \
 340    do {                                               \
 341       NOUVEAU_ERR(str, err);                          \
 342       nv30_screen_destroy(pscreen);                   \
 343       return NULL;                                    \
 344    } while(0)
 345
 346 struct pipe_screen *
 347 nv30_screen_create(struct nouveau_device *dev)
 348 {
 349    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 350    struct pipe_screen *pscreen;
 351    struct nouveau_pushbuf *push;
 352    struct nv04_fifo *fifo;
 353    unsigned oclass = 0;
 354    int ret, i;
 355
 356    if (!screen)
 357       return NULL;
 358
 359    switch (dev->chipset & 0xf0) {
 360    case 0x30:
 361       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 362          oclass = NV30_3D_CLASS;
 363       else
 364       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 365          oclass = NV34_3D_CLASS;
 366       else
 367       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 368          oclass = NV35_3D_CLASS;
 369       break;
 370    case 0x40:
 371       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 372          oclass = NV40_3D_CLASS;
 373       else
 374       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 375          oclass = NV44_3D_CLASS;
 376       break;
 377    case 0x60:
 378       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 379          oclass = NV44_3D_CLASS;
 380       break;
 381    default:
 382       break;
 383    }
 384
 385    if (!oclass) {
 386       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 387       FREE(screen);
 388       return NULL;
 389    }
 390
 391    pscreen = &screen->base.base;
 392    pscreen->destroy = nv30_screen_destroy;
 393    pscreen->get_param = nv30_screen_get_param;
 394    pscreen->get_paramf = nv30_screen_get_paramf;
 395    pscreen->get_shader_param = nv30_screen_get_shader_param;
 396    pscreen->context_create = nv30_context_create;
 397    pscreen->is_format_supported = nv30_screen_is_format_supported;
 398    nv30_resource_screen_init(pscreen);
 399    nouveau_screen_init_vdec(&screen->base);
 400
 401    screen->base.fence.emit = nv30_screen_fence_emit;
 402    screen->base.fence.update = nv30_screen_fence_update;
 403
 404    ret = nouveau_screen_init(&screen->base, dev);
 405    if (ret)
 406       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 407
 408    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 409    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 410    if (oclass == NV40_3D_CLASS) {
 411       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 412       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 413    }
 414
 415    fifo = screen->base.channel->data;
 416    push = screen->base.pushbuf;
 417    push->rsvd_kick = 16;
 418
 419    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 420                             NULL, 0, &screen->null);
 421    if (ret)
 422       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 423
 424    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 425     * this means that the address pointed at by the DMA object must
 426     * be 4KiB aligned, which means this object needs to be the first
 427     * one allocated on the channel.
 428     */
 429    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 430                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 431                             .length = 32 }, sizeof(struct nv04_notify),
 432                             &screen->fence);
 433    if (ret)
 434       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 435
 436    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 437    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 438                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 439                             .length = 32 }, sizeof(struct nv04_notify),
 440                             &screen->ntfy);
 441    if (ret)
 442       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 443
 444    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 445     * the remainder of the "notifier block" assigned by the kernel for
 446     * use as query objects
 447     */
 448    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 449                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 450                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 451                             &screen->query);
 452    if (ret)
 453       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 454
 455    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 456    if (ret)
 457       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 458
 459    LIST_INITHEAD(&screen->queries);
 460
 461    /* Vertex program resources (code/data), currently 6 of the constant
 462     * slots are reserved to implement user clipping planes
 463     */
 464    if (oclass < NV40_3D_CLASS) {
 465       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 466       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 467    } else {
 468       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 469       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 470    }
 471
 472    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 473    if (ret == 0)
 474       nouveau_bo_map(screen->notify, 0, screen->base.client);
 475    if (ret)
 476       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 477
 478    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 479                             NULL, 0, &screen->eng3d);
 480    if (ret)
 481       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 482
 483    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 484    PUSH_DATA (push, screen->eng3d->handle);
 485    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 486    PUSH_DATA (push, screen->ntfy->handle);
 487    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 488    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 489    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 490    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 491    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 492    PUSH_DATA (push, fifo->vram);     /* ZETA */
 493    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 494    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 495    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 496    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 497    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 498    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 499    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 500       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 501       PUSH_DATA (push, 0x00100000);
 502       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 503       PUSH_DATA (push, 3);
 504
 505       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 506       PUSH_DATA (push, 0);
 507       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 508       PUSH_DATA (push, fui(0.0));
 509       PUSH_DATA (push, fui(0.0));
 510       PUSH_DATA (push, fui(1.0));
 511       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 512       for (i = 0; i < 16; i++)
 513          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 514
 515       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 516       PUSH_DATA (push, 0);
 517    } else {
 518       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 519       PUSH_DATA (push, fifo->vram);
 520       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 521
 522       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 523       PUSH_DATA (push, 0x00000004);
 524
 525       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 526       PUSH_DATA (push, 0x00000010);
 527       PUSH_DATA (push, 0x01000100);
 528       PUSH_DATA (push, 0xff800006);
 529
 530       /* vtxprog output routing */
 531       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 532       PUSH_DATA (push, 0x06144321);
 533       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 534       PUSH_DATA (push, 0xedcba987);
 535       PUSH_DATA (push, 0x0000006f);
 536       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 537       PUSH_DATA (push, 0x00171615);
 538       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 539       PUSH_DATA (push, 0x001b1a19);
 540
 541       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 542       PUSH_DATA (push, 0x0020ffff);
 543       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 544       PUSH_DATA (push, 0x01d300d4);
 545
 546       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 547       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 548    }
 549
 550    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 551                             NULL, 0, &screen->m2mf);
 552    if (ret)
 553       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 554
 555    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 556    PUSH_DATA (push, screen->m2mf->handle);
 557    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 558    PUSH_DATA (push, screen->ntfy->handle);
 559
 560    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 561                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 562    if (ret)
 563       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 564
 565    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 566    PUSH_DATA (push, screen->surf2d->handle);
 567    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 568    PUSH_DATA (push, screen->ntfy->handle);
 569
 570    if (dev->chipset < 0x40)
 571       oclass = NV30_SURFACE_SWZ_CLASS;
 572    else
 573       oclass = NV40_SURFACE_SWZ_CLASS;
 574
 575    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 576                             NULL, 0, &screen->swzsurf);
 577    if (ret)
 578       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 579
 580    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 581    PUSH_DATA (push, screen->swzsurf->handle);
 582    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 583    PUSH_DATA (push, screen->ntfy->handle);
 584
 585    if (dev->chipset < 0x40)
 586       oclass = NV30_SIFM_CLASS;
 587    else
 588       oclass = NV40_SIFM_CLASS;
 589
 590    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 591                             NULL, 0, &screen->sifm);
 592    if (ret)
 593       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 594
 595    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 596    PUSH_DATA (push, screen->sifm->handle);
 597    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 598    PUSH_DATA (push, screen->ntfy->handle);
 599    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 600    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 601
 602    nouveau_pushbuf_kick(push, push->channel);
 603
 604    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 605    return pscreen;
 606 }