src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/format/u_format.h"
  27 #include "util/format/u_format_s3tc.h"
  28 #include "util/u_screen.h"
  29 #include "pipe/p_screen.h"
  30 #include "compiler/nir/nir.h"
  31
  32 #include "nv50/nv50_context.h"
  33 #include "nv50/nv50_screen.h"
  34
  35 #include "nouveau_vp3_video.h"
  36
  37 #include "nv_object.xml.h"
  38
  39 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  40 #define LOCAL_WARPS_ALLOC 32
  41 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  42 #define STACK_WARPS_ALLOC 32
  43
  44 #define THREADS_IN_WARP 32
  45
  46 static bool
  47 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  48                                 enum pipe_format format,
  49                                 enum pipe_texture_target target,
  50                                 unsigned sample_count,
  51                                 unsigned storage_sample_count,
  52                                 unsigned bindings)
  53 {
  54    if (sample_count > 8)
  55       return false;
  56    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  57       return false;
  58    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  59       return false;
  60
  61    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  62       return false;
  63
  64    switch (format) {
  65    case PIPE_FORMAT_Z16_UNORM:
  66       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  67          return false;
  68       break;
  69    default:
  70       break;
  71    }
  72
  73    if (bindings & PIPE_BIND_LINEAR)
  74       if (util_format_is_depth_or_stencil(format) ||
  75           (target != PIPE_TEXTURE_1D &&
  76            target != PIPE_TEXTURE_2D &&
  77            target != PIPE_TEXTURE_RECT) ||
  78           sample_count > 1)
  79          return false;
  80
  81    /* shared is always supported */
  82    bindings &= ~(PIPE_BIND_LINEAR |
  83                  PIPE_BIND_SHARED);
  84
  85    return (( nv50_format_table[format].usage |
  86             nv50_vertex_format[format].usage) & bindings) == bindings;
  87 }
  88
  89 static int
  90 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  91 {
  92    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  93    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  94
  95    switch (param) {
  96    /* non-boolean caps */
  97    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
  98       return 8192;
  99    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 100       return 12;
 101    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 102       return 14;
 103    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 104       return 512;
 105    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 106    case PIPE_CAP_MIN_TEXEL_OFFSET:
 107       return -8;
 108    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 109    case PIPE_CAP_MAX_TEXEL_OFFSET:
 110       return 7;
 111    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 112       return 128 * 1024 * 1024;
 113    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 114       return 330;
 115    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 116       return 330;
 117    case PIPE_CAP_MAX_RENDER_TARGETS:
 118       return 8;
 119    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 120       return 1;
 121    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 122    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 123       return 8;
 124    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 125       return 4;
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 128       return 64;
 129    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 130    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 131       return 1024;
 132    case PIPE_CAP_MAX_VERTEX_STREAMS:
 133       return 1;
 134    case PIPE_CAP_MAX_GS_INVOCATIONS:
 135       return 0;
 136    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 137       return 0;
 138    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 139       return 2048;
 140    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 141       return 2047;
 142    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 143       return 256;
 144    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 145       return 16; /* 256 for binding as RT, but that's not possible in GL */
 146    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 147       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 148    case PIPE_CAP_MAX_VIEWPORTS:
 149       return NV50_MAX_VIEWPORTS;
 150    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 151       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 152    case PIPE_CAP_ENDIANNESS:
 153       return PIPE_ENDIAN_LITTLE;
 154    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 155       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 156    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 157       return NV50_MAX_WINDOW_RECTANGLES;
 158    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 159       return 16 * 1024 * 1024;
 160    case PIPE_CAP_MAX_VARYINGS:
 161       return 15;
 162    case PIPE_CAP_MAX_VERTEX_BUFFERS:
 163       return 16;
 164
 165    /* supported caps */
 166    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 167    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 168    case PIPE_CAP_TEXTURE_SWIZZLE:
 169    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 170    case PIPE_CAP_NPOT_TEXTURES:
 171    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 172    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 173    case PIPE_CAP_ANISOTROPIC_FILTER:
 174    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 175    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 176    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 177    case PIPE_CAP_POINT_SPRITE:
 178    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 179    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 180    case PIPE_CAP_VERTEX_SHADER_SATURATE:
 181    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 182    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 183    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 184    case PIPE_CAP_QUERY_TIMESTAMP:
 185    case PIPE_CAP_QUERY_TIME_ELAPSED:
 186    case PIPE_CAP_OCCLUSION_QUERY:
 187    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 188    case PIPE_CAP_INDEP_BLEND_ENABLE:
 189    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 190    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 191    case PIPE_CAP_PRIMITIVE_RESTART:
 192    case PIPE_CAP_TGSI_INSTANCEID:
 193    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 194    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 195    case PIPE_CAP_CONDITIONAL_RENDER:
 196    case PIPE_CAP_TEXTURE_BARRIER:
 197    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 198    case PIPE_CAP_START_INSTANCE:
 199    case PIPE_CAP_USER_VERTEX_BUFFERS:
 200    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 201    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 202    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 203    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 204    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 205    case PIPE_CAP_CLIP_HALFZ:
 206    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 207    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 208    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 209    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 210    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 211    case PIPE_CAP_TGSI_TXQS:
 212    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 213    case PIPE_CAP_SHAREABLE_SHADERS:
 214    case PIPE_CAP_CLEAR_TEXTURE:
 215    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 216    case PIPE_CAP_INVALIDATE_BUFFER:
 217    case PIPE_CAP_STRING_MARKER:
 218    case PIPE_CAP_CULL_DISTANCE:
 219    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 220    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 221    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 222    case PIPE_CAP_TGSI_CLOCK:
 223    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 224    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 225    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
 226    case PIPE_CAP_TGSI_DIV:
 227    case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
 228    case PIPE_CAP_FLATSHADE:
 229    case PIPE_CAP_ALPHA_TEST:
 230    case PIPE_CAP_POINT_SIZE_FIXED:
 231    case PIPE_CAP_TWO_SIDED_COLOR:
 232    case PIPE_CAP_CLIP_PLANES:
 233       return 1;
 234    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 235       return 1; /* class_3d >= NVA0_3D_CLASS; */
 236    /* supported on nva0+ */
 237    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 238       return class_3d >= NVA0_3D_CLASS;
 239    /* supported on nva3+ */
 240    case PIPE_CAP_CUBE_MAP_ARRAY:
 241    case PIPE_CAP_INDEP_BLEND_FUNC:
 242    case PIPE_CAP_TEXTURE_QUERY_LOD:
 243    case PIPE_CAP_SAMPLE_SHADING:
 244    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 245       return class_3d >= NVA3_3D_CLASS;
 246
 247    /* unsupported caps */
 248    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 249    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 250    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 251    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 252    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 253    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 254    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 255    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 256    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 257    case PIPE_CAP_TGSI_TEXCOORD:
 258    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 259    case PIPE_CAP_TEXTURE_GATHER_SM5:
 260    case PIPE_CAP_FAKE_SW_MSAA:
 261    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 262    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 263    case PIPE_CAP_DRAW_INDIRECT:
 264    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 265    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 266    case PIPE_CAP_VERTEXID_NOBASE:
 267    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 268    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 269    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 270    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 271    case PIPE_CAP_DRAW_PARAMETERS:
 272    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 273    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 274    case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
 275    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 276    case PIPE_CAP_GENERATE_MIPMAP:
 277    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 278    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 279    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 280    case PIPE_CAP_QUERY_MEMORY_INFO:
 281    case PIPE_CAP_PCI_GROUP:
 282    case PIPE_CAP_PCI_BUS:
 283    case PIPE_CAP_PCI_DEVICE:
 284    case PIPE_CAP_PCI_FUNCTION:
 285    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 286    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 287    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 288    case PIPE_CAP_TGSI_VOTE:
 289    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 290    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 291    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 292    case PIPE_CAP_NATIVE_FENCE_FD:
 293    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 294    case PIPE_CAP_FBFETCH:
 295    case PIPE_CAP_DOUBLES:
 296    case PIPE_CAP_INT64:
 297    case PIPE_CAP_INT64_DIVMOD:
 298    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 299    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 300    case PIPE_CAP_TGSI_BALLOT:
 301    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 302    case PIPE_CAP_POST_DEPTH_COVERAGE:
 303    case PIPE_CAP_BINDLESS_TEXTURE:
 304    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 305    case PIPE_CAP_QUERY_SO_OVERFLOW:
 306    case PIPE_CAP_MEMOBJ:
 307    case PIPE_CAP_LOAD_CONSTBUF:
 308    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 309    case PIPE_CAP_TILE_RASTER_ORDER:
 310    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 311    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 312    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 313    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 314    case PIPE_CAP_FENCE_SIGNAL:
 315    case PIPE_CAP_CONSTBUF0_FLAGS:
 316    case PIPE_CAP_PACKED_UNIFORMS:
 317    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 318    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 319    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 320    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 321    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 322    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 323    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 324    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 325    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 326    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 327    case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 328    case PIPE_CAP_TGSI_ATOMFADD:
 329    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 330    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 331    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 332    case PIPE_CAP_NIR_COMPACT_ARRAYS:
 333    case PIPE_CAP_COMPUTE:
 334    case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 335    case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
 336    case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
 337    case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
 338    case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
 339    case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
 340    case PIPE_CAP_FBFETCH_COHERENT:
 341    case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
 342    case PIPE_CAP_TGSI_ATOMINC_WRAP:
 343    case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
 344    case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE:
 345    case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS:
 346    case PIPE_CAP_INTEGER_MULTIPLY_32X16: /* could be done */
 347    case PIPE_CAP_FRONTEND_NOOP:
 348    case PIPE_CAP_GL_SPIRV:
 349    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 350    case PIPE_CAP_TEXTURE_SHADOW_LOD: /* investigate */
 351       return 0;
 352
 353    case PIPE_CAP_VENDOR_ID:
 354       return 0x10de;
 355    case PIPE_CAP_DEVICE_ID: {
 356       uint64_t device_id;
 357       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 358          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 359          return -1;
 360       }
 361       return device_id;
 362    }
 363    case PIPE_CAP_ACCELERATED:
 364       return 1;
 365    case PIPE_CAP_VIDEO_MEMORY:
 366       return dev->vram_size >> 20;
 367    case PIPE_CAP_UMA:
 368       return 0;
 369
 370    default:
 371       debug_printf("%s: unhandled cap %d\n", __func__, param);
 372       /* fallthrough */
 373    /* caps where we want the default value */
 374    case PIPE_CAP_DMABUF:
 375    case PIPE_CAP_ESSL_FEATURE_LEVEL:
 376    case PIPE_CAP_THROTTLE:
 377       return u_pipe_screen_get_param_defaults(pscreen, param);
 378    }
 379 }
 380
 381 static int
 382 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
 383                              enum pipe_shader_type shader,
 384                              enum pipe_shader_cap param)
 385 {
 386    const struct nouveau_screen *screen = nouveau_screen(pscreen);
 387
 388    switch (shader) {
 389    case PIPE_SHADER_VERTEX:
 390    case PIPE_SHADER_GEOMETRY:
 391    case PIPE_SHADER_FRAGMENT:
 392       break;
 393    case PIPE_SHADER_COMPUTE:
 394    default:
 395       return 0;
 396    }
 397
 398    switch (param) {
 399    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 400    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 401    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 402    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 403       return 16384;
 404    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 405       return 4;
 406    case PIPE_SHADER_CAP_MAX_INPUTS:
 407       if (shader == PIPE_SHADER_VERTEX)
 408          return 32;
 409       return 15;
 410    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 411       return 16;
 412    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 413       return 65536;
 414    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 415       return NV50_MAX_PIPE_CONSTBUFS;
 416    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 417       return shader != PIPE_SHADER_FRAGMENT;
 418    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 419    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 420    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 421       return 1;
 422    case PIPE_SHADER_CAP_MAX_TEMPS:
 423       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 424    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 425       return 1;
 426    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 427       return 1;
 428    case PIPE_SHADER_CAP_INT64_ATOMICS:
 429    case PIPE_SHADER_CAP_FP16:
 430    case PIPE_SHADER_CAP_SUBROUTINES:
 431       return 0; /* please inline, or provide function declarations */
 432    case PIPE_SHADER_CAP_INTEGERS:
 433       return 1;
 434    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 435       return 1;
 436    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 437       /* The chip could handle more sampler views than samplers */
 438    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 439       return MIN2(16, PIPE_MAX_SAMPLERS);
 440    case PIPE_SHADER_CAP_PREFERRED_IR:
 441       return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
 442    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 443       return 32;
 444    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 445    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 446    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 447    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 448    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 449    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 450    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 451    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 452    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 453    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 454    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 455       return 0;
 456    default:
 457       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 458       return 0;
 459    }
 460 }
 461
 462 static float
 463 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 464 {
 465    switch (param) {
 466    case PIPE_CAPF_MAX_LINE_WIDTH:
 467    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 468       return 10.0f;
 469    case PIPE_CAPF_MAX_POINT_WIDTH:
 470    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 471       return 64.0f;
 472    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 473       return 16.0f;
 474    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 475       return 15.0f;
 476    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 477    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 478    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 479       return 0.0f;
 480    }
 481
 482    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 483    return 0.0f;
 484 }
 485
 486 static int
 487 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 488                               enum pipe_shader_ir ir_type,
 489                               enum pipe_compute_cap param, void *data)
 490 {
 491    struct nv50_screen *screen = nv50_screen(pscreen);
 492
 493 #define RET(x) do {                  \
 494    if (data)                         \
 495       memcpy(data, x, sizeof(x));    \
 496    return sizeof(x);                 \
 497 } while (0)
 498
 499    switch (param) {
 500    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 501       RET((uint64_t []) { 2 });
 502    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 503       RET(((uint64_t []) { 65535, 65535 }));
 504    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 505       RET(((uint64_t []) { 512, 512, 64 }));
 506    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 507       RET((uint64_t []) { 512 });
 508    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 509       RET((uint64_t []) { 1ULL << 32 });
 510    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 511       RET((uint64_t []) { 16 << 10 });
 512    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 513       RET((uint64_t []) { 16 << 10 });
 514    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 515       RET((uint64_t []) { 4096 });
 516    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 517       RET((uint32_t []) { 32 });
 518    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 519       RET((uint64_t []) { 1ULL << 40 });
 520    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 521       RET((uint32_t []) { 0 });
 522    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 523       RET((uint32_t []) { screen->mp_count });
 524    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 525       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 526    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 527       RET((uint32_t []) { 32 });
 528    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 529       RET((uint64_t []) { 0 });
 530    default:
 531       return 0;
 532    }
 533
 534 #undef RET
 535 }
 536
 537 static void
 538 nv50_screen_destroy(struct pipe_screen *pscreen)
 539 {
 540    struct nv50_screen *screen = nv50_screen(pscreen);
 541
 542    if (!nouveau_drm_screen_unref(&screen->base))
 543       return;
 544
 545    if (screen->base.fence.current) {
 546       struct nouveau_fence *current = NULL;
 547
 548       /* nouveau_fence_wait will create a new current fence, so wait on the
 549        * _current_ one, and remove both.
 550        */
 551       nouveau_fence_ref(screen->base.fence.current, &current);
 552       nouveau_fence_wait(current, NULL);
 553       nouveau_fence_ref(NULL, &current);
 554       nouveau_fence_ref(NULL, &screen->base.fence.current);
 555    }
 556    if (screen->base.pushbuf)
 557       screen->base.pushbuf->user_priv = NULL;
 558
 559    if (screen->blitter)
 560       nv50_blitter_destroy(screen);
 561    if (screen->pm.prog) {
 562       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 563       nv50_program_destroy(NULL, screen->pm.prog);
 564       FREE(screen->pm.prog);
 565    }
 566
 567    nouveau_bo_ref(NULL, &screen->code);
 568    nouveau_bo_ref(NULL, &screen->tls_bo);
 569    nouveau_bo_ref(NULL, &screen->stack_bo);
 570    nouveau_bo_ref(NULL, &screen->txc);
 571    nouveau_bo_ref(NULL, &screen->uniforms);
 572    nouveau_bo_ref(NULL, &screen->fence.bo);
 573
 574    nouveau_heap_destroy(&screen->vp_code_heap);
 575    nouveau_heap_destroy(&screen->gp_code_heap);
 576    nouveau_heap_destroy(&screen->fp_code_heap);
 577
 578    FREE(screen->tic.entries);
 579
 580    nouveau_object_del(&screen->tesla);
 581    nouveau_object_del(&screen->eng2d);
 582    nouveau_object_del(&screen->m2mf);
 583    nouveau_object_del(&screen->compute);
 584    nouveau_object_del(&screen->sync);
 585
 586    nouveau_screen_fini(&screen->base);
 587
 588    FREE(screen);
 589 }
 590
 591 static void
 592 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 593 {
 594    struct nv50_screen *screen = nv50_screen(pscreen);
 595    struct nouveau_pushbuf *push = screen->base.pushbuf;
 596
 597    /* we need to do it after possible flush in MARK_RING */
 598    *sequence = ++screen->base.fence.sequence;
 599
 600    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 601    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 602    PUSH_DATAh(push, screen->fence.bo->offset);
 603    PUSH_DATA (push, screen->fence.bo->offset);
 604    PUSH_DATA (push, *sequence);
 605    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 606                     NV50_3D_QUERY_GET_UNK4 |
 607                     NV50_3D_QUERY_GET_UNIT_CROP |
 608                     NV50_3D_QUERY_GET_TYPE_QUERY |
 609                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 610                     NV50_3D_QUERY_GET_SHORT);
 611 }
 612
 613 static u32
 614 nv50_screen_fence_update(struct pipe_screen *pscreen)
 615 {
 616    return nv50_screen(pscreen)->fence.map[0];
 617 }
 618
 619 static void
 620 nv50_screen_init_hwctx(struct nv50_screen *screen)
 621 {
 622    struct nouveau_pushbuf *push = screen->base.pushbuf;
 623    struct nv04_fifo *fifo;
 624    unsigned i;
 625
 626    fifo = (struct nv04_fifo *)screen->base.channel->data;
 627
 628    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 629    PUSH_DATA (push, screen->m2mf->handle);
 630    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 631    PUSH_DATA (push, screen->sync->handle);
 632    PUSH_DATA (push, fifo->vram);
 633    PUSH_DATA (push, fifo->vram);
 634
 635    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 636    PUSH_DATA (push, screen->eng2d->handle);
 637    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 638    PUSH_DATA (push, screen->sync->handle);
 639    PUSH_DATA (push, fifo->vram);
 640    PUSH_DATA (push, fifo->vram);
 641    PUSH_DATA (push, fifo->vram);
 642    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 643    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 644    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 645    PUSH_DATA (push, 0);
 646    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 647    PUSH_DATA (push, 0);
 648    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 649    PUSH_DATA (push, 1);
 650    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 651    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 652
 653    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 654    PUSH_DATA (push, screen->tesla->handle);
 655
 656    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 657    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 658
 659    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 660    PUSH_DATA (push, screen->sync->handle);
 661    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 662    for (i = 0; i < 11; ++i)
 663       PUSH_DATA(push, fifo->vram);
 664    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 665    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 666       PUSH_DATA(push, fifo->vram);
 667
 668    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 669    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 670    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 671    PUSH_DATA (push, 0xf);
 672
 673    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 674       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 675       PUSH_DATA (push, 0x18);
 676    }
 677
 678    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 679    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 680
 681    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 682    for (i = 0; i < 8; ++i)
 683       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 684
 685    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 686    PUSH_DATA (push, 1);
 687
 688    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 689    PUSH_DATA (push, 0);
 690    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 691    PUSH_DATA (push, 0);
 692    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 693    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 694    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 695    PUSH_DATA (push, 0);
 696    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 697    PUSH_DATA (push, 1);
 698    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 699    PUSH_DATA (push, 1);
 700
 701    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 702       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 703       PUSH_DATA (push, 0);
 704    }
 705
 706    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 707    PUSH_DATA (push, 0);
 708    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 709    PUSH_DATA (push, 0);
 710    PUSH_DATA (push, 0);
 711    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 712    PUSH_DATA (push, 0x3f);
 713
 714    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 715    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 716    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 717
 718    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 719    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 720    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 721
 722    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 723    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 724    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 725
 726    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 727    PUSH_DATAh(push, screen->tls_bo->offset);
 728    PUSH_DATA (push, screen->tls_bo->offset);
 729    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 730
 731    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 732    PUSH_DATAh(push, screen->stack_bo->offset);
 733    PUSH_DATA (push, screen->stack_bo->offset);
 734    PUSH_DATA (push, 4);
 735
 736    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 737    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 738    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 739    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 740
 741    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 742    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 743    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 744    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 745
 746    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 747    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 748    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 749    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 750
 751    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 752    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 753    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 754    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 755
 756    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 757    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 758    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 759    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 760
 761    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 762    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 763    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 764    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 765    PUSH_DATAf(push, 0.0f);
 766    PUSH_DATAf(push, 0.0f);
 767    PUSH_DATAf(push, 0.0f);
 768    PUSH_DATAf(push, 0.0f);
 769    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 770    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 771    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 772
 773    nv50_upload_ms_info(push);
 774
 775    /* max TIC (bits 4:8) & TSC bindings, per program type */
 776    for (i = 0; i < 3; ++i) {
 777       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 778       PUSH_DATA (push, 0x54);
 779    }
 780
 781    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 782    PUSH_DATAh(push, screen->txc->offset);
 783    PUSH_DATA (push, screen->txc->offset);
 784    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 785
 786    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 787    PUSH_DATAh(push, screen->txc->offset + 65536);
 788    PUSH_DATA (push, screen->txc->offset + 65536);
 789    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 790
 791    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 792    PUSH_DATA (push, 0);
 793
 794    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 795    PUSH_DATA (push, 0);
 796    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 797    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 798    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 799    for (i = 0; i < 8 * 2; ++i)
 800       PUSH_DATA(push, 0);
 801    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 802    PUSH_DATA (push, 0);
 803
 804    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 805    PUSH_DATA (push, 1);
 806    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 807       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 808       PUSH_DATAf(push, 0.0f);
 809       PUSH_DATAf(push, 1.0f);
 810       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 811       PUSH_DATA (push, 8192 << 16);
 812       PUSH_DATA (push, 8192 << 16);
 813    }
 814
 815    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 816 #ifdef NV50_SCISSORS_CLIPPING
 817    PUSH_DATA (push, 0x0000);
 818 #else
 819    PUSH_DATA (push, 0x1080);
 820 #endif
 821
 822    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 823    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 824
 825    /* We use scissors instead of exact view volume clipping,
 826     * so they're always enabled.
 827     */
 828    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 829       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 830       PUSH_DATA (push, 1);
 831       PUSH_DATA (push, 8192 << 16);
 832       PUSH_DATA (push, 8192 << 16);
 833    }
 834
 835    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 836    PUSH_DATA (push, 1);
 837    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 838    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 839    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 840    PUSH_DATA (push, 0x11111111);
 841    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 842    PUSH_DATA (push, 1);
 843
 844    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 845    PUSH_DATA (push, 0);
 846    if (screen->base.class_3d >= NV84_3D_CLASS) {
 847       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 848       PUSH_DATA (push, 0);
 849    }
 850
 851    BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
 852    PUSH_DATA (push, 1);
 853    BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
 854    PUSH_DATA (push, 1);
 855
 856    PUSH_KICK (push);
 857 }
 858
 859 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 860       uint64_t *tls_size)
 861 {
 862    struct nouveau_device *dev = screen->base.device;
 863    int ret;
 864
 865    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 866          ONE_TEMP_SIZE;
 867    if (nouveau_mesa_debug)
 868       debug_printf("allocating space for %u temps\n",
 869             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 870    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 871          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 872
 873    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 874                         *tls_size, NULL, &screen->tls_bo);
 875    if (ret) {
 876       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 877       return ret;
 878    }
 879
 880    return 0;
 881 }
 882
 883 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 884 {
 885    struct nouveau_pushbuf *push = screen->base.pushbuf;
 886    int ret;
 887    uint64_t tls_size;
 888
 889    if (tls_space < screen->cur_tls_space)
 890       return 0;
 891    if (tls_space > screen->max_tls_space) {
 892       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 893        * LOCAL_WARPS_NO_CLAMP) */
 894       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 895             (unsigned)(tls_space / ONE_TEMP_SIZE),
 896             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 897       return -ENOMEM;
 898    }
 899
 900    nouveau_bo_ref(NULL, &screen->tls_bo);
 901    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 902    if (ret)
 903       return ret;
 904
 905    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 906    PUSH_DATAh(push, screen->tls_bo->offset);
 907    PUSH_DATA (push, screen->tls_bo->offset);
 908    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 909
 910    return 1;
 911 }
 912
 913 static const nir_shader_compiler_options nir_options = {
 914    .fuse_ffma = false, /* nir doesn't track mad vs fma */
 915    .lower_flrp32 = true,
 916    .lower_flrp64 = true,
 917    .lower_fpow = false,
 918    .lower_uadd_carry = true,
 919    .lower_usub_borrow = true,
 920    .lower_sub = true,
 921    .lower_ffract = true,
 922    .lower_pack_half_2x16 = true,
 923    .lower_pack_unorm_2x16 = true,
 924    .lower_pack_snorm_2x16 = true,
 925    .lower_pack_unorm_4x8 = true,
 926    .lower_pack_snorm_4x8 = true,
 927    .lower_unpack_half_2x16 = true,
 928    .lower_unpack_unorm_2x16 = true,
 929    .lower_unpack_snorm_2x16 = true,
 930    .lower_unpack_unorm_4x8 = true,
 931    .lower_unpack_snorm_4x8 = true,
 932    .lower_extract_byte = true,
 933    .lower_extract_word = true,
 934    .lower_all_io_to_temps = false,
 935    .lower_cs_local_index_from_id = true,
 936    .lower_rotate = true,
 937    .lower_to_scalar = true,
 938    .use_interpolated_input_intrinsics = true,
 939    .max_unroll_iterations = 32,
 940 };
 941
 942 static const void *
 943 nv50_screen_get_compiler_options(struct pipe_screen *pscreen,
 944                                  enum pipe_shader_ir ir,
 945                                  enum pipe_shader_type shader)
 946 {
 947    if (ir == PIPE_SHADER_IR_NIR)
 948       return &nir_options;
 949    return NULL;
 950 }
 951
 952 struct nouveau_screen *
 953 nv50_screen_create(struct nouveau_device *dev)
 954 {
 955    struct nv50_screen *screen;
 956    struct pipe_screen *pscreen;
 957    struct nouveau_object *chan;
 958    uint64_t value;
 959    uint32_t tesla_class;
 960    unsigned stack_size;
 961    int ret;
 962
 963    screen = CALLOC_STRUCT(nv50_screen);
 964    if (!screen)
 965       return NULL;
 966    pscreen = &screen->base.base;
 967    pscreen->destroy = nv50_screen_destroy;
 968
 969    ret = nouveau_screen_init(&screen->base, dev);
 970    if (ret) {
 971       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 972       goto fail;
 973    }
 974
 975    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 976     *  admit them to VRAM.
 977     */
 978    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 979       PIPE_BIND_VERTEX_BUFFER;
 980    screen->base.sysmem_bindings |=
 981       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 982
 983    screen->base.pushbuf->user_priv = screen;
 984    screen->base.pushbuf->rsvd_kick = 5;
 985
 986    chan = screen->base.channel;
 987
 988    pscreen->context_create = nv50_create;
 989    pscreen->is_format_supported = nv50_screen_is_format_supported;
 990    pscreen->get_param = nv50_screen_get_param;
 991    pscreen->get_shader_param = nv50_screen_get_shader_param;
 992    pscreen->get_paramf = nv50_screen_get_paramf;
 993    pscreen->get_compute_param = nv50_screen_get_compute_param;
 994    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 995    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 996
 997    /* nir stuff */
 998    pscreen->get_compiler_options = nv50_screen_get_compiler_options;
 999
1000    nv50_screen_init_resource_functions(pscreen);
1001
1002    if (screen->base.device->chipset < 0x84 ||
1003        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
1004       /* PMPEG */
1005       nouveau_screen_init_vdec(&screen->base);
1006    } else if (screen->base.device->chipset < 0x98 ||
1007               screen->base.device->chipset == 0xa0) {
1008       /* VP2 */
1009       screen->base.base.get_video_param = nv84_screen_get_video_param;
1010       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
1011    } else {
1012       /* VP3/4 */
1013       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
1014       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
1015    }
1016
1017    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
1018                         NULL, &screen->fence.bo);
1019    if (ret) {
1020       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
1021       goto fail;
1022    }
1023
1024    nouveau_bo_map(screen->fence.bo, 0, NULL);
1025    screen->fence.map = screen->fence.bo->map;
1026    screen->base.fence.emit = nv50_screen_fence_emit;
1027    screen->base.fence.update = nv50_screen_fence_update;
1028
1029    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
1030                             &(struct nv04_notify){ .length = 32 },
1031                             sizeof(struct nv04_notify), &screen->sync);
1032    if (ret) {
1033       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
1034       goto fail;
1035    }
1036
1037    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
1038                             NULL, 0, &screen->m2mf);
1039    if (ret) {
1040       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
1041       goto fail;
1042    }
1043
1044    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
1045                             NULL, 0, &screen->eng2d);
1046    if (ret) {
1047       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
1048       goto fail;
1049    }
1050
1051    switch (dev->chipset & 0xf0) {
1052    case 0x50:
1053       tesla_class = NV50_3D_CLASS;
1054       break;
1055    case 0x80:
1056    case 0x90:
1057       tesla_class = NV84_3D_CLASS;
1058       break;
1059    case 0xa0:
1060       switch (dev->chipset) {
1061       case 0xa0:
1062       case 0xaa:
1063       case 0xac:
1064          tesla_class = NVA0_3D_CLASS;
1065          break;
1066       case 0xaf:
1067          tesla_class = NVAF_3D_CLASS;
1068          break;
1069       default:
1070          tesla_class = NVA3_3D_CLASS;
1071          break;
1072       }
1073       break;
1074    default:
1075       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
1076       goto fail;
1077    }
1078    screen->base.class_3d = tesla_class;
1079
1080    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
1081                             NULL, 0, &screen->tesla);
1082    if (ret) {
1083       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
1084       goto fail;
1085    }
1086
1087    /* This over-allocates by a page. The GP, which would execute at the end of
1088     * the last page, would trigger faults. The going theory is that it
1089     * prefetches up to a certain amount.
1090     */
1091    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
1092                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
1093                         NULL, &screen->code);
1094    if (ret) {
1095       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
1096       goto fail;
1097    }
1098
1099    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1100    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1101    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1102
1103    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1104
1105    screen->TPs = util_bitcount(value & 0xffff);
1106    screen->MPsInTP = util_bitcount(value & 0x0f000000);
1107
1108    screen->mp_count = screen->TPs * screen->MPsInTP;
1109
1110    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
1111          STACK_WARPS_ALLOC * 64 * 8;
1112
1113    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
1114                         &screen->stack_bo);
1115    if (ret) {
1116       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1117       goto fail;
1118    }
1119
1120    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1121          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
1122          ONE_TEMP_SIZE;
1123    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1124    screen->max_tls_space /= 2; /* half of vram */
1125
1126    /* hw can address max 64 KiB */
1127    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1128
1129    uint64_t tls_size;
1130    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1131    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1132    if (ret)
1133       goto fail;
1134
1135    if (nouveau_mesa_debug)
1136       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1137             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1138
1139    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1140                         &screen->uniforms);
1141    if (ret) {
1142       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1143       goto fail;
1144    }
1145
1146    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1147                         &screen->txc);
1148    if (ret) {
1149       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1150       goto fail;
1151    }
1152
1153    screen->tic.entries = CALLOC(4096, sizeof(void *));
1154    screen->tsc.entries = screen->tic.entries + 2048;
1155
1156    if (!nv50_blitter_create(screen))
1157       goto fail;
1158
1159    nv50_screen_init_hwctx(screen);
1160
1161    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1162    if (ret) {
1163       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1164       goto fail;
1165    }
1166
1167    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1168
1169    return &screen->base;
1170
1171 fail:
1172    screen->base.base.context_create = NULL;
1173    return &screen->base;
1174 }
1175
1176 int
1177 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1178 {
1179    int i = screen->tic.next;
1180
1181    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1182       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1183
1184    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1185
1186    if (screen->tic.entries[i])
1187       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1188
1189    screen->tic.entries[i] = entry;
1190    return i;
1191 }
1192
1193 int
1194 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1195 {
1196    int i = screen->tsc.next;
1197
1198    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1199       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1200
1201    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1202
1203    if (screen->tsc.entries[i])
1204       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1205
1206    screen->tsc.entries[i] = entry;
1207    return i;
1208 }