src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nv50/nv50_context.h"
  31 #include "nv50/nv50_screen.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nv_object.xml.h"
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 static boolean
  45 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  46                                 enum pipe_format format,
  47                                 enum pipe_texture_target target,
  48                                 unsigned sample_count,
  49                                 unsigned bindings)
  50 {
  51    if (sample_count > 8)
  52       return false;
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return false;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return false;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return false;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return false;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* shared is always supported */
  79    bindings &= ~(PIPE_BIND_LINEAR |
  80                  PIPE_BIND_SHARED);
  81
  82    return (( nv50_format_table[format].usage |
  83             nv50_vertex_format[format].usage) & bindings) == bindings;
  84 }
  85
  86 static int
  87 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  88 {
  89    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  90    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  91
  92    switch (param) {
  93    /* non-boolean caps */
  94    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  95       return 14;
  96    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  97       return 12;
  98    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  99       return 14;
 100    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 101       return 512;
 102    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 103    case PIPE_CAP_MIN_TEXEL_OFFSET:
 104       return -8;
 105    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 106    case PIPE_CAP_MAX_TEXEL_OFFSET:
 107       return 7;
 108    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 109       return 128 * 1024 * 1024;
 110    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 111       return 330;
 112    case PIPE_CAP_MAX_RENDER_TARGETS:
 113       return 8;
 114    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 115       return 1;
 116    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 117       return 4;
 118    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 119    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 120       return 64;
 121    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 122    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 123       return 1024;
 124    case PIPE_CAP_MAX_VERTEX_STREAMS:
 125       return 1;
 126    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 127       return 2048;
 128    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 129       return 256;
 130    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 131       return 16; /* 256 for binding as RT, but that's not possible in GL */
 132    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 133       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 134    case PIPE_CAP_MAX_VIEWPORTS:
 135       return NV50_MAX_VIEWPORTS;
 136    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 137       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 138    case PIPE_CAP_ENDIANNESS:
 139       return PIPE_ENDIAN_LITTLE;
 140    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 141       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 142    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 143       return NV50_MAX_WINDOW_RECTANGLES;
 144
 145    /* supported caps */
 146    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 147    case PIPE_CAP_TEXTURE_SWIZZLE:
 148    case PIPE_CAP_NPOT_TEXTURES:
 149    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 150    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 151    case PIPE_CAP_ANISOTROPIC_FILTER:
 152    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 153    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 154    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 155    case PIPE_CAP_POINT_SPRITE:
 156    case PIPE_CAP_SM3:
 157    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 158    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 159    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 160    case PIPE_CAP_QUERY_TIMESTAMP:
 161    case PIPE_CAP_QUERY_TIME_ELAPSED:
 162    case PIPE_CAP_OCCLUSION_QUERY:
 163    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 164    case PIPE_CAP_INDEP_BLEND_ENABLE:
 165    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 166    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 167    case PIPE_CAP_PRIMITIVE_RESTART:
 168    case PIPE_CAP_TGSI_INSTANCEID:
 169    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 170    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 171    case PIPE_CAP_CONDITIONAL_RENDER:
 172    case PIPE_CAP_TEXTURE_BARRIER:
 173    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 174    case PIPE_CAP_START_INSTANCE:
 175    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 176    case PIPE_CAP_USER_VERTEX_BUFFERS:
 177    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 178    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 179    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 180    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 181    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 182    case PIPE_CAP_CLIP_HALFZ:
 183    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 184    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 185    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 186    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 187    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 188    case PIPE_CAP_TGSI_TXQS:
 189    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 190    case PIPE_CAP_SHAREABLE_SHADERS:
 191    case PIPE_CAP_CLEAR_TEXTURE:
 192    case PIPE_CAP_COMPUTE:
 193    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 194    case PIPE_CAP_INVALIDATE_BUFFER:
 195    case PIPE_CAP_STRING_MARKER:
 196    case PIPE_CAP_CULL_DISTANCE:
 197    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 198    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 199    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 200    case PIPE_CAP_TGSI_CLOCK:
 201    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 202    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 203       return 1;
 204    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 205       return 1; /* class_3d >= NVA0_3D_CLASS; */
 206    /* supported on nva0+ */
 207    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 208       return class_3d >= NVA0_3D_CLASS;
 209    /* supported on nva3+ */
 210    case PIPE_CAP_CUBE_MAP_ARRAY:
 211    case PIPE_CAP_INDEP_BLEND_FUNC:
 212    case PIPE_CAP_TEXTURE_QUERY_LOD:
 213    case PIPE_CAP_SAMPLE_SHADING:
 214    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 215       return class_3d >= NVA3_3D_CLASS;
 216
 217    /* unsupported caps */
 218    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 219    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 220    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 221    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 222    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 223    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 224    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 225    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 226    case PIPE_CAP_TGSI_TEXCOORD:
 227    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 228    case PIPE_CAP_TEXTURE_GATHER_SM5:
 229    case PIPE_CAP_FAKE_SW_MSAA:
 230    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 231    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 232    case PIPE_CAP_DRAW_INDIRECT:
 233    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 234    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 235    case PIPE_CAP_VERTEXID_NOBASE:
 236    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 237    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 238    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 239    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 240    case PIPE_CAP_DRAW_PARAMETERS:
 241    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 242    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 243    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 244    case PIPE_CAP_GENERATE_MIPMAP:
 245    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 246    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 247    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 248    case PIPE_CAP_QUERY_MEMORY_INFO:
 249    case PIPE_CAP_PCI_GROUP:
 250    case PIPE_CAP_PCI_BUS:
 251    case PIPE_CAP_PCI_DEVICE:
 252    case PIPE_CAP_PCI_FUNCTION:
 253    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 254    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 255    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 256    case PIPE_CAP_TGSI_VOTE:
 257    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 258    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 259    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 260    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 261    case PIPE_CAP_NATIVE_FENCE_FD:
 262    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 263    case PIPE_CAP_TGSI_FS_FBFETCH:
 264    case PIPE_CAP_DOUBLES:
 265    case PIPE_CAP_INT64:
 266    case PIPE_CAP_INT64_DIVMOD:
 267    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 268    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 269    case PIPE_CAP_TGSI_BALLOT:
 270    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 271    case PIPE_CAP_POST_DEPTH_COVERAGE:
 272    case PIPE_CAP_BINDLESS_TEXTURE:
 273    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 274    case PIPE_CAP_QUERY_SO_OVERFLOW:
 275    case PIPE_CAP_MEMOBJ:
 276    case PIPE_CAP_LOAD_CONSTBUF:
 277    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 278    case PIPE_CAP_TILE_RASTER_ORDER:
 279    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 280    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 281    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 282       return 0;
 283
 284    case PIPE_CAP_VENDOR_ID:
 285       return 0x10de;
 286    case PIPE_CAP_DEVICE_ID: {
 287       uint64_t device_id;
 288       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 289          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 290          return -1;
 291       }
 292       return device_id;
 293    }
 294    case PIPE_CAP_ACCELERATED:
 295       return 1;
 296    case PIPE_CAP_VIDEO_MEMORY:
 297       return dev->vram_size >> 20;
 298    case PIPE_CAP_UMA:
 299       return 0;
 300    }
 301
 302    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 303    return 0;
 304 }
 305
 306 static int
 307 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
 308                              enum pipe_shader_type shader,
 309                              enum pipe_shader_cap param)
 310 {
 311    switch (shader) {
 312    case PIPE_SHADER_VERTEX:
 313    case PIPE_SHADER_GEOMETRY:
 314    case PIPE_SHADER_FRAGMENT:
 315       break;
 316    case PIPE_SHADER_COMPUTE:
 317    default:
 318       return 0;
 319    }
 320
 321    switch (param) {
 322    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 323    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 324    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 325    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 326       return 16384;
 327    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 328       return 4;
 329    case PIPE_SHADER_CAP_MAX_INPUTS:
 330       if (shader == PIPE_SHADER_VERTEX)
 331          return 32;
 332       return 15;
 333    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 334       return 16;
 335    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 336       return 65536;
 337    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 338       return NV50_MAX_PIPE_CONSTBUFS;
 339    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 340       return shader != PIPE_SHADER_FRAGMENT;
 341    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 342    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 343    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 344       return 1;
 345    case PIPE_SHADER_CAP_MAX_TEMPS:
 346       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 347    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 348       return 1;
 349    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 350       return 1;
 351    case PIPE_SHADER_CAP_INT64_ATOMICS:
 352    case PIPE_SHADER_CAP_FP16:
 353    case PIPE_SHADER_CAP_SUBROUTINES:
 354       return 0; /* please inline, or provide function declarations */
 355    case PIPE_SHADER_CAP_INTEGERS:
 356       return 1;
 357    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 358       return 1;
 359    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 360       /* The chip could handle more sampler views than samplers */
 361    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 362       return MIN2(16, PIPE_MAX_SAMPLERS);
 363    case PIPE_SHADER_CAP_PREFERRED_IR:
 364       return PIPE_SHADER_IR_TGSI;
 365    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 366       return 32;
 367    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 368    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 369    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 370    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 371    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 372    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 373    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 374    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 375    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 376    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 377    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 378       return 0;
 379    default:
 380       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 381       return 0;
 382    }
 383 }
 384
 385 static float
 386 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 387 {
 388    switch (param) {
 389    case PIPE_CAPF_MAX_LINE_WIDTH:
 390    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 391       return 10.0f;
 392    case PIPE_CAPF_MAX_POINT_WIDTH:
 393    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 394       return 64.0f;
 395    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 396       return 16.0f;
 397    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 398       return 4.0f;
 399    case PIPE_CAPF_GUARD_BAND_LEFT:
 400    case PIPE_CAPF_GUARD_BAND_TOP:
 401       return 0.0f;
 402    case PIPE_CAPF_GUARD_BAND_RIGHT:
 403    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 404       return 0.0f; /* that or infinity */
 405    }
 406
 407    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 408    return 0.0f;
 409 }
 410
 411 static int
 412 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 413                               enum pipe_shader_ir ir_type,
 414                               enum pipe_compute_cap param, void *data)
 415 {
 416    struct nv50_screen *screen = nv50_screen(pscreen);
 417
 418 #define RET(x) do {                  \
 419    if (data)                         \
 420       memcpy(data, x, sizeof(x));    \
 421    return sizeof(x);                 \
 422 } while (0)
 423
 424    switch (param) {
 425    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 426       RET((uint64_t []) { 2 });
 427    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 428       RET(((uint64_t []) { 65535, 65535 }));
 429    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 430       RET(((uint64_t []) { 512, 512, 64 }));
 431    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 432       RET((uint64_t []) { 512 });
 433    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 434       RET((uint64_t []) { 1ULL << 32 });
 435    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 436       RET((uint64_t []) { 16 << 10 });
 437    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 438       RET((uint64_t []) { 16 << 10 });
 439    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 440       RET((uint64_t []) { 4096 });
 441    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 442       RET((uint32_t []) { 32 });
 443    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 444       RET((uint64_t []) { 1ULL << 40 });
 445    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 446       RET((uint32_t []) { 0 });
 447    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 448       RET((uint32_t []) { screen->mp_count });
 449    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 450       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 451    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 452       RET((uint32_t []) { 32 });
 453    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 454       RET((uint64_t []) { 0 });
 455    default:
 456       return 0;
 457    }
 458
 459 #undef RET
 460 }
 461
 462 static void
 463 nv50_screen_destroy(struct pipe_screen *pscreen)
 464 {
 465    struct nv50_screen *screen = nv50_screen(pscreen);
 466
 467    if (!nouveau_drm_screen_unref(&screen->base))
 468       return;
 469
 470    if (screen->base.fence.current) {
 471       struct nouveau_fence *current = NULL;
 472
 473       /* nouveau_fence_wait will create a new current fence, so wait on the
 474        * _current_ one, and remove both.
 475        */
 476       nouveau_fence_ref(screen->base.fence.current, &current);
 477       nouveau_fence_wait(current, NULL);
 478       nouveau_fence_ref(NULL, &current);
 479       nouveau_fence_ref(NULL, &screen->base.fence.current);
 480    }
 481    if (screen->base.pushbuf)
 482       screen->base.pushbuf->user_priv = NULL;
 483
 484    if (screen->blitter)
 485       nv50_blitter_destroy(screen);
 486    if (screen->pm.prog) {
 487       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 488       nv50_program_destroy(NULL, screen->pm.prog);
 489       FREE(screen->pm.prog);
 490    }
 491
 492    nouveau_bo_ref(NULL, &screen->code);
 493    nouveau_bo_ref(NULL, &screen->tls_bo);
 494    nouveau_bo_ref(NULL, &screen->stack_bo);
 495    nouveau_bo_ref(NULL, &screen->txc);
 496    nouveau_bo_ref(NULL, &screen->uniforms);
 497    nouveau_bo_ref(NULL, &screen->fence.bo);
 498
 499    nouveau_heap_destroy(&screen->vp_code_heap);
 500    nouveau_heap_destroy(&screen->gp_code_heap);
 501    nouveau_heap_destroy(&screen->fp_code_heap);
 502
 503    FREE(screen->tic.entries);
 504
 505    nouveau_object_del(&screen->tesla);
 506    nouveau_object_del(&screen->eng2d);
 507    nouveau_object_del(&screen->m2mf);
 508    nouveau_object_del(&screen->compute);
 509    nouveau_object_del(&screen->sync);
 510
 511    nouveau_screen_fini(&screen->base);
 512
 513    FREE(screen);
 514 }
 515
 516 static void
 517 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 518 {
 519    struct nv50_screen *screen = nv50_screen(pscreen);
 520    struct nouveau_pushbuf *push = screen->base.pushbuf;
 521
 522    /* we need to do it after possible flush in MARK_RING */
 523    *sequence = ++screen->base.fence.sequence;
 524
 525    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 526    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 527    PUSH_DATAh(push, screen->fence.bo->offset);
 528    PUSH_DATA (push, screen->fence.bo->offset);
 529    PUSH_DATA (push, *sequence);
 530    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 531                     NV50_3D_QUERY_GET_UNK4 |
 532                     NV50_3D_QUERY_GET_UNIT_CROP |
 533                     NV50_3D_QUERY_GET_TYPE_QUERY |
 534                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 535                     NV50_3D_QUERY_GET_SHORT);
 536 }
 537
 538 static u32
 539 nv50_screen_fence_update(struct pipe_screen *pscreen)
 540 {
 541    return nv50_screen(pscreen)->fence.map[0];
 542 }
 543
 544 static void
 545 nv50_screen_init_hwctx(struct nv50_screen *screen)
 546 {
 547    struct nouveau_pushbuf *push = screen->base.pushbuf;
 548    struct nv04_fifo *fifo;
 549    unsigned i;
 550
 551    fifo = (struct nv04_fifo *)screen->base.channel->data;
 552
 553    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 554    PUSH_DATA (push, screen->m2mf->handle);
 555    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 556    PUSH_DATA (push, screen->sync->handle);
 557    PUSH_DATA (push, fifo->vram);
 558    PUSH_DATA (push, fifo->vram);
 559
 560    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 561    PUSH_DATA (push, screen->eng2d->handle);
 562    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 563    PUSH_DATA (push, screen->sync->handle);
 564    PUSH_DATA (push, fifo->vram);
 565    PUSH_DATA (push, fifo->vram);
 566    PUSH_DATA (push, fifo->vram);
 567    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 568    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 569    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 570    PUSH_DATA (push, 0);
 571    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 572    PUSH_DATA (push, 0);
 573    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 574    PUSH_DATA (push, 1);
 575    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 576    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 577
 578    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 579    PUSH_DATA (push, screen->tesla->handle);
 580
 581    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 582    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 583
 584    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 585    PUSH_DATA (push, screen->sync->handle);
 586    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 587    for (i = 0; i < 11; ++i)
 588       PUSH_DATA(push, fifo->vram);
 589    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 590    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 591       PUSH_DATA(push, fifo->vram);
 592
 593    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 594    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 595    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 596    PUSH_DATA (push, 0xf);
 597
 598    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 599       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 600       PUSH_DATA (push, 0x18);
 601    }
 602
 603    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 604    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 605
 606    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 607    for (i = 0; i < 8; ++i)
 608       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 609
 610    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 611    PUSH_DATA (push, 1);
 612
 613    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 614    PUSH_DATA (push, 0);
 615    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 616    PUSH_DATA (push, 0);
 617    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 618    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 619    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 620    PUSH_DATA (push, 0);
 621    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 622    PUSH_DATA (push, 1);
 623    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 624    PUSH_DATA (push, 1);
 625
 626    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 627       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 628       PUSH_DATA (push, 0);
 629    }
 630
 631    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 632    PUSH_DATA (push, 0);
 633    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 634    PUSH_DATA (push, 0);
 635    PUSH_DATA (push, 0);
 636    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 637    PUSH_DATA (push, 0x3f);
 638
 639    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 640    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 641    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 642
 643    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 644    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 645    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 646
 647    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 648    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 649    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 650
 651    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 652    PUSH_DATAh(push, screen->tls_bo->offset);
 653    PUSH_DATA (push, screen->tls_bo->offset);
 654    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 655
 656    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 657    PUSH_DATAh(push, screen->stack_bo->offset);
 658    PUSH_DATA (push, screen->stack_bo->offset);
 659    PUSH_DATA (push, 4);
 660
 661    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 662    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 663    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 664    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 665
 666    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 667    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 668    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 669    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 670
 671    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 672    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 673    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 674    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 675
 676    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 677    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 678    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 679    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 680
 681    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 682    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 683    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 684    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 685
 686    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 687    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 688    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 689    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 690    PUSH_DATAf(push, 0.0f);
 691    PUSH_DATAf(push, 0.0f);
 692    PUSH_DATAf(push, 0.0f);
 693    PUSH_DATAf(push, 0.0f);
 694    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 695    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 696    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 697
 698    nv50_upload_ms_info(push);
 699
 700    /* max TIC (bits 4:8) & TSC bindings, per program type */
 701    for (i = 0; i < 3; ++i) {
 702       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 703       PUSH_DATA (push, 0x54);
 704    }
 705
 706    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 707    PUSH_DATAh(push, screen->txc->offset);
 708    PUSH_DATA (push, screen->txc->offset);
 709    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 710
 711    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 712    PUSH_DATAh(push, screen->txc->offset + 65536);
 713    PUSH_DATA (push, screen->txc->offset + 65536);
 714    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 715
 716    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 717    PUSH_DATA (push, 0);
 718
 719    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 720    PUSH_DATA (push, 0);
 721    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 722    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 723    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 724    for (i = 0; i < 8 * 2; ++i)
 725       PUSH_DATA(push, 0);
 726    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 727    PUSH_DATA (push, 0);
 728
 729    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 730    PUSH_DATA (push, 1);
 731    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 732       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 733       PUSH_DATAf(push, 0.0f);
 734       PUSH_DATAf(push, 1.0f);
 735       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 736       PUSH_DATA (push, 8192 << 16);
 737       PUSH_DATA (push, 8192 << 16);
 738    }
 739
 740    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 741 #ifdef NV50_SCISSORS_CLIPPING
 742    PUSH_DATA (push, 0x0000);
 743 #else
 744    PUSH_DATA (push, 0x1080);
 745 #endif
 746
 747    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 748    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 749
 750    /* We use scissors instead of exact view volume clipping,
 751     * so they're always enabled.
 752     */
 753    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 754       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 755       PUSH_DATA (push, 1);
 756       PUSH_DATA (push, 8192 << 16);
 757       PUSH_DATA (push, 8192 << 16);
 758    }
 759
 760    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 761    PUSH_DATA (push, 1);
 762    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 763    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 764    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 765    PUSH_DATA (push, 0x11111111);
 766    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 767    PUSH_DATA (push, 1);
 768
 769    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 770    PUSH_DATA (push, 0);
 771    if (screen->base.class_3d >= NV84_3D_CLASS) {
 772       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 773       PUSH_DATA (push, 0);
 774    }
 775
 776    BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
 777    PUSH_DATA (push, 1);
 778    BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
 779    PUSH_DATA (push, 1);
 780
 781    PUSH_KICK (push);
 782 }
 783
 784 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 785       uint64_t *tls_size)
 786 {
 787    struct nouveau_device *dev = screen->base.device;
 788    int ret;
 789
 790    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 791          ONE_TEMP_SIZE;
 792    if (nouveau_mesa_debug)
 793       debug_printf("allocating space for %u temps\n",
 794             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 795    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 796          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 797
 798    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 799                         *tls_size, NULL, &screen->tls_bo);
 800    if (ret) {
 801       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 802       return ret;
 803    }
 804
 805    return 0;
 806 }
 807
 808 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 809 {
 810    struct nouveau_pushbuf *push = screen->base.pushbuf;
 811    int ret;
 812    uint64_t tls_size;
 813
 814    if (tls_space < screen->cur_tls_space)
 815       return 0;
 816    if (tls_space > screen->max_tls_space) {
 817       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 818        * LOCAL_WARPS_NO_CLAMP) */
 819       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 820             (unsigned)(tls_space / ONE_TEMP_SIZE),
 821             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 822       return -ENOMEM;
 823    }
 824
 825    nouveau_bo_ref(NULL, &screen->tls_bo);
 826    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 827    if (ret)
 828       return ret;
 829
 830    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 831    PUSH_DATAh(push, screen->tls_bo->offset);
 832    PUSH_DATA (push, screen->tls_bo->offset);
 833    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 834
 835    return 1;
 836 }
 837
 838 struct nouveau_screen *
 839 nv50_screen_create(struct nouveau_device *dev)
 840 {
 841    struct nv50_screen *screen;
 842    struct pipe_screen *pscreen;
 843    struct nouveau_object *chan;
 844    uint64_t value;
 845    uint32_t tesla_class;
 846    unsigned stack_size;
 847    int ret;
 848
 849    screen = CALLOC_STRUCT(nv50_screen);
 850    if (!screen)
 851       return NULL;
 852    pscreen = &screen->base.base;
 853    pscreen->destroy = nv50_screen_destroy;
 854
 855    ret = nouveau_screen_init(&screen->base, dev);
 856    if (ret) {
 857       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 858       goto fail;
 859    }
 860
 861    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 862     *  admit them to VRAM.
 863     */
 864    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 865       PIPE_BIND_VERTEX_BUFFER;
 866    screen->base.sysmem_bindings |=
 867       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 868
 869    screen->base.pushbuf->user_priv = screen;
 870    screen->base.pushbuf->rsvd_kick = 5;
 871
 872    chan = screen->base.channel;
 873
 874    pscreen->context_create = nv50_create;
 875    pscreen->is_format_supported = nv50_screen_is_format_supported;
 876    pscreen->get_param = nv50_screen_get_param;
 877    pscreen->get_shader_param = nv50_screen_get_shader_param;
 878    pscreen->get_paramf = nv50_screen_get_paramf;
 879    pscreen->get_compute_param = nv50_screen_get_compute_param;
 880    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 881    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 882
 883    nv50_screen_init_resource_functions(pscreen);
 884
 885    if (screen->base.device->chipset < 0x84 ||
 886        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 887       /* PMPEG */
 888       nouveau_screen_init_vdec(&screen->base);
 889    } else if (screen->base.device->chipset < 0x98 ||
 890               screen->base.device->chipset == 0xa0) {
 891       /* VP2 */
 892       screen->base.base.get_video_param = nv84_screen_get_video_param;
 893       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 894    } else {
 895       /* VP3/4 */
 896       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 897       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 898    }
 899
 900    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 901                         NULL, &screen->fence.bo);
 902    if (ret) {
 903       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 904       goto fail;
 905    }
 906
 907    nouveau_bo_map(screen->fence.bo, 0, NULL);
 908    screen->fence.map = screen->fence.bo->map;
 909    screen->base.fence.emit = nv50_screen_fence_emit;
 910    screen->base.fence.update = nv50_screen_fence_update;
 911
 912    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 913                             &(struct nv04_notify){ .length = 32 },
 914                             sizeof(struct nv04_notify), &screen->sync);
 915    if (ret) {
 916       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 917       goto fail;
 918    }
 919
 920    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 921                             NULL, 0, &screen->m2mf);
 922    if (ret) {
 923       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 924       goto fail;
 925    }
 926
 927    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 928                             NULL, 0, &screen->eng2d);
 929    if (ret) {
 930       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 931       goto fail;
 932    }
 933
 934    switch (dev->chipset & 0xf0) {
 935    case 0x50:
 936       tesla_class = NV50_3D_CLASS;
 937       break;
 938    case 0x80:
 939    case 0x90:
 940       tesla_class = NV84_3D_CLASS;
 941       break;
 942    case 0xa0:
 943       switch (dev->chipset) {
 944       case 0xa0:
 945       case 0xaa:
 946       case 0xac:
 947          tesla_class = NVA0_3D_CLASS;
 948          break;
 949       case 0xaf:
 950          tesla_class = NVAF_3D_CLASS;
 951          break;
 952       default:
 953          tesla_class = NVA3_3D_CLASS;
 954          break;
 955       }
 956       break;
 957    default:
 958       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 959       goto fail;
 960    }
 961    screen->base.class_3d = tesla_class;
 962
 963    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 964                             NULL, 0, &screen->tesla);
 965    if (ret) {
 966       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 967       goto fail;
 968    }
 969
 970    /* This over-allocates by a page. The GP, which would execute at the end of
 971     * the last page, would trigger faults. The going theory is that it
 972     * prefetches up to a certain amount.
 973     */
 974    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 975                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 976                         NULL, &screen->code);
 977    if (ret) {
 978       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 979       goto fail;
 980    }
 981
 982    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 983    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 984    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 985
 986    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 987
 988    screen->TPs = util_bitcount(value & 0xffff);
 989    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 990
 991    screen->mp_count = screen->TPs * screen->MPsInTP;
 992
 993    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 994          STACK_WARPS_ALLOC * 64 * 8;
 995
 996    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 997                         &screen->stack_bo);
 998    if (ret) {
 999       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1000       goto fail;
1001    }
1002
1003    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1004          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
1005          ONE_TEMP_SIZE;
1006    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1007    screen->max_tls_space /= 2; /* half of vram */
1008
1009    /* hw can address max 64 KiB */
1010    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1011
1012    uint64_t tls_size;
1013    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1014    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1015    if (ret)
1016       goto fail;
1017
1018    if (nouveau_mesa_debug)
1019       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1020             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1021
1022    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1023                         &screen->uniforms);
1024    if (ret) {
1025       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1026       goto fail;
1027    }
1028
1029    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1030                         &screen->txc);
1031    if (ret) {
1032       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1033       goto fail;
1034    }
1035
1036    screen->tic.entries = CALLOC(4096, sizeof(void *));
1037    screen->tsc.entries = screen->tic.entries + 2048;
1038
1039    if (!nv50_blitter_create(screen))
1040       goto fail;
1041
1042    nv50_screen_init_hwctx(screen);
1043
1044    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1045    if (ret) {
1046       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1047       goto fail;
1048    }
1049
1050    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1051
1052    return &screen->base;
1053
1054 fail:
1055    screen->base.base.context_create = NULL;
1056    return &screen->base;
1057 }
1058
1059 int
1060 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1061 {
1062    int i = screen->tic.next;
1063
1064    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1065       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1066
1067    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1068
1069    if (screen->tic.entries[i])
1070       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1071
1072    screen->tic.entries[i] = entry;
1073    return i;
1074 }
1075
1076 int
1077 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1078 {
1079    int i = screen->tsc.next;
1080
1081    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1082       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1083
1084    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1085
1086    if (screen->tsc.entries[i])
1087       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1088
1089    screen->tsc.entries[i] = entry;
1090    return i;
1091 }