src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50/nv50_context.h"
  28 #include "nv50/nv50_screen.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nv_object.xml.h"
  33 #include <errno.h>
  34
  35 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  36 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  37 #endif
  38
  39 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  40 #define LOCAL_WARPS_ALLOC 32
  41 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  42 #define STACK_WARPS_ALLOC 32
  43
  44 #define THREADS_IN_WARP 32
  45
  46 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
  47
  48 static boolean
  49 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  50                                 enum pipe_format format,
  51                                 enum pipe_texture_target target,
  52                                 unsigned sample_count,
  53                                 unsigned bindings)
  54 {
  55    if (sample_count > 8)
  56       return FALSE;
  57    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  58       return FALSE;
  59    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  60       return FALSE;
  61
  62    if (!util_format_is_supported(format, bindings))
  63       return FALSE;
  64
  65    switch (format) {
  66    case PIPE_FORMAT_Z16_UNORM:
  67       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  68          return FALSE;
  69       break;
  70    default:
  71       break;
  72    }
  73
  74    /* transfers & shared are always supported */
  75    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  76                  PIPE_BIND_TRANSFER_WRITE |
  77                  PIPE_BIND_SHARED);
  78
  79    return (nv50_format_table[format].usage & bindings) == bindings;
  80 }
  81
  82 static int
  83 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  84 {
  85    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  86
  87    switch (param) {
  88    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  89       return 14;
  90    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  91       return 12;
  92    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  93       return 14;
  94    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  95       return 512;
  96    case PIPE_CAP_MIN_TEXEL_OFFSET:
  97       return -8;
  98    case PIPE_CAP_MAX_TEXEL_OFFSET:
  99       return 7;
 100    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 101    case PIPE_CAP_TEXTURE_SWIZZLE:
 102    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 103    case PIPE_CAP_NPOT_TEXTURES:
 104    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 105    case PIPE_CAP_ANISOTROPIC_FILTER:
 106    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 107       return 1;
 108    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 109       return 65536;
 110    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 111       return 1; /* nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS; */
 112    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 113       return 0;
 114    case PIPE_CAP_CUBE_MAP_ARRAY:
 115       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 116    case PIPE_CAP_TWO_SIDED_STENCIL:
 117    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 118    case PIPE_CAP_POINT_SPRITE:
 119       return 1;
 120    case PIPE_CAP_SM3:
 121       return 1;
 122    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 123       return 330;
 124    case PIPE_CAP_MAX_RENDER_TARGETS:
 125       return 8;
 126    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 127       return 1;
 128    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 129    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 130    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 131       return 1;
 132    case PIPE_CAP_QUERY_TIMESTAMP:
 133    case PIPE_CAP_QUERY_TIME_ELAPSED:
 134    case PIPE_CAP_OCCLUSION_QUERY:
 135       return 1;
 136    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 137       return 4;
 138    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 139    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 140       return 64;
 141    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 142    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 143       return 1024;
 144    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 145       return (class_3d >= NVA0_3D_CLASS) ? 1 : 0;
 146    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 147    case PIPE_CAP_INDEP_BLEND_ENABLE:
 148       return 1;
 149    case PIPE_CAP_INDEP_BLEND_FUNC:
 150       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 151    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 152    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 153       return 1;
 154    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 155    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 156       return 0;
 157    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 158       return 0;
 159    case PIPE_CAP_PRIMITIVE_RESTART:
 160    case PIPE_CAP_TGSI_INSTANCEID:
 161    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 162    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 163    case PIPE_CAP_CONDITIONAL_RENDER:
 164    case PIPE_CAP_TEXTURE_BARRIER:
 165    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 166    case PIPE_CAP_START_INSTANCE:
 167       return 1;
 168    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 169       return 0; /* state trackers will know better */
 170    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 171    case PIPE_CAP_USER_INDEX_BUFFERS:
 172    case PIPE_CAP_USER_VERTEX_BUFFERS:
 173       return 1;
 174    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 175       return 256;
 176    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 177       return 1; /* 256 for binding as RT, but that's not possible in GL */
 178    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 179       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 180    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 181    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 182    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 183    case PIPE_CAP_TGSI_TEXCOORD:
 184       return 0;
 185    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 186       return 1;
 187    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 188       return 1;
 189    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 190       return 0;
 191    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 192       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 193    case PIPE_CAP_ENDIANNESS:
 194       return PIPE_ENDIAN_LITTLE;
 195    case PIPE_CAP_TGSI_VS_LAYER:
 196    case PIPE_CAP_TEXTURE_GATHER_SM5:
 197    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 198    case PIPE_CAP_FAKE_SW_MSAA:
 199    case PIPE_CAP_TEXTURE_QUERY_LOD:
 200       return 0;
 201    case PIPE_CAP_MAX_VIEWPORTS:
 202       return NV50_MAX_VIEWPORTS;
 203    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 204       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 205    default:
 206       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 207       return 0;
 208    }
 209 }
 210
 211 static int
 212 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 213                              enum pipe_shader_cap param)
 214 {
 215    switch (shader) {
 216    case PIPE_SHADER_VERTEX:
 217    case PIPE_SHADER_GEOMETRY:
 218    case PIPE_SHADER_FRAGMENT:
 219       break;
 220    default:
 221       return 0;
 222    }
 223
 224    switch (param) {
 225    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 226    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 227    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 228    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 229       return 16384;
 230    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 231       return 4;
 232    case PIPE_SHADER_CAP_MAX_INPUTS:
 233       if (shader == PIPE_SHADER_VERTEX)
 234          return 32;
 235       return 15;
 236    case PIPE_SHADER_CAP_MAX_CONSTS:
 237       return 65536 / 16;
 238    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 239       return NV50_MAX_PIPE_CONSTBUFS;
 240    case PIPE_SHADER_CAP_MAX_ADDRS:
 241       return 1;
 242    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 243    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 244       return shader != PIPE_SHADER_FRAGMENT;
 245    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 246    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 247       return 1;
 248    case PIPE_SHADER_CAP_MAX_PREDS:
 249       return 0;
 250    case PIPE_SHADER_CAP_MAX_TEMPS:
 251       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 252    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 253       return 1;
 254    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 255       return 0;
 256    case PIPE_SHADER_CAP_SUBROUTINES:
 257       return 0; /* please inline, or provide function declarations */
 258    case PIPE_SHADER_CAP_INTEGERS:
 259       return 1;
 260    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 261       /* The chip could handle more sampler views than samplers */
 262    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 263       return MIN2(32, PIPE_MAX_SAMPLERS);
 264    default:
 265       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 266       return 0;
 267    }
 268 }
 269
 270 static float
 271 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 272 {
 273    switch (param) {
 274    case PIPE_CAPF_MAX_LINE_WIDTH:
 275    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 276       return 10.0f;
 277    case PIPE_CAPF_MAX_POINT_WIDTH:
 278    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 279       return 64.0f;
 280    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 281       return 16.0f;
 282    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 283       return 4.0f;
 284    default:
 285       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 286       return 0.0f;
 287    }
 288 }
 289
 290 static void
 291 nv50_screen_destroy(struct pipe_screen *pscreen)
 292 {
 293    struct nv50_screen *screen = nv50_screen(pscreen);
 294
 295    if (!nouveau_drm_screen_unref(&screen->base))
 296       return;
 297
 298    if (screen->base.fence.current) {
 299       struct nouveau_fence *current = NULL;
 300
 301       /* nouveau_fence_wait will create a new current fence, so wait on the
 302        * _current_ one, and remove both.
 303        */
 304       nouveau_fence_ref(screen->base.fence.current, &current);
 305       nouveau_fence_wait(current);
 306       nouveau_fence_ref(NULL, &current);
 307       nouveau_fence_ref(NULL, &screen->base.fence.current);
 308    }
 309    if (screen->base.pushbuf)
 310       screen->base.pushbuf->user_priv = NULL;
 311
 312    if (screen->blitter)
 313       nv50_blitter_destroy(screen);
 314
 315    nouveau_bo_ref(NULL, &screen->code);
 316    nouveau_bo_ref(NULL, &screen->tls_bo);
 317    nouveau_bo_ref(NULL, &screen->stack_bo);
 318    nouveau_bo_ref(NULL, &screen->txc);
 319    nouveau_bo_ref(NULL, &screen->uniforms);
 320    nouveau_bo_ref(NULL, &screen->fence.bo);
 321
 322    nouveau_heap_destroy(&screen->vp_code_heap);
 323    nouveau_heap_destroy(&screen->gp_code_heap);
 324    nouveau_heap_destroy(&screen->fp_code_heap);
 325
 326    FREE(screen->tic.entries);
 327
 328    nouveau_object_del(&screen->tesla);
 329    nouveau_object_del(&screen->eng2d);
 330    nouveau_object_del(&screen->m2mf);
 331    nouveau_object_del(&screen->sync);
 332
 333    nouveau_screen_fini(&screen->base);
 334
 335    FREE(screen);
 336 }
 337
 338 static void
 339 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 340 {
 341    struct nv50_screen *screen = nv50_screen(pscreen);
 342    struct nouveau_pushbuf *push = screen->base.pushbuf;
 343
 344    /* we need to do it after possible flush in MARK_RING */
 345    *sequence = ++screen->base.fence.sequence;
 346
 347    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 348    PUSH_DATAh(push, screen->fence.bo->offset);
 349    PUSH_DATA (push, screen->fence.bo->offset);
 350    PUSH_DATA (push, *sequence);
 351    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 352                     NV50_3D_QUERY_GET_UNK4 |
 353                     NV50_3D_QUERY_GET_UNIT_CROP |
 354                     NV50_3D_QUERY_GET_TYPE_QUERY |
 355                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 356                     NV50_3D_QUERY_GET_SHORT);
 357 }
 358
 359 static u32
 360 nv50_screen_fence_update(struct pipe_screen *pscreen)
 361 {
 362    return nv50_screen(pscreen)->fence.map[0];
 363 }
 364
 365 static void
 366 nv50_screen_init_hwctx(struct nv50_screen *screen)
 367 {
 368    struct nouveau_pushbuf *push = screen->base.pushbuf;
 369    struct nv04_fifo *fifo;
 370    unsigned i;
 371
 372    fifo = (struct nv04_fifo *)screen->base.channel->data;
 373
 374    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 375    PUSH_DATA (push, screen->m2mf->handle);
 376    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 377    PUSH_DATA (push, screen->sync->handle);
 378    PUSH_DATA (push, fifo->vram);
 379    PUSH_DATA (push, fifo->vram);
 380
 381    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 382    PUSH_DATA (push, screen->eng2d->handle);
 383    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 384    PUSH_DATA (push, screen->sync->handle);
 385    PUSH_DATA (push, fifo->vram);
 386    PUSH_DATA (push, fifo->vram);
 387    PUSH_DATA (push, fifo->vram);
 388    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 389    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 390    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 391    PUSH_DATA (push, 0);
 392    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 393    PUSH_DATA (push, 0);
 394    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 395    PUSH_DATA (push, 1);
 396
 397    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 398    PUSH_DATA (push, screen->tesla->handle);
 399
 400    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 401    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 402
 403    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 404    PUSH_DATA (push, screen->sync->handle);
 405    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 406    for (i = 0; i < 11; ++i)
 407       PUSH_DATA(push, fifo->vram);
 408    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 409    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 410       PUSH_DATA(push, fifo->vram);
 411
 412    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 413    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 414    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 415    PUSH_DATA (push, 0xf);
 416
 417    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 418       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 419       PUSH_DATA (push, 0x18);
 420    }
 421
 422    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 423    PUSH_DATA (push, 1);
 424
 425    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 426    PUSH_DATA (push, 0);
 427    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 428    PUSH_DATA (push, 0);
 429    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 430    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 431    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 432    PUSH_DATA (push, 0);
 433    BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
 434    PUSH_DATA (push, 0);
 435    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 436    PUSH_DATA (push, 1);
 437
 438    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 439       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 440       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 441    }
 442
 443    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 444    PUSH_DATA (push, 0);
 445    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 446    PUSH_DATA (push, 0);
 447    PUSH_DATA (push, 0);
 448    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 449    PUSH_DATA (push, 0x3f);
 450
 451    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 452    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 453    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 454
 455    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 456    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 457    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 458
 459    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 460    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 461    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 462
 463    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 464    PUSH_DATAh(push, screen->tls_bo->offset);
 465    PUSH_DATA (push, screen->tls_bo->offset);
 466    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 467
 468    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 469    PUSH_DATAh(push, screen->stack_bo->offset);
 470    PUSH_DATA (push, screen->stack_bo->offset);
 471    PUSH_DATA (push, 4);
 472
 473    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 474    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 475    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 476    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 477
 478    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 479    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 480    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 481    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 482
 483    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 484    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 485    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 486    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 487
 488    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 489    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 490    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 491    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 492
 493    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 494    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 495    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 496    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 497
 498    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 499    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 500    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 501    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 502    PUSH_DATAf(push, 0.0f);
 503    PUSH_DATAf(push, 0.0f);
 504    PUSH_DATAf(push, 0.0f);
 505    PUSH_DATAf(push, 0.0f);
 506    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 507    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 508    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 509
 510    nv50_upload_ms_info(push);
 511
 512    /* max TIC (bits 4:8) & TSC bindings, per program type */
 513    for (i = 0; i < 3; ++i) {
 514       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 515       PUSH_DATA (push, 0x54);
 516    }
 517
 518    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 519    PUSH_DATAh(push, screen->txc->offset);
 520    PUSH_DATA (push, screen->txc->offset);
 521    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 522
 523    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 524    PUSH_DATAh(push, screen->txc->offset + 65536);
 525    PUSH_DATA (push, screen->txc->offset + 65536);
 526    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 527
 528    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 529    PUSH_DATA (push, 0);
 530
 531    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 532    PUSH_DATA (push, 0);
 533    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 534    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 535    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 536    for (i = 0; i < 8 * 2; ++i)
 537       PUSH_DATA(push, 0);
 538    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 539    PUSH_DATA (push, 0);
 540
 541    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 542    PUSH_DATA (push, 1);
 543    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 544       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 545       PUSH_DATAf(push, 0.0f);
 546       PUSH_DATAf(push, 1.0f);
 547       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 548       PUSH_DATA (push, 8192 << 16);
 549       PUSH_DATA (push, 8192 << 16);
 550    }
 551
 552    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 553 #ifdef NV50_SCISSORS_CLIPPING
 554    PUSH_DATA (push, 0x0000);
 555 #else
 556    PUSH_DATA (push, 0x1080);
 557 #endif
 558
 559    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 560    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 561
 562    /* We use scissors instead of exact view volume clipping,
 563     * so they're always enabled.
 564     */
 565    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 566       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 567       PUSH_DATA (push, 1);
 568       PUSH_DATA (push, 8192 << 16);
 569       PUSH_DATA (push, 8192 << 16);
 570    }
 571
 572    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 573    PUSH_DATA (push, 1);
 574    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 575    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 576    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 577    PUSH_DATA (push, 0x11111111);
 578    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 579    PUSH_DATA (push, 1);
 580
 581    PUSH_KICK (push);
 582 }
 583
 584 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 585       uint64_t *tls_size)
 586 {
 587    struct nouveau_device *dev = screen->base.device;
 588    int ret;
 589
 590    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 591          ONE_TEMP_SIZE;
 592    if (nouveau_mesa_debug)
 593       debug_printf("allocating space for %u temps\n",
 594             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 595    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 596          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 597
 598    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 599                         *tls_size, NULL, &screen->tls_bo);
 600    if (ret) {
 601       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 602       return ret;
 603    }
 604
 605    return 0;
 606 }
 607
 608 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 609 {
 610    struct nouveau_pushbuf *push = screen->base.pushbuf;
 611    int ret;
 612    uint64_t tls_size;
 613
 614    if (tls_space < screen->cur_tls_space)
 615       return 0;
 616    if (tls_space > screen->max_tls_space) {
 617       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 618        * LOCAL_WARPS_NO_CLAMP) */
 619       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 620             (unsigned)(tls_space / ONE_TEMP_SIZE),
 621             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 622       return -ENOMEM;
 623    }
 624
 625    nouveau_bo_ref(NULL, &screen->tls_bo);
 626    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 627    if (ret)
 628       return ret;
 629
 630    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 631    PUSH_DATAh(push, screen->tls_bo->offset);
 632    PUSH_DATA (push, screen->tls_bo->offset);
 633    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 634
 635    return 1;
 636 }
 637
 638 struct pipe_screen *
 639 nv50_screen_create(struct nouveau_device *dev)
 640 {
 641    struct nv50_screen *screen;
 642    struct pipe_screen *pscreen;
 643    struct nouveau_object *chan;
 644    uint64_t value;
 645    uint32_t tesla_class;
 646    unsigned stack_size;
 647    int ret;
 648
 649    screen = CALLOC_STRUCT(nv50_screen);
 650    if (!screen)
 651       return NULL;
 652    pscreen = &screen->base.base;
 653
 654    ret = nouveau_screen_init(&screen->base, dev);
 655    if (ret) {
 656       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 657       goto fail;
 658    }
 659
 660    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 661     *  admit them to VRAM.
 662     */
 663    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 664       PIPE_BIND_VERTEX_BUFFER;
 665    screen->base.sysmem_bindings |=
 666       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 667
 668    screen->base.pushbuf->user_priv = screen;
 669    screen->base.pushbuf->rsvd_kick = 5;
 670
 671    chan = screen->base.channel;
 672
 673    pscreen->destroy = nv50_screen_destroy;
 674    pscreen->context_create = nv50_create;
 675    pscreen->is_format_supported = nv50_screen_is_format_supported;
 676    pscreen->get_param = nv50_screen_get_param;
 677    pscreen->get_shader_param = nv50_screen_get_shader_param;
 678    pscreen->get_paramf = nv50_screen_get_paramf;
 679
 680    nv50_screen_init_resource_functions(pscreen);
 681
 682    if (screen->base.device->chipset < 0x84 ||
 683        debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) {
 684       /* PMPEG */
 685       nouveau_screen_init_vdec(&screen->base);
 686    } else if (screen->base.device->chipset < 0x98 ||
 687               screen->base.device->chipset == 0xa0) {
 688       /* VP2 */
 689       screen->base.base.get_video_param = nv84_screen_get_video_param;
 690       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 691    } else {
 692       /* VP3/4 */
 693       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 694       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 695    }
 696
 697    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 698                         NULL, &screen->fence.bo);
 699    if (ret) {
 700       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 701       goto fail;
 702    }
 703
 704    nouveau_bo_map(screen->fence.bo, 0, NULL);
 705    screen->fence.map = screen->fence.bo->map;
 706    screen->base.fence.emit = nv50_screen_fence_emit;
 707    screen->base.fence.update = nv50_screen_fence_update;
 708
 709    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 710                             &(struct nv04_notify){ .length = 32 },
 711                             sizeof(struct nv04_notify), &screen->sync);
 712    if (ret) {
 713       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 714       goto fail;
 715    }
 716
 717    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 718                             NULL, 0, &screen->m2mf);
 719    if (ret) {
 720       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 721       goto fail;
 722    }
 723
 724    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 725                             NULL, 0, &screen->eng2d);
 726    if (ret) {
 727       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 728       goto fail;
 729    }
 730
 731    switch (dev->chipset & 0xf0) {
 732    case 0x50:
 733       tesla_class = NV50_3D_CLASS;
 734       break;
 735    case 0x80:
 736    case 0x90:
 737       tesla_class = NV84_3D_CLASS;
 738       break;
 739    case 0xa0:
 740       switch (dev->chipset) {
 741       case 0xa0:
 742       case 0xaa:
 743       case 0xac:
 744          tesla_class = NVA0_3D_CLASS;
 745          break;
 746       case 0xaf:
 747          tesla_class = NVAF_3D_CLASS;
 748          break;
 749       default:
 750          tesla_class = NVA3_3D_CLASS;
 751          break;
 752       }
 753       break;
 754    default:
 755       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 756       goto fail;
 757    }
 758    screen->base.class_3d = tesla_class;
 759
 760    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 761                             NULL, 0, &screen->tesla);
 762    if (ret) {
 763       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 764       goto fail;
 765    }
 766
 767    /* This over-allocates by a page. The GP, which would execute at the end of
 768     * the last page, would trigger faults. The going theory is that it
 769     * prefetches up to a certain amount.
 770     */
 771    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 772                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
 773                         NULL, &screen->code);
 774    if (ret) {
 775       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 776       goto fail;
 777    }
 778
 779    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 780    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 781    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 782
 783    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 784
 785    screen->TPs = util_bitcount(value & 0xffff);
 786    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 787
 788    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 789          STACK_WARPS_ALLOC * 64 * 8;
 790
 791    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 792                         &screen->stack_bo);
 793    if (ret) {
 794       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 795       goto fail;
 796    }
 797
 798    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 799          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 800          ONE_TEMP_SIZE;
 801    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 802    screen->max_tls_space /= 2; /* half of vram */
 803
 804    /* hw can address max 64 KiB */
 805    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 806
 807    uint64_t tls_size;
 808    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 809    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 810    if (ret)
 811       goto fail;
 812
 813    if (nouveau_mesa_debug)
 814       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 815             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 816
 817    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 818                         &screen->uniforms);
 819    if (ret) {
 820       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 821       goto fail;
 822    }
 823
 824    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 825                         &screen->txc);
 826    if (ret) {
 827       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 828       goto fail;
 829    }
 830
 831    screen->tic.entries = CALLOC(4096, sizeof(void *));
 832    screen->tsc.entries = screen->tic.entries + 2048;
 833
 834    if (!nv50_blitter_create(screen))
 835       goto fail;
 836
 837    nv50_screen_init_hwctx(screen);
 838
 839    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 840
 841    return pscreen;
 842
 843 fail:
 844    nv50_screen_destroy(pscreen);
 845    return NULL;
 846 }
 847
 848 int
 849 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 850 {
 851    int i = screen->tic.next;
 852
 853    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 854       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 855
 856    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 857
 858    if (screen->tic.entries[i])
 859       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 860
 861    screen->tic.entries[i] = entry;
 862    return i;
 863 }
 864
 865 int
 866 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 867 {
 868    int i = screen->tsc.next;
 869
 870    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 871       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 872
 873    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 874
 875    if (screen->tsc.entries[i])
 876       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 877
 878    screen->tsc.entries[i] = entry;
 879    return i;
 880 }