src/gallium/drivers/nouveau/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <errno.h>
  24 #include <xf86drm.h>
  25 #include <nouveau_drm.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "util/u_screen.h"
  29 #include "pipe/p_screen.h"
  30
  31 #include "nv50/nv50_context.h"
  32 #include "nv50/nv50_screen.h"
  33
  34 #include "nouveau_vp3_video.h"
  35
  36 #include "nv_object.xml.h"
  37
  38 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  39 #define LOCAL_WARPS_ALLOC 32
  40 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  41 #define STACK_WARPS_ALLOC 32
  42
  43 #define THREADS_IN_WARP 32
  44
  45 static boolean
  46 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  47                                 enum pipe_format format,
  48                                 enum pipe_texture_target target,
  49                                 unsigned sample_count,
  50                                 unsigned storage_sample_count,
  51                                 unsigned bindings)
  52 {
  53    if (sample_count > 8)
  54       return false;
  55    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  56       return false;
  57    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  58       return false;
  59
  60    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
  61       return false;
  62
  63    switch (format) {
  64    case PIPE_FORMAT_Z16_UNORM:
  65       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  66          return false;
  67       break;
  68    default:
  69       break;
  70    }
  71
  72    if (bindings & PIPE_BIND_LINEAR)
  73       if (util_format_is_depth_or_stencil(format) ||
  74           (target != PIPE_TEXTURE_1D &&
  75            target != PIPE_TEXTURE_2D &&
  76            target != PIPE_TEXTURE_RECT) ||
  77           sample_count > 1)
  78          return false;
  79
  80    /* shared is always supported */
  81    bindings &= ~(PIPE_BIND_LINEAR |
  82                  PIPE_BIND_SHARED);
  83
  84    return (( nv50_format_table[format].usage |
  85             nv50_vertex_format[format].usage) & bindings) == bindings;
  86 }
  87
  88 static int
  89 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  90 {
  91    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  92    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  93
  94    switch (param) {
  95    /* non-boolean caps */
  96    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  97       return 14;
  98    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  99       return 12;
 100    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 101       return 14;
 102    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 103       return 512;
 104    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 105    case PIPE_CAP_MIN_TEXEL_OFFSET:
 106       return -8;
 107    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 108    case PIPE_CAP_MAX_TEXEL_OFFSET:
 109       return 7;
 110    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 111       return 128 * 1024 * 1024;
 112    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 113       return 330;
 114    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 115       return 330;
 116    case PIPE_CAP_MAX_RENDER_TARGETS:
 117       return 8;
 118    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 119       return 1;
 120    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 121    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 122       return 8;
 123    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 124       return 4;
 125    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 127       return 64;
 128    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 129    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 130       return 1024;
 131    case PIPE_CAP_MAX_VERTEX_STREAMS:
 132       return 1;
 133    case PIPE_CAP_MAX_GS_INVOCATIONS:
 134       return 0;
 135    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 136       return 0;
 137    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 138       return 2048;
 139    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 140       return 2047;
 141    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 142       return 256;
 143    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 144       return 16; /* 256 for binding as RT, but that's not possible in GL */
 145    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 146       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 147    case PIPE_CAP_MAX_VIEWPORTS:
 148       return NV50_MAX_VIEWPORTS;
 149    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 150       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 151    case PIPE_CAP_ENDIANNESS:
 152       return PIPE_ENDIAN_LITTLE;
 153    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 154       return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
 155    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 156       return NV50_MAX_WINDOW_RECTANGLES;
 157    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 158       return 16 * 1024 * 1024;
 159
 160    /* supported caps */
 161    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 162    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 163    case PIPE_CAP_TEXTURE_SWIZZLE:
 164    case PIPE_CAP_NPOT_TEXTURES:
 165    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 166    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 167    case PIPE_CAP_ANISOTROPIC_FILTER:
 168    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 169    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 170    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 171    case PIPE_CAP_POINT_SPRITE:
 172    case PIPE_CAP_SM3:
 173    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 174    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 175    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 176    case PIPE_CAP_QUERY_TIMESTAMP:
 177    case PIPE_CAP_QUERY_TIME_ELAPSED:
 178    case PIPE_CAP_OCCLUSION_QUERY:
 179    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 180    case PIPE_CAP_INDEP_BLEND_ENABLE:
 181    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 182    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 183    case PIPE_CAP_PRIMITIVE_RESTART:
 184    case PIPE_CAP_TGSI_INSTANCEID:
 185    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 186    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 187    case PIPE_CAP_CONDITIONAL_RENDER:
 188    case PIPE_CAP_TEXTURE_BARRIER:
 189    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 190    case PIPE_CAP_START_INSTANCE:
 191    case PIPE_CAP_USER_VERTEX_BUFFERS:
 192    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 193    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 194    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 195    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 196    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 197    case PIPE_CAP_CLIP_HALFZ:
 198    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 199    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 200    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 201    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 202    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 203    case PIPE_CAP_TGSI_TXQS:
 204    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 205    case PIPE_CAP_SHAREABLE_SHADERS:
 206    case PIPE_CAP_CLEAR_TEXTURE:
 207    case PIPE_CAP_COMPUTE:
 208    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 209    case PIPE_CAP_INVALIDATE_BUFFER:
 210    case PIPE_CAP_STRING_MARKER:
 211    case PIPE_CAP_CULL_DISTANCE:
 212    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 213    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 214    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 215    case PIPE_CAP_TGSI_CLOCK:
 216    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 217    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 218    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
 219       return 1;
 220    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 221       return 1; /* class_3d >= NVA0_3D_CLASS; */
 222    /* supported on nva0+ */
 223    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 224       return class_3d >= NVA0_3D_CLASS;
 225    /* supported on nva3+ */
 226    case PIPE_CAP_CUBE_MAP_ARRAY:
 227    case PIPE_CAP_INDEP_BLEND_FUNC:
 228    case PIPE_CAP_TEXTURE_QUERY_LOD:
 229    case PIPE_CAP_SAMPLE_SHADING:
 230    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 231       return class_3d >= NVA3_3D_CLASS;
 232
 233    /* unsupported caps */
 234    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 235    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 236    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 237    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 238    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 239    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 240    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 241    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 242    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 243    case PIPE_CAP_TGSI_TEXCOORD:
 244    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 245    case PIPE_CAP_TEXTURE_GATHER_SM5:
 246    case PIPE_CAP_FAKE_SW_MSAA:
 247    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 248    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 249    case PIPE_CAP_DRAW_INDIRECT:
 250    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 251    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 252    case PIPE_CAP_VERTEXID_NOBASE:
 253    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
 254    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 255    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 256    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 257    case PIPE_CAP_DRAW_PARAMETERS:
 258    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 259    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 260    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 261    case PIPE_CAP_GENERATE_MIPMAP:
 262    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 263    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 264    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 265    case PIPE_CAP_QUERY_MEMORY_INFO:
 266    case PIPE_CAP_PCI_GROUP:
 267    case PIPE_CAP_PCI_BUS:
 268    case PIPE_CAP_PCI_DEVICE:
 269    case PIPE_CAP_PCI_FUNCTION:
 270    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 271    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 272    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 273    case PIPE_CAP_TGSI_VOTE:
 274    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 275    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 276    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 277    case PIPE_CAP_NATIVE_FENCE_FD:
 278    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 279    case PIPE_CAP_TGSI_FS_FBFETCH:
 280    case PIPE_CAP_DOUBLES:
 281    case PIPE_CAP_INT64:
 282    case PIPE_CAP_INT64_DIVMOD:
 283    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 284    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 285    case PIPE_CAP_TGSI_BALLOT:
 286    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 287    case PIPE_CAP_POST_DEPTH_COVERAGE:
 288    case PIPE_CAP_BINDLESS_TEXTURE:
 289    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 290    case PIPE_CAP_QUERY_SO_OVERFLOW:
 291    case PIPE_CAP_MEMOBJ:
 292    case PIPE_CAP_LOAD_CONSTBUF:
 293    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 294    case PIPE_CAP_TILE_RASTER_ORDER:
 295    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 296    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 297    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 298    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 299    case PIPE_CAP_FENCE_SIGNAL:
 300    case PIPE_CAP_CONSTBUF0_FLAGS:
 301    case PIPE_CAP_PACKED_UNIFORMS:
 302    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 303    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 304    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 305    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 306    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 307    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 308    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 309    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
 310    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 311    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 312    case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 313    case PIPE_CAP_TGSI_ATOMFADD:
 314    case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
 315    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
 316    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
 317       return 0;
 318
 319    case PIPE_CAP_VENDOR_ID:
 320       return 0x10de;
 321    case PIPE_CAP_DEVICE_ID: {
 322       uint64_t device_id;
 323       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 324          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 325          return -1;
 326       }
 327       return device_id;
 328    }
 329    case PIPE_CAP_ACCELERATED:
 330       return 1;
 331    case PIPE_CAP_VIDEO_MEMORY:
 332       return dev->vram_size >> 20;
 333    case PIPE_CAP_UMA:
 334       return 0;
 335    default:
 336       debug_printf("%s: unhandled cap %d\n", __func__, param);
 337       return u_pipe_screen_get_param_defaults(pscreen, param);
 338    }
 339 }
 340
 341 static int
 342 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
 343                              enum pipe_shader_type shader,
 344                              enum pipe_shader_cap param)
 345 {
 346    switch (shader) {
 347    case PIPE_SHADER_VERTEX:
 348    case PIPE_SHADER_GEOMETRY:
 349    case PIPE_SHADER_FRAGMENT:
 350       break;
 351    case PIPE_SHADER_COMPUTE:
 352    default:
 353       return 0;
 354    }
 355
 356    switch (param) {
 357    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 358    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 359    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 360    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 361       return 16384;
 362    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 363       return 4;
 364    case PIPE_SHADER_CAP_MAX_INPUTS:
 365       if (shader == PIPE_SHADER_VERTEX)
 366          return 32;
 367       return 15;
 368    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 369       return 16;
 370    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 371       return 65536;
 372    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 373       return NV50_MAX_PIPE_CONSTBUFS;
 374    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 375       return shader != PIPE_SHADER_FRAGMENT;
 376    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 377    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 378    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 379       return 1;
 380    case PIPE_SHADER_CAP_MAX_TEMPS:
 381       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 382    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 383       return 1;
 384    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 385       return 1;
 386    case PIPE_SHADER_CAP_INT64_ATOMICS:
 387    case PIPE_SHADER_CAP_FP16:
 388    case PIPE_SHADER_CAP_SUBROUTINES:
 389       return 0; /* please inline, or provide function declarations */
 390    case PIPE_SHADER_CAP_INTEGERS:
 391       return 1;
 392    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 393       return 1;
 394    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 395       /* The chip could handle more sampler views than samplers */
 396    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 397       return MIN2(16, PIPE_MAX_SAMPLERS);
 398    case PIPE_SHADER_CAP_PREFERRED_IR:
 399       return PIPE_SHADER_IR_TGSI;
 400    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 401       return 32;
 402    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 403    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 404    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 405    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 406    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 407    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 408    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 409    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 410    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 411    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 412    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 413       return 0;
 414    case PIPE_SHADER_CAP_SCALAR_ISA:
 415       return 1;
 416    default:
 417       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 418       return 0;
 419    }
 420 }
 421
 422 static float
 423 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 424 {
 425    switch (param) {
 426    case PIPE_CAPF_MAX_LINE_WIDTH:
 427    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 428       return 10.0f;
 429    case PIPE_CAPF_MAX_POINT_WIDTH:
 430    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 431       return 64.0f;
 432    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 433       return 16.0f;
 434    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 435       return 4.0f;
 436    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 437    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 438    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 439       return 0.0f;
 440    }
 441
 442    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 443    return 0.0f;
 444 }
 445
 446 static int
 447 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
 448                               enum pipe_shader_ir ir_type,
 449                               enum pipe_compute_cap param, void *data)
 450 {
 451    struct nv50_screen *screen = nv50_screen(pscreen);
 452
 453 #define RET(x) do {                  \
 454    if (data)                         \
 455       memcpy(data, x, sizeof(x));    \
 456    return sizeof(x);                 \
 457 } while (0)
 458
 459    switch (param) {
 460    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 461       RET((uint64_t []) { 2 });
 462    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 463       RET(((uint64_t []) { 65535, 65535 }));
 464    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 465       RET(((uint64_t []) { 512, 512, 64 }));
 466    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 467       RET((uint64_t []) { 512 });
 468    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
 469       RET((uint64_t []) { 1ULL << 32 });
 470    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 471       RET((uint64_t []) { 16 << 10 });
 472    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 473       RET((uint64_t []) { 16 << 10 });
 474    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 475       RET((uint64_t []) { 4096 });
 476    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 477       RET((uint32_t []) { 32 });
 478    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 479       RET((uint64_t []) { 1ULL << 40 });
 480    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 481       RET((uint32_t []) { 0 });
 482    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 483       RET((uint32_t []) { screen->mp_count });
 484    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 485       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 486    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 487       RET((uint32_t []) { 32 });
 488    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 489       RET((uint64_t []) { 0 });
 490    default:
 491       return 0;
 492    }
 493
 494 #undef RET
 495 }
 496
 497 static void
 498 nv50_screen_destroy(struct pipe_screen *pscreen)
 499 {
 500    struct nv50_screen *screen = nv50_screen(pscreen);
 501
 502    if (!nouveau_drm_screen_unref(&screen->base))
 503       return;
 504
 505    if (screen->base.fence.current) {
 506       struct nouveau_fence *current = NULL;
 507
 508       /* nouveau_fence_wait will create a new current fence, so wait on the
 509        * _current_ one, and remove both.
 510        */
 511       nouveau_fence_ref(screen->base.fence.current, &current);
 512       nouveau_fence_wait(current, NULL);
 513       nouveau_fence_ref(NULL, &current);
 514       nouveau_fence_ref(NULL, &screen->base.fence.current);
 515    }
 516    if (screen->base.pushbuf)
 517       screen->base.pushbuf->user_priv = NULL;
 518
 519    if (screen->blitter)
 520       nv50_blitter_destroy(screen);
 521    if (screen->pm.prog) {
 522       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 523       nv50_program_destroy(NULL, screen->pm.prog);
 524       FREE(screen->pm.prog);
 525    }
 526
 527    nouveau_bo_ref(NULL, &screen->code);
 528    nouveau_bo_ref(NULL, &screen->tls_bo);
 529    nouveau_bo_ref(NULL, &screen->stack_bo);
 530    nouveau_bo_ref(NULL, &screen->txc);
 531    nouveau_bo_ref(NULL, &screen->uniforms);
 532    nouveau_bo_ref(NULL, &screen->fence.bo);
 533
 534    nouveau_heap_destroy(&screen->vp_code_heap);
 535    nouveau_heap_destroy(&screen->gp_code_heap);
 536    nouveau_heap_destroy(&screen->fp_code_heap);
 537
 538    FREE(screen->tic.entries);
 539
 540    nouveau_object_del(&screen->tesla);
 541    nouveau_object_del(&screen->eng2d);
 542    nouveau_object_del(&screen->m2mf);
 543    nouveau_object_del(&screen->compute);
 544    nouveau_object_del(&screen->sync);
 545
 546    nouveau_screen_fini(&screen->base);
 547
 548    FREE(screen);
 549 }
 550
 551 static void
 552 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 553 {
 554    struct nv50_screen *screen = nv50_screen(pscreen);
 555    struct nouveau_pushbuf *push = screen->base.pushbuf;
 556
 557    /* we need to do it after possible flush in MARK_RING */
 558    *sequence = ++screen->base.fence.sequence;
 559
 560    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 561    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 562    PUSH_DATAh(push, screen->fence.bo->offset);
 563    PUSH_DATA (push, screen->fence.bo->offset);
 564    PUSH_DATA (push, *sequence);
 565    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 566                     NV50_3D_QUERY_GET_UNK4 |
 567                     NV50_3D_QUERY_GET_UNIT_CROP |
 568                     NV50_3D_QUERY_GET_TYPE_QUERY |
 569                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 570                     NV50_3D_QUERY_GET_SHORT);
 571 }
 572
 573 static u32
 574 nv50_screen_fence_update(struct pipe_screen *pscreen)
 575 {
 576    return nv50_screen(pscreen)->fence.map[0];
 577 }
 578
 579 static void
 580 nv50_screen_init_hwctx(struct nv50_screen *screen)
 581 {
 582    struct nouveau_pushbuf *push = screen->base.pushbuf;
 583    struct nv04_fifo *fifo;
 584    unsigned i;
 585
 586    fifo = (struct nv04_fifo *)screen->base.channel->data;
 587
 588    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 589    PUSH_DATA (push, screen->m2mf->handle);
 590    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 591    PUSH_DATA (push, screen->sync->handle);
 592    PUSH_DATA (push, fifo->vram);
 593    PUSH_DATA (push, fifo->vram);
 594
 595    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 596    PUSH_DATA (push, screen->eng2d->handle);
 597    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 598    PUSH_DATA (push, screen->sync->handle);
 599    PUSH_DATA (push, fifo->vram);
 600    PUSH_DATA (push, fifo->vram);
 601    PUSH_DATA (push, fifo->vram);
 602    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 603    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 604    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 605    PUSH_DATA (push, 0);
 606    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 607    PUSH_DATA (push, 0);
 608    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 609    PUSH_DATA (push, 1);
 610    BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
 611    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 612
 613    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 614    PUSH_DATA (push, screen->tesla->handle);
 615
 616    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 617    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 618
 619    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 620    PUSH_DATA (push, screen->sync->handle);
 621    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 622    for (i = 0; i < 11; ++i)
 623       PUSH_DATA(push, fifo->vram);
 624    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 625    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 626       PUSH_DATA(push, fifo->vram);
 627
 628    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 629    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 630    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 631    PUSH_DATA (push, 0xf);
 632
 633    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 634       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 635       PUSH_DATA (push, 0x18);
 636    }
 637
 638    BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
 639    PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 640
 641    BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
 642    for (i = 0; i < 8; ++i)
 643       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 644
 645    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 646    PUSH_DATA (push, 1);
 647
 648    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 649    PUSH_DATA (push, 0);
 650    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 651    PUSH_DATA (push, 0);
 652    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 653    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 654    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 655    PUSH_DATA (push, 0);
 656    BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 657    PUSH_DATA (push, 1);
 658    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 659    PUSH_DATA (push, 1);
 660
 661    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 662       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 663       PUSH_DATA (push, 0);
 664    }
 665
 666    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 667    PUSH_DATA (push, 0);
 668    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 669    PUSH_DATA (push, 0);
 670    PUSH_DATA (push, 0);
 671    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 672    PUSH_DATA (push, 0x3f);
 673
 674    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 675    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 676    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 677
 678    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 679    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 680    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 681
 682    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 683    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 684    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 685
 686    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 687    PUSH_DATAh(push, screen->tls_bo->offset);
 688    PUSH_DATA (push, screen->tls_bo->offset);
 689    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 690
 691    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 692    PUSH_DATAh(push, screen->stack_bo->offset);
 693    PUSH_DATA (push, screen->stack_bo->offset);
 694    PUSH_DATA (push, 4);
 695
 696    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 697    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 698    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 699    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 700
 701    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 702    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 703    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 704    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 705
 706    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 707    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 708    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 709    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 710
 711    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 712    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 713    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 714    PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
 715
 716    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 717    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 718    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 719    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 720
 721    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 722    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 723    PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
 724    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 725    PUSH_DATAf(push, 0.0f);
 726    PUSH_DATAf(push, 0.0f);
 727    PUSH_DATAf(push, 0.0f);
 728    PUSH_DATAf(push, 0.0f);
 729    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 730    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 731    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
 732
 733    nv50_upload_ms_info(push);
 734
 735    /* max TIC (bits 4:8) & TSC bindings, per program type */
 736    for (i = 0; i < 3; ++i) {
 737       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 738       PUSH_DATA (push, 0x54);
 739    }
 740
 741    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 742    PUSH_DATAh(push, screen->txc->offset);
 743    PUSH_DATA (push, screen->txc->offset);
 744    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 745
 746    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 747    PUSH_DATAh(push, screen->txc->offset + 65536);
 748    PUSH_DATA (push, screen->txc->offset + 65536);
 749    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 750
 751    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 752    PUSH_DATA (push, 0);
 753
 754    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 755    PUSH_DATA (push, 0);
 756    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 757    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 758    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 759    for (i = 0; i < 8 * 2; ++i)
 760       PUSH_DATA(push, 0);
 761    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 762    PUSH_DATA (push, 0);
 763
 764    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 765    PUSH_DATA (push, 1);
 766    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 767       BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
 768       PUSH_DATAf(push, 0.0f);
 769       PUSH_DATAf(push, 1.0f);
 770       BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
 771       PUSH_DATA (push, 8192 << 16);
 772       PUSH_DATA (push, 8192 << 16);
 773    }
 774
 775    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 776 #ifdef NV50_SCISSORS_CLIPPING
 777    PUSH_DATA (push, 0x0000);
 778 #else
 779    PUSH_DATA (push, 0x1080);
 780 #endif
 781
 782    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 783    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 784
 785    /* We use scissors instead of exact view volume clipping,
 786     * so they're always enabled.
 787     */
 788    for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
 789       BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
 790       PUSH_DATA (push, 1);
 791       PUSH_DATA (push, 8192 << 16);
 792       PUSH_DATA (push, 8192 << 16);
 793    }
 794
 795    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 796    PUSH_DATA (push, 1);
 797    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 798    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 799    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 800    PUSH_DATA (push, 0x11111111);
 801    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 802    PUSH_DATA (push, 1);
 803
 804    BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 805    PUSH_DATA (push, 0);
 806    if (screen->base.class_3d >= NV84_3D_CLASS) {
 807       BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 808       PUSH_DATA (push, 0);
 809    }
 810
 811    BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
 812    PUSH_DATA (push, 1);
 813    BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
 814    PUSH_DATA (push, 1);
 815
 816    PUSH_KICK (push);
 817 }
 818
 819 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 820       uint64_t *tls_size)
 821 {
 822    struct nouveau_device *dev = screen->base.device;
 823    int ret;
 824
 825    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 826          ONE_TEMP_SIZE;
 827    if (nouveau_mesa_debug)
 828       debug_printf("allocating space for %u temps\n",
 829             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 830    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 831          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 832
 833    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 834                         *tls_size, NULL, &screen->tls_bo);
 835    if (ret) {
 836       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 837       return ret;
 838    }
 839
 840    return 0;
 841 }
 842
 843 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 844 {
 845    struct nouveau_pushbuf *push = screen->base.pushbuf;
 846    int ret;
 847    uint64_t tls_size;
 848
 849    if (tls_space < screen->cur_tls_space)
 850       return 0;
 851    if (tls_space > screen->max_tls_space) {
 852       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 853        * LOCAL_WARPS_NO_CLAMP) */
 854       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 855             (unsigned)(tls_space / ONE_TEMP_SIZE),
 856             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 857       return -ENOMEM;
 858    }
 859
 860    nouveau_bo_ref(NULL, &screen->tls_bo);
 861    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 862    if (ret)
 863       return ret;
 864
 865    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 866    PUSH_DATAh(push, screen->tls_bo->offset);
 867    PUSH_DATA (push, screen->tls_bo->offset);
 868    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 869
 870    return 1;
 871 }
 872
 873 struct nouveau_screen *
 874 nv50_screen_create(struct nouveau_device *dev)
 875 {
 876    struct nv50_screen *screen;
 877    struct pipe_screen *pscreen;
 878    struct nouveau_object *chan;
 879    uint64_t value;
 880    uint32_t tesla_class;
 881    unsigned stack_size;
 882    int ret;
 883
 884    screen = CALLOC_STRUCT(nv50_screen);
 885    if (!screen)
 886       return NULL;
 887    pscreen = &screen->base.base;
 888    pscreen->destroy = nv50_screen_destroy;
 889
 890    ret = nouveau_screen_init(&screen->base, dev);
 891    if (ret) {
 892       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 893       goto fail;
 894    }
 895
 896    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 897     *  admit them to VRAM.
 898     */
 899    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 900       PIPE_BIND_VERTEX_BUFFER;
 901    screen->base.sysmem_bindings |=
 902       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 903
 904    screen->base.pushbuf->user_priv = screen;
 905    screen->base.pushbuf->rsvd_kick = 5;
 906
 907    chan = screen->base.channel;
 908
 909    pscreen->context_create = nv50_create;
 910    pscreen->is_format_supported = nv50_screen_is_format_supported;
 911    pscreen->get_param = nv50_screen_get_param;
 912    pscreen->get_shader_param = nv50_screen_get_shader_param;
 913    pscreen->get_paramf = nv50_screen_get_paramf;
 914    pscreen->get_compute_param = nv50_screen_get_compute_param;
 915    pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
 916    pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
 917
 918    nv50_screen_init_resource_functions(pscreen);
 919
 920    if (screen->base.device->chipset < 0x84 ||
 921        debug_get_bool_option("NOUVEAU_PMPEG", false)) {
 922       /* PMPEG */
 923       nouveau_screen_init_vdec(&screen->base);
 924    } else if (screen->base.device->chipset < 0x98 ||
 925               screen->base.device->chipset == 0xa0) {
 926       /* VP2 */
 927       screen->base.base.get_video_param = nv84_screen_get_video_param;
 928       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 929    } else {
 930       /* VP3/4 */
 931       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 932       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 933    }
 934
 935    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 936                         NULL, &screen->fence.bo);
 937    if (ret) {
 938       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 939       goto fail;
 940    }
 941
 942    nouveau_bo_map(screen->fence.bo, 0, NULL);
 943    screen->fence.map = screen->fence.bo->map;
 944    screen->base.fence.emit = nv50_screen_fence_emit;
 945    screen->base.fence.update = nv50_screen_fence_update;
 946
 947    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 948                             &(struct nv04_notify){ .length = 32 },
 949                             sizeof(struct nv04_notify), &screen->sync);
 950    if (ret) {
 951       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 952       goto fail;
 953    }
 954
 955    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 956                             NULL, 0, &screen->m2mf);
 957    if (ret) {
 958       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 959       goto fail;
 960    }
 961
 962    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 963                             NULL, 0, &screen->eng2d);
 964    if (ret) {
 965       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 966       goto fail;
 967    }
 968
 969    switch (dev->chipset & 0xf0) {
 970    case 0x50:
 971       tesla_class = NV50_3D_CLASS;
 972       break;
 973    case 0x80:
 974    case 0x90:
 975       tesla_class = NV84_3D_CLASS;
 976       break;
 977    case 0xa0:
 978       switch (dev->chipset) {
 979       case 0xa0:
 980       case 0xaa:
 981       case 0xac:
 982          tesla_class = NVA0_3D_CLASS;
 983          break;
 984       case 0xaf:
 985          tesla_class = NVAF_3D_CLASS;
 986          break;
 987       default:
 988          tesla_class = NVA3_3D_CLASS;
 989          break;
 990       }
 991       break;
 992    default:
 993       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 994       goto fail;
 995    }
 996    screen->base.class_3d = tesla_class;
 997
 998    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 999                             NULL, 0, &screen->tesla);
1000    if (ret) {
1001       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
1002       goto fail;
1003    }
1004
1005    /* This over-allocates by a page. The GP, which would execute at the end of
1006     * the last page, would trigger faults. The going theory is that it
1007     * prefetches up to a certain amount.
1008     */
1009    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
1010                         (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
1011                         NULL, &screen->code);
1012    if (ret) {
1013       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
1014       goto fail;
1015    }
1016
1017    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1018    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1019    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1020
1021    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1022
1023    screen->TPs = util_bitcount(value & 0xffff);
1024    screen->MPsInTP = util_bitcount(value & 0x0f000000);
1025
1026    screen->mp_count = screen->TPs * screen->MPsInTP;
1027
1028    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
1029          STACK_WARPS_ALLOC * 64 * 8;
1030
1031    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
1032                         &screen->stack_bo);
1033    if (ret) {
1034       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1035       goto fail;
1036    }
1037
1038    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1039          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
1040          ONE_TEMP_SIZE;
1041    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1042    screen->max_tls_space /= 2; /* half of vram */
1043
1044    /* hw can address max 64 KiB */
1045    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1046
1047    uint64_t tls_size;
1048    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1049    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1050    if (ret)
1051       goto fail;
1052
1053    if (nouveau_mesa_debug)
1054       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1055             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1056
1057    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
1058                         &screen->uniforms);
1059    if (ret) {
1060       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1061       goto fail;
1062    }
1063
1064    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1065                         &screen->txc);
1066    if (ret) {
1067       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1068       goto fail;
1069    }
1070
1071    screen->tic.entries = CALLOC(4096, sizeof(void *));
1072    screen->tsc.entries = screen->tic.entries + 2048;
1073
1074    if (!nv50_blitter_create(screen))
1075       goto fail;
1076
1077    nv50_screen_init_hwctx(screen);
1078
1079    ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1080    if (ret) {
1081       NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1082       goto fail;
1083    }
1084
1085    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1086
1087    return &screen->base;
1088
1089 fail:
1090    screen->base.base.context_create = NULL;
1091    return &screen->base;
1092 }
1093
1094 int
1095 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1096 {
1097    int i = screen->tic.next;
1098
1099    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1100       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1101
1102    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1103
1104    if (screen->tic.entries[i])
1105       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1106
1107    screen->tic.entries[i] = entry;
1108    return i;
1109 }
1110
1111 int
1112 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1113 {
1114    int i = screen->tsc.next;
1115
1116    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1117       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1118
1119    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1120
1121    if (screen->tsc.entries[i])
1122       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1123
1124    screen->tsc.entries[i] = entry;
1125    return i;
1126 }