src/gallium/drivers/nouveau/nv50/nv50_vbo.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "pipe/p_context.h"
  24 #include "pipe/p_state.h"
  25 #include "util/u_inlines.h"
  26 #include "util/format/u_format.h"
  27 #include "translate/translate.h"
  28
  29 #include "nv50/nv50_context.h"
  30 #include "nv50/nv50_query_hw.h"
  31 #include "nv50/nv50_resource.h"
  32
  33 #include "nv50/nv50_3d.xml.h"
  34
  35 void
  36 nv50_vertex_state_delete(struct pipe_context *pipe,
  37                          void *hwcso)
  38 {
  39    struct nv50_vertex_stateobj *so = hwcso;
  40
  41    if (so->translate)
  42       so->translate->release(so->translate);
  43    FREE(hwcso);
  44 }
  45
  46 void *
  47 nv50_vertex_state_create(struct pipe_context *pipe,
  48                          unsigned num_elements,
  49                          const struct pipe_vertex_element *elements)
  50 {
  51     struct nv50_vertex_stateobj *so;
  52     struct translate_key transkey;
  53     unsigned i;
  54
  55     so = MALLOC(sizeof(*so) +
  56                 num_elements * sizeof(struct nv50_vertex_element));
  57     if (!so)
  58         return NULL;
  59     so->num_elements = num_elements;
  60     so->instance_elts = 0;
  61     so->instance_bufs = 0;
  62     so->need_conversion = false;
  63
  64     memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
  65
  66     for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
  67        so->min_instance_div[i] = 0xffffffff;
  68
  69     transkey.nr_elements = 0;
  70     transkey.output_stride = 0;
  71
  72     for (i = 0; i < num_elements; ++i) {
  73         const struct pipe_vertex_element *ve = &elements[i];
  74         const unsigned vbi = ve->vertex_buffer_index;
  75         unsigned size;
  76         enum pipe_format fmt = ve->src_format;
  77
  78         so->element[i].pipe = elements[i];
  79         so->element[i].state = nv50_vertex_format[fmt].vtx;
  80
  81         if (!so->element[i].state) {
  82             switch (util_format_get_nr_components(fmt)) {
  83             case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
  84             case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
  85             case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
  86             case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
  87             default:
  88                 assert(0);
  89                 FREE(so);
  90                 return NULL;
  91             }
  92             so->element[i].state = nv50_vertex_format[fmt].vtx;
  93             so->need_conversion = true;
  94             pipe_debug_message(&nouveau_context(pipe)->debug, FALLBACK,
  95                                "Converting vertex element %d, no hw format %s",
  96                                i, util_format_name(ve->src_format));
  97         }
  98         so->element[i].state |= i;
  99
 100         size = util_format_get_blocksize(fmt);
 101         if (so->vb_access_size[vbi] < (ve->src_offset + size))
 102            so->vb_access_size[vbi] = ve->src_offset + size;
 103
 104         if (1) {
 105             unsigned j = transkey.nr_elements++;
 106
 107             transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
 108             transkey.element[j].input_format = ve->src_format;
 109             transkey.element[j].input_buffer = vbi;
 110             transkey.element[j].input_offset = ve->src_offset;
 111             transkey.element[j].instance_divisor = ve->instance_divisor;
 112
 113             transkey.element[j].output_format = fmt;
 114             transkey.element[j].output_offset = transkey.output_stride;
 115             transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
 116
 117             if (unlikely(ve->instance_divisor)) {
 118                so->instance_elts |= 1 << i;
 119                so->instance_bufs |= 1 << vbi;
 120                if (ve->instance_divisor < so->min_instance_div[vbi])
 121                   so->min_instance_div[vbi] = ve->instance_divisor;
 122             }
 123         }
 124     }
 125
 126     so->translate = translate_create(&transkey);
 127     so->vertex_size = transkey.output_stride / 4;
 128     so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN /
 129        MAX2(so->vertex_size, 1);
 130
 131     return so;
 132 }
 133
 134 #define NV50_3D_VERTEX_ATTRIB_INACTIVE              \
 135    NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT |         \
 136    NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \
 137    NV50_3D_VERTEX_ARRAY_ATTRIB_CONST
 138
 139 static void
 140 nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb,
 141                   struct pipe_vertex_element *ve, unsigned attr)
 142 {
 143    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 144    const void *data = (const uint8_t *)vb->buffer.user + ve->src_offset;
 145    float v[4];
 146    const unsigned nc = util_format_get_nr_components(ve->src_format);
 147    const struct util_format_description *desc =
 148       util_format_description(ve->src_format);
 149
 150    assert(vb->is_user_buffer);
 151
 152    util_format_unpack_rgba(ve->src_format, v, data, 1);
 153
 154    switch (nc) {
 155    case 4:
 156       BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4);
 157       PUSH_DATAf(push, v[0]);
 158       PUSH_DATAf(push, v[1]);
 159       PUSH_DATAf(push, v[2]);
 160       PUSH_DATAf(push, v[3]);
 161       break;
 162    case 3:
 163       BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3);
 164       PUSH_DATAf(push, v[0]);
 165       PUSH_DATAf(push, v[1]);
 166       PUSH_DATAf(push, v[2]);
 167       break;
 168    case 2:
 169       BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2);
 170       PUSH_DATAf(push, v[0]);
 171       PUSH_DATAf(push, v[1]);
 172       break;
 173    case 1:
 174       if (attr == nv50->vertprog->vp.edgeflag) {
 175          BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 176          PUSH_DATA (push, v[0] ? 1 : 0);
 177       }
 178       BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1);
 179       PUSH_DATAf(push, v[0]);
 180       break;
 181    default:
 182       assert(0);
 183       break;
 184    }
 185 }
 186
 187 static inline void
 188 nv50_user_vbuf_range(struct nv50_context *nv50, unsigned vbi,
 189                      uint32_t *base, uint32_t *size)
 190 {
 191    assert(vbi < PIPE_MAX_ATTRIBS);
 192    if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) {
 193       /* TODO: use min and max instance divisor to get a proper range */
 194       *base = 0;
 195       *size = nv50->vtxbuf[vbi].buffer.resource->width0;
 196    } else {
 197       /* NOTE: if there are user buffers, we *must* have index bounds */
 198       assert(nv50->vb_elt_limit != ~0);
 199       *base = nv50->vb_elt_first * nv50->vtxbuf[vbi].stride;
 200       *size = nv50->vb_elt_limit * nv50->vtxbuf[vbi].stride +
 201          nv50->vertex->vb_access_size[vbi];
 202    }
 203 }
 204
 205 static void
 206 nv50_upload_user_buffers(struct nv50_context *nv50,
 207                          uint64_t addrs[], uint32_t limits[])
 208 {
 209    unsigned b;
 210
 211    assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
 212    for (b = 0; b < nv50->num_vtxbufs; ++b) {
 213       struct nouveau_bo *bo;
 214       const struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
 215       uint32_t base, size;
 216
 217       if (!(nv50->vbo_user & (1 << b)) || !vb->stride)
 218          continue;
 219       nv50_user_vbuf_range(nv50, b, &base, &size);
 220
 221       limits[b] = base + size - 1;
 222       addrs[b] = nouveau_scratch_data(&nv50->base, vb->buffer.user, base, size,
 223                                       &bo);
 224       if (addrs[b])
 225          BCTX_REFN_bo(nv50->bufctx_3d, 3D_VERTEX_TMP, NOUVEAU_BO_GART |
 226                       NOUVEAU_BO_RD, bo);
 227    }
 228    nv50->base.vbo_dirty = true;
 229 }
 230
 231 static void
 232 nv50_update_user_vbufs(struct nv50_context *nv50)
 233 {
 234    uint64_t address[PIPE_MAX_ATTRIBS];
 235    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 236    unsigned i;
 237    uint32_t written = 0;
 238
 239    for (i = 0; i < nv50->vertex->num_elements; ++i) {
 240       struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe;
 241       const unsigned b = ve->vertex_buffer_index;
 242       struct pipe_vertex_buffer *vb;
 243       uint32_t base, size;
 244
 245       assert(b < PIPE_MAX_ATTRIBS);
 246       vb = &nv50->vtxbuf[b];
 247
 248       if (!(nv50->vbo_user & (1 << b)))
 249          continue;
 250
 251       if (!vb->stride) {
 252          nv50_emit_vtxattr(nv50, vb, ve, i);
 253          continue;
 254       }
 255       nv50_user_vbuf_range(nv50, b, &base, &size);
 256
 257       if (!(written & (1 << b))) {
 258          struct nouveau_bo *bo;
 259          const uint32_t bo_flags = NOUVEAU_BO_GART | NOUVEAU_BO_RD;
 260          written |= 1 << b;
 261          address[b] = nouveau_scratch_data(&nv50->base, vb->buffer.user,
 262                                            base, size, &bo);
 263          if (address[b])
 264             BCTX_REFN_bo(nv50->bufctx_3d, 3D_VERTEX_TMP, bo_flags, bo);
 265       }
 266
 267       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 268       PUSH_DATAh(push, address[b] + base + size - 1);
 269       PUSH_DATA (push, address[b] + base + size - 1);
 270       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
 271       PUSH_DATAh(push, address[b] + ve->src_offset);
 272       PUSH_DATA (push, address[b] + ve->src_offset);
 273    }
 274    nv50->base.vbo_dirty = true;
 275 }
 276
 277 static inline void
 278 nv50_release_user_vbufs(struct nv50_context *nv50)
 279 {
 280    if (nv50->vbo_user) {
 281       nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_VERTEX_TMP);
 282       nouveau_scratch_done(&nv50->base);
 283    }
 284 }
 285
 286 void
 287 nv50_vertex_arrays_validate(struct nv50_context *nv50)
 288 {
 289    uint64_t addrs[PIPE_MAX_ATTRIBS];
 290    uint32_t limits[PIPE_MAX_ATTRIBS];
 291    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 292    struct nv50_vertex_stateobj *vertex = nv50->vertex;
 293    struct pipe_vertex_buffer *vb;
 294    struct nv50_vertex_element *ve;
 295    uint32_t mask;
 296    uint32_t refd = 0;
 297    unsigned i;
 298    const unsigned n = MAX2(vertex->num_elements, nv50->state.num_vtxelts);
 299
 300    if (unlikely(vertex->need_conversion))
 301       nv50->vbo_fifo = ~0;
 302    else
 303    if (nv50->vbo_user & ~nv50->vbo_constant)
 304       nv50->vbo_fifo = nv50->vbo_push_hint ? ~0 : 0;
 305    else
 306       nv50->vbo_fifo = 0;
 307
 308    if (!nv50->vbo_fifo) {
 309       /* if vertex buffer was written by GPU - flush VBO cache */
 310       assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
 311       for (i = 0; i < nv50->num_vtxbufs; ++i) {
 312          struct nv04_resource *buf = nv04_resource(nv50->vtxbuf[i].buffer.resource);
 313          if (!nv50->vtxbuf[i].is_user_buffer &&
 314              buf && buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 315             buf->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 316             nv50->base.vbo_dirty = true;
 317          }
 318       }
 319    }
 320
 321    /* update vertex format state */
 322    BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n);
 323    if (nv50->vbo_fifo) {
 324       nv50->state.num_vtxelts = vertex->num_elements;
 325       for (i = 0; i < vertex->num_elements; ++i)
 326          PUSH_DATA (push, vertex->element[i].state);
 327       for (; i < n; ++i)
 328          PUSH_DATA (push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
 329       for (i = 0; i < n; ++i) {
 330          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 331          PUSH_DATA (push, 0);
 332       }
 333       return;
 334    }
 335    for (i = 0; i < vertex->num_elements; ++i) {
 336       const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
 337
 338       assert(b < PIPE_MAX_ATTRIBS);
 339       ve = &vertex->element[i];
 340       vb = &nv50->vtxbuf[b];
 341
 342       if (likely(vb->stride) || !(nv50->vbo_user & (1 << b)))
 343          PUSH_DATA(push, ve->state);
 344       else
 345          PUSH_DATA(push, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST);
 346    }
 347    for (; i < n; ++i)
 348       PUSH_DATA(push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
 349
 350    /* update per-instance enables */
 351    mask = vertex->instance_elts ^ nv50->state.instance_elts;
 352    while (mask) {
 353       const int i = ffs(mask) - 1;
 354       mask &= ~(1 << i);
 355       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
 356       PUSH_DATA (push, (vertex->instance_elts >> i) & 1);
 357    }
 358    nv50->state.instance_elts = vertex->instance_elts;
 359
 360    if (nv50->vbo_user & ~nv50->vbo_constant)
 361       nv50_upload_user_buffers(nv50, addrs, limits);
 362
 363    /* update buffers and set constant attributes */
 364    for (i = 0; i < vertex->num_elements; ++i) {
 365       uint64_t address, limit;
 366       const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
 367
 368       assert(b < PIPE_MAX_ATTRIBS);
 369       ve = &vertex->element[i];
 370       vb = &nv50->vtxbuf[b];
 371
 372       if (unlikely(nv50->vbo_constant & (1 << b))) {
 373          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 374          PUSH_DATA (push, 0);
 375          nv50_emit_vtxattr(nv50, vb, &ve->pipe, i);
 376          continue;
 377       } else
 378       if (nv50->vbo_user & (1 << b)) {
 379          address = addrs[b] + ve->pipe.src_offset;
 380          limit = addrs[b] + limits[b];
 381       } else
 382       if (!vb->buffer.resource) {
 383          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 384          PUSH_DATA (push, 0);
 385          continue;
 386       } else {
 387          struct nv04_resource *buf = nv04_resource(vb->buffer.resource);
 388          if (!(refd & (1 << b))) {
 389             refd |= 1 << b;
 390             BCTX_REFN(nv50->bufctx_3d, 3D_VERTEX, buf, RD);
 391          }
 392          address = buf->address + vb->buffer_offset + ve->pipe.src_offset;
 393          limit = buf->address + buf->base.width0 - 1;
 394       }
 395
 396       if (unlikely(ve->pipe.instance_divisor)) {
 397          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 4);
 398          PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 399          PUSH_DATAh(push, address);
 400          PUSH_DATA (push, address);
 401          PUSH_DATA (push, ve->pipe.instance_divisor);
 402       } else {
 403          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 3);
 404          PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
 405          PUSH_DATAh(push, address);
 406          PUSH_DATA (push, address);
 407       }
 408       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
 409       PUSH_DATAh(push, limit);
 410       PUSH_DATA (push, limit);
 411    }
 412    for (; i < nv50->state.num_vtxelts; ++i) {
 413       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
 414       PUSH_DATA (push, 0);
 415    }
 416    nv50->state.num_vtxelts = vertex->num_elements;
 417 }
 418
 419 #define NV50_PRIM_GL_CASE(n) \
 420    case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
 421
 422 static inline unsigned
 423 nv50_prim_gl(unsigned prim)
 424 {
 425    switch (prim) {
 426    NV50_PRIM_GL_CASE(POINTS);
 427    NV50_PRIM_GL_CASE(LINES);
 428    NV50_PRIM_GL_CASE(LINE_LOOP);
 429    NV50_PRIM_GL_CASE(LINE_STRIP);
 430    NV50_PRIM_GL_CASE(TRIANGLES);
 431    NV50_PRIM_GL_CASE(TRIANGLE_STRIP);
 432    NV50_PRIM_GL_CASE(TRIANGLE_FAN);
 433    NV50_PRIM_GL_CASE(QUADS);
 434    NV50_PRIM_GL_CASE(QUAD_STRIP);
 435    NV50_PRIM_GL_CASE(POLYGON);
 436    NV50_PRIM_GL_CASE(LINES_ADJACENCY);
 437    NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
 438    NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
 439    NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
 440    default:
 441       return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
 442       break;
 443    }
 444 }
 445
 446 /* For pre-nva0 transform feedback. */
 447 static const uint8_t nv50_pipe_prim_to_prim_size[PIPE_PRIM_MAX + 1] =
 448 {
 449    [PIPE_PRIM_POINTS] = 1,
 450    [PIPE_PRIM_LINES] = 2,
 451    [PIPE_PRIM_LINE_LOOP] = 2,
 452    [PIPE_PRIM_LINE_STRIP] = 2,
 453    [PIPE_PRIM_TRIANGLES] = 3,
 454    [PIPE_PRIM_TRIANGLE_STRIP] = 3,
 455    [PIPE_PRIM_TRIANGLE_FAN] = 3,
 456    [PIPE_PRIM_QUADS] = 3,
 457    [PIPE_PRIM_QUAD_STRIP] = 3,
 458    [PIPE_PRIM_POLYGON] = 3,
 459    [PIPE_PRIM_LINES_ADJACENCY] = 2,
 460    [PIPE_PRIM_LINE_STRIP_ADJACENCY] = 2,
 461    [PIPE_PRIM_TRIANGLES_ADJACENCY] = 3,
 462    [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = 3
 463 };
 464
 465 static void
 466 nv50_draw_arrays(struct nv50_context *nv50,
 467                  unsigned mode, unsigned start, unsigned count,
 468                  unsigned instance_count)
 469 {
 470    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 471    unsigned prim;
 472
 473    if (nv50->state.index_bias) {
 474       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 475       PUSH_DATA (push, 0);
 476       if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
 477          BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 478          PUSH_DATA (push, 0);
 479       }
 480       nv50->state.index_bias = 0;
 481    }
 482
 483    prim = nv50_prim_gl(mode);
 484
 485    while (instance_count--) {
 486       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 487       PUSH_DATA (push, prim);
 488       BEGIN_NV04(push, NV50_3D(VERTEX_BUFFER_FIRST), 2);
 489       PUSH_DATA (push, start);
 490       PUSH_DATA (push, count);
 491       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 492       PUSH_DATA (push, 0);
 493
 494       prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 495    }
 496 }
 497
 498 static void
 499 nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
 500                               unsigned start, unsigned count)
 501 {
 502    map += start;
 503
 504    if (count & 3) {
 505       unsigned i;
 506       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), count & 3);
 507       for (i = 0; i < (count & 3); ++i)
 508          PUSH_DATA(push, *map++);
 509       count &= ~3;
 510    }
 511    while (count) {
 512       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
 513
 514       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U8), nr);
 515       for (i = 0; i < nr; ++i) {
 516          PUSH_DATA(push,
 517                    (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
 518          map += 4;
 519       }
 520       count -= nr * 4;
 521    }
 522 }
 523
 524 static void
 525 nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
 526                               unsigned start, unsigned count)
 527 {
 528    map += start;
 529
 530    if (count & 1) {
 531       count &= ~1;
 532       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
 533       PUSH_DATA (push, *map++);
 534    }
 535    while (count) {
 536       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 537
 538       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
 539       for (i = 0; i < nr; ++i) {
 540          PUSH_DATA(push, (map[1] << 16) | map[0]);
 541          map += 2;
 542       }
 543       count -= nr * 2;
 544    }
 545 }
 546
 547 static void
 548 nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
 549                               unsigned start, unsigned count)
 550 {
 551    map += start;
 552
 553    while (count) {
 554       const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
 555
 556       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), nr);
 557       PUSH_DATAp(push, map, nr);
 558
 559       map += nr;
 560       count -= nr;
 561    }
 562 }
 563
 564 static void
 565 nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
 566                                     const uint32_t *map,
 567                                     unsigned start, unsigned count)
 568 {
 569    map += start;
 570
 571    if (count & 1) {
 572       count--;
 573       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
 574       PUSH_DATA (push, *map++);
 575    }
 576    while (count) {
 577       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
 578
 579       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
 580       for (i = 0; i < nr; ++i) {
 581          PUSH_DATA(push, (map[1] << 16) | map[0]);
 582          map += 2;
 583       }
 584       count -= nr * 2;
 585    }
 586 }
 587
 588 static void
 589 nv50_draw_elements(struct nv50_context *nv50, bool shorten,
 590                    const struct pipe_draw_info *info,
 591                    unsigned mode, unsigned start, unsigned count,
 592                    unsigned instance_count, int32_t index_bias,
 593                    unsigned index_size)
 594 {
 595    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 596    unsigned prim;
 597
 598    prim = nv50_prim_gl(mode);
 599
 600    if (index_bias != nv50->state.index_bias) {
 601       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
 602       PUSH_DATA (push, index_bias);
 603       if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
 604          BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
 605          PUSH_DATA (push, index_bias);
 606       }
 607       nv50->state.index_bias = index_bias;
 608    }
 609
 610    if (!info->has_user_indices) {
 611       struct nv04_resource *buf = nv04_resource(info->index.resource);
 612       unsigned pb_start;
 613       unsigned pb_bytes;
 614       const unsigned base = buf->offset & ~3;
 615
 616       start += (buf->offset & 3) >> (index_size >> 1);
 617
 618       assert(nouveau_resource_mapped_by_gpu(info->index.resource));
 619
 620       /* This shouldn't have to be here. The going theory is that the buffer
 621        * is being filled in by PGRAPH, and it's not done yet by the time it
 622        * gets submitted to PFIFO, which in turn starts immediately prefetching
 623        * the not-yet-written data. Ideally this wait would only happen on
 624        * pushbuf submit, but it's probably not a big performance difference.
 625        */
 626       if (buf->fence_wr && !nouveau_fence_signalled(buf->fence_wr))
 627          nouveau_fence_wait(buf->fence_wr, &nv50->base.debug);
 628
 629       while (instance_count--) {
 630          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 631          PUSH_DATA (push, prim);
 632
 633          nouveau_pushbuf_space(push, 16, 0, 1);
 634          PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain);
 635
 636          switch (index_size) {
 637          case 4:
 638             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U32), count);
 639             nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4);
 640             break;
 641          case 2:
 642             pb_start = (start & ~1) * 2;
 643             pb_bytes = ((start + count + 1) & ~1) * 2 - pb_start;
 644
 645             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
 646             PUSH_DATA (push, (start << 31) | count);
 647             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U16), pb_bytes / 4);
 648             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
 649             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
 650             PUSH_DATA (push, 0);
 651             break;
 652          default:
 653             assert(index_size == 1);
 654             pb_start = start & ~3;
 655             pb_bytes = ((start + count + 3) & ~3) - pb_start;
 656
 657             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
 658             PUSH_DATA (push, (start << 30) | count);
 659             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U8), pb_bytes / 4);
 660             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
 661             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
 662             PUSH_DATA (push, 0);
 663             break;
 664          }
 665          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 666          PUSH_DATA (push, 0);
 667
 668          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 669       }
 670    } else {
 671       const void *data = info->index.user;
 672
 673       while (instance_count--) {
 674          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 675          PUSH_DATA (push, prim);
 676          switch (index_size) {
 677          case 1:
 678             nv50_draw_elements_inline_u08(push, data, start, count);
 679             break;
 680          case 2:
 681             nv50_draw_elements_inline_u16(push, data, start, count);
 682             break;
 683          case 4:
 684             if (shorten)
 685                nv50_draw_elements_inline_u32_short(push, data, start, count);
 686             else
 687                nv50_draw_elements_inline_u32(push, data, start, count);
 688             break;
 689          default:
 690             assert(0);
 691             return;
 692          }
 693          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 694          PUSH_DATA (push, 0);
 695
 696          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 697       }
 698    }
 699    NOUVEAU_DRV_STAT(&nv50->screen->base, draw_calls_indexed, 1);
 700 }
 701
 702 static void
 703 nva0_draw_stream_output(struct nv50_context *nv50,
 704                         const struct pipe_draw_info *info)
 705 {
 706    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 707    struct nv50_so_target *so = nv50_so_target(info->count_from_stream_output);
 708    struct nv04_resource *res = nv04_resource(so->pipe.buffer);
 709    unsigned num_instances = info->instance_count;
 710    unsigned mode = nv50_prim_gl(info->mode);
 711
 712    if (unlikely(nv50->screen->base.class_3d < NVA0_3D_CLASS)) {
 713       /* A proper implementation without waiting doesn't seem possible,
 714        * so don't bother.
 715        */
 716       NOUVEAU_ERR("draw_stream_output not supported on pre-NVA0 cards\n");
 717       return;
 718    }
 719
 720    if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 721       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 722       PUSH_SPACE(push, 4);
 723       BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
 724       PUSH_DATA (push, 0);
 725       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
 726       PUSH_DATA (push, 0);
 727    }
 728
 729    assert(num_instances);
 730    do {
 731       PUSH_SPACE(push, 8);
 732       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
 733       PUSH_DATA (push, mode);
 734       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BASE), 1);
 735       PUSH_DATA (push, 0);
 736       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_STRIDE), 1);
 737       PUSH_DATA (push, so->stride);
 738       nv50_hw_query_pushbuf_submit(push, NVA0_3D_DRAW_TFB_BYTES,
 739                                    nv50_query(so->pq), 0x4);
 740       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
 741       PUSH_DATA (push, 0);
 742
 743       mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
 744    } while (--num_instances);
 745 }
 746
 747 static void
 748 nv50_draw_vbo_kick_notify(struct nouveau_pushbuf *chan)
 749 {
 750    struct nv50_screen *screen = chan->user_priv;
 751
 752    nouveau_fence_update(&screen->base, true);
 753
 754    nv50_bufctx_fence(screen->cur_ctx->bufctx_3d, true);
 755 }
 756
 757 void
 758 nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 759 {
 760    struct nv50_context *nv50 = nv50_context(pipe);
 761    struct nouveau_pushbuf *push = nv50->base.pushbuf;
 762    bool tex_dirty = false;
 763    int s;
 764
 765    if (info->index_size && !info->has_user_indices)
 766       BCTX_REFN(nv50->bufctx_3d, 3D_INDEX, nv04_resource(info->index.resource), RD);
 767
 768    /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
 769    nv50->vb_elt_first = info->min_index + info->index_bias;
 770    nv50->vb_elt_limit = info->max_index - info->min_index;
 771    nv50->instance_off = info->start_instance;
 772    nv50->instance_max = info->instance_count - 1;
 773
 774    /* For picking only a few vertices from a large user buffer, push is better,
 775     * if index count is larger and we expect repeated vertices, suggest upload.
 776     */
 777    nv50->vbo_push_hint = /* the 64 is heuristic */
 778       !(info->index_size && ((nv50->vb_elt_limit + 64) < info->count));
 779
 780    if (nv50->vbo_user && !(nv50->dirty_3d & (NV50_NEW_3D_ARRAYS | NV50_NEW_3D_VERTEX))) {
 781       if (!!nv50->vbo_fifo != nv50->vbo_push_hint)
 782          nv50->dirty_3d |= NV50_NEW_3D_ARRAYS;
 783       else
 784       if (!nv50->vbo_fifo)
 785          nv50_update_user_vbufs(nv50);
 786    }
 787
 788    if (unlikely(nv50->num_so_targets && !nv50->gmtyprog))
 789       nv50->state.prim_size = nv50_pipe_prim_to_prim_size[info->mode];
 790
 791    nv50_state_validate_3d(nv50, ~0);
 792
 793    push->kick_notify = nv50_draw_vbo_kick_notify;
 794
 795    for (s = 0; s < 3 && !nv50->cb_dirty; ++s) {
 796       if (nv50->constbuf_coherent[s])
 797          nv50->cb_dirty = true;
 798    }
 799
 800    /* If there are any coherent constbufs, flush the cache */
 801    if (nv50->cb_dirty) {
 802       BEGIN_NV04(push, NV50_3D(CODE_CB_FLUSH), 1);
 803       PUSH_DATA (push, 0);
 804       nv50->cb_dirty = false;
 805    }
 806
 807    for (s = 0; s < 3 && !tex_dirty; ++s) {
 808       if (nv50->textures_coherent[s])
 809          tex_dirty = true;
 810    }
 811
 812    if (tex_dirty) {
 813       BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1);
 814       PUSH_DATA (push, 0x20);
 815    }
 816
 817    if (nv50->screen->base.class_3d >= NVA0_3D_CLASS &&
 818        nv50->seamless_cube_map != nv50->state.seamless_cube_map) {
 819       nv50->state.seamless_cube_map = nv50->seamless_cube_map;
 820       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 821       PUSH_DATA (push, nv50->seamless_cube_map ? NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP : 0);
 822    }
 823
 824    if (nv50->vertprog->mul_zero_wins != nv50->state.mul_zero_wins) {
 825       nv50->state.mul_zero_wins = nv50->vertprog->mul_zero_wins;
 826       BEGIN_NV04(push, NV50_3D(UNK1690), 1);
 827       PUSH_DATA (push, 0x00010000 * !!nv50->state.mul_zero_wins);
 828    }
 829
 830    if (nv50->vbo_fifo) {
 831       nv50_push_vbo(nv50, info);
 832       goto cleanup;
 833    }
 834
 835    if (nv50->state.instance_base != info->start_instance) {
 836       nv50->state.instance_base = info->start_instance;
 837       /* NOTE: this does not affect the shader input, should it ? */
 838       BEGIN_NV04(push, NV50_3D(VB_INSTANCE_BASE), 1);
 839       PUSH_DATA (push, info->start_instance);
 840    }
 841
 842    nv50->base.vbo_dirty |= !!nv50->vtxbufs_coherent;
 843
 844    if (nv50->base.vbo_dirty) {
 845       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
 846       PUSH_DATA (push, 0);
 847       nv50->base.vbo_dirty = false;
 848    }
 849
 850    if (info->index_size) {
 851       bool shorten = info->max_index <= 65535;
 852
 853       if (info->primitive_restart != nv50->state.prim_restart) {
 854          if (info->primitive_restart) {
 855             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 2);
 856             PUSH_DATA (push, 1);
 857             PUSH_DATA (push, info->restart_index);
 858
 859             if (info->restart_index > 65535)
 860                shorten = false;
 861          } else {
 862             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 1);
 863             PUSH_DATA (push, 0);
 864          }
 865          nv50->state.prim_restart = info->primitive_restart;
 866       } else
 867       if (info->primitive_restart) {
 868          BEGIN_NV04(push, NV50_3D(PRIM_RESTART_INDEX), 1);
 869          PUSH_DATA (push, info->restart_index);
 870
 871          if (info->restart_index > 65535)
 872             shorten = false;
 873       }
 874
 875       nv50_draw_elements(nv50, shorten, info,
 876                          info->mode, info->start, info->count,
 877                          info->instance_count, info->index_bias, info->index_size);
 878    } else
 879    if (unlikely(info->count_from_stream_output)) {
 880       nva0_draw_stream_output(nv50, info);
 881    } else {
 882       nv50_draw_arrays(nv50,
 883                        info->mode, info->start, info->count,
 884                        info->instance_count);
 885    }
 886
 887 cleanup:
 888    push->kick_notify = nv50_default_kick_notify;
 889
 890    nv50_release_user_vbufs(nv50);
 891
 892    nouveau_pushbuf_bufctx(push, NULL);
 893
 894    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_INDEX);
 895 }