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gallium: add PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/u_format.h"
27 #include "util/u_format_s3tc.h"
28 #include "pipe/p_screen.h"
29
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "nouveau_vp3_video.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39 #include "nvc0/mme/com90c0.mme.h"
40
41 static boolean
42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
43 enum pipe_format format,
44 enum pipe_texture_target target,
45 unsigned sample_count,
46 unsigned bindings)
47 {
48 const struct util_format_description *desc = util_format_description(format);
49
50 if (sample_count > 8)
51 return false;
52 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
53 return false;
54
55 /* Short-circuit the rest of the logic -- this is used by the state tracker
56 * to determine valid MS levels in a no-attachments scenario.
57 */
58 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
59 return true;
60
61 if (!util_format_is_supported(format, bindings))
62 return false;
63
64 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
65 if (util_format_get_blocksizebits(format) == 3 * 32)
66 return false;
67
68 if (bindings & PIPE_BIND_LINEAR)
69 if (util_format_is_depth_or_stencil(format) ||
70 (target != PIPE_TEXTURE_1D &&
71 target != PIPE_TEXTURE_2D &&
72 target != PIPE_TEXTURE_RECT) ||
73 sample_count > 1)
74 return false;
75
76 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
77 */
78 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
79 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
80 /* The claim is that this should work on GM107 but it doesn't. Need to
81 * test further and figure out if it's a nouveau issue or a HW one.
82 nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
83 */
84 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
85 return false;
86
87 /* shared is always supported */
88 bindings &= ~(PIPE_BIND_LINEAR |
89 PIPE_BIND_SHARED);
90
91 if (bindings & PIPE_BIND_SHADER_IMAGE && sample_count > 1 &&
92 nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
93 /* MS images are currently unsupported on Maxwell because they have to
94 * be handled explicitly. */
95 return false;
96 }
97
98 return (( nvc0_format_table[format].usage |
99 nvc0_vertex_format[format].usage) & bindings) == bindings;
100 }
101
102 static int
103 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
104 {
105 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
106 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
107
108 switch (param) {
109 /* non-boolean caps */
110 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
111 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
112 return 15;
113 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
114 return 12;
115 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
116 return 2048;
117 case PIPE_CAP_MIN_TEXEL_OFFSET:
118 return -8;
119 case PIPE_CAP_MAX_TEXEL_OFFSET:
120 return 7;
121 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
122 return -32;
123 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
124 return 31;
125 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
126 return 128 * 1024 * 1024;
127 case PIPE_CAP_GLSL_FEATURE_LEVEL:
128 if (class_3d <= NVF0_3D_CLASS)
129 return 430;
130 return 410;
131 case PIPE_CAP_MAX_RENDER_TARGETS:
132 return 8;
133 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
134 return 1;
135 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
136 return 4;
137 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
138 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
139 return 128;
140 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
141 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
142 return 1024;
143 case PIPE_CAP_MAX_VERTEX_STREAMS:
144 return 4;
145 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
146 return 2048;
147 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
148 return 256;
149 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
150 return 16; /* 256 for binding as RT, but that's not possible in GL */
151 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
152 return 16;
153 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
154 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
155 case PIPE_CAP_MAX_VIEWPORTS:
156 return NVC0_MAX_VIEWPORTS;
157 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
158 return 4;
159 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
160 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
161 case PIPE_CAP_ENDIANNESS:
162 return PIPE_ENDIAN_LITTLE;
163 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
164 return 30;
165 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
166 return NVC0_MAX_WINDOW_RECTANGLES;
167
168 /* supported caps */
169 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
170 case PIPE_CAP_TEXTURE_SWIZZLE:
171 case PIPE_CAP_TEXTURE_SHADOW_MAP:
172 case PIPE_CAP_NPOT_TEXTURES:
173 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
174 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
175 case PIPE_CAP_ANISOTROPIC_FILTER:
176 case PIPE_CAP_SEAMLESS_CUBE_MAP:
177 case PIPE_CAP_CUBE_MAP_ARRAY:
178 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
179 case PIPE_CAP_TEXTURE_MULTISAMPLE:
180 case PIPE_CAP_TWO_SIDED_STENCIL:
181 case PIPE_CAP_DEPTH_CLIP_DISABLE:
182 case PIPE_CAP_POINT_SPRITE:
183 case PIPE_CAP_TGSI_TEXCOORD:
184 case PIPE_CAP_SM3:
185 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
186 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
187 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
188 case PIPE_CAP_QUERY_TIMESTAMP:
189 case PIPE_CAP_QUERY_TIME_ELAPSED:
190 case PIPE_CAP_OCCLUSION_QUERY:
191 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
192 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
193 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
194 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
195 case PIPE_CAP_INDEP_BLEND_ENABLE:
196 case PIPE_CAP_INDEP_BLEND_FUNC:
197 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
198 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
199 case PIPE_CAP_PRIMITIVE_RESTART:
200 case PIPE_CAP_TGSI_INSTANCEID:
201 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
202 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
203 case PIPE_CAP_CONDITIONAL_RENDER:
204 case PIPE_CAP_TEXTURE_BARRIER:
205 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
206 case PIPE_CAP_START_INSTANCE:
207 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
208 case PIPE_CAP_DRAW_INDIRECT:
209 case PIPE_CAP_USER_CONSTANT_BUFFERS:
210 case PIPE_CAP_USER_INDEX_BUFFERS:
211 case PIPE_CAP_USER_VERTEX_BUFFERS:
212 case PIPE_CAP_TEXTURE_QUERY_LOD:
213 case PIPE_CAP_SAMPLE_SHADING:
214 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
215 case PIPE_CAP_TEXTURE_GATHER_SM5:
216 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
217 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
218 case PIPE_CAP_SAMPLER_VIEW_TARGET:
219 case PIPE_CAP_CLIP_HALFZ:
220 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
221 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
222 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
223 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
224 case PIPE_CAP_DEPTH_BOUNDS_TEST:
225 case PIPE_CAP_TGSI_TXQS:
226 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
227 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
228 case PIPE_CAP_SHAREABLE_SHADERS:
229 case PIPE_CAP_CLEAR_TEXTURE:
230 case PIPE_CAP_DRAW_PARAMETERS:
231 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
232 case PIPE_CAP_MULTI_DRAW_INDIRECT:
233 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
234 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
235 case PIPE_CAP_QUERY_BUFFER_OBJECT:
236 case PIPE_CAP_INVALIDATE_BUFFER:
237 case PIPE_CAP_STRING_MARKER:
238 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
239 case PIPE_CAP_CULL_DISTANCE:
240 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
241 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
242 case PIPE_CAP_TGSI_VOTE:
243 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
244 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
245 return 1;
246 case PIPE_CAP_COMPUTE:
247 return (class_3d < GP100_3D_CLASS);
248 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
249 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
250 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
251 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
252
253 /* unsupported caps */
254 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
255 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
256 case PIPE_CAP_SHADER_STENCIL_EXPORT:
257 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
258 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
259 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
260 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
261 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
262 case PIPE_CAP_FAKE_SW_MSAA:
263 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
264 case PIPE_CAP_VERTEXID_NOBASE:
265 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
266 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
267 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
268 case PIPE_CAP_GENERATE_MIPMAP:
269 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
270 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
271 case PIPE_CAP_QUERY_MEMORY_INFO:
272 case PIPE_CAP_PCI_GROUP:
273 case PIPE_CAP_PCI_BUS:
274 case PIPE_CAP_PCI_DEVICE:
275 case PIPE_CAP_PCI_FUNCTION:
276 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
277 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
278 case PIPE_CAP_NATIVE_FENCE_FD:
279 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
280 return 0;
281
282 case PIPE_CAP_VENDOR_ID:
283 return 0x10de;
284 case PIPE_CAP_DEVICE_ID: {
285 uint64_t device_id;
286 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
287 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
288 return -1;
289 }
290 return device_id;
291 }
292 case PIPE_CAP_ACCELERATED:
293 return 1;
294 case PIPE_CAP_VIDEO_MEMORY:
295 return dev->vram_size >> 20;
296 case PIPE_CAP_UMA:
297 return 0;
298 }
299
300 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
301 return 0;
302 }
303
304 static int
305 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
306 enum pipe_shader_cap param)
307 {
308 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
309
310 switch (shader) {
311 case PIPE_SHADER_VERTEX:
312 case PIPE_SHADER_GEOMETRY:
313 case PIPE_SHADER_FRAGMENT:
314 case PIPE_SHADER_COMPUTE:
315 case PIPE_SHADER_TESS_CTRL:
316 case PIPE_SHADER_TESS_EVAL:
317 break;
318 default:
319 return 0;
320 }
321
322 switch (param) {
323 case PIPE_SHADER_CAP_PREFERRED_IR:
324 return PIPE_SHADER_IR_TGSI;
325 case PIPE_SHADER_CAP_SUPPORTED_IRS:
326 return 1 << PIPE_SHADER_IR_TGSI;
327 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
328 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
329 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
330 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
331 return 16384;
332 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
333 return 16;
334 case PIPE_SHADER_CAP_MAX_INPUTS:
335 if (shader == PIPE_SHADER_VERTEX)
336 return 32;
337 /* NOTE: These only count our slots for GENERIC varyings.
338 * The address space may be larger, but the actual hard limit seems to be
339 * less than what the address space layout permits, so don't add TEXCOORD,
340 * COLOR, etc. here.
341 */
342 if (shader == PIPE_SHADER_FRAGMENT)
343 return 0x1f0 / 16;
344 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
345 * and excludes 0x60 per-patch inputs.
346 */
347 return 0x200 / 16;
348 case PIPE_SHADER_CAP_MAX_OUTPUTS:
349 return 32;
350 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
351 return 65536;
352 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
353 return NVC0_MAX_PIPE_CONSTBUFS;
354 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
355 return shader != PIPE_SHADER_FRAGMENT;
356 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
357 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
358 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
359 return 1;
360 case PIPE_SHADER_CAP_MAX_PREDS:
361 return 0;
362 case PIPE_SHADER_CAP_MAX_TEMPS:
363 return NVC0_CAP_MAX_PROGRAM_TEMPS;
364 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
365 return 1;
366 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
367 return 1;
368 case PIPE_SHADER_CAP_SUBROUTINES:
369 return 1;
370 case PIPE_SHADER_CAP_INTEGERS:
371 return 1;
372 case PIPE_SHADER_CAP_DOUBLES:
373 return 1;
374 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
375 return 1;
376 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
377 return 1;
378 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
379 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
380 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
381 return 0;
382 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
383 return NVC0_MAX_BUFFERS;
384 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
385 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
386 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
387 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
388 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
389 return 32;
390 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
391 if (class_3d == NVE4_3D_CLASS || class_3d == NVF0_3D_CLASS)
392 return NVC0_MAX_IMAGES;
393 if (class_3d < NVE4_3D_CLASS)
394 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
395 return NVC0_MAX_IMAGES;
396 return 0;
397 default:
398 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
399 return 0;
400 }
401 }
402
403 static float
404 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
405 {
406 switch (param) {
407 case PIPE_CAPF_MAX_LINE_WIDTH:
408 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
409 return 10.0f;
410 case PIPE_CAPF_MAX_POINT_WIDTH:
411 return 63.0f;
412 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
413 return 63.375f;
414 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
415 return 16.0f;
416 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
417 return 15.0f;
418 case PIPE_CAPF_GUARD_BAND_LEFT:
419 case PIPE_CAPF_GUARD_BAND_TOP:
420 return 0.0f;
421 case PIPE_CAPF_GUARD_BAND_RIGHT:
422 case PIPE_CAPF_GUARD_BAND_BOTTOM:
423 return 0.0f; /* that or infinity */
424 }
425
426 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
427 return 0.0f;
428 }
429
430 static int
431 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
432 enum pipe_shader_ir ir_type,
433 enum pipe_compute_cap param, void *data)
434 {
435 struct nvc0_screen *screen = nvc0_screen(pscreen);
436 const uint16_t obj_class = screen->compute->oclass;
437
438 #define RET(x) do { \
439 if (data) \
440 memcpy(data, x, sizeof(x)); \
441 return sizeof(x); \
442 } while (0)
443
444 switch (param) {
445 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
446 RET((uint64_t []) { 3 });
447 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
448 if (obj_class >= NVE4_COMPUTE_CLASS) {
449 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
450 } else {
451 RET(((uint64_t []) { 65535, 65535, 65535 }));
452 }
453 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
454 RET(((uint64_t []) { 1024, 1024, 64 }));
455 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
456 RET((uint64_t []) { 1024 });
457 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
458 if (obj_class >= NVE4_COMPUTE_CLASS) {
459 RET((uint64_t []) { 1024 });
460 } else {
461 RET((uint64_t []) { 512 });
462 }
463 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
464 RET((uint64_t []) { 1ULL << 40 });
465 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
466 switch (obj_class) {
467 case GM200_COMPUTE_CLASS:
468 RET((uint64_t []) { 96 << 10 });
469 break;
470 case GM107_COMPUTE_CLASS:
471 RET((uint64_t []) { 64 << 10 });
472 break;
473 default:
474 RET((uint64_t []) { 48 << 10 });
475 break;
476 }
477 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
478 RET((uint64_t []) { 512 << 10 });
479 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
480 RET((uint64_t []) { 4096 });
481 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
482 RET((uint32_t []) { 32 });
483 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
484 RET((uint64_t []) { 1ULL << 40 });
485 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
486 RET((uint32_t []) { 0 });
487 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
488 RET((uint32_t []) { screen->mp_count_compute });
489 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
490 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
491 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
492 RET((uint32_t []) { 64 });
493 default:
494 return 0;
495 }
496
497 #undef RET
498 }
499
500 static void
501 nvc0_screen_destroy(struct pipe_screen *pscreen)
502 {
503 struct nvc0_screen *screen = nvc0_screen(pscreen);
504
505 if (!nouveau_drm_screen_unref(&screen->base))
506 return;
507
508 if (screen->base.fence.current) {
509 struct nouveau_fence *current = NULL;
510
511 /* nouveau_fence_wait will create a new current fence, so wait on the
512 * _current_ one, and remove both.
513 */
514 nouveau_fence_ref(screen->base.fence.current, &current);
515 nouveau_fence_wait(current, NULL);
516 nouveau_fence_ref(NULL, &current);
517 nouveau_fence_ref(NULL, &screen->base.fence.current);
518 }
519 if (screen->base.pushbuf)
520 screen->base.pushbuf->user_priv = NULL;
521
522 if (screen->blitter)
523 nvc0_blitter_destroy(screen);
524 if (screen->pm.prog) {
525 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
526 nvc0_program_destroy(NULL, screen->pm.prog);
527 FREE(screen->pm.prog);
528 }
529
530 nouveau_bo_ref(NULL, &screen->text);
531 nouveau_bo_ref(NULL, &screen->uniform_bo);
532 nouveau_bo_ref(NULL, &screen->tls);
533 nouveau_bo_ref(NULL, &screen->txc);
534 nouveau_bo_ref(NULL, &screen->fence.bo);
535 nouveau_bo_ref(NULL, &screen->poly_cache);
536
537 nouveau_heap_destroy(&screen->lib_code);
538 nouveau_heap_destroy(&screen->text_heap);
539
540 FREE(screen->tic.entries);
541
542 nouveau_object_del(&screen->eng3d);
543 nouveau_object_del(&screen->eng2d);
544 nouveau_object_del(&screen->m2mf);
545 nouveau_object_del(&screen->compute);
546 nouveau_object_del(&screen->nvsw);
547
548 nouveau_screen_fini(&screen->base);
549
550 FREE(screen);
551 }
552
553 static int
554 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
555 unsigned size, const uint32_t *data)
556 {
557 struct nouveau_pushbuf *push = screen->base.pushbuf;
558
559 size /= 4;
560
561 assert((pos + size) <= 0x800);
562
563 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
564 PUSH_DATA (push, (m - 0x3800) / 8);
565 PUSH_DATA (push, pos);
566 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
567 PUSH_DATA (push, pos);
568 PUSH_DATAp(push, data, size);
569
570 return pos + size;
571 }
572
573 static void
574 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
575 {
576 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
577 PUSH_DATA (push, 0xff);
578 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
579 PUSH_DATA (push, 0xff);
580 PUSH_DATA (push, 0xff);
581 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
582 PUSH_DATA (push, 0xff);
583 PUSH_DATA (push, 0xff);
584 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
585 PUSH_DATA (push, 0x3f);
586
587 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
588 PUSH_DATA (push, (3 << 16) | 3);
589 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
590 PUSH_DATA (push, (2 << 16) | 2);
591
592 if (obj_class < GM107_3D_CLASS) {
593 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
594 PUSH_DATA (push, 0);
595 }
596 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
597 PUSH_DATA (push, 0x10);
598 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
599 PUSH_DATA (push, 0x10);
600 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
601 PUSH_DATA (push, 0x10);
602 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
603 PUSH_DATA (push, 0x10);
604 PUSH_DATA (push, 0x10);
605 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
606 PUSH_DATA (push, 0x10);
607 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
608 PUSH_DATA (push, 0xe);
609
610 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
611 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
612 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
613 PUSH_DATA (push, 0);
614 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
615 PUSH_DATA (push, 3);
616
617 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
618 PUSH_DATA (push, 0x3fffff);
619 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
620 PUSH_DATA (push, 1);
621 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
622 PUSH_DATA (push, 1);
623
624 if (obj_class < GM107_3D_CLASS) {
625 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
626 PUSH_DATA (push, 3);
627
628 if (obj_class >= NVE4_3D_CLASS) {
629 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
630 PUSH_DATA (push, 1);
631 }
632 }
633
634 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
635 * are supposed to do */
636 }
637
638 static void
639 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
640 {
641 struct nvc0_screen *screen = nvc0_screen(pscreen);
642 struct nouveau_pushbuf *push = screen->base.pushbuf;
643
644 /* we need to do it after possible flush in MARK_RING */
645 *sequence = ++screen->base.fence.sequence;
646
647 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
648 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
649 PUSH_DATAh(push, screen->fence.bo->offset);
650 PUSH_DATA (push, screen->fence.bo->offset);
651 PUSH_DATA (push, *sequence);
652 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
653 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
654 }
655
656 static u32
657 nvc0_screen_fence_update(struct pipe_screen *pscreen)
658 {
659 struct nvc0_screen *screen = nvc0_screen(pscreen);
660 return screen->fence.map[0];
661 }
662
663 static int
664 nvc0_screen_init_compute(struct nvc0_screen *screen)
665 {
666 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
667
668 switch (screen->base.device->chipset & ~0xf) {
669 case 0xc0:
670 case 0xd0:
671 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
672 case 0xe0:
673 case 0xf0:
674 case 0x100:
675 case 0x110:
676 case 0x120:
677 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
678 case 0x130:
679 return 0;
680 default:
681 return -1;
682 }
683 }
684
685 static int
686 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
687 uint32_t lpos, uint32_t lneg, uint32_t cstack)
688 {
689 struct nouveau_bo *bo = NULL;
690 int ret;
691 uint64_t size = (lpos + lneg) * 32 + cstack;
692
693 if (size >= (1 << 20)) {
694 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
695 return -1;
696 }
697
698 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
699 size = align(size, 0x8000);
700 size *= screen->mp_count;
701
702 size = align(size, 1 << 17);
703
704 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
705 NULL, &bo);
706 if (ret)
707 return ret;
708 nouveau_bo_ref(NULL, &screen->tls);
709 screen->tls = bo;
710 return 0;
711 }
712
713 int
714 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
715 {
716 struct nouveau_pushbuf *push = screen->base.pushbuf;
717 struct nouveau_bo *bo;
718 int ret;
719
720 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
721 1 << 17, size, NULL, &bo);
722 if (ret)
723 return ret;
724
725 nouveau_bo_ref(NULL, &screen->text);
726 screen->text = bo;
727
728 nouveau_heap_destroy(&screen->lib_code);
729 nouveau_heap_destroy(&screen->text_heap);
730
731 /* XXX: getting a page fault at the end of the code buffer every few
732 * launches, don't use the last 256 bytes to work around them - prefetch ?
733 */
734 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
735
736 /* update the code segment setup */
737 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
738 PUSH_DATAh(push, screen->text->offset);
739 PUSH_DATA (push, screen->text->offset);
740 if (screen->compute) {
741 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
742 PUSH_DATAh(push, screen->text->offset);
743 PUSH_DATA (push, screen->text->offset);
744 }
745
746 return 0;
747 }
748
749 #define FAIL_SCREEN_INIT(str, err) \
750 do { \
751 NOUVEAU_ERR(str, err); \
752 goto fail; \
753 } while(0)
754
755 struct nouveau_screen *
756 nvc0_screen_create(struct nouveau_device *dev)
757 {
758 struct nvc0_screen *screen;
759 struct pipe_screen *pscreen;
760 struct nouveau_object *chan;
761 struct nouveau_pushbuf *push;
762 uint64_t value;
763 uint32_t obj_class;
764 uint32_t flags;
765 int ret;
766 unsigned i;
767
768 switch (dev->chipset & ~0xf) {
769 case 0xc0:
770 case 0xd0:
771 case 0xe0:
772 case 0xf0:
773 case 0x100:
774 case 0x110:
775 case 0x120:
776 case 0x130:
777 break;
778 default:
779 return NULL;
780 }
781
782 screen = CALLOC_STRUCT(nvc0_screen);
783 if (!screen)
784 return NULL;
785 pscreen = &screen->base.base;
786 pscreen->destroy = nvc0_screen_destroy;
787
788 ret = nouveau_screen_init(&screen->base, dev);
789 if (ret)
790 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
791 chan = screen->base.channel;
792 push = screen->base.pushbuf;
793 push->user_priv = screen;
794 push->rsvd_kick = 5;
795
796 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
797 PIPE_BIND_SHADER_BUFFER |
798 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
799 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
800 screen->base.sysmem_bindings |=
801 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
802
803 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
804 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
805 screen->base.vidmem_bindings = 0;
806 }
807
808 pscreen->context_create = nvc0_create;
809 pscreen->is_format_supported = nvc0_screen_is_format_supported;
810 pscreen->get_param = nvc0_screen_get_param;
811 pscreen->get_shader_param = nvc0_screen_get_shader_param;
812 pscreen->get_paramf = nvc0_screen_get_paramf;
813 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
814 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
815
816 nvc0_screen_init_resource_functions(pscreen);
817
818 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
819 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
820
821 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
822 if (screen->base.drm->version >= 0x01000202)
823 flags |= NOUVEAU_BO_COHERENT;
824
825 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
826 if (ret)
827 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
828 nouveau_bo_map(screen->fence.bo, 0, NULL);
829 screen->fence.map = screen->fence.bo->map;
830 screen->base.fence.emit = nvc0_screen_fence_emit;
831 screen->base.fence.update = nvc0_screen_fence_update;
832
833
834 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
835 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
836 if (ret)
837 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
838
839 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
840 PUSH_DATA (push, screen->nvsw->handle);
841
842 switch (dev->chipset & ~0xf) {
843 case 0x130:
844 case 0x120:
845 case 0x110:
846 case 0x100:
847 case 0xf0:
848 obj_class = NVF0_P2MF_CLASS;
849 break;
850 case 0xe0:
851 obj_class = NVE4_P2MF_CLASS;
852 break;
853 default:
854 obj_class = NVC0_M2MF_CLASS;
855 break;
856 }
857 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
858 &screen->m2mf);
859 if (ret)
860 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
861
862 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
863 PUSH_DATA (push, screen->m2mf->oclass);
864 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
865 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
866 PUSH_DATA (push, 0xa0b5);
867 }
868
869 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
870 &screen->eng2d);
871 if (ret)
872 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
873
874 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
875 PUSH_DATA (push, screen->eng2d->oclass);
876 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
877 PUSH_DATA (push, 0);
878 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
879 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
880 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
881 PUSH_DATA (push, 0);
882 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
883 PUSH_DATA (push, 0);
884 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
885 PUSH_DATA (push, 0x3f);
886 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
887 PUSH_DATA (push, 1);
888 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
889 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
890
891 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
892 PUSH_DATAh(push, screen->fence.bo->offset + 16);
893 PUSH_DATA (push, screen->fence.bo->offset + 16);
894
895 switch (dev->chipset & ~0xf) {
896 case 0x130:
897 obj_class = GP100_3D_CLASS;
898 break;
899 case 0x120:
900 obj_class = GM200_3D_CLASS;
901 break;
902 case 0x110:
903 obj_class = GM107_3D_CLASS;
904 break;
905 case 0x100:
906 case 0xf0:
907 obj_class = NVF0_3D_CLASS;
908 break;
909 case 0xe0:
910 switch (dev->chipset) {
911 case 0xea:
912 obj_class = NVEA_3D_CLASS;
913 break;
914 default:
915 obj_class = NVE4_3D_CLASS;
916 break;
917 }
918 break;
919 case 0xd0:
920 obj_class = NVC8_3D_CLASS;
921 break;
922 case 0xc0:
923 default:
924 switch (dev->chipset) {
925 case 0xc8:
926 obj_class = NVC8_3D_CLASS;
927 break;
928 case 0xc1:
929 obj_class = NVC1_3D_CLASS;
930 break;
931 default:
932 obj_class = NVC0_3D_CLASS;
933 break;
934 }
935 break;
936 }
937 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
938 &screen->eng3d);
939 if (ret)
940 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
941 screen->base.class_3d = obj_class;
942
943 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
944 PUSH_DATA (push, screen->eng3d->oclass);
945
946 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
947 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
948
949 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
950 /* kill shaders after about 1 second (at 100 MHz) */
951 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
952 PUSH_DATA (push, 0x17);
953 }
954
955 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
956 screen->base.drm->version >= 0x01000101);
957 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
958 for (i = 0; i < 8; ++i)
959 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
960
961 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
962 PUSH_DATA (push, 1);
963
964 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
965 PUSH_DATA (push, 0);
966 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
967 PUSH_DATA (push, 0);
968 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
969 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
970 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
971 PUSH_DATA (push, 0);
972 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
973 PUSH_DATA (push, 1);
974 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
975 PUSH_DATA (push, 1);
976 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
977 PUSH_DATA (push, 1);
978 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
979 PUSH_DATA (push, 0);
980 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
981 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
982 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
983 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
984 } else {
985 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
986 PUSH_DATA (push, 15);
987 }
988 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
989 PUSH_DATA (push, 8); /* 128 */
990 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
991 PUSH_DATA (push, 1);
992 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
993 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
994 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
995 }
996
997 nvc0_magic_3d_init(push, screen->eng3d->oclass);
998
999 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1000 if (ret)
1001 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1002
1003 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
1004 &screen->uniform_bo);
1005 if (ret)
1006 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1007
1008 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1009
1010 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1011 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1012 PUSH_DATA (push, 256);
1013 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1014 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1015 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1016 PUSH_DATA (push, 0);
1017 PUSH_DATAf(push, 0.0f);
1018 PUSH_DATAf(push, 0.0f);
1019 PUSH_DATAf(push, 0.0f);
1020 PUSH_DATAf(push, 0.0f);
1021 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1022 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1023 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1024
1025 if (screen->base.drm->version >= 0x01000101) {
1026 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1027 if (ret)
1028 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1029 } else {
1030 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1031 value = (8 << 8) | 4;
1032 else
1033 value = (16 << 8) | 4;
1034 }
1035 screen->gpc_count = value & 0x000000ff;
1036 screen->mp_count = value >> 8;
1037 screen->mp_count_compute = screen->mp_count;
1038
1039 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1040 if (ret)
1041 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1042
1043 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1044 PUSH_DATAh(push, screen->tls->offset);
1045 PUSH_DATA (push, screen->tls->offset);
1046 PUSH_DATA (push, screen->tls->size >> 32);
1047 PUSH_DATA (push, screen->tls->size);
1048 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1049 PUSH_DATA (push, 0);
1050 /* Reduce likelihood of collision with real buffers by placing the hole at
1051 * the top of the 4G area. This will have to be dealt with for real
1052 * eventually by blocking off that area from the VM.
1053 */
1054 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1055 PUSH_DATA (push, 0xff << 24);
1056
1057 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1058 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1059 &screen->poly_cache);
1060 if (ret)
1061 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1062
1063 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1064 PUSH_DATAh(push, screen->poly_cache->offset);
1065 PUSH_DATA (push, screen->poly_cache->offset);
1066 PUSH_DATA (push, 3);
1067 }
1068
1069 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1070 &screen->txc);
1071 if (ret)
1072 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1073
1074 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1075 PUSH_DATAh(push, screen->txc->offset);
1076 PUSH_DATA (push, screen->txc->offset);
1077 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1078 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1079 screen->tic.maxwell = true;
1080 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1081 screen->tic.maxwell =
1082 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1083 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1084 }
1085 }
1086
1087 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1088 PUSH_DATAh(push, screen->txc->offset + 65536);
1089 PUSH_DATA (push, screen->txc->offset + 65536);
1090 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1091
1092 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1093 PUSH_DATA (push, 0);
1094 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1095 PUSH_DATA (push, 0);
1096 PUSH_DATA (push, 0);
1097 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1098 PUSH_DATA (push, 0x3f);
1099
1100 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1101 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1102 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1103 for (i = 0; i < 8 * 2; ++i)
1104 PUSH_DATA(push, 0);
1105 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1106 PUSH_DATA (push, 0);
1107 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1108 PUSH_DATA (push, 0);
1109
1110 /* neither scissors, viewport nor stencil mask should affect clears */
1111 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1112 PUSH_DATA (push, 0);
1113
1114 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1115 PUSH_DATA (push, 1);
1116 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1117 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1118 PUSH_DATAf(push, 0.0f);
1119 PUSH_DATAf(push, 1.0f);
1120 }
1121 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1122 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1123
1124 /* We use scissors instead of exact view volume clipping,
1125 * so they're always enabled.
1126 */
1127 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1128 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1129 PUSH_DATA (push, 1);
1130 PUSH_DATA (push, 8192 << 16);
1131 PUSH_DATA (push, 8192 << 16);
1132 }
1133
1134 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1135
1136 i = 0;
1137 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1138 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1139 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1140 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1141 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1142 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1143 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1144 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1145 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1146 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1147 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1148 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1149 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1150
1151 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1152 PUSH_DATA (push, 1);
1153 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1154 PUSH_DATA (push, 1);
1155 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1156 PUSH_DATA (push, 0x40);
1157 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1158 PUSH_DATA (push, 0);
1159 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1160 PUSH_DATA (push, 0x30);
1161 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1162 PUSH_DATA (push, 3);
1163 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1164 PUSH_DATA (push, 0x20);
1165 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1166 PUSH_DATA (push, 0x00);
1167 screen->save_state.patch_vertices = 3;
1168
1169 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1170 PUSH_DATA (push, 0);
1171 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1172 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1173
1174 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1175
1176 if (nvc0_screen_init_compute(screen))
1177 goto fail;
1178
1179 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1180 for (i = 0; i < 5; ++i) {
1181 /* TIC and TSC entries for each unit (nve4+ only) */
1182 /* auxiliary constants (6 user clip planes, base instance id) */
1183 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1184 PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1185 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1186 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1187 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1188 PUSH_DATA (push, (15 << 4) | 1);
1189 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1190 unsigned j;
1191 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1192 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1193 for (j = 0; j < 8; ++j)
1194 PUSH_DATA(push, j);
1195 } else {
1196 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1197 PUSH_DATA (push, 0x54);
1198 }
1199
1200 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1201 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1202 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1203 PUSH_DATA (push, 0); /* 0 */
1204 PUSH_DATA (push, 0);
1205 PUSH_DATA (push, 1); /* 1 */
1206 PUSH_DATA (push, 0);
1207 PUSH_DATA (push, 0); /* 2 */
1208 PUSH_DATA (push, 1);
1209 PUSH_DATA (push, 1); /* 3 */
1210 PUSH_DATA (push, 1);
1211 PUSH_DATA (push, 2); /* 4 */
1212 PUSH_DATA (push, 0);
1213 PUSH_DATA (push, 3); /* 5 */
1214 PUSH_DATA (push, 0);
1215 PUSH_DATA (push, 2); /* 6 */
1216 PUSH_DATA (push, 1);
1217 PUSH_DATA (push, 3); /* 7 */
1218 PUSH_DATA (push, 1);
1219 }
1220 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1221 PUSH_DATA (push, 0);
1222
1223 PUSH_KICK (push);
1224
1225 screen->tic.entries = CALLOC(4096, sizeof(void *));
1226 screen->tsc.entries = screen->tic.entries + 2048;
1227
1228 if (!nvc0_blitter_create(screen))
1229 goto fail;
1230
1231 nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1232
1233 return &screen->base;
1234
1235 fail:
1236 screen->base.base.context_create = NULL;
1237 return &screen->base;
1238 }
1239
1240 int
1241 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1242 {
1243 int i = screen->tic.next;
1244
1245 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1246 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1247
1248 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1249
1250 if (screen->tic.entries[i])
1251 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1252
1253 screen->tic.entries[i] = entry;
1254 return i;
1255 }
1256
1257 int
1258 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1259 {
1260 int i = screen->tsc.next;
1261
1262 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1263 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1264
1265 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1266
1267 if (screen->tsc.entries[i])
1268 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1269
1270 screen->tsc.entries[i] = entry;
1271 return i;
1272 }