projects / mesa.git / blob
? search:


2c3a6978d585226efd45a8720b375c55191d257b
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
26
27 #include "vl/vl_decoder.h"
28 #include "vl/vl_video_buffer.h"
29
30 #include "nouveau_vp3_video.h"
31
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_screen.h"
34
35 #include "nvc0/nvc0_graph_macros.h"
36
37 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
38 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
39 #endif
40
41 static boolean
42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
43 enum pipe_format format,
44 enum pipe_texture_target target,
45 unsigned sample_count,
46 unsigned bindings)
47 {
48 if (sample_count > 8)
49 return FALSE;
50 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
51 return FALSE;
52
53 if (!util_format_is_supported(format, bindings))
54 return FALSE;
55
56 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
57 if (util_format_get_blocksizebits(format) == 3 * 32)
58 return FALSE;
59
60 /* transfers & shared are always supported */
61 bindings &= ~(PIPE_BIND_TRANSFER_READ |
62 PIPE_BIND_TRANSFER_WRITE |
63 PIPE_BIND_SHARED);
64
65 return (nvc0_format_table[format].usage & bindings) == bindings;
66 }
67
68 static int
69 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
70 {
71 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
72
73 switch (param) {
74 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
75 return 16 * 5;
76 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
77 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
78 return 15;
79 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
80 return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
81 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
82 return 2048;
83 case PIPE_CAP_MIN_TEXEL_OFFSET:
84 return -8;
85 case PIPE_CAP_MAX_TEXEL_OFFSET:
86 return 7;
87 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
88 case PIPE_CAP_TEXTURE_SWIZZLE:
89 case PIPE_CAP_TEXTURE_SHADOW_MAP:
90 case PIPE_CAP_NPOT_TEXTURES:
91 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
92 case PIPE_CAP_ANISOTROPIC_FILTER:
93 case PIPE_CAP_SEAMLESS_CUBE_MAP:
94 case PIPE_CAP_CUBE_MAP_ARRAY:
95 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
96 case PIPE_CAP_TEXTURE_MULTISAMPLE:
97 return 1;
98 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
99 return 65536;
100 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
101 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
102 case PIPE_CAP_TWO_SIDED_STENCIL:
103 case PIPE_CAP_DEPTH_CLIP_DISABLE:
104 case PIPE_CAP_POINT_SPRITE:
105 case PIPE_CAP_TGSI_TEXCOORD:
106 return 1;
107 case PIPE_CAP_SM3:
108 return 1;
109 case PIPE_CAP_GLSL_FEATURE_LEVEL:
110 return 150;
111 case PIPE_CAP_MAX_RENDER_TARGETS:
112 return 8;
113 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
114 return 1;
115 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
116 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
117 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
118 return 1;
119 case PIPE_CAP_QUERY_TIMESTAMP:
120 case PIPE_CAP_QUERY_TIME_ELAPSED:
121 case PIPE_CAP_OCCLUSION_QUERY:
122 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
123 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
124 return 1;
125 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
126 return 4;
127 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
128 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
129 return 128;
130 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
131 case PIPE_CAP_INDEP_BLEND_ENABLE:
132 case PIPE_CAP_INDEP_BLEND_FUNC:
133 return 1;
134 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
135 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
136 return 1;
137 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
138 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
139 return 0;
140 case PIPE_CAP_SHADER_STENCIL_EXPORT:
141 return 0;
142 case PIPE_CAP_PRIMITIVE_RESTART:
143 case PIPE_CAP_TGSI_INSTANCEID:
144 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
145 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
146 case PIPE_CAP_CONDITIONAL_RENDER:
147 case PIPE_CAP_TEXTURE_BARRIER:
148 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
149 case PIPE_CAP_START_INSTANCE:
150 return 1;
151 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
152 return 0; /* state trackers will know better */
153 case PIPE_CAP_USER_CONSTANT_BUFFERS:
154 case PIPE_CAP_USER_INDEX_BUFFERS:
155 case PIPE_CAP_USER_VERTEX_BUFFERS:
156 return 1;
157 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
158 return 256;
159 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
160 return 1; /* 256 for binding as RT, but that's not possible in GL */
161 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
162 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
163 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
164 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
165 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
166 return 0;
167 case PIPE_CAP_COMPUTE:
168 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
169 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
170 return 1;
171 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
172 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
173 case PIPE_CAP_ENDIANNESS:
174 return PIPE_ENDIAN_LITTLE;
175 case PIPE_CAP_TGSI_VS_LAYER:
176 return 0;
177 default:
178 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
179 return 0;
180 }
181 }
182
183 static int
184 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
185 enum pipe_shader_cap param)
186 {
187 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
188
189 switch (shader) {
190 case PIPE_SHADER_VERTEX:
191 /*
192 case PIPE_SHADER_TESSELLATION_CONTROL:
193 case PIPE_SHADER_TESSELLATION_EVALUATION:
194 */
195 case PIPE_SHADER_GEOMETRY:
196 case PIPE_SHADER_FRAGMENT:
197 break;
198 case PIPE_SHADER_COMPUTE:
199 if (class_3d < NVE4_3D_CLASS)
200 return 0;
201 break;
202 default:
203 return 0;
204 }
205
206 switch (param) {
207 case PIPE_SHADER_CAP_PREFERRED_IR:
208 return PIPE_SHADER_IR_TGSI;
209 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
210 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
211 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
212 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
213 return 16384;
214 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
215 return 16;
216 case PIPE_SHADER_CAP_MAX_INPUTS:
217 if (shader == PIPE_SHADER_VERTEX)
218 return 32;
219 /* NOTE: These only count our slots for GENERIC varyings.
220 * The address space may be larger, but the actual hard limit seems to be
221 * less than what the address space layout permits, so don't add TEXCOORD,
222 * COLOR, etc. here.
223 */
224 if (shader == PIPE_SHADER_FRAGMENT)
225 return 0x1f0 / 16;
226 /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
227 * and excludes 0x60 per-patch inputs.
228 */
229 return 0x200 / 16;
230 case PIPE_SHADER_CAP_MAX_CONSTS:
231 return 65536 / 16;
232 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
233 if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
234 return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
235 return NVC0_MAX_PIPE_CONSTBUFS;
236 case PIPE_SHADER_CAP_MAX_ADDRS:
237 return 1;
238 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
239 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
240 return shader != PIPE_SHADER_FRAGMENT;
241 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
242 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
243 return 1;
244 case PIPE_SHADER_CAP_MAX_PREDS:
245 return 0;
246 case PIPE_SHADER_CAP_MAX_TEMPS:
247 return NVC0_CAP_MAX_PROGRAM_TEMPS;
248 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
249 return 1;
250 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
251 return 0;
252 case PIPE_SHADER_CAP_SUBROUTINES:
253 return 1;
254 case PIPE_SHADER_CAP_INTEGERS:
255 return 1;
256 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
257 return 16; /* would be 32 in linked (OpenGL-style) mode */
258 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
259 return 16; /* XXX not sure if more are really safe */
260 default:
261 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
262 return 0;
263 }
264 }
265
266 static float
267 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
268 {
269 switch (param) {
270 case PIPE_CAPF_MAX_LINE_WIDTH:
271 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
272 return 10.0f;
273 case PIPE_CAPF_MAX_POINT_WIDTH:
274 return 63.0f;
275 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
276 return 63.375f;
277 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
278 return 16.0f;
279 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
280 return 15.0f;
281 default:
282 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
283 return 0.0f;
284 }
285 }
286
287 static int
288 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
289 enum pipe_compute_cap param, void *data)
290 {
291 uint64_t *data64 = (uint64_t *)data;
292 const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
293
294 switch (param) {
295 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
296 data64[0] = 3;
297 return 8;
298 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
299 data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
300 data64[1] = 65535;
301 data64[2] = 65535;
302 return 24;
303 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
304 data64[0] = 1024;
305 data64[1] = 1024;
306 data64[2] = 64;
307 return 24;
308 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
309 data64[0] = 1024;
310 return 8;
311 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
312 data64[0] = (uint64_t)1 << 40;
313 return 8;
314 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
315 data64[0] = 48 << 10;
316 return 8;
317 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
318 data64[0] = 512 << 10;
319 return 8;
320 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
321 data64[0] = 4096;
322 return 8;
323 default:
324 return 0;
325 }
326 }
327
328 static void
329 nvc0_screen_destroy(struct pipe_screen *pscreen)
330 {
331 struct nvc0_screen *screen = nvc0_screen(pscreen);
332
333 if (screen->base.fence.current) {
334 nouveau_fence_wait(screen->base.fence.current);
335 nouveau_fence_ref(NULL, &screen->base.fence.current);
336 }
337 if (screen->base.pushbuf)
338 screen->base.pushbuf->user_priv = NULL;
339
340 if (screen->blitter)
341 nvc0_blitter_destroy(screen);
342 if (screen->pm.prog) {
343 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
344 nvc0_program_destroy(NULL, screen->pm.prog);
345 }
346
347 nouveau_bo_ref(NULL, &screen->text);
348 nouveau_bo_ref(NULL, &screen->uniform_bo);
349 nouveau_bo_ref(NULL, &screen->tls);
350 nouveau_bo_ref(NULL, &screen->txc);
351 nouveau_bo_ref(NULL, &screen->fence.bo);
352 nouveau_bo_ref(NULL, &screen->poly_cache);
353 nouveau_bo_ref(NULL, &screen->parm);
354
355 nouveau_heap_destroy(&screen->lib_code);
356 nouveau_heap_destroy(&screen->text_heap);
357
358 FREE(screen->tic.entries);
359
360 nouveau_mm_destroy(screen->mm_VRAM_fe0);
361
362 nouveau_object_del(&screen->eng3d);
363 nouveau_object_del(&screen->eng2d);
364 nouveau_object_del(&screen->m2mf);
365 nouveau_object_del(&screen->compute);
366
367 nouveau_screen_fini(&screen->base);
368
369 FREE(screen);
370 }
371
372 static int
373 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
374 unsigned size, const uint32_t *data)
375 {
376 struct nouveau_pushbuf *push = screen->base.pushbuf;
377
378 size /= 4;
379
380 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
381 PUSH_DATA (push, (m - 0x3800) / 8);
382 PUSH_DATA (push, pos);
383 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
384 PUSH_DATA (push, pos);
385 PUSH_DATAp(push, data, size);
386
387 return pos + size;
388 }
389
390 static void
391 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
392 {
393 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
394 PUSH_DATA (push, 0xff);
395 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
396 PUSH_DATA (push, 0xff);
397 PUSH_DATA (push, 0xff);
398 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
399 PUSH_DATA (push, 0xff);
400 PUSH_DATA (push, 0xff);
401 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
402 PUSH_DATA (push, 0x3f);
403
404 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
405 PUSH_DATA (push, (3 << 16) | 3);
406 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
407 PUSH_DATA (push, (2 << 16) | 2);
408 BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
409 PUSH_DATA (push, 1);
410
411 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
412 PUSH_DATA (push, 0);
413 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
414 PUSH_DATA (push, 0x10);
415 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
416 PUSH_DATA (push, 0x10);
417 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
418 PUSH_DATA (push, 0x10);
419 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
420 PUSH_DATA (push, 0x10);
421 PUSH_DATA (push, 0x10);
422 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
423 PUSH_DATA (push, 0x10);
424 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
425 PUSH_DATA (push, 0xe);
426
427 BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
428 PUSH_DATA (push, 1 << 12);
429 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
430 PUSH_DATA (push, 0);
431 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
432 PUSH_DATA (push, 3);
433
434 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
435 PUSH_DATA (push, 0x3fffff);
436 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
437 PUSH_DATA (push, 1);
438 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
439 PUSH_DATA (push, 1);
440 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
441 PUSH_DATA (push, 3);
442
443 if (obj_class >= NVE4_3D_CLASS) {
444 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
445 PUSH_DATA (push, 1);
446 }
447
448 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
449 * are supposed to do */
450 }
451
452 static void
453 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
454 {
455 struct nvc0_screen *screen = nvc0_screen(pscreen);
456 struct nouveau_pushbuf *push = screen->base.pushbuf;
457
458 /* we need to do it after possible flush in MARK_RING */
459 *sequence = ++screen->base.fence.sequence;
460
461 BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
462 PUSH_DATAh(push, screen->fence.bo->offset);
463 PUSH_DATA (push, screen->fence.bo->offset);
464 PUSH_DATA (push, *sequence);
465 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
466 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
467 }
468
469 static u32
470 nvc0_screen_fence_update(struct pipe_screen *pscreen)
471 {
472 struct nvc0_screen *screen = nvc0_screen(pscreen);
473 return screen->fence.map[0];
474 }
475
476 static int
477 nvc0_screen_init_compute(struct nvc0_screen *screen)
478 {
479 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
480
481 switch (screen->base.device->chipset & ~0xf) {
482 case 0xc0:
483 case 0xd0:
484 /* Using COMPUTE has weird effects on 3D state, we need to
485 * investigate this further before enabling it by default.
486 */
487 if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
488 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
489 return 0;
490 case 0xe0:
491 case 0xf0:
492 case 0x100:
493 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
494 default:
495 return -1;
496 }
497 }
498
499 boolean
500 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
501 uint32_t lpos, uint32_t lneg, uint32_t cstack)
502 {
503 struct nouveau_bo *bo = NULL;
504 int ret;
505 uint64_t size = (lpos + lneg) * 32 + cstack;
506
507 if (size >= (1 << 20)) {
508 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
509 return FALSE;
510 }
511
512 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
513 size = align(size, 0x8000);
514 size *= screen->mp_count;
515
516 size = align(size, 1 << 17);
517
518 ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
519 NULL, &bo);
520 if (ret) {
521 NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
522 return FALSE;
523 }
524 nouveau_bo_ref(NULL, &screen->tls);
525 screen->tls = bo;
526 return TRUE;
527 }
528
529 #define FAIL_SCREEN_INIT(str, err) \
530 do { \
531 NOUVEAU_ERR(str, err); \
532 nvc0_screen_destroy(pscreen); \
533 return NULL; \
534 } while(0)
535
536 struct pipe_screen *
537 nvc0_screen_create(struct nouveau_device *dev)
538 {
539 struct nvc0_screen *screen;
540 struct pipe_screen *pscreen;
541 struct nouveau_object *chan;
542 struct nouveau_pushbuf *push;
543 uint64_t value;
544 uint32_t obj_class;
545 int ret;
546 unsigned i;
547 union nouveau_bo_config mm_config;
548
549 switch (dev->chipset & ~0xf) {
550 case 0xc0:
551 case 0xd0:
552 case 0xe0:
553 case 0xf0:
554 case 0x100:
555 break;
556 default:
557 return NULL;
558 }
559
560 screen = CALLOC_STRUCT(nvc0_screen);
561 if (!screen)
562 return NULL;
563 pscreen = &screen->base.base;
564
565 ret = nouveau_screen_init(&screen->base, dev);
566 if (ret) {
567 nvc0_screen_destroy(pscreen);
568 return NULL;
569 }
570 chan = screen->base.channel;
571 push = screen->base.pushbuf;
572 push->user_priv = screen;
573 push->rsvd_kick = 5;
574
575 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
576 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
577 screen->base.sysmem_bindings |=
578 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
579
580 pscreen->destroy = nvc0_screen_destroy;
581 pscreen->context_create = nvc0_create;
582 pscreen->is_format_supported = nvc0_screen_is_format_supported;
583 pscreen->get_param = nvc0_screen_get_param;
584 pscreen->get_shader_param = nvc0_screen_get_shader_param;
585 pscreen->get_paramf = nvc0_screen_get_paramf;
586 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
587
588 nvc0_screen_init_resource_functions(pscreen);
589
590 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
591 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
592
593 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
594 &screen->fence.bo);
595 if (ret)
596 goto fail;
597 nouveau_bo_map(screen->fence.bo, 0, NULL);
598 screen->fence.map = screen->fence.bo->map;
599 screen->base.fence.emit = nvc0_screen_fence_emit;
600 screen->base.fence.update = nvc0_screen_fence_update;
601
602 switch (dev->chipset & ~0xf) {
603 case 0x100:
604 case 0xf0:
605 obj_class = NVF0_P2MF_CLASS;
606 break;
607 case 0xe0:
608 obj_class = NVE4_P2MF_CLASS;
609 break;
610 default:
611 obj_class = NVC0_M2MF_CLASS;
612 break;
613 }
614 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
615 &screen->m2mf);
616 if (ret)
617 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
618
619 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
620 PUSH_DATA (push, screen->m2mf->oclass);
621 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
622 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
623 PUSH_DATA (push, 0xa0b5);
624 }
625
626 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
627 &screen->eng2d);
628 if (ret)
629 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
630
631 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
632 PUSH_DATA (push, screen->eng2d->oclass);
633 BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
634 PUSH_DATA (push, 0);
635 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
636 PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
637 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
638 PUSH_DATA (push, 0);
639 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
640 PUSH_DATA (push, 0);
641 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
642 PUSH_DATA (push, 0x3f);
643 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
644 PUSH_DATA (push, 1);
645
646 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
647 PUSH_DATAh(push, screen->fence.bo->offset + 16);
648 PUSH_DATA (push, screen->fence.bo->offset + 16);
649
650 switch (dev->chipset & ~0xf) {
651 case 0x100:
652 case 0xf0:
653 obj_class = NVF0_3D_CLASS;
654 break;
655 case 0xe0:
656 obj_class = NVE4_3D_CLASS;
657 break;
658 case 0xd0:
659 case 0xc0:
660 default:
661 switch (dev->chipset) {
662 case 0xd9:
663 case 0xc8:
664 obj_class = NVC8_3D_CLASS;
665 break;
666 case 0xc1:
667 obj_class = NVC1_3D_CLASS;
668 break;
669 default:
670 obj_class = NVC0_3D_CLASS;
671 break;
672 }
673 break;
674 }
675 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
676 &screen->eng3d);
677 if (ret)
678 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
679 screen->base.class_3d = obj_class;
680
681 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
682 PUSH_DATA (push, screen->eng3d->oclass);
683
684 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
685 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
686
687 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
688 /* kill shaders after about 1 second (at 100 MHz) */
689 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
690 PUSH_DATA (push, 0x17);
691 }
692
693 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
694 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
695 for (i = 0; i < 8; ++i)
696 PUSH_DATA(push, dev->drm_version >= 0x01000101);
697
698 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
699 PUSH_DATA (push, 1);
700
701 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
702 PUSH_DATA (push, 0);
703 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
704 PUSH_DATA (push, 0);
705 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
706 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
707 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
708 PUSH_DATA (push, 0);
709 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
710 PUSH_DATA (push, 1);
711 BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
712 PUSH_DATA (push, 0);
713 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
714 PUSH_DATA (push, 1);
715 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
716 PUSH_DATA (push, 0);
717 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
718 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
719 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
720 } else {
721 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
722 PUSH_DATA (push, 15);
723 }
724 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
725 PUSH_DATA (push, 8); /* 128 */
726 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
727 PUSH_DATA (push, 1);
728 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
729 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
730 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
731 }
732
733 nvc0_magic_3d_init(push, screen->eng3d->oclass);
734
735 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
736 &screen->text);
737 if (ret)
738 goto fail;
739
740 /* XXX: getting a page fault at the end of the code buffer every few
741 * launches, don't use the last 256 bytes to work around them - prefetch ?
742 */
743 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
744
745 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
746 &screen->uniform_bo);
747 if (ret)
748 goto fail;
749
750 PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
751
752 for (i = 0; i < 5; ++i) {
753 /* TIC and TSC entries for each unit (nve4+ only) */
754 /* auxiliary constants (6 user clip planes, base instance id) */
755 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
756 PUSH_DATA (push, 512);
757 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
758 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
759 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
760 PUSH_DATA (push, (15 << 4) | 1);
761 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
762 unsigned j;
763 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
764 PUSH_DATA (push, 0);
765 for (j = 0; j < 8; ++j)
766 PUSH_DATA(push, j);
767 } else {
768 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
769 PUSH_DATA (push, 0x54);
770 }
771 }
772 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
773 PUSH_DATA (push, 0);
774
775 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
776 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
777 PUSH_DATA (push, 256);
778 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
779 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
780 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
781 PUSH_DATA (push, 0);
782 PUSH_DATAf(push, 0.0f);
783 PUSH_DATAf(push, 0.0f);
784 PUSH_DATAf(push, 0.0f);
785 PUSH_DATAf(push, 0.0f);
786 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
787 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
788 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
789
790 if (dev->drm_version >= 0x01000101) {
791 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
792 if (ret) {
793 NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
794 goto fail;
795 }
796 } else {
797 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
798 value = (8 << 8) | 4;
799 else
800 value = (16 << 8) | 4;
801 }
802 screen->mp_count = value >> 8;
803 screen->mp_count_compute = screen->mp_count;
804
805 nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
806
807 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
808 PUSH_DATAh(push, screen->text->offset);
809 PUSH_DATA (push, screen->text->offset);
810 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
811 PUSH_DATAh(push, screen->tls->offset);
812 PUSH_DATA (push, screen->tls->offset);
813 PUSH_DATA (push, screen->tls->size >> 32);
814 PUSH_DATA (push, screen->tls->size);
815 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
816 PUSH_DATA (push, 0);
817 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
818 PUSH_DATA (push, 0);
819
820 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
821 &screen->poly_cache);
822 if (ret)
823 goto fail;
824
825 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
826 PUSH_DATAh(push, screen->poly_cache->offset);
827 PUSH_DATA (push, screen->poly_cache->offset);
828 PUSH_DATA (push, 3);
829
830 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
831 &screen->txc);
832 if (ret)
833 goto fail;
834
835 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
836 PUSH_DATAh(push, screen->txc->offset);
837 PUSH_DATA (push, screen->txc->offset);
838 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
839
840 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
841 PUSH_DATAh(push, screen->txc->offset + 65536);
842 PUSH_DATA (push, screen->txc->offset + 65536);
843 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
844
845 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
846 PUSH_DATA (push, 0);
847 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
848 PUSH_DATA (push, 0);
849 PUSH_DATA (push, 0);
850 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
851 PUSH_DATA (push, 0x3f);
852
853 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
854 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
855 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
856 for (i = 0; i < 8 * 2; ++i)
857 PUSH_DATA(push, 0);
858 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
859 PUSH_DATA (push, 0);
860 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
861 PUSH_DATA (push, 0);
862
863 /* neither scissors, viewport nor stencil mask should affect clears */
864 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
865 PUSH_DATA (push, 0);
866
867 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
868 PUSH_DATA (push, 1);
869 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
870 PUSH_DATAf(push, 0.0f);
871 PUSH_DATAf(push, 1.0f);
872 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
873 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
874
875 /* We use scissors instead of exact view volume clipping,
876 * so they're always enabled.
877 */
878 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
879 PUSH_DATA (push, 1);
880 PUSH_DATA (push, 8192 << 16);
881 PUSH_DATA (push, 8192 << 16);
882
883 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
884
885 i = 0;
886 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf);
887 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables);
888 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
889 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select);
890 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select);
891 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
892 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
893
894 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
895 PUSH_DATA (push, 1);
896 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
897 PUSH_DATA (push, 1);
898 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
899 PUSH_DATA (push, 0x40);
900 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
901 PUSH_DATA (push, 0);
902 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
903 PUSH_DATA (push, 0x30);
904 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
905 PUSH_DATA (push, 3);
906 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
907 PUSH_DATA (push, 0x20);
908 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
909 PUSH_DATA (push, 0x00);
910
911 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
912 PUSH_DATA (push, 0);
913 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
914 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
915
916 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
917
918 if (nvc0_screen_init_compute(screen))
919 goto fail;
920
921 PUSH_KICK (push);
922
923 screen->tic.entries = CALLOC(4096, sizeof(void *));
924 screen->tsc.entries = screen->tic.entries + 2048;
925
926 mm_config.nvc0.tile_mode = 0;
927 mm_config.nvc0.memtype = 0xfe0;
928 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
929
930 if (!nvc0_blitter_create(screen))
931 goto fail;
932
933 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
934
935 return pscreen;
936
937 fail:
938 nvc0_screen_destroy(pscreen);
939 return NULL;
940 }
941
942 int
943 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
944 {
945 int i = screen->tic.next;
946
947 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
948 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
949
950 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
951
952 if (screen->tic.entries[i])
953 nv50_tic_entry(screen->tic.entries[i])->id = -1;
954
955 screen->tic.entries[i] = entry;
956 return i;
957 }
958
959 int
960 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
961 {
962 int i = screen->tsc.next;
963
964 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
965 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
966
967 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
968
969 if (screen->tsc.entries[i])
970 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
971
972 screen->tsc.entries[i] = entry;
973 return i;
974 }