src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nvc0/nvc0_context.h"
  36 #include "nvc0/nvc0_screen.h"
  37
  38 #include "nvc0/mme/com9097.mme.h"
  39 #include "nvc0/mme/com90c0.mme.h"
  40
  41 static boolean
  42 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  43                                 enum pipe_format format,
  44                                 enum pipe_texture_target target,
  45                                 unsigned sample_count,
  46                                 unsigned bindings)
  47 {
  48    const struct util_format_description *desc = util_format_description(format);
  49
  50    if (sample_count > 8)
  51       return false;
  52    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  53       return false;
  54
  55    /* Short-circuit the rest of the logic -- this is used by the state tracker
  56     * to determine valid MS levels in a no-attachments scenario.
  57     */
  58    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  59       return true;
  60
  61    if (!util_format_is_supported(format, bindings))
  62       return false;
  63
  64    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  65       if (util_format_get_blocksizebits(format) == 3 * 32)
  66          return false;
  67
  68    if (bindings & PIPE_BIND_LINEAR)
  69       if (util_format_is_depth_or_stencil(format) ||
  70           (target != PIPE_TEXTURE_1D &&
  71            target != PIPE_TEXTURE_2D &&
  72            target != PIPE_TEXTURE_RECT) ||
  73           sample_count > 1)
  74          return false;
  75
  76    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  77     */
  78    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  79         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  80        /* The claim is that this should work on GM107 but it doesn't. Need to
  81         * test further and figure out if it's a nouveau issue or a HW one.
  82        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  83         */
  84        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  85       return false;
  86
  87    /* transfers & shared are always supported */
  88    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  89                  PIPE_BIND_TRANSFER_WRITE |
  90                  PIPE_BIND_LINEAR |
  91                  PIPE_BIND_SHARED);
  92
  93    return (( nvc0_format_table[format].usage |
  94             nvc0_vertex_format[format].usage) & bindings) == bindings;
  95 }
  96
  97 static int
  98 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  99 {
 100    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 101    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 102
 103    switch (param) {
 104    /* non-boolean caps */
 105    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 106    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 107       return 15;
 108    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 109       return 12;
 110    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 111       return 2048;
 112    case PIPE_CAP_MIN_TEXEL_OFFSET:
 113       return -8;
 114    case PIPE_CAP_MAX_TEXEL_OFFSET:
 115       return 7;
 116    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 117       return -32;
 118    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 119       return 31;
 120    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 121       return 128 * 1024 * 1024;
 122    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 123       if (class_3d == NVE4_3D_CLASS || class_3d == NVF0_3D_CLASS)
 124          return 420;
 125       return 410;
 126    case PIPE_CAP_MAX_RENDER_TARGETS:
 127       return 8;
 128    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 129       return 1;
 130    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 131       return 4;
 132    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 133    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 134       return 128;
 135    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 136    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 137       return 1024;
 138    case PIPE_CAP_MAX_VERTEX_STREAMS:
 139       return 4;
 140    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 141       return 2048;
 142    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 143       return 256;
 144    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 145       return 16; /* 256 for binding as RT, but that's not possible in GL */
 146    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 147       return 16;
 148    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 149       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 150    case PIPE_CAP_MAX_VIEWPORTS:
 151       return NVC0_MAX_VIEWPORTS;
 152    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 153       return 4;
 154    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 155       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 156    case PIPE_CAP_ENDIANNESS:
 157       return PIPE_ENDIAN_LITTLE;
 158    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 159       return 30;
 160
 161    /* supported caps */
 162    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 163    case PIPE_CAP_TEXTURE_SWIZZLE:
 164    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 165    case PIPE_CAP_NPOT_TEXTURES:
 166    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 167    case PIPE_CAP_ANISOTROPIC_FILTER:
 168    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 169    case PIPE_CAP_CUBE_MAP_ARRAY:
 170    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 171    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 172    case PIPE_CAP_TWO_SIDED_STENCIL:
 173    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 174    case PIPE_CAP_POINT_SPRITE:
 175    case PIPE_CAP_TGSI_TEXCOORD:
 176    case PIPE_CAP_SM3:
 177    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 178    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 179    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 180    case PIPE_CAP_QUERY_TIMESTAMP:
 181    case PIPE_CAP_QUERY_TIME_ELAPSED:
 182    case PIPE_CAP_OCCLUSION_QUERY:
 183    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 184    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 185    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 186    case PIPE_CAP_INDEP_BLEND_ENABLE:
 187    case PIPE_CAP_INDEP_BLEND_FUNC:
 188    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 189    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 190    case PIPE_CAP_PRIMITIVE_RESTART:
 191    case PIPE_CAP_TGSI_INSTANCEID:
 192    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 193    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 194    case PIPE_CAP_CONDITIONAL_RENDER:
 195    case PIPE_CAP_TEXTURE_BARRIER:
 196    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 197    case PIPE_CAP_START_INSTANCE:
 198    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 199    case PIPE_CAP_DRAW_INDIRECT:
 200    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 201    case PIPE_CAP_USER_INDEX_BUFFERS:
 202    case PIPE_CAP_USER_VERTEX_BUFFERS:
 203    case PIPE_CAP_TEXTURE_QUERY_LOD:
 204    case PIPE_CAP_SAMPLE_SHADING:
 205    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 206    case PIPE_CAP_TEXTURE_GATHER_SM5:
 207    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 208    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 209    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 210    case PIPE_CAP_CLIP_HALFZ:
 211    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 212    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 213    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 214    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 215    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 216    case PIPE_CAP_TGSI_TXQS:
 217    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 218    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 219    case PIPE_CAP_SHAREABLE_SHADERS:
 220    case PIPE_CAP_CLEAR_TEXTURE:
 221    case PIPE_CAP_DRAW_PARAMETERS:
 222    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 223    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 224    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 225    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 226    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 227    case PIPE_CAP_INVALIDATE_BUFFER:
 228    case PIPE_CAP_STRING_MARKER:
 229    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 230    case PIPE_CAP_CULL_DISTANCE:
 231       return 1;
 232    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 233       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 234    case PIPE_CAP_COMPUTE:
 235       return 1;
 236    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 237       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 238
 239    /* unsupported caps */
 240    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 241    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 242    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 243    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 244    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 245    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 246    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 247    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 248    case PIPE_CAP_FAKE_SW_MSAA:
 249    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 250    case PIPE_CAP_VERTEXID_NOBASE:
 251    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 252    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 253    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 254    case PIPE_CAP_GENERATE_MIPMAP:
 255    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 256    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 257    case PIPE_CAP_QUERY_MEMORY_INFO:
 258    case PIPE_CAP_PCI_GROUP:
 259    case PIPE_CAP_PCI_BUS:
 260    case PIPE_CAP_PCI_DEVICE:
 261    case PIPE_CAP_PCI_FUNCTION:
 262    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 263       return 0;
 264
 265    case PIPE_CAP_VENDOR_ID:
 266       return 0x10de;
 267    case PIPE_CAP_DEVICE_ID: {
 268       uint64_t device_id;
 269       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 270          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 271          return -1;
 272       }
 273       return device_id;
 274    }
 275    case PIPE_CAP_ACCELERATED:
 276       return 1;
 277    case PIPE_CAP_VIDEO_MEMORY:
 278       return dev->vram_size >> 20;
 279    case PIPE_CAP_UMA:
 280       return 0;
 281    }
 282
 283    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 284    return 0;
 285 }
 286
 287 static int
 288 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 289                              enum pipe_shader_cap param)
 290 {
 291    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 292
 293    switch (shader) {
 294    case PIPE_SHADER_VERTEX:
 295    case PIPE_SHADER_GEOMETRY:
 296    case PIPE_SHADER_FRAGMENT:
 297    case PIPE_SHADER_COMPUTE:
 298       break;
 299    case PIPE_SHADER_TESS_CTRL:
 300    case PIPE_SHADER_TESS_EVAL:
 301       if (class_3d >= GM107_3D_CLASS)
 302          return 0;
 303       break;
 304    default:
 305       return 0;
 306    }
 307
 308    switch (param) {
 309    case PIPE_SHADER_CAP_PREFERRED_IR:
 310       return PIPE_SHADER_IR_TGSI;
 311    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 312       return 1 << PIPE_SHADER_IR_TGSI;
 313    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 314    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 315    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 316    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 317       return 16384;
 318    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 319       return 16;
 320    case PIPE_SHADER_CAP_MAX_INPUTS:
 321       if (shader == PIPE_SHADER_VERTEX)
 322          return 32;
 323       /* NOTE: These only count our slots for GENERIC varyings.
 324        * The address space may be larger, but the actual hard limit seems to be
 325        * less than what the address space layout permits, so don't add TEXCOORD,
 326        * COLOR, etc. here.
 327        */
 328       if (shader == PIPE_SHADER_FRAGMENT)
 329          return 0x1f0 / 16;
 330       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 331        * and excludes 0x60 per-patch inputs.
 332        */
 333       return 0x200 / 16;
 334    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 335       return 32;
 336    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 337       return 65536;
 338    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 339       return NVC0_MAX_PIPE_CONSTBUFS;
 340    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 341       return shader != PIPE_SHADER_FRAGMENT;
 342    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 343       return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
 344    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 345    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 346       return 1;
 347    case PIPE_SHADER_CAP_MAX_PREDS:
 348       return 0;
 349    case PIPE_SHADER_CAP_MAX_TEMPS:
 350       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 351    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 352       return 1;
 353    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 354       return 1;
 355    case PIPE_SHADER_CAP_SUBROUTINES:
 356       return 1;
 357    case PIPE_SHADER_CAP_INTEGERS:
 358       return 1;
 359    case PIPE_SHADER_CAP_DOUBLES:
 360       return 1;
 361    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 362       return 1;
 363    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 364       return 1;
 365    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 366    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 367       return 0;
 368    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 369       return NVC0_MAX_BUFFERS;
 370    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 371       return 16; /* would be 32 in linked (OpenGL-style) mode */
 372    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 373       return 16; /* XXX not sure if more are really safe */
 374    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 375       return 32;
 376    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 377       if (class_3d == NVE4_3D_CLASS || class_3d == NVF0_3D_CLASS)
 378          return NVC0_MAX_IMAGES;
 379       return 0;
 380    default:
 381       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 382       return 0;
 383    }
 384 }
 385
 386 static float
 387 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 388 {
 389    switch (param) {
 390    case PIPE_CAPF_MAX_LINE_WIDTH:
 391    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 392       return 10.0f;
 393    case PIPE_CAPF_MAX_POINT_WIDTH:
 394       return 63.0f;
 395    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 396       return 63.375f;
 397    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 398       return 16.0f;
 399    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 400       return 15.0f;
 401    case PIPE_CAPF_GUARD_BAND_LEFT:
 402    case PIPE_CAPF_GUARD_BAND_TOP:
 403       return 0.0f;
 404    case PIPE_CAPF_GUARD_BAND_RIGHT:
 405    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 406       return 0.0f; /* that or infinity */
 407    }
 408
 409    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 410    return 0.0f;
 411 }
 412
 413 static int
 414 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 415                               enum pipe_shader_ir ir_type,
 416                               enum pipe_compute_cap param, void *data)
 417 {
 418    struct nvc0_screen *screen = nvc0_screen(pscreen);
 419    const uint16_t obj_class = screen->compute->oclass;
 420
 421 #define RET(x) do {                  \
 422    if (data)                         \
 423       memcpy(data, x, sizeof(x));    \
 424    return sizeof(x);                 \
 425 } while (0)
 426
 427    switch (param) {
 428    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 429       RET((uint64_t []) { 3 });
 430    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 431       if (obj_class >= NVE4_COMPUTE_CLASS) {
 432          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 433       } else {
 434          RET(((uint64_t []) { 65535, 65535, 65535 }));
 435       }
 436    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 437       RET(((uint64_t []) { 1024, 1024, 64 }));
 438    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 439       RET((uint64_t []) { 1024 });
 440    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 441       RET((uint64_t []) { 1ULL << 40 });
 442    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 443       switch (obj_class) {
 444       case GM200_COMPUTE_CLASS:
 445          RET((uint64_t []) { 96 << 10 });
 446          break;
 447       case GM107_COMPUTE_CLASS:
 448          RET((uint64_t []) { 64 << 10 });
 449          break;
 450       default:
 451          RET((uint64_t []) { 48 << 10 });
 452          break;
 453       }
 454    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 455       RET((uint64_t []) { 512 << 10 });
 456    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 457       RET((uint64_t []) { 4096 });
 458    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 459       RET((uint32_t []) { 32 });
 460    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 461       RET((uint64_t []) { 1ULL << 40 });
 462    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 463       RET((uint32_t []) { 0 });
 464    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 465       RET((uint32_t []) { screen->mp_count_compute });
 466    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 467       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 468    default:
 469       return 0;
 470    }
 471
 472 #undef RET
 473 }
 474
 475 static void
 476 nvc0_screen_destroy(struct pipe_screen *pscreen)
 477 {
 478    struct nvc0_screen *screen = nvc0_screen(pscreen);
 479
 480    if (!nouveau_drm_screen_unref(&screen->base))
 481       return;
 482
 483    if (screen->base.fence.current) {
 484       struct nouveau_fence *current = NULL;
 485
 486       /* nouveau_fence_wait will create a new current fence, so wait on the
 487        * _current_ one, and remove both.
 488        */
 489       nouveau_fence_ref(screen->base.fence.current, &current);
 490       nouveau_fence_wait(current, NULL);
 491       nouveau_fence_ref(NULL, &current);
 492       nouveau_fence_ref(NULL, &screen->base.fence.current);
 493    }
 494    if (screen->base.pushbuf)
 495       screen->base.pushbuf->user_priv = NULL;
 496
 497    if (screen->blitter)
 498       nvc0_blitter_destroy(screen);
 499    if (screen->pm.prog) {
 500       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 501       nvc0_program_destroy(NULL, screen->pm.prog);
 502       FREE(screen->pm.prog);
 503    }
 504
 505    nouveau_bo_ref(NULL, &screen->text);
 506    nouveau_bo_ref(NULL, &screen->uniform_bo);
 507    nouveau_bo_ref(NULL, &screen->tls);
 508    nouveau_bo_ref(NULL, &screen->txc);
 509    nouveau_bo_ref(NULL, &screen->fence.bo);
 510    nouveau_bo_ref(NULL, &screen->poly_cache);
 511
 512    nouveau_heap_destroy(&screen->lib_code);
 513    nouveau_heap_destroy(&screen->text_heap);
 514
 515    FREE(screen->tic.entries);
 516
 517    nouveau_object_del(&screen->eng3d);
 518    nouveau_object_del(&screen->eng2d);
 519    nouveau_object_del(&screen->m2mf);
 520    nouveau_object_del(&screen->compute);
 521    nouveau_object_del(&screen->nvsw);
 522
 523    nouveau_screen_fini(&screen->base);
 524
 525    FREE(screen);
 526 }
 527
 528 static int
 529 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 530                      unsigned size, const uint32_t *data)
 531 {
 532    struct nouveau_pushbuf *push = screen->base.pushbuf;
 533
 534    size /= 4;
 535
 536    assert((pos + size) <= 0x800);
 537
 538    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 539    PUSH_DATA (push, (m - 0x3800) / 8);
 540    PUSH_DATA (push, pos);
 541    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 542    PUSH_DATA (push, pos);
 543    PUSH_DATAp(push, data, size);
 544
 545    return pos + size;
 546 }
 547
 548 static void
 549 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 550 {
 551    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 552    PUSH_DATA (push, 0xff);
 553    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 554    PUSH_DATA (push, 0xff);
 555    PUSH_DATA (push, 0xff);
 556    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 557    PUSH_DATA (push, 0xff);
 558    PUSH_DATA (push, 0xff);
 559    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 560    PUSH_DATA (push, 0x3f);
 561
 562    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 563    PUSH_DATA (push, (3 << 16) | 3);
 564    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 565    PUSH_DATA (push, (2 << 16) | 2);
 566
 567    if (obj_class < GM107_3D_CLASS) {
 568       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 569       PUSH_DATA (push, 0);
 570    }
 571    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 572    PUSH_DATA (push, 0x10);
 573    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 574    PUSH_DATA (push, 0x10);
 575    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 576    PUSH_DATA (push, 0x10);
 577    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 578    PUSH_DATA (push, 0x10);
 579    PUSH_DATA (push, 0x10);
 580    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 581    PUSH_DATA (push, 0x10);
 582    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 583    PUSH_DATA (push, 0xe);
 584
 585    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 586    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 587    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 588    PUSH_DATA (push, 0);
 589    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 590    PUSH_DATA (push, 3);
 591
 592    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 593    PUSH_DATA (push, 0x3fffff);
 594    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 595    PUSH_DATA (push, 1);
 596    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 597    PUSH_DATA (push, 1);
 598
 599    if (obj_class < GM107_3D_CLASS) {
 600       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 601       PUSH_DATA (push, 3);
 602
 603       if (obj_class >= NVE4_3D_CLASS) {
 604          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 605          PUSH_DATA (push, 1);
 606       }
 607    }
 608
 609    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 610     * are supposed to do */
 611 }
 612
 613 static void
 614 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 615 {
 616    struct nvc0_screen *screen = nvc0_screen(pscreen);
 617    struct nouveau_pushbuf *push = screen->base.pushbuf;
 618
 619    /* we need to do it after possible flush in MARK_RING */
 620    *sequence = ++screen->base.fence.sequence;
 621
 622    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 623    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 624    PUSH_DATAh(push, screen->fence.bo->offset);
 625    PUSH_DATA (push, screen->fence.bo->offset);
 626    PUSH_DATA (push, *sequence);
 627    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 628               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 629 }
 630
 631 static u32
 632 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 633 {
 634    struct nvc0_screen *screen = nvc0_screen(pscreen);
 635    return screen->fence.map[0];
 636 }
 637
 638 static int
 639 nvc0_screen_init_compute(struct nvc0_screen *screen)
 640 {
 641    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 642
 643    switch (screen->base.device->chipset & ~0xf) {
 644    case 0xc0:
 645    case 0xd0:
 646       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 647    case 0xe0:
 648    case 0xf0:
 649    case 0x100:
 650    case 0x110:
 651    case 0x120:
 652       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 653    default:
 654       return -1;
 655    }
 656 }
 657
 658 bool
 659 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 660                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 661 {
 662    struct nouveau_bo *bo = NULL;
 663    int ret;
 664    uint64_t size = (lpos + lneg) * 32 + cstack;
 665
 666    if (size >= (1 << 20)) {
 667       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 668       return false;
 669    }
 670
 671    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 672    size  = align(size, 0x8000);
 673    size *= screen->mp_count;
 674
 675    size = align(size, 1 << 17);
 676
 677    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 678                         NULL, &bo);
 679    if (ret) {
 680       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
 681       return false;
 682    }
 683    nouveau_bo_ref(NULL, &screen->tls);
 684    screen->tls = bo;
 685    return true;
 686 }
 687
 688 #define FAIL_SCREEN_INIT(str, err)                    \
 689    do {                                               \
 690       NOUVEAU_ERR(str, err);                          \
 691       goto fail;                                      \
 692    } while(0)
 693
 694 struct nouveau_screen *
 695 nvc0_screen_create(struct nouveau_device *dev)
 696 {
 697    struct nvc0_screen *screen;
 698    struct pipe_screen *pscreen;
 699    struct nouveau_object *chan;
 700    struct nouveau_pushbuf *push;
 701    uint64_t value;
 702    uint32_t obj_class;
 703    uint32_t flags;
 704    int ret;
 705    unsigned i;
 706
 707    switch (dev->chipset & ~0xf) {
 708    case 0xc0:
 709    case 0xd0:
 710    case 0xe0:
 711    case 0xf0:
 712    case 0x100:
 713    case 0x110:
 714    case 0x120:
 715       break;
 716    default:
 717       return NULL;
 718    }
 719
 720    screen = CALLOC_STRUCT(nvc0_screen);
 721    if (!screen)
 722       return NULL;
 723    pscreen = &screen->base.base;
 724    pscreen->destroy = nvc0_screen_destroy;
 725
 726    ret = nouveau_screen_init(&screen->base, dev);
 727    if (ret) {
 728       nvc0_screen_destroy(pscreen);
 729       return NULL;
 730    }
 731    chan = screen->base.channel;
 732    push = screen->base.pushbuf;
 733    push->user_priv = screen;
 734    push->rsvd_kick = 5;
 735
 736    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 737       PIPE_BIND_SHADER_BUFFER |
 738       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 739       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 740    screen->base.sysmem_bindings |=
 741       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 742
 743    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 744       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 745       screen->base.vidmem_bindings = 0;
 746    }
 747
 748    pscreen->context_create = nvc0_create;
 749    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 750    pscreen->get_param = nvc0_screen_get_param;
 751    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 752    pscreen->get_paramf = nvc0_screen_get_paramf;
 753    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 754    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 755
 756    nvc0_screen_init_resource_functions(pscreen);
 757
 758    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 759    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 760
 761    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 762    if (screen->base.drm->version >= 0x01000202)
 763       flags |= NOUVEAU_BO_COHERENT;
 764
 765    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 766    if (ret)
 767       goto fail;
 768    nouveau_bo_map(screen->fence.bo, 0, NULL);
 769    screen->fence.map = screen->fence.bo->map;
 770    screen->base.fence.emit = nvc0_screen_fence_emit;
 771    screen->base.fence.update = nvc0_screen_fence_update;
 772
 773
 774    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 775                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 776    if (ret)
 777       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 778
 779    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 780    PUSH_DATA (push, screen->nvsw->handle);
 781
 782    switch (dev->chipset & ~0xf) {
 783    case 0x120:
 784    case 0x110:
 785    case 0x100:
 786    case 0xf0:
 787       obj_class = NVF0_P2MF_CLASS;
 788       break;
 789    case 0xe0:
 790       obj_class = NVE4_P2MF_CLASS;
 791       break;
 792    default:
 793       obj_class = NVC0_M2MF_CLASS;
 794       break;
 795    }
 796    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 797                             &screen->m2mf);
 798    if (ret)
 799       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 800
 801    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 802    PUSH_DATA (push, screen->m2mf->oclass);
 803    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 804       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 805       PUSH_DATA (push, 0xa0b5);
 806    }
 807
 808    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 809                             &screen->eng2d);
 810    if (ret)
 811       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 812
 813    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 814    PUSH_DATA (push, screen->eng2d->oclass);
 815    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 816    PUSH_DATA (push, 0);
 817    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 818    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 819    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 820    PUSH_DATA (push, 0);
 821    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 822    PUSH_DATA (push, 0);
 823    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 824    PUSH_DATA (push, 0x3f);
 825    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 826    PUSH_DATA (push, 1);
 827    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 828    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 829
 830    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 831    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 832    PUSH_DATA (push, screen->fence.bo->offset + 16);
 833
 834    switch (dev->chipset & ~0xf) {
 835    case 0x120:
 836       obj_class = GM200_3D_CLASS;
 837       break;
 838    case 0x110:
 839       obj_class = GM107_3D_CLASS;
 840       break;
 841    case 0x100:
 842    case 0xf0:
 843       obj_class = NVF0_3D_CLASS;
 844       break;
 845    case 0xe0:
 846       switch (dev->chipset) {
 847       case 0xea:
 848          obj_class = NVEA_3D_CLASS;
 849          break;
 850       default:
 851          obj_class = NVE4_3D_CLASS;
 852          break;
 853       }
 854       break;
 855    case 0xd0:
 856       obj_class = NVC8_3D_CLASS;
 857       break;
 858    case 0xc0:
 859    default:
 860       switch (dev->chipset) {
 861       case 0xc8:
 862          obj_class = NVC8_3D_CLASS;
 863          break;
 864       case 0xc1:
 865          obj_class = NVC1_3D_CLASS;
 866          break;
 867       default:
 868          obj_class = NVC0_3D_CLASS;
 869          break;
 870       }
 871       break;
 872    }
 873    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 874                             &screen->eng3d);
 875    if (ret)
 876       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 877    screen->base.class_3d = obj_class;
 878
 879    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 880    PUSH_DATA (push, screen->eng3d->oclass);
 881
 882    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 883    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 884
 885    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 886       /* kill shaders after about 1 second (at 100 MHz) */
 887       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 888       PUSH_DATA (push, 0x17);
 889    }
 890
 891    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
 892                     screen->base.drm->version >= 0x01000101);
 893    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 894    for (i = 0; i < 8; ++i)
 895            PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 896
 897    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 898    PUSH_DATA (push, 1);
 899
 900    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 901    PUSH_DATA (push, 0);
 902    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 903    PUSH_DATA (push, 0);
 904    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 905    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 906    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 907    PUSH_DATA (push, 0);
 908    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 909    PUSH_DATA (push, 1);
 910    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 911    PUSH_DATA (push, 1);
 912    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 913    PUSH_DATA (push, 1);
 914    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 915    PUSH_DATA (push, 0);
 916    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
 917    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
 918    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 919       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
 920    } else {
 921       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 922       PUSH_DATA (push, 15);
 923    }
 924    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 925    PUSH_DATA (push, 8); /* 128 */
 926    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 927    PUSH_DATA (push, 1);
 928    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 929       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 930       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 931    }
 932
 933    nvc0_magic_3d_init(push, screen->eng3d->oclass);
 934
 935    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
 936                         &screen->text);
 937    if (ret)
 938       goto fail;
 939
 940    /* XXX: getting a page fault at the end of the code buffer every few
 941     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 942     */
 943    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
 944
 945    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
 946                         &screen->uniform_bo);
 947    if (ret)
 948       goto fail;
 949
 950    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
 951
 952    for (i = 0; i < 5; ++i) {
 953       /* TIC and TSC entries for each unit (nve4+ only) */
 954       /* auxiliary constants (6 user clip planes, base instance id) */
 955       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 956       PUSH_DATA (push, 2048);
 957       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
 958       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
 959       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
 960       PUSH_DATA (push, (15 << 4) | 1);
 961       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
 962          unsigned j;
 963          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
 964          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
 965          for (j = 0; j < 8; ++j)
 966             PUSH_DATA(push, j);
 967       } else {
 968          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
 969          PUSH_DATA (push, 0x54);
 970       }
 971    }
 972    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
 973    PUSH_DATA (push, 0);
 974
 975    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
 976    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
 977    PUSH_DATA (push, 256);
 978    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 979    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 980    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
 981    PUSH_DATA (push, 0);
 982    PUSH_DATAf(push, 0.0f);
 983    PUSH_DATAf(push, 0.0f);
 984    PUSH_DATAf(push, 0.0f);
 985    PUSH_DATAf(push, 0.0f);
 986    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 987    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 988    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
 989
 990    if (screen->base.drm->version >= 0x01000101) {
 991       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 992       if (ret) {
 993          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
 994          goto fail;
 995       }
 996    } else {
 997       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
 998          value = (8 << 8) | 4;
 999       else
1000          value = (16 << 8) | 4;
1001    }
1002    screen->gpc_count = value & 0x000000ff;
1003    screen->mp_count = value >> 8;
1004    screen->mp_count_compute = screen->mp_count;
1005
1006    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1007
1008    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
1009    PUSH_DATAh(push, screen->text->offset);
1010    PUSH_DATA (push, screen->text->offset);
1011    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1012    PUSH_DATAh(push, screen->tls->offset);
1013    PUSH_DATA (push, screen->tls->offset);
1014    PUSH_DATA (push, screen->tls->size >> 32);
1015    PUSH_DATA (push, screen->tls->size);
1016    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1017    PUSH_DATA (push, 0);
1018    /* Reduce likelihood of collision with real buffers by placing the hole at
1019     * the top of the 4G area. This will have to be dealt with for real
1020     * eventually by blocking off that area from the VM.
1021     */
1022    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1023    PUSH_DATA (push, 0xff << 24);
1024
1025    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1026       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1027                            &screen->poly_cache);
1028       if (ret)
1029          goto fail;
1030
1031       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1032       PUSH_DATAh(push, screen->poly_cache->offset);
1033       PUSH_DATA (push, screen->poly_cache->offset);
1034       PUSH_DATA (push, 3);
1035    }
1036
1037    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1038                         &screen->txc);
1039    if (ret)
1040       goto fail;
1041
1042    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1043    PUSH_DATAh(push, screen->txc->offset);
1044    PUSH_DATA (push, screen->txc->offset);
1045    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1046    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1047       screen->tic.maxwell = true;
1048       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1049          screen->tic.maxwell =
1050             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1051          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1052       }
1053    }
1054
1055    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1056    PUSH_DATAh(push, screen->txc->offset + 65536);
1057    PUSH_DATA (push, screen->txc->offset + 65536);
1058    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1059
1060    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1061    PUSH_DATA (push, 0);
1062    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1063    PUSH_DATA (push, 0);
1064    PUSH_DATA (push, 0);
1065    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1066    PUSH_DATA (push, 0x3f);
1067
1068    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1069    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1070    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1071    for (i = 0; i < 8 * 2; ++i)
1072       PUSH_DATA(push, 0);
1073    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1074    PUSH_DATA (push, 0);
1075    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1076    PUSH_DATA (push, 0);
1077
1078    /* neither scissors, viewport nor stencil mask should affect clears */
1079    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1080    PUSH_DATA (push, 0);
1081
1082    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1083    PUSH_DATA (push, 1);
1084    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1085       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1086       PUSH_DATAf(push, 0.0f);
1087       PUSH_DATAf(push, 1.0f);
1088    }
1089    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1090    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1091
1092    /* We use scissors instead of exact view volume clipping,
1093     * so they're always enabled.
1094     */
1095    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1096       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1097       PUSH_DATA (push, 1);
1098       PUSH_DATA (push, 8192 << 16);
1099       PUSH_DATA (push, 8192 << 16);
1100    }
1101
1102 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1103
1104    i = 0;
1105    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1106    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1107    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1108    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1109    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1110    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1111    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1112    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1113    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1114    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1115    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1116    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1117    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1118
1119    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1120    PUSH_DATA (push, 1);
1121    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1122    PUSH_DATA (push, 1);
1123    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1124    PUSH_DATA (push, 0x40);
1125    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1126    PUSH_DATA (push, 0);
1127    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1128    PUSH_DATA (push, 0x30);
1129    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1130    PUSH_DATA (push, 3);
1131    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1132    PUSH_DATA (push, 0x20);
1133    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1134    PUSH_DATA (push, 0x00);
1135    screen->save_state.patch_vertices = 3;
1136
1137    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1138    PUSH_DATA (push, 0);
1139    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1140    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1141
1142    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1143
1144    if (nvc0_screen_init_compute(screen))
1145       goto fail;
1146
1147    PUSH_KICK (push);
1148
1149    screen->tic.entries = CALLOC(4096, sizeof(void *));
1150    screen->tsc.entries = screen->tic.entries + 2048;
1151
1152    if (!nvc0_blitter_create(screen))
1153       goto fail;
1154
1155    nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
1156
1157    return &screen->base;
1158
1159 fail:
1160    screen->base.base.context_create = NULL;
1161    return &screen->base;
1162 }
1163
1164 int
1165 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1166 {
1167    int i = screen->tic.next;
1168
1169    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1170       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1171
1172    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1173
1174    if (screen->tic.entries[i])
1175       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1176
1177    screen->tic.entries[i] = entry;
1178    return i;
1179 }
1180
1181 int
1182 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1183 {
1184    int i = screen->tsc.next;
1185
1186    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1187       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1188
1189    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1190
1191    if (screen->tsc.entries[i])
1192       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1193
1194    screen->tsc.entries[i] = entry;
1195    return i;
1196 }