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nvc0: enable spirv caps with nir
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <xf86drm.h>
24 #include <nouveau_drm.h>
25 #include <nvif/class.h>
26 #include "util/format/u_format.h"
27 #include "util/format/u_format_s3tc.h"
28 #include "util/u_screen.h"
29 #include "pipe/p_screen.h"
30
31 #include "nouveau_vp3_video.h"
32
33 #include "codegen/nv50_ir_driver.h"
34
35 #include "nvc0/nvc0_context.h"
36 #include "nvc0/nvc0_screen.h"
37
38 #include "nvc0/mme/com9097.mme.h"
39 #include "nvc0/mme/com90c0.mme.h"
40 #include "nvc0/mme/comc597.mme.h"
41
42 #include "nv50/g80_texture.xml.h"
43
44 static bool
45 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
46 enum pipe_format format,
47 enum pipe_texture_target target,
48 unsigned sample_count,
49 unsigned storage_sample_count,
50 unsigned bindings)
51 {
52 const struct util_format_description *desc = util_format_description(format);
53
54 if (sample_count > 8)
55 return false;
56 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
57 return false;
58
59 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
60 return false;
61
62 /* Short-circuit the rest of the logic -- this is used by the gallium frontend
63 * to determine valid MS levels in a no-attachments scenario.
64 */
65 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
66 return true;
67
68 if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
69 if (util_format_get_blocksizebits(format) == 3 * 32)
70 return false;
71
72 if (bindings & PIPE_BIND_LINEAR)
73 if (util_format_is_depth_or_stencil(format) ||
74 (target != PIPE_TEXTURE_1D &&
75 target != PIPE_TEXTURE_2D &&
76 target != PIPE_TEXTURE_RECT) ||
77 sample_count > 1)
78 return false;
79
80 /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A
81 * and GM20B.
82 */
83 if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
84 desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
85 nouveau_screen(pscreen)->device->chipset != 0x12b &&
86 nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
87 return false;
88
89 /* shared is always supported */
90 bindings &= ~(PIPE_BIND_LINEAR |
91 PIPE_BIND_SHARED);
92
93 if (bindings & PIPE_BIND_SHADER_IMAGE) {
94 if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
95 nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
96 /* This should work on Fermi, but for currently unknown reasons it
97 * does not and results in breaking reads from pbos. */
98 return false;
99 }
100 }
101
102 return (( nvc0_format_table[format].usage |
103 nvc0_vertex_format[format].usage) & bindings) == bindings;
104 }
105
106 static int
107 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
108 {
109 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
110 const struct nouveau_screen *screen = nouveau_screen(pscreen);
111 struct nouveau_device *dev = screen->device;
112
113 switch (param) {
114 /* non-boolean caps */
115 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
116 return 16384;
117 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
118 return 15;
119 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
120 return 12;
121 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
122 return 2048;
123 case PIPE_CAP_MIN_TEXEL_OFFSET:
124 return -8;
125 case PIPE_CAP_MAX_TEXEL_OFFSET:
126 return 7;
127 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
128 return -32;
129 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
130 return 31;
131 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
132 return 128 * 1024 * 1024;
133 case PIPE_CAP_GLSL_FEATURE_LEVEL:
134 return 430;
135 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
136 return 430;
137 case PIPE_CAP_MAX_RENDER_TARGETS:
138 return 8;
139 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
140 return 1;
141 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
142 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
143 return 8;
144 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
145 return 4;
146 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
147 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
148 return 128;
149 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
150 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
151 return 1024;
152 case PIPE_CAP_MAX_VERTEX_STREAMS:
153 return 4;
154 case PIPE_CAP_MAX_GS_INVOCATIONS:
155 return 32;
156 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
157 return 1 << 27;
158 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
159 return 2048;
160 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
161 return 2047;
162 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
163 return 256;
164 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
165 if (class_3d < GM107_3D_CLASS)
166 return 256; /* IMAGE bindings require alignment to 256 */
167 return 16;
168 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
169 return 16;
170 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
171 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
172 case PIPE_CAP_MAX_VIEWPORTS:
173 return NVC0_MAX_VIEWPORTS;
174 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
175 return 4;
176 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
177 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
178 case PIPE_CAP_ENDIANNESS:
179 return PIPE_ENDIAN_LITTLE;
180 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
181 return 30;
182 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
183 return NVC0_MAX_WINDOW_RECTANGLES;
184 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
185 return class_3d >= GM200_3D_CLASS ? 8 : 0;
186 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
187 return 64 * 1024 * 1024;
188 case PIPE_CAP_MAX_VARYINGS:
189 /* NOTE: These only count our slots for GENERIC varyings.
190 * The address space may be larger, but the actual hard limit seems to be
191 * less than what the address space layout permits, so don't add TEXCOORD,
192 * COLOR, etc. here.
193 */
194 return 0x1f0 / 16;
195 case PIPE_CAP_MAX_VERTEX_BUFFERS:
196 return 16;
197 case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
198 return 512 * 1024; /* TODO: Investigate tuning this */
199
200 /* supported caps */
201 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
202 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
203 case PIPE_CAP_TEXTURE_SWIZZLE:
204 case PIPE_CAP_TEXTURE_SHADOW_MAP:
205 case PIPE_CAP_NPOT_TEXTURES:
206 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
207 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
208 case PIPE_CAP_ANISOTROPIC_FILTER:
209 case PIPE_CAP_SEAMLESS_CUBE_MAP:
210 case PIPE_CAP_CUBE_MAP_ARRAY:
211 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
212 case PIPE_CAP_TEXTURE_MULTISAMPLE:
213 case PIPE_CAP_DEPTH_CLIP_DISABLE:
214 case PIPE_CAP_POINT_SPRITE:
215 case PIPE_CAP_TGSI_TEXCOORD:
216 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
217 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
218 case PIPE_CAP_VERTEX_SHADER_SATURATE:
219 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
220 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
221 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
222 case PIPE_CAP_QUERY_TIMESTAMP:
223 case PIPE_CAP_QUERY_TIME_ELAPSED:
224 case PIPE_CAP_OCCLUSION_QUERY:
225 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
226 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
227 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
228 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
229 case PIPE_CAP_INDEP_BLEND_ENABLE:
230 case PIPE_CAP_INDEP_BLEND_FUNC:
231 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
232 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
233 case PIPE_CAP_PRIMITIVE_RESTART:
234 case PIPE_CAP_TGSI_INSTANCEID:
235 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
236 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
237 case PIPE_CAP_CONDITIONAL_RENDER:
238 case PIPE_CAP_TEXTURE_BARRIER:
239 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
240 case PIPE_CAP_START_INSTANCE:
241 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
242 case PIPE_CAP_DRAW_INDIRECT:
243 case PIPE_CAP_USER_VERTEX_BUFFERS:
244 case PIPE_CAP_TEXTURE_QUERY_LOD:
245 case PIPE_CAP_SAMPLE_SHADING:
246 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
247 case PIPE_CAP_TEXTURE_GATHER_SM5:
248 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
249 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
250 case PIPE_CAP_SAMPLER_VIEW_TARGET:
251 case PIPE_CAP_CLIP_HALFZ:
252 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
253 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
254 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
255 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
256 case PIPE_CAP_DEPTH_BOUNDS_TEST:
257 case PIPE_CAP_TGSI_TXQS:
258 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
259 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
260 case PIPE_CAP_SHAREABLE_SHADERS:
261 case PIPE_CAP_CLEAR_TEXTURE:
262 case PIPE_CAP_DRAW_PARAMETERS:
263 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
264 case PIPE_CAP_MULTI_DRAW_INDIRECT:
265 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
266 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
267 case PIPE_CAP_QUERY_BUFFER_OBJECT:
268 case PIPE_CAP_INVALIDATE_BUFFER:
269 case PIPE_CAP_STRING_MARKER:
270 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
271 case PIPE_CAP_CULL_DISTANCE:
272 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
273 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
274 case PIPE_CAP_TGSI_VOTE:
275 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
276 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
277 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
278 case PIPE_CAP_DOUBLES:
279 case PIPE_CAP_INT64:
280 case PIPE_CAP_TGSI_TEX_TXF_LZ:
281 case PIPE_CAP_TGSI_CLOCK:
282 case PIPE_CAP_COMPUTE:
283 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
284 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
285 case PIPE_CAP_QUERY_SO_OVERFLOW:
286 case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
287 case PIPE_CAP_TGSI_DIV:
288 case PIPE_CAP_TGSI_ATOMINC_WRAP:
289 case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
290 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
291 case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
292 case PIPE_CAP_FLATSHADE:
293 case PIPE_CAP_ALPHA_TEST:
294 case PIPE_CAP_POINT_SIZE_FIXED:
295 case PIPE_CAP_TWO_SIDED_COLOR:
296 case PIPE_CAP_CLIP_PLANES:
297 case PIPE_CAP_TEXTURE_SHADOW_LOD:
298 case PIPE_CAP_PACKED_STREAM_OUTPUT:
299 case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES:
300 return 1;
301 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
302 return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
303 case PIPE_CAP_FBFETCH:
304 return class_3d >= NVE4_3D_CLASS ? 1 : 0; /* needs testing on fermi */
305 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
306 case PIPE_CAP_TGSI_BALLOT:
307 return class_3d >= NVE4_3D_CLASS;
308 case PIPE_CAP_BINDLESS_TEXTURE:
309 return class_3d >= NVE4_3D_CLASS;
310 case PIPE_CAP_TGSI_ATOMFADD:
311 return class_3d < GM107_3D_CLASS; /* needs additional lowering */
312 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
313 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
314 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
315 case PIPE_CAP_POST_DEPTH_COVERAGE:
316 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
317 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
318 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
319 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
320 case PIPE_CAP_VIEWPORT_SWIZZLE:
321 case PIPE_CAP_VIEWPORT_MASK:
322 return class_3d >= GM200_3D_CLASS;
323 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
324 return class_3d >= GP100_3D_CLASS;
325
326 /* caps has to be turned on with nir */
327 case PIPE_CAP_GL_SPIRV:
328 case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS:
329 case PIPE_CAP_INT64_DIVMOD:
330 return screen->prefer_nir ? 1 : 0;
331
332 /* nir related caps */
333 case PIPE_CAP_NIR_IMAGES_AS_DEREF:
334 return 0;
335
336 /* unsupported caps */
337 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
338 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
339 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
340 case PIPE_CAP_SHADER_STENCIL_EXPORT:
341 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
342 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
343 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
344 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
345 case PIPE_CAP_FAKE_SW_MSAA:
346 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
347 case PIPE_CAP_VERTEXID_NOBASE:
348 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
349 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
350 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
351 case PIPE_CAP_GENERATE_MIPMAP:
352 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
353 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
354 case PIPE_CAP_QUERY_MEMORY_INFO:
355 case PIPE_CAP_PCI_GROUP:
356 case PIPE_CAP_PCI_BUS:
357 case PIPE_CAP_PCI_DEVICE:
358 case PIPE_CAP_PCI_FUNCTION:
359 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
360 case PIPE_CAP_NATIVE_FENCE_FD:
361 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
362 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
363 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
364 case PIPE_CAP_MEMOBJ:
365 case PIPE_CAP_LOAD_CONSTBUF:
366 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
367 case PIPE_CAP_TILE_RASTER_ORDER:
368 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
369 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
370 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
371 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
372 case PIPE_CAP_FENCE_SIGNAL:
373 case PIPE_CAP_CONSTBUF0_FLAGS:
374 case PIPE_CAP_PACKED_UNIFORMS:
375 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
376 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
377 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
378 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
379 case PIPE_CAP_SURFACE_SAMPLE_COUNT:
380 case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
381 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
382 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
383 case PIPE_CAP_NIR_COMPACT_ARRAYS:
384 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
385 case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
386 case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
387 case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
388 case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
389 case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
390 case PIPE_CAP_FBFETCH_COHERENT:
391 case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
392 case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE:
393 case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS: /* could be done */
394 case PIPE_CAP_INTEGER_MULTIPLY_32X16: /* could be done */
395 case PIPE_CAP_FRONTEND_NOOP:
396 case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
397 case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
398 case PIPE_CAP_PSIZ_CLAMPED:
399 return 0;
400
401 case PIPE_CAP_VENDOR_ID:
402 return 0x10de;
403 case PIPE_CAP_DEVICE_ID: {
404 uint64_t device_id;
405 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
406 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
407 return -1;
408 }
409 return device_id;
410 }
411 case PIPE_CAP_ACCELERATED:
412 return 1;
413 case PIPE_CAP_VIDEO_MEMORY:
414 return dev->vram_size >> 20;
415 case PIPE_CAP_UMA:
416 return 0;
417
418 default:
419 debug_printf("%s: unhandled cap %d\n", __func__, param);
420 /* fallthrough */
421 /* caps where we want the default value */
422 case PIPE_CAP_DMABUF:
423 case PIPE_CAP_ESSL_FEATURE_LEVEL:
424 case PIPE_CAP_THROTTLE:
425 return u_pipe_screen_get_param_defaults(pscreen, param);
426 }
427 }
428
429 static int
430 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
431 enum pipe_shader_type shader,
432 enum pipe_shader_cap param)
433 {
434 const struct nouveau_screen *screen = nouveau_screen(pscreen);
435 const uint16_t class_3d = screen->class_3d;
436
437 switch (shader) {
438 case PIPE_SHADER_VERTEX:
439 case PIPE_SHADER_GEOMETRY:
440 case PIPE_SHADER_FRAGMENT:
441 case PIPE_SHADER_COMPUTE:
442 case PIPE_SHADER_TESS_CTRL:
443 case PIPE_SHADER_TESS_EVAL:
444 break;
445 default:
446 return 0;
447 }
448
449 switch (param) {
450 case PIPE_SHADER_CAP_PREFERRED_IR:
451 return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
452 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
453 uint32_t irs = 1 << PIPE_SHADER_IR_NIR |
454 ((class_3d >= GV100_3D_CLASS) ? 0 : 1 << PIPE_SHADER_IR_TGSI);
455 if (screen->force_enable_cl)
456 irs |= 1 << PIPE_SHADER_IR_NIR_SERIALIZED;
457 return irs;
458 }
459 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
460 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
461 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
462 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
463 return 16384;
464 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
465 return 16;
466 case PIPE_SHADER_CAP_MAX_INPUTS:
467 return 0x200 / 16;
468 case PIPE_SHADER_CAP_MAX_OUTPUTS:
469 return 32;
470 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
471 return NVC0_MAX_CONSTBUF_SIZE;
472 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
473 return NVC0_MAX_PIPE_CONSTBUFS;
474 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
475 return shader != PIPE_SHADER_FRAGMENT;
476 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
477 /* HW doesn't support indirect addressing of fragment program inputs
478 * on Volta. The binary driver generates a function to handle every
479 * possible indirection, and indirectly calls the function to handle
480 * this instead.
481 */
482 if (class_3d >= GV100_3D_CLASS)
483 return shader != PIPE_SHADER_FRAGMENT;
484 return 1;
485 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
486 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
487 return 1;
488 case PIPE_SHADER_CAP_MAX_TEMPS:
489 return NVC0_CAP_MAX_PROGRAM_TEMPS;
490 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
491 return 1;
492 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
493 return 1;
494 case PIPE_SHADER_CAP_SUBROUTINES:
495 return 1;
496 case PIPE_SHADER_CAP_INTEGERS:
497 return 1;
498 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
499 return 1;
500 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
501 return 1;
502 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
503 return 1;
504 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
505 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
506 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
507 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
508 case PIPE_SHADER_CAP_INT64_ATOMICS:
509 case PIPE_SHADER_CAP_FP16:
510 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
511 case PIPE_SHADER_CAP_INT16:
512 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
513 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
514 return 0;
515 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
516 return NVC0_MAX_BUFFERS;
517 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
518 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
519 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
520 return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
521 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
522 return 32;
523 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
524 if (class_3d >= NVE4_3D_CLASS)
525 return NVC0_MAX_IMAGES;
526 if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
527 return NVC0_MAX_IMAGES;
528 return 0;
529 default:
530 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
531 return 0;
532 }
533 }
534
535 static float
536 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
537 {
538 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
539
540 switch (param) {
541 case PIPE_CAPF_MAX_LINE_WIDTH:
542 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
543 return 10.0f;
544 case PIPE_CAPF_MAX_POINT_WIDTH:
545 return 63.0f;
546 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
547 return 63.375f;
548 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
549 return 16.0f;
550 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
551 return 15.0f;
552 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
553 return 0.0f;
554 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
555 return class_3d >= GM200_3D_CLASS ? 0.75f : 0.0f;
556 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
557 return class_3d >= GM200_3D_CLASS ? 0.25f : 0.0f;
558 }
559
560 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
561 return 0.0f;
562 }
563
564 static int
565 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
566 enum pipe_shader_ir ir_type,
567 enum pipe_compute_cap param, void *data)
568 {
569 struct nvc0_screen *screen = nvc0_screen(pscreen);
570 const uint16_t obj_class = screen->compute->oclass;
571
572 #define RET(x) do { \
573 if (data) \
574 memcpy(data, x, sizeof(x)); \
575 return sizeof(x); \
576 } while (0)
577
578 switch (param) {
579 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
580 RET((uint64_t []) { 3 });
581 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
582 if (obj_class >= NVE4_COMPUTE_CLASS) {
583 RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
584 } else {
585 RET(((uint64_t []) { 65535, 65535, 65535 }));
586 }
587 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
588 RET(((uint64_t []) { 1024, 1024, 64 }));
589 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
590 RET((uint64_t []) { 1024 });
591 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
592 if (obj_class >= NVE4_COMPUTE_CLASS) {
593 RET((uint64_t []) { 1024 });
594 } else {
595 RET((uint64_t []) { 512 });
596 }
597 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
598 RET((uint64_t []) { 1ULL << 40 });
599 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
600 switch (obj_class) {
601 case GM200_COMPUTE_CLASS:
602 RET((uint64_t []) { 96 << 10 });
603 break;
604 case GM107_COMPUTE_CLASS:
605 RET((uint64_t []) { 64 << 10 });
606 break;
607 default:
608 RET((uint64_t []) { 48 << 10 });
609 break;
610 }
611 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
612 RET((uint64_t []) { 512 << 10 });
613 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
614 RET((uint64_t []) { 4096 });
615 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
616 RET((uint32_t []) { 32 });
617 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
618 RET((uint64_t []) { 1ULL << 40 });
619 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
620 RET((uint32_t []) { 0 });
621 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
622 RET((uint32_t []) { screen->mp_count_compute });
623 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
624 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
625 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
626 RET((uint32_t []) { 64 });
627 default:
628 return 0;
629 }
630
631 #undef RET
632 }
633
634 static void
635 nvc0_screen_get_sample_pixel_grid(struct pipe_screen *pscreen,
636 unsigned sample_count,
637 unsigned *width, unsigned *height)
638 {
639 switch (sample_count) {
640 case 0:
641 case 1:
642 /* this could be 4x4, but the GL state tracker makes it difficult to
643 * create a 1x MSAA texture and smaller grids save CB space */
644 *width = 2;
645 *height = 4;
646 break;
647 case 2:
648 *width = 2;
649 *height = 4;
650 break;
651 case 4:
652 *width = 2;
653 *height = 2;
654 break;
655 case 8:
656 *width = 1;
657 *height = 2;
658 break;
659 default:
660 assert(0);
661 }
662 }
663
664 static void
665 nvc0_screen_destroy(struct pipe_screen *pscreen)
666 {
667 struct nvc0_screen *screen = nvc0_screen(pscreen);
668
669 if (!nouveau_drm_screen_unref(&screen->base))
670 return;
671
672 if (screen->base.fence.current) {
673 struct nouveau_fence *current = NULL;
674
675 /* nouveau_fence_wait will create a new current fence, so wait on the
676 * _current_ one, and remove both.
677 */
678 nouveau_fence_ref(screen->base.fence.current, &current);
679 nouveau_fence_wait(current, NULL);
680 nouveau_fence_ref(NULL, &current);
681 nouveau_fence_ref(NULL, &screen->base.fence.current);
682 }
683 if (screen->base.pushbuf)
684 screen->base.pushbuf->user_priv = NULL;
685
686 if (screen->blitter)
687 nvc0_blitter_destroy(screen);
688 if (screen->pm.prog) {
689 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
690 nvc0_program_destroy(NULL, screen->pm.prog);
691 FREE(screen->pm.prog);
692 }
693
694 nouveau_bo_ref(NULL, &screen->text);
695 nouveau_bo_ref(NULL, &screen->uniform_bo);
696 nouveau_bo_ref(NULL, &screen->tls);
697 nouveau_bo_ref(NULL, &screen->txc);
698 nouveau_bo_ref(NULL, &screen->fence.bo);
699 nouveau_bo_ref(NULL, &screen->poly_cache);
700
701 nouveau_heap_destroy(&screen->lib_code);
702 nouveau_heap_destroy(&screen->text_heap);
703
704 FREE(screen->tic.entries);
705
706 nouveau_object_del(&screen->eng3d);
707 nouveau_object_del(&screen->eng2d);
708 nouveau_object_del(&screen->m2mf);
709 nouveau_object_del(&screen->compute);
710 nouveau_object_del(&screen->nvsw);
711
712 nouveau_screen_fini(&screen->base);
713
714 FREE(screen);
715 }
716
717 static int
718 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
719 unsigned size, const uint32_t *data)
720 {
721 struct nouveau_pushbuf *push = screen->base.pushbuf;
722
723 size /= 4;
724
725 assert((pos + size) <= 0x800);
726
727 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
728 PUSH_DATA (push, (m - 0x3800) / 8);
729 PUSH_DATA (push, pos);
730 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
731 PUSH_DATA (push, pos);
732 PUSH_DATAp(push, data, size);
733
734 return pos + size;
735 }
736
737 static int
738 tu102_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
739 unsigned size, const uint32_t *data)
740 {
741 struct nouveau_pushbuf *push = screen->base.pushbuf;
742
743 size /= 4;
744
745 assert((pos + size) <= 0x800);
746
747 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
748 PUSH_DATA (push, (m - 0x3800) / 8);
749 PUSH_DATA (push, pos);
750 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
751 PUSH_DATA (push, pos);
752 PUSH_DATAp(push, data, size);
753
754 return pos + (size / 3);
755 }
756
757 static void
758 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
759 {
760 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
761 PUSH_DATA (push, 0xff);
762 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
763 PUSH_DATA (push, 0xff);
764 PUSH_DATA (push, 0xff);
765 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
766 PUSH_DATA (push, 0xff);
767 PUSH_DATA (push, 0xff);
768 if (obj_class < GV100_3D_CLASS) {
769 BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
770 PUSH_DATA (push, 0x3f);
771 }
772
773 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
774 PUSH_DATA (push, (3 << 16) | 3);
775 BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
776 PUSH_DATA (push, (2 << 16) | 2);
777
778 if (obj_class < GM107_3D_CLASS) {
779 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
780 PUSH_DATA (push, 0);
781 }
782 BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
783 PUSH_DATA (push, 0x10);
784 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
785 PUSH_DATA (push, 0x10);
786 BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
787 PUSH_DATA (push, 0x10);
788 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
789 PUSH_DATA (push, 0x10);
790 PUSH_DATA (push, 0x10);
791 BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
792 PUSH_DATA (push, 0x10);
793 BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
794 PUSH_DATA (push, 0xe);
795
796 BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
797 PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
798 BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
799 PUSH_DATA (push, 0);
800 BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
801 PUSH_DATA (push, 3);
802
803 if (obj_class < GV100_3D_CLASS) {
804 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
805 PUSH_DATA (push, 0x3fffff);
806 }
807 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
808 PUSH_DATA (push, 1);
809 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
810 PUSH_DATA (push, 1);
811
812 if (obj_class < GM107_3D_CLASS) {
813 BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
814 PUSH_DATA (push, 3);
815
816 if (obj_class >= NVE4_3D_CLASS) {
817 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
818 PUSH_DATA (push, 1);
819 }
820 }
821
822 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
823 * are supposed to do */
824 }
825
826 static void
827 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
828 {
829 struct nvc0_screen *screen = nvc0_screen(pscreen);
830 struct nouveau_pushbuf *push = screen->base.pushbuf;
831
832 /* we need to do it after possible flush in MARK_RING */
833 *sequence = ++screen->base.fence.sequence;
834
835 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
836 PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
837 PUSH_DATAh(push, screen->fence.bo->offset);
838 PUSH_DATA (push, screen->fence.bo->offset);
839 PUSH_DATA (push, *sequence);
840 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
841 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
842 }
843
844 static u32
845 nvc0_screen_fence_update(struct pipe_screen *pscreen)
846 {
847 struct nvc0_screen *screen = nvc0_screen(pscreen);
848 return screen->fence.map[0];
849 }
850
851 static int
852 nvc0_screen_init_compute(struct nvc0_screen *screen)
853 {
854 screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
855
856 switch (screen->base.device->chipset & ~0xf) {
857 case 0xc0:
858 case 0xd0:
859 return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
860 case 0xe0:
861 case 0xf0:
862 case 0x100:
863 case 0x110:
864 case 0x120:
865 case 0x130:
866 case 0x140:
867 case 0x160:
868 return nve4_screen_compute_setup(screen, screen->base.pushbuf);
869 default:
870 return -1;
871 }
872 }
873
874 static int
875 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
876 uint32_t lpos, uint32_t lneg, uint32_t cstack)
877 {
878 struct nouveau_bo *bo = NULL;
879 int ret;
880 uint64_t size = (lpos + lneg) * 32 + cstack;
881
882 if (size >= (1 << 20)) {
883 NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
884 return -1;
885 }
886
887 size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
888 size = align(size, 0x8000);
889 size *= screen->mp_count;
890
891 size = align(size, 1 << 17);
892
893 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
894 NULL, &bo);
895 if (ret)
896 return ret;
897
898 /* Make sure that the pushbuf has acquired a reference to the old tls
899 * segment, as it may have commands that will reference it.
900 */
901 if (screen->tls)
902 PUSH_REFN(screen->base.pushbuf, screen->tls,
903 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
904 nouveau_bo_ref(NULL, &screen->tls);
905 screen->tls = bo;
906 return 0;
907 }
908
909 int
910 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
911 {
912 struct nouveau_pushbuf *push = screen->base.pushbuf;
913 struct nouveau_bo *bo;
914 int ret;
915
916 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
917 1 << 17, size, NULL, &bo);
918 if (ret)
919 return ret;
920
921 /* Make sure that the pushbuf has acquired a reference to the old text
922 * segment, as it may have commands that will reference it.
923 */
924 if (screen->text)
925 PUSH_REFN(push, screen->text,
926 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
927 nouveau_bo_ref(NULL, &screen->text);
928 screen->text = bo;
929
930 nouveau_heap_destroy(&screen->lib_code);
931 nouveau_heap_destroy(&screen->text_heap);
932
933 /* XXX: getting a page fault at the end of the code buffer every few
934 * launches, don't use the last 256 bytes to work around them - prefetch ?
935 */
936 nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
937
938 /* update the code segment setup */
939 if (screen->eng3d->oclass < GV100_3D_CLASS) {
940 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
941 PUSH_DATAh(push, screen->text->offset);
942 PUSH_DATA (push, screen->text->offset);
943 if (screen->compute) {
944 BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
945 PUSH_DATAh(push, screen->text->offset);
946 PUSH_DATA (push, screen->text->offset);
947 }
948 }
949
950 return 0;
951 }
952
953 void
954 nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
955 int stage, int index, int size, uint64_t addr)
956 {
957 assert(stage != 5);
958
959 struct nouveau_pushbuf *push = screen->base.pushbuf;
960
961 if (screen->base.class_3d >= GM107_3D_CLASS) {
962 struct nvc0_cb_binding *binding = &screen->cb_bindings[stage][index];
963
964 // TODO: Better figure out the conditions in which this is needed
965 bool serialize = binding->addr == addr && binding->size != size;
966 if (can_serialize)
967 serialize = serialize && *can_serialize;
968 if (serialize) {
969 IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
970 if (can_serialize)
971 *can_serialize = false;
972 }
973
974 binding->addr = addr;
975 binding->size = size;
976 }
977
978 if (size >= 0) {
979 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
980 PUSH_DATA (push, size);
981 PUSH_DATAh(push, addr);
982 PUSH_DATA (push, addr);
983 }
984 IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
985 }
986
987 static const void *
988 nvc0_screen_get_compiler_options(struct pipe_screen *pscreen,
989 enum pipe_shader_ir ir,
990 enum pipe_shader_type shader)
991 {
992 struct nvc0_screen *screen = nvc0_screen(pscreen);
993 if (ir == PIPE_SHADER_IR_NIR)
994 return nv50_ir_nir_shader_compiler_options(screen->base.device->chipset);
995 return NULL;
996 }
997
998 #define FAIL_SCREEN_INIT(str, err) \
999 do { \
1000 NOUVEAU_ERR(str, err); \
1001 goto fail; \
1002 } while(0)
1003
1004 struct nouveau_screen *
1005 nvc0_screen_create(struct nouveau_device *dev)
1006 {
1007 struct nvc0_screen *screen;
1008 struct pipe_screen *pscreen;
1009 struct nouveau_object *chan;
1010 struct nouveau_pushbuf *push;
1011 uint64_t value;
1012 uint32_t obj_class;
1013 uint32_t flags;
1014 int ret;
1015 unsigned i;
1016
1017 switch (dev->chipset & ~0xf) {
1018 case 0xc0:
1019 case 0xd0:
1020 case 0xe0:
1021 case 0xf0:
1022 case 0x100:
1023 case 0x110:
1024 case 0x120:
1025 case 0x130:
1026 case 0x140:
1027 case 0x160:
1028 break;
1029 default:
1030 return NULL;
1031 }
1032
1033 screen = CALLOC_STRUCT(nvc0_screen);
1034 if (!screen)
1035 return NULL;
1036 pscreen = &screen->base.base;
1037 pscreen->destroy = nvc0_screen_destroy;
1038
1039 ret = nouveau_screen_init(&screen->base, dev);
1040 if (ret)
1041 FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
1042 chan = screen->base.channel;
1043 push = screen->base.pushbuf;
1044 push->user_priv = screen;
1045 push->rsvd_kick = 5;
1046
1047 /* TODO: could this be higher on Kepler+? how does reclocking vs no
1048 * reclocking affect performance?
1049 * TODO: could this be higher on Fermi?
1050 */
1051 if (dev->chipset >= 0xe0)
1052 screen->base.transfer_pushbuf_threshold = 1024;
1053
1054 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
1055 PIPE_BIND_SHADER_BUFFER |
1056 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
1057 PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
1058 screen->base.sysmem_bindings |=
1059 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
1060
1061 if (screen->base.vram_domain & NOUVEAU_BO_GART) {
1062 screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
1063 screen->base.vidmem_bindings = 0;
1064 }
1065
1066 pscreen->context_create = nvc0_create;
1067 pscreen->is_format_supported = nvc0_screen_is_format_supported;
1068 pscreen->get_param = nvc0_screen_get_param;
1069 pscreen->get_shader_param = nvc0_screen_get_shader_param;
1070 pscreen->get_paramf = nvc0_screen_get_paramf;
1071 pscreen->get_sample_pixel_grid = nvc0_screen_get_sample_pixel_grid;
1072 pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
1073 pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
1074 /* nir stuff */
1075 pscreen->get_compiler_options = nvc0_screen_get_compiler_options;
1076
1077 nvc0_screen_init_resource_functions(pscreen);
1078
1079 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
1080 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
1081
1082 flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
1083 if (screen->base.drm->version >= 0x01000202)
1084 flags |= NOUVEAU_BO_COHERENT;
1085
1086 ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
1087 if (ret)
1088 FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
1089 nouveau_bo_map(screen->fence.bo, 0, NULL);
1090 screen->fence.map = screen->fence.bo->map;
1091 screen->base.fence.emit = nvc0_screen_fence_emit;
1092 screen->base.fence.update = nvc0_screen_fence_update;
1093
1094 if (dev->chipset < 0x140) {
1095 ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
1096 NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
1097 if (ret)
1098 FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
1099
1100 BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
1101 PUSH_DATA (push, screen->nvsw->handle);
1102 }
1103
1104 switch (dev->chipset & ~0xf) {
1105 case 0x160:
1106 case 0x140:
1107 case 0x130:
1108 case 0x120:
1109 case 0x110:
1110 case 0x100:
1111 case 0xf0:
1112 obj_class = NVF0_P2MF_CLASS;
1113 break;
1114 case 0xe0:
1115 obj_class = NVE4_P2MF_CLASS;
1116 break;
1117 default:
1118 obj_class = NVC0_M2MF_CLASS;
1119 break;
1120 }
1121 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
1122 &screen->m2mf);
1123 if (ret)
1124 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
1125
1126 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
1127 PUSH_DATA (push, screen->m2mf->oclass);
1128 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
1129 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
1130 PUSH_DATA (push, 0xa0b5);
1131 }
1132
1133 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
1134 &screen->eng2d);
1135 if (ret)
1136 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
1137
1138 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
1139 PUSH_DATA (push, screen->eng2d->oclass);
1140 BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
1141 PUSH_DATA (push, 0);
1142 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
1143 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
1144 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
1145 PUSH_DATA (push, 0);
1146 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
1147 PUSH_DATA (push, 0);
1148 BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
1149 PUSH_DATA (push, 0x3f);
1150 BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
1151 PUSH_DATA (push, 1);
1152 BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
1153 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
1154
1155 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
1156 PUSH_DATAh(push, screen->fence.bo->offset + 16);
1157 PUSH_DATA (push, screen->fence.bo->offset + 16);
1158
1159 switch (dev->chipset & ~0xf) {
1160 case 0x160:
1161 obj_class = TU102_3D_CLASS;
1162 break;
1163 case 0x140:
1164 obj_class = GV100_3D_CLASS;
1165 break;
1166 case 0x130:
1167 switch (dev->chipset) {
1168 case 0x130:
1169 case 0x13b:
1170 obj_class = GP100_3D_CLASS;
1171 break;
1172 default:
1173 obj_class = GP102_3D_CLASS;
1174 break;
1175 }
1176 break;
1177 case 0x120:
1178 obj_class = GM200_3D_CLASS;
1179 break;
1180 case 0x110:
1181 obj_class = GM107_3D_CLASS;
1182 break;
1183 case 0x100:
1184 case 0xf0:
1185 obj_class = NVF0_3D_CLASS;
1186 break;
1187 case 0xe0:
1188 switch (dev->chipset) {
1189 case 0xea:
1190 obj_class = NVEA_3D_CLASS;
1191 break;
1192 default:
1193 obj_class = NVE4_3D_CLASS;
1194 break;
1195 }
1196 break;
1197 case 0xd0:
1198 obj_class = NVC8_3D_CLASS;
1199 break;
1200 case 0xc0:
1201 default:
1202 switch (dev->chipset) {
1203 case 0xc8:
1204 obj_class = NVC8_3D_CLASS;
1205 break;
1206 case 0xc1:
1207 obj_class = NVC1_3D_CLASS;
1208 break;
1209 default:
1210 obj_class = NVC0_3D_CLASS;
1211 break;
1212 }
1213 break;
1214 }
1215 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
1216 &screen->eng3d);
1217 if (ret)
1218 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
1219 screen->base.class_3d = obj_class;
1220
1221 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
1222 PUSH_DATA (push, screen->eng3d->oclass);
1223
1224 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
1225 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
1226
1227 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
1228 /* kill shaders after about 1 second (at 100 MHz) */
1229 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
1230 PUSH_DATA (push, 0x17);
1231 }
1232
1233 IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1234 screen->base.drm->version >= 0x01000101);
1235 BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1236 for (i = 0; i < 8; ++i)
1237 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1238
1239 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1240 PUSH_DATA (push, 1);
1241
1242 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1243 PUSH_DATA (push, 0);
1244 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1245 PUSH_DATA (push, 0);
1246 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1247 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1248 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1249 PUSH_DATA (push, 0);
1250 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1251 PUSH_DATA (push, 1);
1252 BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1253 PUSH_DATA (push, 1);
1254 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1255 PUSH_DATA (push, 1);
1256 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1257 PUSH_DATA (push, 0);
1258 BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1259 PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1260 if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1261 IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1262 } else {
1263 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1264 PUSH_DATA (push, 15);
1265 }
1266 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1267 PUSH_DATA (push, 8); /* 128 */
1268 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1269 PUSH_DATA (push, 1);
1270 if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1271 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1272 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1273 }
1274
1275 nvc0_magic_3d_init(push, screen->eng3d->oclass);
1276
1277 ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1278 if (ret)
1279 FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1280
1281 /* 6 user uniform areas, 6 driver areas, and 1 for the runout */
1282 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1283 &screen->uniform_bo);
1284 if (ret)
1285 FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1286
1287 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1288
1289 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1290 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1291 PUSH_DATA (push, 256);
1292 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1293 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1294 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1295 PUSH_DATA (push, 0);
1296 PUSH_DATAf(push, 0.0f);
1297 PUSH_DATAf(push, 0.0f);
1298 PUSH_DATAf(push, 0.0f);
1299 PUSH_DATAf(push, 0.0f);
1300 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1301 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1302 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1303
1304 if (screen->base.drm->version >= 0x01000101) {
1305 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1306 if (ret)
1307 FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1308 } else {
1309 if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1310 value = (8 << 8) | 4;
1311 else
1312 value = (16 << 8) | 4;
1313 }
1314 screen->gpc_count = value & 0x000000ff;
1315 screen->mp_count = value >> 8;
1316 screen->mp_count_compute = screen->mp_count;
1317
1318 ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1319 if (ret)
1320 FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1321
1322 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1323 PUSH_DATAh(push, screen->tls->offset);
1324 PUSH_DATA (push, screen->tls->offset);
1325 PUSH_DATA (push, screen->tls->size >> 32);
1326 PUSH_DATA (push, screen->tls->size);
1327 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1328 PUSH_DATA (push, 0);
1329 /* Reduce likelihood of collision with real buffers by placing the hole at
1330 * the top of the 4G area. This will have to be dealt with for real
1331 * eventually by blocking off that area from the VM.
1332 */
1333 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1334 PUSH_DATA (push, 0xff << 24);
1335
1336 if (screen->eng3d->oclass < GM107_3D_CLASS) {
1337 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1338 &screen->poly_cache);
1339 if (ret)
1340 FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1341
1342 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1343 PUSH_DATAh(push, screen->poly_cache->offset);
1344 PUSH_DATA (push, screen->poly_cache->offset);
1345 PUSH_DATA (push, 3);
1346 }
1347
1348 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1349 &screen->txc);
1350 if (ret)
1351 FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1352
1353 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1354 PUSH_DATAh(push, screen->txc->offset);
1355 PUSH_DATA (push, screen->txc->offset);
1356 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1357 if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1358 screen->tic.maxwell = true;
1359 if (screen->eng3d->oclass == GM107_3D_CLASS) {
1360 screen->tic.maxwell =
1361 debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1362 IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1363 }
1364 }
1365
1366 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1367 PUSH_DATAh(push, screen->txc->offset + 65536);
1368 PUSH_DATA (push, screen->txc->offset + 65536);
1369 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1370
1371 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1372 PUSH_DATA (push, 0);
1373 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1374 PUSH_DATA (push, 0);
1375 PUSH_DATA (push, 0);
1376 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1377 PUSH_DATA (push, 0x3f);
1378
1379 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1380 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1381 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1382 for (i = 0; i < 8 * 2; ++i)
1383 PUSH_DATA(push, 0);
1384 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1385 PUSH_DATA (push, 0);
1386 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1387 PUSH_DATA (push, 0);
1388
1389 /* neither scissors, viewport nor stencil mask should affect clears */
1390 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1391 PUSH_DATA (push, 0);
1392
1393 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1394 PUSH_DATA (push, 1);
1395 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1396 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1397 PUSH_DATAf(push, 0.0f);
1398 PUSH_DATAf(push, 1.0f);
1399 }
1400 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1401 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1402
1403 /* We use scissors instead of exact view volume clipping,
1404 * so they're always enabled.
1405 */
1406 for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1407 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1408 PUSH_DATA (push, 1);
1409 PUSH_DATA (push, 16384 << 16);
1410 PUSH_DATA (push, 16384 << 16);
1411 }
1412
1413 if (screen->eng3d->oclass < TU102_3D_CLASS) {
1414 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1415
1416 i = 0;
1417 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1418 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1419 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1420 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1421 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1422 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1423 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1424 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1425 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1426 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1427 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1428 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1429 MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
1430 MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mme9097_compute_counter);
1431 MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mme9097_compute_counter_to_query);
1432 MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1433 } else {
1434 #undef MK_MACRO
1435 #define MK_MACRO(m, n) i = tu102_graph_set_macro(screen, m, i, sizeof(n), n);
1436
1437 i = 0;
1438 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mmec597_per_instance_bf);
1439 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mmec597_blend_enables);
1440 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mmec597_vertex_array_select);
1441 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mmec597_tep_select);
1442 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mmec597_gp_select);
1443 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mmec597_poly_mode_front);
1444 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mmec597_poly_mode_back);
1445 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mmec597_draw_arrays_indirect);
1446 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mmec597_draw_elts_indirect);
1447 MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mmec597_draw_arrays_indirect_count);
1448 MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mmec597_draw_elts_indirect_count);
1449 MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mmec597_query_buffer_write);
1450 MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mmec597_conservative_raster_state);
1451 MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mmec597_compute_counter);
1452 MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mmec597_compute_counter_to_query);
1453 }
1454
1455 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1456 PUSH_DATA (push, 1);
1457 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1458 PUSH_DATA (push, 1);
1459 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1460 PUSH_DATA (push, 0x40);
1461 BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1462 PUSH_DATA (push, 0);
1463 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1464 PUSH_DATA (push, 0x30);
1465 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1466 PUSH_DATA (push, 3);
1467 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1468 PUSH_DATA (push, 0x20);
1469 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1470 PUSH_DATA (push, 0x00);
1471 screen->save_state.patch_vertices = 3;
1472
1473 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1474 PUSH_DATA (push, 0);
1475 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1476 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1477
1478 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1479
1480 if (nvc0_screen_init_compute(screen))
1481 goto fail;
1482
1483 /* XXX: Compute and 3D are somehow aliased on Fermi. */
1484 for (i = 0; i < 5; ++i) {
1485 unsigned j = 0;
1486 for (j = 0; j < 16; j++)
1487 screen->cb_bindings[i][j].size = -1;
1488
1489 /* TIC and TSC entries for each unit (nve4+ only) */
1490 /* auxiliary constants (6 user clip planes, base instance id) */
1491 nvc0_screen_bind_cb_3d(screen, NULL, i, 15, NVC0_CB_AUX_SIZE,
1492 screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1493 if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1494 unsigned j;
1495 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1496 PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1497 for (j = 0; j < 8; ++j)
1498 PUSH_DATA(push, j);
1499 } else {
1500 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1501 PUSH_DATA (push, 0x54);
1502 }
1503
1504 /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1505 BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1506 PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1507 PUSH_DATA (push, 0); /* 0 */
1508 PUSH_DATA (push, 0);
1509 PUSH_DATA (push, 1); /* 1 */
1510 PUSH_DATA (push, 0);
1511 PUSH_DATA (push, 0); /* 2 */
1512 PUSH_DATA (push, 1);
1513 PUSH_DATA (push, 1); /* 3 */
1514 PUSH_DATA (push, 1);
1515 PUSH_DATA (push, 2); /* 4 */
1516 PUSH_DATA (push, 0);
1517 PUSH_DATA (push, 3); /* 5 */
1518 PUSH_DATA (push, 0);
1519 PUSH_DATA (push, 2); /* 6 */
1520 PUSH_DATA (push, 1);
1521 PUSH_DATA (push, 3); /* 7 */
1522 PUSH_DATA (push, 1);
1523 }
1524 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1525 PUSH_DATA (push, 0);
1526
1527 PUSH_KICK (push);
1528
1529 screen->tic.entries = CALLOC(
1530 NVC0_TIC_MAX_ENTRIES + NVC0_TSC_MAX_ENTRIES + NVE4_IMG_MAX_HANDLES,
1531 sizeof(void *));
1532 screen->tsc.entries = screen->tic.entries + NVC0_TIC_MAX_ENTRIES;
1533 screen->img.entries = (void *)(screen->tsc.entries + NVC0_TSC_MAX_ENTRIES);
1534
1535 if (!nvc0_blitter_create(screen))
1536 goto fail;
1537
1538 nouveau_fence_new(&screen->base, &screen->base.fence.current);
1539
1540 return &screen->base;
1541
1542 fail:
1543 screen->base.base.context_create = NULL;
1544 return &screen->base;
1545 }
1546
1547 int
1548 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1549 {
1550 int i = screen->tic.next;
1551
1552 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1553 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1554
1555 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1556
1557 if (screen->tic.entries[i])
1558 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1559
1560 screen->tic.entries[i] = entry;
1561 return i;
1562 }
1563
1564 int
1565 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1566 {
1567 int i = screen->tsc.next;
1568
1569 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1570 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1571
1572 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1573
1574 if (screen->tsc.entries[i])
1575 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1576
1577 screen->tsc.entries[i] = entry;
1578 return i;
1579 }