src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "nouveau_vp3_video.h"
  31
  32 #include "nvc0/nvc0_context.h"
  33 #include "nvc0/nvc0_screen.h"
  34
  35 #include "nvc0/mme/com9097.mme.h"
  36 #include "nvc0/mme/com90c0.mme.h"
  37
  38 #include "nv50/g80_texture.xml.h"
  39
  40 static boolean
  41 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  42                                 enum pipe_format format,
  43                                 enum pipe_texture_target target,
  44                                 unsigned sample_count,
  45                                 unsigned bindings)
  46 {
  47    const struct util_format_description *desc = util_format_description(format);
  48
  49    if (sample_count > 8)
  50       return false;
  51    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  52       return false;
  53
  54    /* Short-circuit the rest of the logic -- this is used by the state tracker
  55     * to determine valid MS levels in a no-attachments scenario.
  56     */
  57    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  58       return true;
  59
  60    if (!util_format_is_supported(format, bindings))
  61       return false;
  62
  63    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  64       if (util_format_get_blocksizebits(format) == 3 * 32)
  65          return false;
  66
  67    if (bindings & PIPE_BIND_LINEAR)
  68       if (util_format_is_depth_or_stencil(format) ||
  69           (target != PIPE_TEXTURE_1D &&
  70            target != PIPE_TEXTURE_2D &&
  71            target != PIPE_TEXTURE_RECT) ||
  72           sample_count > 1)
  73          return false;
  74
  75    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  76     */
  77    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  78         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  79        /* The claim is that this should work on GM107 but it doesn't. Need to
  80         * test further and figure out if it's a nouveau issue or a HW one.
  81        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  82         */
  83        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  84       return false;
  85
  86    /* shared is always supported */
  87    bindings &= ~(PIPE_BIND_LINEAR |
  88                  PIPE_BIND_SHARED);
  89
  90    if (bindings & PIPE_BIND_SHADER_IMAGE) {
  91       if (sample_count > 1 &&
  92           nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
  93          /* MS images are currently unsupported on Maxwell because they have to
  94           * be handled explicitly. */
  95          return false;
  96       }
  97
  98       if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
  99           nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
 100          /* This should work on Fermi, but for currently unknown reasons it
 101           * does not and results in breaking reads from pbos. */
 102          return false;
 103       }
 104    }
 105
 106    return (( nvc0_format_table[format].usage |
 107             nvc0_vertex_format[format].usage) & bindings) == bindings;
 108 }
 109
 110 static int
 111 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 112 {
 113    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 114    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 115
 116    switch (param) {
 117    /* non-boolean caps */
 118    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 119    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 120       return 15;
 121    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 122       return 12;
 123    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 124       return 2048;
 125    case PIPE_CAP_MIN_TEXEL_OFFSET:
 126       return -8;
 127    case PIPE_CAP_MAX_TEXEL_OFFSET:
 128       return 7;
 129    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 130       return -32;
 131    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 132       return 31;
 133    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 134       return 128 * 1024 * 1024;
 135    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 136       return 430;
 137    case PIPE_CAP_MAX_RENDER_TARGETS:
 138       return 8;
 139    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 140       return 1;
 141    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 142       return 4;
 143    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 144    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 145       return 128;
 146    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 147    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 148       return 1024;
 149    case PIPE_CAP_MAX_VERTEX_STREAMS:
 150       return 4;
 151    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 152       return 2048;
 153    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 154       return 256;
 155    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 156       if (class_3d < GM107_3D_CLASS)
 157          return 256; /* IMAGE bindings require alignment to 256 */
 158       return 16;
 159    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 160       return 16;
 161    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 162       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 163    case PIPE_CAP_MAX_VIEWPORTS:
 164       return NVC0_MAX_VIEWPORTS;
 165    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 166       return 4;
 167    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 168       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 169    case PIPE_CAP_ENDIANNESS:
 170       return PIPE_ENDIAN_LITTLE;
 171    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 172       return 30;
 173    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 174       return NVC0_MAX_WINDOW_RECTANGLES;
 175
 176    /* supported caps */
 177    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 178    case PIPE_CAP_TEXTURE_SWIZZLE:
 179    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 180    case PIPE_CAP_NPOT_TEXTURES:
 181    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 182    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 183    case PIPE_CAP_ANISOTROPIC_FILTER:
 184    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 185    case PIPE_CAP_CUBE_MAP_ARRAY:
 186    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 187    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 188    case PIPE_CAP_TWO_SIDED_STENCIL:
 189    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 190    case PIPE_CAP_POINT_SPRITE:
 191    case PIPE_CAP_TGSI_TEXCOORD:
 192    case PIPE_CAP_SM3:
 193    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 194    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 195    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 196    case PIPE_CAP_QUERY_TIMESTAMP:
 197    case PIPE_CAP_QUERY_TIME_ELAPSED:
 198    case PIPE_CAP_OCCLUSION_QUERY:
 199    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 200    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 201    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 202    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 203    case PIPE_CAP_INDEP_BLEND_ENABLE:
 204    case PIPE_CAP_INDEP_BLEND_FUNC:
 205    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 206    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 207    case PIPE_CAP_PRIMITIVE_RESTART:
 208    case PIPE_CAP_TGSI_INSTANCEID:
 209    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 210    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 211    case PIPE_CAP_CONDITIONAL_RENDER:
 212    case PIPE_CAP_TEXTURE_BARRIER:
 213    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 214    case PIPE_CAP_START_INSTANCE:
 215    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 216    case PIPE_CAP_DRAW_INDIRECT:
 217    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 218    case PIPE_CAP_USER_VERTEX_BUFFERS:
 219    case PIPE_CAP_TEXTURE_QUERY_LOD:
 220    case PIPE_CAP_SAMPLE_SHADING:
 221    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 222    case PIPE_CAP_TEXTURE_GATHER_SM5:
 223    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 224    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 225    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 226    case PIPE_CAP_CLIP_HALFZ:
 227    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 228    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 229    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 230    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 231    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 232    case PIPE_CAP_TGSI_TXQS:
 233    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 234    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 235    case PIPE_CAP_SHAREABLE_SHADERS:
 236    case PIPE_CAP_CLEAR_TEXTURE:
 237    case PIPE_CAP_DRAW_PARAMETERS:
 238    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 239    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 240    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 241    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 242    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 243    case PIPE_CAP_INVALIDATE_BUFFER:
 244    case PIPE_CAP_STRING_MARKER:
 245    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 246    case PIPE_CAP_CULL_DISTANCE:
 247    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 248    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 249    case PIPE_CAP_TGSI_VOTE:
 250    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 251    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 252    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 253    case PIPE_CAP_DOUBLES:
 254    case PIPE_CAP_INT64:
 255    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 256    case PIPE_CAP_TGSI_CLOCK:
 257    case PIPE_CAP_COMPUTE:
 258    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 259    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 260       return 1;
 261    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 262       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 263    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 264       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 265    case PIPE_CAP_TGSI_FS_FBFETCH:
 266       return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
 267    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 268    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 269    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 270    case PIPE_CAP_POST_DEPTH_COVERAGE:
 271       return class_3d >= GM200_3D_CLASS;
 272    case PIPE_CAP_TGSI_BALLOT:
 273       return class_3d >= NVE4_3D_CLASS;
 274
 275    /* unsupported caps */
 276    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 277    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 278    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 279    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 280    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 281    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 282    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 283    case PIPE_CAP_FAKE_SW_MSAA:
 284    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 285    case PIPE_CAP_VERTEXID_NOBASE:
 286    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 287    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 288    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 289    case PIPE_CAP_GENERATE_MIPMAP:
 290    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 291    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 292    case PIPE_CAP_QUERY_MEMORY_INFO:
 293    case PIPE_CAP_PCI_GROUP:
 294    case PIPE_CAP_PCI_BUS:
 295    case PIPE_CAP_PCI_DEVICE:
 296    case PIPE_CAP_PCI_FUNCTION:
 297    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 298    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 299    case PIPE_CAP_NATIVE_FENCE_FD:
 300    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 301    case PIPE_CAP_INT64_DIVMOD:
 302    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 303    case PIPE_CAP_BINDLESS_TEXTURE:
 304    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 305    case PIPE_CAP_QUERY_SO_OVERFLOW:
 306    case PIPE_CAP_MEMOBJ:
 307    case PIPE_CAP_LOAD_CONSTBUF:
 308    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 309    case PIPE_CAP_TILE_RASTER_ORDER:
 310    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 311    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 312    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 313       return 0;
 314
 315    case PIPE_CAP_VENDOR_ID:
 316       return 0x10de;
 317    case PIPE_CAP_DEVICE_ID: {
 318       uint64_t device_id;
 319       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 320          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 321          return -1;
 322       }
 323       return device_id;
 324    }
 325    case PIPE_CAP_ACCELERATED:
 326       return 1;
 327    case PIPE_CAP_VIDEO_MEMORY:
 328       return dev->vram_size >> 20;
 329    case PIPE_CAP_UMA:
 330       return 0;
 331    }
 332
 333    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 334    return 0;
 335 }
 336
 337 static int
 338 nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
 339                              enum pipe_shader_type shader,
 340                              enum pipe_shader_cap param)
 341 {
 342    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 343
 344    switch (shader) {
 345    case PIPE_SHADER_VERTEX:
 346    case PIPE_SHADER_GEOMETRY:
 347    case PIPE_SHADER_FRAGMENT:
 348    case PIPE_SHADER_COMPUTE:
 349    case PIPE_SHADER_TESS_CTRL:
 350    case PIPE_SHADER_TESS_EVAL:
 351       break;
 352    default:
 353       return 0;
 354    }
 355
 356    switch (param) {
 357    case PIPE_SHADER_CAP_PREFERRED_IR:
 358       return PIPE_SHADER_IR_TGSI;
 359    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 360       return 1 << PIPE_SHADER_IR_TGSI;
 361    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 362    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 363    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 364    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 365       return 16384;
 366    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 367       return 16;
 368    case PIPE_SHADER_CAP_MAX_INPUTS:
 369       if (shader == PIPE_SHADER_VERTEX)
 370          return 32;
 371       /* NOTE: These only count our slots for GENERIC varyings.
 372        * The address space may be larger, but the actual hard limit seems to be
 373        * less than what the address space layout permits, so don't add TEXCOORD,
 374        * COLOR, etc. here.
 375        */
 376       if (shader == PIPE_SHADER_FRAGMENT)
 377          return 0x1f0 / 16;
 378       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 379        * and excludes 0x60 per-patch inputs.
 380        */
 381       return 0x200 / 16;
 382    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 383       return 32;
 384    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 385       return 65536;
 386    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 387       return NVC0_MAX_PIPE_CONSTBUFS;
 388    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 389       return shader != PIPE_SHADER_FRAGMENT;
 390    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 391    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 392    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 393       return 1;
 394    case PIPE_SHADER_CAP_MAX_TEMPS:
 395       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 396    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 397       return 1;
 398    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 399       return 1;
 400    case PIPE_SHADER_CAP_SUBROUTINES:
 401       return 1;
 402    case PIPE_SHADER_CAP_INTEGERS:
 403       return 1;
 404    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 405       return 1;
 406    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 407       return 1;
 408    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 409       return 1;
 410    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 411    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 412    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 413    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 414    case PIPE_SHADER_CAP_INT64_ATOMICS:
 415    case PIPE_SHADER_CAP_FP16:
 416    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 417    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 418       return 0;
 419    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 420       return NVC0_MAX_BUFFERS;
 421    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 422       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 423    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 424       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 425    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 426       return 32;
 427    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 428       if (class_3d >= NVE4_3D_CLASS)
 429          return NVC0_MAX_IMAGES;
 430       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 431          return NVC0_MAX_IMAGES;
 432       return 0;
 433    default:
 434       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 435       return 0;
 436    }
 437 }
 438
 439 static float
 440 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 441 {
 442    switch (param) {
 443    case PIPE_CAPF_MAX_LINE_WIDTH:
 444    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 445       return 10.0f;
 446    case PIPE_CAPF_MAX_POINT_WIDTH:
 447       return 63.0f;
 448    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 449       return 63.375f;
 450    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 451       return 16.0f;
 452    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 453       return 15.0f;
 454    case PIPE_CAPF_GUARD_BAND_LEFT:
 455    case PIPE_CAPF_GUARD_BAND_TOP:
 456       return 0.0f;
 457    case PIPE_CAPF_GUARD_BAND_RIGHT:
 458    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 459       return 0.0f; /* that or infinity */
 460    }
 461
 462    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 463    return 0.0f;
 464 }
 465
 466 static int
 467 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 468                               enum pipe_shader_ir ir_type,
 469                               enum pipe_compute_cap param, void *data)
 470 {
 471    struct nvc0_screen *screen = nvc0_screen(pscreen);
 472    const uint16_t obj_class = screen->compute->oclass;
 473
 474 #define RET(x) do {                  \
 475    if (data)                         \
 476       memcpy(data, x, sizeof(x));    \
 477    return sizeof(x);                 \
 478 } while (0)
 479
 480    switch (param) {
 481    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 482       RET((uint64_t []) { 3 });
 483    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 484       if (obj_class >= NVE4_COMPUTE_CLASS) {
 485          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 486       } else {
 487          RET(((uint64_t []) { 65535, 65535, 65535 }));
 488       }
 489    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 490       RET(((uint64_t []) { 1024, 1024, 64 }));
 491    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 492       RET((uint64_t []) { 1024 });
 493    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 494       if (obj_class >= NVE4_COMPUTE_CLASS) {
 495          RET((uint64_t []) { 1024 });
 496       } else {
 497          RET((uint64_t []) { 512 });
 498       }
 499    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 500       RET((uint64_t []) { 1ULL << 40 });
 501    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 502       switch (obj_class) {
 503       case GM200_COMPUTE_CLASS:
 504          RET((uint64_t []) { 96 << 10 });
 505          break;
 506       case GM107_COMPUTE_CLASS:
 507          RET((uint64_t []) { 64 << 10 });
 508          break;
 509       default:
 510          RET((uint64_t []) { 48 << 10 });
 511          break;
 512       }
 513    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 514       RET((uint64_t []) { 512 << 10 });
 515    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 516       RET((uint64_t []) { 4096 });
 517    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 518       RET((uint32_t []) { 32 });
 519    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 520       RET((uint64_t []) { 1ULL << 40 });
 521    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 522       RET((uint32_t []) { 0 });
 523    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 524       RET((uint32_t []) { screen->mp_count_compute });
 525    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 526       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 527    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 528       RET((uint32_t []) { 64 });
 529    default:
 530       return 0;
 531    }
 532
 533 #undef RET
 534 }
 535
 536 static void
 537 nvc0_screen_destroy(struct pipe_screen *pscreen)
 538 {
 539    struct nvc0_screen *screen = nvc0_screen(pscreen);
 540
 541    if (!nouveau_drm_screen_unref(&screen->base))
 542       return;
 543
 544    if (screen->base.fence.current) {
 545       struct nouveau_fence *current = NULL;
 546
 547       /* nouveau_fence_wait will create a new current fence, so wait on the
 548        * _current_ one, and remove both.
 549        */
 550       nouveau_fence_ref(screen->base.fence.current, &current);
 551       nouveau_fence_wait(current, NULL);
 552       nouveau_fence_ref(NULL, &current);
 553       nouveau_fence_ref(NULL, &screen->base.fence.current);
 554    }
 555    if (screen->base.pushbuf)
 556       screen->base.pushbuf->user_priv = NULL;
 557
 558    if (screen->blitter)
 559       nvc0_blitter_destroy(screen);
 560    if (screen->pm.prog) {
 561       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 562       nvc0_program_destroy(NULL, screen->pm.prog);
 563       FREE(screen->pm.prog);
 564    }
 565
 566    nouveau_bo_ref(NULL, &screen->text);
 567    nouveau_bo_ref(NULL, &screen->uniform_bo);
 568    nouveau_bo_ref(NULL, &screen->tls);
 569    nouveau_bo_ref(NULL, &screen->txc);
 570    nouveau_bo_ref(NULL, &screen->fence.bo);
 571    nouveau_bo_ref(NULL, &screen->poly_cache);
 572
 573    nouveau_heap_destroy(&screen->lib_code);
 574    nouveau_heap_destroy(&screen->text_heap);
 575
 576    FREE(screen->default_tsc);
 577    FREE(screen->tic.entries);
 578
 579    nouveau_object_del(&screen->eng3d);
 580    nouveau_object_del(&screen->eng2d);
 581    nouveau_object_del(&screen->m2mf);
 582    nouveau_object_del(&screen->compute);
 583    nouveau_object_del(&screen->nvsw);
 584
 585    nouveau_screen_fini(&screen->base);
 586
 587    FREE(screen);
 588 }
 589
 590 static int
 591 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 592                      unsigned size, const uint32_t *data)
 593 {
 594    struct nouveau_pushbuf *push = screen->base.pushbuf;
 595
 596    size /= 4;
 597
 598    assert((pos + size) <= 0x800);
 599
 600    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 601    PUSH_DATA (push, (m - 0x3800) / 8);
 602    PUSH_DATA (push, pos);
 603    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 604    PUSH_DATA (push, pos);
 605    PUSH_DATAp(push, data, size);
 606
 607    return pos + size;
 608 }
 609
 610 static void
 611 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 612 {
 613    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 614    PUSH_DATA (push, 0xff);
 615    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 616    PUSH_DATA (push, 0xff);
 617    PUSH_DATA (push, 0xff);
 618    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 619    PUSH_DATA (push, 0xff);
 620    PUSH_DATA (push, 0xff);
 621    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 622    PUSH_DATA (push, 0x3f);
 623
 624    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 625    PUSH_DATA (push, (3 << 16) | 3);
 626    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 627    PUSH_DATA (push, (2 << 16) | 2);
 628
 629    if (obj_class < GM107_3D_CLASS) {
 630       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 631       PUSH_DATA (push, 0);
 632    }
 633    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 634    PUSH_DATA (push, 0x10);
 635    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 636    PUSH_DATA (push, 0x10);
 637    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 638    PUSH_DATA (push, 0x10);
 639    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 640    PUSH_DATA (push, 0x10);
 641    PUSH_DATA (push, 0x10);
 642    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 643    PUSH_DATA (push, 0x10);
 644    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 645    PUSH_DATA (push, 0xe);
 646
 647    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 648    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 649    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 650    PUSH_DATA (push, 0);
 651    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 652    PUSH_DATA (push, 3);
 653
 654    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 655    PUSH_DATA (push, 0x3fffff);
 656    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 657    PUSH_DATA (push, 1);
 658    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 659    PUSH_DATA (push, 1);
 660
 661    if (obj_class < GM107_3D_CLASS) {
 662       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 663       PUSH_DATA (push, 3);
 664
 665       if (obj_class >= NVE4_3D_CLASS) {
 666          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 667          PUSH_DATA (push, 1);
 668       }
 669    }
 670
 671    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 672     * are supposed to do */
 673 }
 674
 675 static void
 676 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 677 {
 678    struct nvc0_screen *screen = nvc0_screen(pscreen);
 679    struct nouveau_pushbuf *push = screen->base.pushbuf;
 680
 681    /* we need to do it after possible flush in MARK_RING */
 682    *sequence = ++screen->base.fence.sequence;
 683
 684    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 685    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 686    PUSH_DATAh(push, screen->fence.bo->offset);
 687    PUSH_DATA (push, screen->fence.bo->offset);
 688    PUSH_DATA (push, *sequence);
 689    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 690               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 691 }
 692
 693 static u32
 694 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 695 {
 696    struct nvc0_screen *screen = nvc0_screen(pscreen);
 697    return screen->fence.map[0];
 698 }
 699
 700 static int
 701 nvc0_screen_init_compute(struct nvc0_screen *screen)
 702 {
 703    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 704
 705    switch (screen->base.device->chipset & ~0xf) {
 706    case 0xc0:
 707    case 0xd0:
 708       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 709    case 0xe0:
 710    case 0xf0:
 711    case 0x100:
 712    case 0x110:
 713    case 0x120:
 714    case 0x130:
 715       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 716    default:
 717       return -1;
 718    }
 719 }
 720
 721 static int
 722 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 723                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 724 {
 725    struct nouveau_bo *bo = NULL;
 726    int ret;
 727    uint64_t size = (lpos + lneg) * 32 + cstack;
 728
 729    if (size >= (1 << 20)) {
 730       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 731       return -1;
 732    }
 733
 734    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 735    size  = align(size, 0x8000);
 736    size *= screen->mp_count;
 737
 738    size = align(size, 1 << 17);
 739
 740    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 741                         NULL, &bo);
 742    if (ret)
 743       return ret;
 744    nouveau_bo_ref(NULL, &screen->tls);
 745    screen->tls = bo;
 746    return 0;
 747 }
 748
 749 int
 750 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 751 {
 752    struct nouveau_pushbuf *push = screen->base.pushbuf;
 753    struct nouveau_bo *bo;
 754    int ret;
 755
 756    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 757                         1 << 17, size, NULL, &bo);
 758    if (ret)
 759       return ret;
 760
 761    nouveau_bo_ref(NULL, &screen->text);
 762    screen->text = bo;
 763
 764    nouveau_heap_destroy(&screen->lib_code);
 765    nouveau_heap_destroy(&screen->text_heap);
 766
 767    /* XXX: getting a page fault at the end of the code buffer every few
 768     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 769     */
 770    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 771
 772    /* update the code segment setup */
 773    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 774    PUSH_DATAh(push, screen->text->offset);
 775    PUSH_DATA (push, screen->text->offset);
 776    if (screen->compute) {
 777       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 778       PUSH_DATAh(push, screen->text->offset);
 779       PUSH_DATA (push, screen->text->offset);
 780    }
 781
 782    return 0;
 783 }
 784
 785 #define FAIL_SCREEN_INIT(str, err)                    \
 786    do {                                               \
 787       NOUVEAU_ERR(str, err);                          \
 788       goto fail;                                      \
 789    } while(0)
 790
 791 struct nouveau_screen *
 792 nvc0_screen_create(struct nouveau_device *dev)
 793 {
 794    struct nvc0_screen *screen;
 795    struct pipe_screen *pscreen;
 796    struct nouveau_object *chan;
 797    struct nouveau_pushbuf *push;
 798    uint64_t value;
 799    uint32_t obj_class;
 800    uint32_t flags;
 801    int ret;
 802    unsigned i;
 803
 804    switch (dev->chipset & ~0xf) {
 805    case 0xc0:
 806    case 0xd0:
 807    case 0xe0:
 808    case 0xf0:
 809    case 0x100:
 810    case 0x110:
 811    case 0x120:
 812    case 0x130:
 813       break;
 814    default:
 815       return NULL;
 816    }
 817
 818    screen = CALLOC_STRUCT(nvc0_screen);
 819    if (!screen)
 820       return NULL;
 821    pscreen = &screen->base.base;
 822    pscreen->destroy = nvc0_screen_destroy;
 823
 824    ret = nouveau_screen_init(&screen->base, dev);
 825    if (ret)
 826       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
 827    chan = screen->base.channel;
 828    push = screen->base.pushbuf;
 829    push->user_priv = screen;
 830    push->rsvd_kick = 5;
 831
 832    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 833       PIPE_BIND_SHADER_BUFFER |
 834       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 835       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 836    screen->base.sysmem_bindings |=
 837       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 838
 839    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 840       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 841       screen->base.vidmem_bindings = 0;
 842    }
 843
 844    pscreen->context_create = nvc0_create;
 845    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 846    pscreen->get_param = nvc0_screen_get_param;
 847    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 848    pscreen->get_paramf = nvc0_screen_get_paramf;
 849    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 850    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 851
 852    nvc0_screen_init_resource_functions(pscreen);
 853
 854    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 855    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 856
 857    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 858    if (screen->base.drm->version >= 0x01000202)
 859       flags |= NOUVEAU_BO_COHERENT;
 860
 861    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 862    if (ret)
 863       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
 864    nouveau_bo_map(screen->fence.bo, 0, NULL);
 865    screen->fence.map = screen->fence.bo->map;
 866    screen->base.fence.emit = nvc0_screen_fence_emit;
 867    screen->base.fence.update = nvc0_screen_fence_update;
 868
 869
 870    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 871                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 872    if (ret)
 873       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 874
 875    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 876    PUSH_DATA (push, screen->nvsw->handle);
 877
 878    switch (dev->chipset & ~0xf) {
 879    case 0x130:
 880    case 0x120:
 881    case 0x110:
 882    case 0x100:
 883    case 0xf0:
 884       obj_class = NVF0_P2MF_CLASS;
 885       break;
 886    case 0xe0:
 887       obj_class = NVE4_P2MF_CLASS;
 888       break;
 889    default:
 890       obj_class = NVC0_M2MF_CLASS;
 891       break;
 892    }
 893    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 894                             &screen->m2mf);
 895    if (ret)
 896       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 897
 898    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 899    PUSH_DATA (push, screen->m2mf->oclass);
 900    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 901       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 902       PUSH_DATA (push, 0xa0b5);
 903    }
 904
 905    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 906                             &screen->eng2d);
 907    if (ret)
 908       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 909
 910    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 911    PUSH_DATA (push, screen->eng2d->oclass);
 912    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 913    PUSH_DATA (push, 0);
 914    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 915    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 916    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 917    PUSH_DATA (push, 0);
 918    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 919    PUSH_DATA (push, 0);
 920    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 921    PUSH_DATA (push, 0x3f);
 922    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 923    PUSH_DATA (push, 1);
 924    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 925    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 926
 927    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 928    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 929    PUSH_DATA (push, screen->fence.bo->offset + 16);
 930
 931    switch (dev->chipset & ~0xf) {
 932    case 0x130:
 933       switch (dev->chipset) {
 934       case 0x130:
 935       case 0x13b:
 936          obj_class = GP100_3D_CLASS;
 937          break;
 938       default:
 939          obj_class = GP102_3D_CLASS;
 940          break;
 941       }
 942       break;
 943    case 0x120:
 944       obj_class = GM200_3D_CLASS;
 945       break;
 946    case 0x110:
 947       obj_class = GM107_3D_CLASS;
 948       break;
 949    case 0x100:
 950    case 0xf0:
 951       obj_class = NVF0_3D_CLASS;
 952       break;
 953    case 0xe0:
 954       switch (dev->chipset) {
 955       case 0xea:
 956          obj_class = NVEA_3D_CLASS;
 957          break;
 958       default:
 959          obj_class = NVE4_3D_CLASS;
 960          break;
 961       }
 962       break;
 963    case 0xd0:
 964       obj_class = NVC8_3D_CLASS;
 965       break;
 966    case 0xc0:
 967    default:
 968       switch (dev->chipset) {
 969       case 0xc8:
 970          obj_class = NVC8_3D_CLASS;
 971          break;
 972       case 0xc1:
 973          obj_class = NVC1_3D_CLASS;
 974          break;
 975       default:
 976          obj_class = NVC0_3D_CLASS;
 977          break;
 978       }
 979       break;
 980    }
 981    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 982                             &screen->eng3d);
 983    if (ret)
 984       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 985    screen->base.class_3d = obj_class;
 986
 987    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 988    PUSH_DATA (push, screen->eng3d->oclass);
 989
 990    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 991    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 992
 993    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 994       /* kill shaders after about 1 second (at 100 MHz) */
 995       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 996       PUSH_DATA (push, 0x17);
 997    }
 998
 999    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
1000                     screen->base.drm->version >= 0x01000101);
1001    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
1002    for (i = 0; i < 8; ++i)
1003       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
1004
1005    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
1006    PUSH_DATA (push, 1);
1007
1008    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
1009    PUSH_DATA (push, 0);
1010    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
1011    PUSH_DATA (push, 0);
1012    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
1013    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
1014    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
1015    PUSH_DATA (push, 0);
1016    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
1017    PUSH_DATA (push, 1);
1018    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
1019    PUSH_DATA (push, 1);
1020    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
1021    PUSH_DATA (push, 1);
1022    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
1023    PUSH_DATA (push, 0);
1024    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
1025    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
1026    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
1027       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
1028    } else {
1029       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
1030       PUSH_DATA (push, 15);
1031    }
1032    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
1033    PUSH_DATA (push, 8); /* 128 */
1034    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
1035    PUSH_DATA (push, 1);
1036    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
1037       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
1038       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
1039    }
1040
1041    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1042
1043    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1044    if (ret)
1045       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1046
1047    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
1048                         &screen->uniform_bo);
1049    if (ret)
1050       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1051
1052    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1053
1054    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1055    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1056    PUSH_DATA (push, 256);
1057    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1058    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1059    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1060    PUSH_DATA (push, 0);
1061    PUSH_DATAf(push, 0.0f);
1062    PUSH_DATAf(push, 0.0f);
1063    PUSH_DATAf(push, 0.0f);
1064    PUSH_DATAf(push, 0.0f);
1065    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1066    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1067    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1068
1069    if (screen->base.drm->version >= 0x01000101) {
1070       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1071       if (ret)
1072          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1073    } else {
1074       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1075          value = (8 << 8) | 4;
1076       else
1077          value = (16 << 8) | 4;
1078    }
1079    screen->gpc_count = value & 0x000000ff;
1080    screen->mp_count = value >> 8;
1081    screen->mp_count_compute = screen->mp_count;
1082
1083    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1084    if (ret)
1085       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1086
1087    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1088    PUSH_DATAh(push, screen->tls->offset);
1089    PUSH_DATA (push, screen->tls->offset);
1090    PUSH_DATA (push, screen->tls->size >> 32);
1091    PUSH_DATA (push, screen->tls->size);
1092    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1093    PUSH_DATA (push, 0);
1094    /* Reduce likelihood of collision with real buffers by placing the hole at
1095     * the top of the 4G area. This will have to be dealt with for real
1096     * eventually by blocking off that area from the VM.
1097     */
1098    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1099    PUSH_DATA (push, 0xff << 24);
1100
1101    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1102       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1103                            &screen->poly_cache);
1104       if (ret)
1105          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1106
1107       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1108       PUSH_DATAh(push, screen->poly_cache->offset);
1109       PUSH_DATA (push, screen->poly_cache->offset);
1110       PUSH_DATA (push, 3);
1111    }
1112
1113    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1114                         &screen->txc);
1115    if (ret)
1116       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1117
1118    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1119    PUSH_DATAh(push, screen->txc->offset);
1120    PUSH_DATA (push, screen->txc->offset);
1121    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1122    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1123       screen->tic.maxwell = true;
1124       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1125          screen->tic.maxwell =
1126             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1127          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1128       }
1129    }
1130
1131    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1132    PUSH_DATAh(push, screen->txc->offset + 65536);
1133    PUSH_DATA (push, screen->txc->offset + 65536);
1134    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1135
1136    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1137    PUSH_DATA (push, 0);
1138    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1139    PUSH_DATA (push, 0);
1140    PUSH_DATA (push, 0);
1141    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1142    PUSH_DATA (push, 0x3f);
1143
1144    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1145    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1146    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1147    for (i = 0; i < 8 * 2; ++i)
1148       PUSH_DATA(push, 0);
1149    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1150    PUSH_DATA (push, 0);
1151    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1152    PUSH_DATA (push, 0);
1153
1154    /* neither scissors, viewport nor stencil mask should affect clears */
1155    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1156    PUSH_DATA (push, 0);
1157
1158    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1159    PUSH_DATA (push, 1);
1160    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1161       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1162       PUSH_DATAf(push, 0.0f);
1163       PUSH_DATAf(push, 1.0f);
1164    }
1165    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1166    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1167
1168    /* We use scissors instead of exact view volume clipping,
1169     * so they're always enabled.
1170     */
1171    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1172       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1173       PUSH_DATA (push, 1);
1174       PUSH_DATA (push, 8192 << 16);
1175       PUSH_DATA (push, 8192 << 16);
1176    }
1177
1178 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1179
1180    i = 0;
1181    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1182    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1183    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1184    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1185    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1186    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1187    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1188    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1189    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1190    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1191    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1192    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1193    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1194
1195    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1196    PUSH_DATA (push, 1);
1197    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1198    PUSH_DATA (push, 1);
1199    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1200    PUSH_DATA (push, 0x40);
1201    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1202    PUSH_DATA (push, 0);
1203    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1204    PUSH_DATA (push, 0x30);
1205    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1206    PUSH_DATA (push, 3);
1207    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1208    PUSH_DATA (push, 0x20);
1209    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1210    PUSH_DATA (push, 0x00);
1211    screen->save_state.patch_vertices = 3;
1212
1213    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1214    PUSH_DATA (push, 0);
1215    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1216    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1217
1218    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1219
1220    if (nvc0_screen_init_compute(screen))
1221       goto fail;
1222
1223    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1224    for (i = 0; i < 5; ++i) {
1225       /* TIC and TSC entries for each unit (nve4+ only) */
1226       /* auxiliary constants (6 user clip planes, base instance id) */
1227       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1228       PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1229       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1230       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1231       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1232       PUSH_DATA (push, (15 << 4) | 1);
1233       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1234          unsigned j;
1235          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1236          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1237          for (j = 0; j < 8; ++j)
1238             PUSH_DATA(push, j);
1239       } else {
1240          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1241          PUSH_DATA (push, 0x54);
1242       }
1243
1244       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1245       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1246       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1247       PUSH_DATA (push, 0); /* 0 */
1248       PUSH_DATA (push, 0);
1249       PUSH_DATA (push, 1); /* 1 */
1250       PUSH_DATA (push, 0);
1251       PUSH_DATA (push, 0); /* 2 */
1252       PUSH_DATA (push, 1);
1253       PUSH_DATA (push, 1); /* 3 */
1254       PUSH_DATA (push, 1);
1255       PUSH_DATA (push, 2); /* 4 */
1256       PUSH_DATA (push, 0);
1257       PUSH_DATA (push, 3); /* 5 */
1258       PUSH_DATA (push, 0);
1259       PUSH_DATA (push, 2); /* 6 */
1260       PUSH_DATA (push, 1);
1261       PUSH_DATA (push, 3); /* 7 */
1262       PUSH_DATA (push, 1);
1263    }
1264    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1265    PUSH_DATA (push, 0);
1266
1267    PUSH_KICK (push);
1268
1269    screen->tic.entries = CALLOC(4096, sizeof(void *));
1270    screen->tsc.entries = screen->tic.entries + 2048;
1271
1272    if (!nvc0_blitter_create(screen))
1273       goto fail;
1274
1275    screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1276    screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1277
1278    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1279
1280    return &screen->base;
1281
1282 fail:
1283    screen->base.base.context_create = NULL;
1284    return &screen->base;
1285 }
1286
1287 int
1288 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1289 {
1290    int i = screen->tic.next;
1291
1292    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1293       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1294
1295    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1296
1297    if (screen->tic.entries[i])
1298       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1299
1300    screen->tic.entries[i] = entry;
1301    return i;
1302 }
1303
1304 int
1305 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1306 {
1307    int i = screen->tsc.next;
1308
1309    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1310       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1311
1312    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1313
1314    if (screen->tsc.entries[i])
1315       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1316
1317    screen->tsc.entries[i] = entry;
1318    return i;
1319 }