src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <xf86drm.h>
  24 #include <nouveau_drm.h>
  25 #include <nvif/class.h>
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28 #include "pipe/p_screen.h"
  29
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32
  33 #include "nouveau_vp3_video.h"
  34
  35 #include "nvc0/nvc0_context.h"
  36 #include "nvc0/nvc0_screen.h"
  37
  38 #include "nvc0/mme/com9097.mme.h"
  39 #include "nvc0/mme/com90c0.mme.h"
  40
  41 #include "nv50/g80_texture.xml.h"
  42
  43 static boolean
  44 nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  45                                 enum pipe_format format,
  46                                 enum pipe_texture_target target,
  47                                 unsigned sample_count,
  48                                 unsigned bindings)
  49 {
  50    const struct util_format_description *desc = util_format_description(format);
  51
  52    if (sample_count > 8)
  53       return false;
  54    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  55       return false;
  56
  57    /* Short-circuit the rest of the logic -- this is used by the state tracker
  58     * to determine valid MS levels in a no-attachments scenario.
  59     */
  60    if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
  61       return true;
  62
  63    if (!util_format_is_supported(format, bindings))
  64       return false;
  65
  66    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  67       if (util_format_get_blocksizebits(format) == 3 * 32)
  68          return false;
  69
  70    if (bindings & PIPE_BIND_LINEAR)
  71       if (util_format_is_depth_or_stencil(format) ||
  72           (target != PIPE_TEXTURE_1D &&
  73            target != PIPE_TEXTURE_2D &&
  74            target != PIPE_TEXTURE_RECT) ||
  75           sample_count > 1)
  76          return false;
  77
  78    /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
  79     */
  80    if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
  81         desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
  82        /* The claim is that this should work on GM107 but it doesn't. Need to
  83         * test further and figure out if it's a nouveau issue or a HW one.
  84        nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
  85         */
  86        nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
  87       return false;
  88
  89    /* shared is always supported */
  90    bindings &= ~(PIPE_BIND_LINEAR |
  91                  PIPE_BIND_SHARED);
  92
  93    if (bindings & PIPE_BIND_SHADER_IMAGE && sample_count > 1 &&
  94        nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
  95       /* MS images are currently unsupported on Maxwell because they have to
  96        * be handled explicitly. */
  97       return false;
  98    }
  99
 100    return (( nvc0_format_table[format].usage |
 101             nvc0_vertex_format[format].usage) & bindings) == bindings;
 102 }
 103
 104 static int
 105 nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 106 {
 107    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 108    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
 109
 110    switch (param) {
 111    /* non-boolean caps */
 112    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 113    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 114       return 15;
 115    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 116       return 12;
 117    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 118       return 2048;
 119    case PIPE_CAP_MIN_TEXEL_OFFSET:
 120       return -8;
 121    case PIPE_CAP_MAX_TEXEL_OFFSET:
 122       return 7;
 123    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 124       return -32;
 125    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 126       return 31;
 127    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 128       return 128 * 1024 * 1024;
 129    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 130       return 430;
 131    case PIPE_CAP_MAX_RENDER_TARGETS:
 132       return 8;
 133    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 134       return 1;
 135    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 136       return 4;
 137    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 138    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 139       return 128;
 140    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 141    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 142       return 1024;
 143    case PIPE_CAP_MAX_VERTEX_STREAMS:
 144       return 4;
 145    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 146       return 2048;
 147    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 148       return 256;
 149    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 150       return 16; /* 256 for binding as RT, but that's not possible in GL */
 151    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 152       return 16;
 153    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 154       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 155    case PIPE_CAP_MAX_VIEWPORTS:
 156       return NVC0_MAX_VIEWPORTS;
 157    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 158       return 4;
 159    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 160       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 161    case PIPE_CAP_ENDIANNESS:
 162       return PIPE_ENDIAN_LITTLE;
 163    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 164       return 30;
 165    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 166       return NVC0_MAX_WINDOW_RECTANGLES;
 167
 168    /* supported caps */
 169    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 170    case PIPE_CAP_TEXTURE_SWIZZLE:
 171    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 172    case PIPE_CAP_NPOT_TEXTURES:
 173    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 174    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 175    case PIPE_CAP_ANISOTROPIC_FILTER:
 176    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 177    case PIPE_CAP_CUBE_MAP_ARRAY:
 178    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 179    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 180    case PIPE_CAP_TWO_SIDED_STENCIL:
 181    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 182    case PIPE_CAP_POINT_SPRITE:
 183    case PIPE_CAP_TGSI_TEXCOORD:
 184    case PIPE_CAP_SM3:
 185    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 186    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 187    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 188    case PIPE_CAP_QUERY_TIMESTAMP:
 189    case PIPE_CAP_QUERY_TIME_ELAPSED:
 190    case PIPE_CAP_OCCLUSION_QUERY:
 191    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 192    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 193    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 194    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 195    case PIPE_CAP_INDEP_BLEND_ENABLE:
 196    case PIPE_CAP_INDEP_BLEND_FUNC:
 197    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 198    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 199    case PIPE_CAP_PRIMITIVE_RESTART:
 200    case PIPE_CAP_TGSI_INSTANCEID:
 201    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 202    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 203    case PIPE_CAP_CONDITIONAL_RENDER:
 204    case PIPE_CAP_TEXTURE_BARRIER:
 205    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 206    case PIPE_CAP_START_INSTANCE:
 207    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 208    case PIPE_CAP_DRAW_INDIRECT:
 209    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 210    case PIPE_CAP_USER_INDEX_BUFFERS:
 211    case PIPE_CAP_USER_VERTEX_BUFFERS:
 212    case PIPE_CAP_TEXTURE_QUERY_LOD:
 213    case PIPE_CAP_SAMPLE_SHADING:
 214    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 215    case PIPE_CAP_TEXTURE_GATHER_SM5:
 216    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 217    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 218    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 219    case PIPE_CAP_CLIP_HALFZ:
 220    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 221    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 222    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 223    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 224    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 225    case PIPE_CAP_TGSI_TXQS:
 226    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 227    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 228    case PIPE_CAP_SHAREABLE_SHADERS:
 229    case PIPE_CAP_CLEAR_TEXTURE:
 230    case PIPE_CAP_DRAW_PARAMETERS:
 231    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 232    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 233    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 234    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 235    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 236    case PIPE_CAP_INVALIDATE_BUFFER:
 237    case PIPE_CAP_STRING_MARKER:
 238    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 239    case PIPE_CAP_CULL_DISTANCE:
 240    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 241    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 242    case PIPE_CAP_TGSI_VOTE:
 243    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 244    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 245    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 246    case PIPE_CAP_DOUBLES:
 247       return 1;
 248    case PIPE_CAP_COMPUTE:
 249       return (class_3d < GP100_3D_CLASS);
 250    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 251       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
 252    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 253       return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
 254    case PIPE_CAP_TGSI_FS_FBFETCH:
 255       return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
 256
 257    /* unsupported caps */
 258    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 259    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 260    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 261    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 262    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 263    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 264    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 265    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 266    case PIPE_CAP_FAKE_SW_MSAA:
 267    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 268    case PIPE_CAP_VERTEXID_NOBASE:
 269    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 270    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 271    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 272    case PIPE_CAP_GENERATE_MIPMAP:
 273    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 274    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 275    case PIPE_CAP_QUERY_MEMORY_INFO:
 276    case PIPE_CAP_PCI_GROUP:
 277    case PIPE_CAP_PCI_BUS:
 278    case PIPE_CAP_PCI_DEVICE:
 279    case PIPE_CAP_PCI_FUNCTION:
 280    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 281    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 282    case PIPE_CAP_NATIVE_FENCE_FD:
 283    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 284    case PIPE_CAP_INT64:
 285       return 0;
 286
 287    case PIPE_CAP_VENDOR_ID:
 288       return 0x10de;
 289    case PIPE_CAP_DEVICE_ID: {
 290       uint64_t device_id;
 291       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
 292          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
 293          return -1;
 294       }
 295       return device_id;
 296    }
 297    case PIPE_CAP_ACCELERATED:
 298       return 1;
 299    case PIPE_CAP_VIDEO_MEMORY:
 300       return dev->vram_size >> 20;
 301    case PIPE_CAP_UMA:
 302       return 0;
 303    }
 304
 305    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 306    return 0;
 307 }
 308
 309 static int
 310 nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 311                              enum pipe_shader_cap param)
 312 {
 313    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 314
 315    switch (shader) {
 316    case PIPE_SHADER_VERTEX:
 317    case PIPE_SHADER_GEOMETRY:
 318    case PIPE_SHADER_FRAGMENT:
 319    case PIPE_SHADER_COMPUTE:
 320    case PIPE_SHADER_TESS_CTRL:
 321    case PIPE_SHADER_TESS_EVAL:
 322       break;
 323    default:
 324       return 0;
 325    }
 326
 327    switch (param) {
 328    case PIPE_SHADER_CAP_PREFERRED_IR:
 329       return PIPE_SHADER_IR_TGSI;
 330    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 331       return 1 << PIPE_SHADER_IR_TGSI;
 332    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 333    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 334    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 335    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 336       return 16384;
 337    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 338       return 16;
 339    case PIPE_SHADER_CAP_MAX_INPUTS:
 340       if (shader == PIPE_SHADER_VERTEX)
 341          return 32;
 342       /* NOTE: These only count our slots for GENERIC varyings.
 343        * The address space may be larger, but the actual hard limit seems to be
 344        * less than what the address space layout permits, so don't add TEXCOORD,
 345        * COLOR, etc. here.
 346        */
 347       if (shader == PIPE_SHADER_FRAGMENT)
 348          return 0x1f0 / 16;
 349       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
 350        * and excludes 0x60 per-patch inputs.
 351        */
 352       return 0x200 / 16;
 353    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 354       return 32;
 355    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 356       return 65536;
 357    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 358       return NVC0_MAX_PIPE_CONSTBUFS;
 359    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 360       return shader != PIPE_SHADER_FRAGMENT;
 361    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 362    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 363    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 364       return 1;
 365    case PIPE_SHADER_CAP_MAX_PREDS:
 366       return 0;
 367    case PIPE_SHADER_CAP_MAX_TEMPS:
 368       return NVC0_CAP_MAX_PROGRAM_TEMPS;
 369    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 370       return 1;
 371    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 372       return 1;
 373    case PIPE_SHADER_CAP_SUBROUTINES:
 374       return 1;
 375    case PIPE_SHADER_CAP_INTEGERS:
 376       return 1;
 377    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 378       return 1;
 379    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 380       return 1;
 381    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 382    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 383    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 384       return 0;
 385    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 386       return NVC0_MAX_BUFFERS;
 387    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 388       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 389    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 390       return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
 391    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 392       return 32;
 393    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 394       if (class_3d >= NVE4_3D_CLASS)
 395          return NVC0_MAX_IMAGES;
 396       if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
 397          return NVC0_MAX_IMAGES;
 398       return 0;
 399    default:
 400       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 401       return 0;
 402    }
 403 }
 404
 405 static float
 406 nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 407 {
 408    switch (param) {
 409    case PIPE_CAPF_MAX_LINE_WIDTH:
 410    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 411       return 10.0f;
 412    case PIPE_CAPF_MAX_POINT_WIDTH:
 413       return 63.0f;
 414    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 415       return 63.375f;
 416    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 417       return 16.0f;
 418    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 419       return 15.0f;
 420    case PIPE_CAPF_GUARD_BAND_LEFT:
 421    case PIPE_CAPF_GUARD_BAND_TOP:
 422       return 0.0f;
 423    case PIPE_CAPF_GUARD_BAND_RIGHT:
 424    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 425       return 0.0f; /* that or infinity */
 426    }
 427
 428    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
 429    return 0.0f;
 430 }
 431
 432 static int
 433 nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
 434                               enum pipe_shader_ir ir_type,
 435                               enum pipe_compute_cap param, void *data)
 436 {
 437    struct nvc0_screen *screen = nvc0_screen(pscreen);
 438    const uint16_t obj_class = screen->compute->oclass;
 439
 440 #define RET(x) do {                  \
 441    if (data)                         \
 442       memcpy(data, x, sizeof(x));    \
 443    return sizeof(x);                 \
 444 } while (0)
 445
 446    switch (param) {
 447    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 448       RET((uint64_t []) { 3 });
 449    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 450       if (obj_class >= NVE4_COMPUTE_CLASS) {
 451          RET(((uint64_t []) { 0x7fffffff, 65535, 65535 }));
 452       } else {
 453          RET(((uint64_t []) { 65535, 65535, 65535 }));
 454       }
 455    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 456       RET(((uint64_t []) { 1024, 1024, 64 }));
 457    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 458       RET((uint64_t []) { 1024 });
 459    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 460       if (obj_class >= NVE4_COMPUTE_CLASS) {
 461          RET((uint64_t []) { 1024 });
 462       } else {
 463          RET((uint64_t []) { 512 });
 464       }
 465    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
 466       RET((uint64_t []) { 1ULL << 40 });
 467    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
 468       switch (obj_class) {
 469       case GM200_COMPUTE_CLASS:
 470          RET((uint64_t []) { 96 << 10 });
 471          break;
 472       case GM107_COMPUTE_CLASS:
 473          RET((uint64_t []) { 64 << 10 });
 474          break;
 475       default:
 476          RET((uint64_t []) { 48 << 10 });
 477          break;
 478       }
 479    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
 480       RET((uint64_t []) { 512 << 10 });
 481    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
 482       RET((uint64_t []) { 4096 });
 483    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 484       RET((uint32_t []) { 32 });
 485    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 486       RET((uint64_t []) { 1ULL << 40 });
 487    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 488       RET((uint32_t []) { 0 });
 489    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 490       RET((uint32_t []) { screen->mp_count_compute });
 491    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 492       RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
 493    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 494       RET((uint32_t []) { 64 });
 495    default:
 496       return 0;
 497    }
 498
 499 #undef RET
 500 }
 501
 502 static void
 503 nvc0_screen_destroy(struct pipe_screen *pscreen)
 504 {
 505    struct nvc0_screen *screen = nvc0_screen(pscreen);
 506
 507    if (!nouveau_drm_screen_unref(&screen->base))
 508       return;
 509
 510    if (screen->base.fence.current) {
 511       struct nouveau_fence *current = NULL;
 512
 513       /* nouveau_fence_wait will create a new current fence, so wait on the
 514        * _current_ one, and remove both.
 515        */
 516       nouveau_fence_ref(screen->base.fence.current, &current);
 517       nouveau_fence_wait(current, NULL);
 518       nouveau_fence_ref(NULL, &current);
 519       nouveau_fence_ref(NULL, &screen->base.fence.current);
 520    }
 521    if (screen->base.pushbuf)
 522       screen->base.pushbuf->user_priv = NULL;
 523
 524    if (screen->blitter)
 525       nvc0_blitter_destroy(screen);
 526    if (screen->pm.prog) {
 527       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
 528       nvc0_program_destroy(NULL, screen->pm.prog);
 529       FREE(screen->pm.prog);
 530    }
 531
 532    nouveau_bo_ref(NULL, &screen->text);
 533    nouveau_bo_ref(NULL, &screen->uniform_bo);
 534    nouveau_bo_ref(NULL, &screen->tls);
 535    nouveau_bo_ref(NULL, &screen->txc);
 536    nouveau_bo_ref(NULL, &screen->fence.bo);
 537    nouveau_bo_ref(NULL, &screen->poly_cache);
 538
 539    nouveau_heap_destroy(&screen->lib_code);
 540    nouveau_heap_destroy(&screen->text_heap);
 541
 542    FREE(screen->default_tsc);
 543    FREE(screen->tic.entries);
 544
 545    nouveau_object_del(&screen->eng3d);
 546    nouveau_object_del(&screen->eng2d);
 547    nouveau_object_del(&screen->m2mf);
 548    nouveau_object_del(&screen->compute);
 549    nouveau_object_del(&screen->nvsw);
 550
 551    nouveau_screen_fini(&screen->base);
 552
 553    FREE(screen);
 554 }
 555
 556 static int
 557 nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
 558                      unsigned size, const uint32_t *data)
 559 {
 560    struct nouveau_pushbuf *push = screen->base.pushbuf;
 561
 562    size /= 4;
 563
 564    assert((pos + size) <= 0x800);
 565
 566    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
 567    PUSH_DATA (push, (m - 0x3800) / 8);
 568    PUSH_DATA (push, pos);
 569    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
 570    PUSH_DATA (push, pos);
 571    PUSH_DATAp(push, data, size);
 572
 573    return pos + size;
 574 }
 575
 576 static void
 577 nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
 578 {
 579    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
 580    PUSH_DATA (push, 0xff);
 581    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
 582    PUSH_DATA (push, 0xff);
 583    PUSH_DATA (push, 0xff);
 584    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
 585    PUSH_DATA (push, 0xff);
 586    PUSH_DATA (push, 0xff);
 587    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
 588    PUSH_DATA (push, 0x3f);
 589
 590    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
 591    PUSH_DATA (push, (3 << 16) | 3);
 592    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
 593    PUSH_DATA (push, (2 << 16) | 2);
 594
 595    if (obj_class < GM107_3D_CLASS) {
 596       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
 597       PUSH_DATA (push, 0);
 598    }
 599    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
 600    PUSH_DATA (push, 0x10);
 601    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
 602    PUSH_DATA (push, 0x10);
 603    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
 604    PUSH_DATA (push, 0x10);
 605    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
 606    PUSH_DATA (push, 0x10);
 607    PUSH_DATA (push, 0x10);
 608    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
 609    PUSH_DATA (push, 0x10);
 610    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
 611    PUSH_DATA (push, 0xe);
 612
 613    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
 614    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
 615    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
 616    PUSH_DATA (push, 0);
 617    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
 618    PUSH_DATA (push, 3);
 619
 620    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
 621    PUSH_DATA (push, 0x3fffff);
 622    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
 623    PUSH_DATA (push, 1);
 624    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
 625    PUSH_DATA (push, 1);
 626
 627    if (obj_class < GM107_3D_CLASS) {
 628       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
 629       PUSH_DATA (push, 3);
 630
 631       if (obj_class >= NVE4_3D_CLASS) {
 632          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
 633          PUSH_DATA (push, 1);
 634       }
 635    }
 636
 637    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
 638     * are supposed to do */
 639 }
 640
 641 static void
 642 nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 643 {
 644    struct nvc0_screen *screen = nvc0_screen(pscreen);
 645    struct nouveau_pushbuf *push = screen->base.pushbuf;
 646
 647    /* we need to do it after possible flush in MARK_RING */
 648    *sequence = ++screen->base.fence.sequence;
 649
 650    assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
 651    PUSH_DATA (push, NVC0_FIFO_PKHDR_SQ(NVC0_3D(QUERY_ADDRESS_HIGH), 4));
 652    PUSH_DATAh(push, screen->fence.bo->offset);
 653    PUSH_DATA (push, screen->fence.bo->offset);
 654    PUSH_DATA (push, *sequence);
 655    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
 656               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
 657 }
 658
 659 static u32
 660 nvc0_screen_fence_update(struct pipe_screen *pscreen)
 661 {
 662    struct nvc0_screen *screen = nvc0_screen(pscreen);
 663    return screen->fence.map[0];
 664 }
 665
 666 static int
 667 nvc0_screen_init_compute(struct nvc0_screen *screen)
 668 {
 669    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 670
 671    switch (screen->base.device->chipset & ~0xf) {
 672    case 0xc0:
 673    case 0xd0:
 674       return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
 675    case 0xe0:
 676    case 0xf0:
 677    case 0x100:
 678    case 0x110:
 679    case 0x120:
 680       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
 681    case 0x130:
 682       return 0;
 683    default:
 684       return -1;
 685    }
 686 }
 687
 688 static int
 689 nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
 690                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
 691 {
 692    struct nouveau_bo *bo = NULL;
 693    int ret;
 694    uint64_t size = (lpos + lneg) * 32 + cstack;
 695
 696    if (size >= (1 << 20)) {
 697       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
 698       return -1;
 699    }
 700
 701    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
 702    size  = align(size, 0x8000);
 703    size *= screen->mp_count;
 704
 705    size = align(size, 1 << 17);
 706
 707    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
 708                         NULL, &bo);
 709    if (ret)
 710       return ret;
 711    nouveau_bo_ref(NULL, &screen->tls);
 712    screen->tls = bo;
 713    return 0;
 714 }
 715
 716 int
 717 nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
 718 {
 719    struct nouveau_pushbuf *push = screen->base.pushbuf;
 720    struct nouveau_bo *bo;
 721    int ret;
 722
 723    ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
 724                         1 << 17, size, NULL, &bo);
 725    if (ret)
 726       return ret;
 727
 728    nouveau_bo_ref(NULL, &screen->text);
 729    screen->text = bo;
 730
 731    nouveau_heap_destroy(&screen->lib_code);
 732    nouveau_heap_destroy(&screen->text_heap);
 733
 734    /* XXX: getting a page fault at the end of the code buffer every few
 735     *  launches, don't use the last 256 bytes to work around them - prefetch ?
 736     */
 737    nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
 738
 739    /* update the code segment setup */
 740    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
 741    PUSH_DATAh(push, screen->text->offset);
 742    PUSH_DATA (push, screen->text->offset);
 743    if (screen->compute) {
 744       BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
 745       PUSH_DATAh(push, screen->text->offset);
 746       PUSH_DATA (push, screen->text->offset);
 747    }
 748
 749    return 0;
 750 }
 751
 752 #define FAIL_SCREEN_INIT(str, err)                    \
 753    do {                                               \
 754       NOUVEAU_ERR(str, err);                          \
 755       goto fail;                                      \
 756    } while(0)
 757
 758 struct nouveau_screen *
 759 nvc0_screen_create(struct nouveau_device *dev)
 760 {
 761    struct nvc0_screen *screen;
 762    struct pipe_screen *pscreen;
 763    struct nouveau_object *chan;
 764    struct nouveau_pushbuf *push;
 765    uint64_t value;
 766    uint32_t obj_class;
 767    uint32_t flags;
 768    int ret;
 769    unsigned i;
 770
 771    switch (dev->chipset & ~0xf) {
 772    case 0xc0:
 773    case 0xd0:
 774    case 0xe0:
 775    case 0xf0:
 776    case 0x100:
 777    case 0x110:
 778    case 0x120:
 779    case 0x130:
 780       break;
 781    default:
 782       return NULL;
 783    }
 784
 785    screen = CALLOC_STRUCT(nvc0_screen);
 786    if (!screen)
 787       return NULL;
 788    pscreen = &screen->base.base;
 789    pscreen->destroy = nvc0_screen_destroy;
 790
 791    ret = nouveau_screen_init(&screen->base, dev);
 792    if (ret)
 793       FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
 794    chan = screen->base.channel;
 795    push = screen->base.pushbuf;
 796    push->user_priv = screen;
 797    push->rsvd_kick = 5;
 798
 799    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 800       PIPE_BIND_SHADER_BUFFER |
 801       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
 802       PIPE_BIND_COMMAND_ARGS_BUFFER | PIPE_BIND_QUERY_BUFFER;
 803    screen->base.sysmem_bindings |=
 804       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 805
 806    if (screen->base.vram_domain & NOUVEAU_BO_GART) {
 807       screen->base.sysmem_bindings |= screen->base.vidmem_bindings;
 808       screen->base.vidmem_bindings = 0;
 809    }
 810
 811    pscreen->context_create = nvc0_create;
 812    pscreen->is_format_supported = nvc0_screen_is_format_supported;
 813    pscreen->get_param = nvc0_screen_get_param;
 814    pscreen->get_shader_param = nvc0_screen_get_shader_param;
 815    pscreen->get_paramf = nvc0_screen_get_paramf;
 816    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
 817    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
 818
 819    nvc0_screen_init_resource_functions(pscreen);
 820
 821    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 822    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 823
 824    flags = NOUVEAU_BO_GART | NOUVEAU_BO_MAP;
 825    if (screen->base.drm->version >= 0x01000202)
 826       flags |= NOUVEAU_BO_COHERENT;
 827
 828    ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
 829    if (ret)
 830       FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
 831    nouveau_bo_map(screen->fence.bo, 0, NULL);
 832    screen->fence.map = screen->fence.bo->map;
 833    screen->base.fence.emit = nvc0_screen_fence_emit;
 834    screen->base.fence.update = nvc0_screen_fence_update;
 835
 836
 837    ret = nouveau_object_new(chan, (dev->chipset < 0xe0) ? 0x1f906e : 0x906e,
 838                             NVIF_CLASS_SW_GF100, NULL, 0, &screen->nvsw);
 839    if (ret)
 840       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
 841
 842    BEGIN_NVC0(push, SUBC_SW(NV01_SUBCHAN_OBJECT), 1);
 843    PUSH_DATA (push, screen->nvsw->handle);
 844
 845    switch (dev->chipset & ~0xf) {
 846    case 0x130:
 847    case 0x120:
 848    case 0x110:
 849    case 0x100:
 850    case 0xf0:
 851       obj_class = NVF0_P2MF_CLASS;
 852       break;
 853    case 0xe0:
 854       obj_class = NVE4_P2MF_CLASS;
 855       break;
 856    default:
 857       obj_class = NVC0_M2MF_CLASS;
 858       break;
 859    }
 860    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
 861                             &screen->m2mf);
 862    if (ret)
 863       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 864
 865    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 866    PUSH_DATA (push, screen->m2mf->oclass);
 867    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
 868       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
 869       PUSH_DATA (push, 0xa0b5);
 870    }
 871
 872    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
 873                             &screen->eng2d);
 874    if (ret)
 875       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 876
 877    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 878    PUSH_DATA (push, screen->eng2d->oclass);
 879    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
 880    PUSH_DATA (push, 0);
 881    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
 882    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 883    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
 884    PUSH_DATA (push, 0);
 885    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
 886    PUSH_DATA (push, 0);
 887    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
 888    PUSH_DATA (push, 0x3f);
 889    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
 890    PUSH_DATA (push, 1);
 891    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
 892    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
 893
 894    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
 895    PUSH_DATAh(push, screen->fence.bo->offset + 16);
 896    PUSH_DATA (push, screen->fence.bo->offset + 16);
 897
 898    switch (dev->chipset & ~0xf) {
 899    case 0x130:
 900       obj_class = GP100_3D_CLASS;
 901       break;
 902    case 0x120:
 903       obj_class = GM200_3D_CLASS;
 904       break;
 905    case 0x110:
 906       obj_class = GM107_3D_CLASS;
 907       break;
 908    case 0x100:
 909    case 0xf0:
 910       obj_class = NVF0_3D_CLASS;
 911       break;
 912    case 0xe0:
 913       switch (dev->chipset) {
 914       case 0xea:
 915          obj_class = NVEA_3D_CLASS;
 916          break;
 917       default:
 918          obj_class = NVE4_3D_CLASS;
 919          break;
 920       }
 921       break;
 922    case 0xd0:
 923       obj_class = NVC8_3D_CLASS;
 924       break;
 925    case 0xc0:
 926    default:
 927       switch (dev->chipset) {
 928       case 0xc8:
 929          obj_class = NVC8_3D_CLASS;
 930          break;
 931       case 0xc1:
 932          obj_class = NVC1_3D_CLASS;
 933          break;
 934       default:
 935          obj_class = NVC0_3D_CLASS;
 936          break;
 937       }
 938       break;
 939    }
 940    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
 941                             &screen->eng3d);
 942    if (ret)
 943       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 944    screen->base.class_3d = obj_class;
 945
 946    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 947    PUSH_DATA (push, screen->eng3d->oclass);
 948
 949    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
 950    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
 951
 952    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
 953       /* kill shaders after about 1 second (at 100 MHz) */
 954       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
 955       PUSH_DATA (push, 0x17);
 956    }
 957
 958    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE),
 959                     screen->base.drm->version >= 0x01000101);
 960    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
 961    for (i = 0; i < 8; ++i)
 962       PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
 963
 964    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
 965    PUSH_DATA (push, 1);
 966
 967    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
 968    PUSH_DATA (push, 0);
 969    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
 970    PUSH_DATA (push, 0);
 971    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
 972    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
 973    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
 974    PUSH_DATA (push, 0);
 975    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
 976    PUSH_DATA (push, 1);
 977    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
 978    PUSH_DATA (push, 1);
 979    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
 980    PUSH_DATA (push, 1);
 981    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
 982    PUSH_DATA (push, 0);
 983    BEGIN_NVC0(push, NVC0_3D(SHADE_MODEL), 1);
 984    PUSH_DATA (push, NVC0_3D_SHADE_MODEL_SMOOTH);
 985    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
 986       IMMED_NVC0(push, NVC0_3D(TEX_MISC), 0);
 987    } else {
 988       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
 989       PUSH_DATA (push, 15);
 990    }
 991    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
 992    PUSH_DATA (push, 8); /* 128 */
 993    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
 994    PUSH_DATA (push, 1);
 995    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
 996       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
 997       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
 998    }
 999
1000    nvc0_magic_3d_init(push, screen->eng3d->oclass);
1001
1002    ret = nvc0_screen_resize_text_area(screen, 1 << 19);
1003    if (ret)
1004       FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
1005
1006    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
1007                         &screen->uniform_bo);
1008    if (ret)
1009       FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
1010
1011    PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1012
1013    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
1014    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1015    PUSH_DATA (push, 256);
1016    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1017    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1018    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
1019    PUSH_DATA (push, 0);
1020    PUSH_DATAf(push, 0.0f);
1021    PUSH_DATAf(push, 0.0f);
1022    PUSH_DATAf(push, 0.0f);
1023    PUSH_DATAf(push, 0.0f);
1024    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
1025    PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1026    PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
1027
1028    if (screen->base.drm->version >= 0x01000101) {
1029       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1030       if (ret)
1031          FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
1032    } else {
1033       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
1034          value = (8 << 8) | 4;
1035       else
1036          value = (16 << 8) | 4;
1037    }
1038    screen->gpc_count = value & 0x000000ff;
1039    screen->mp_count = value >> 8;
1040    screen->mp_count_compute = screen->mp_count;
1041
1042    ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
1043    if (ret)
1044       FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
1045
1046    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
1047    PUSH_DATAh(push, screen->tls->offset);
1048    PUSH_DATA (push, screen->tls->offset);
1049    PUSH_DATA (push, screen->tls->size >> 32);
1050    PUSH_DATA (push, screen->tls->size);
1051    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
1052    PUSH_DATA (push, 0);
1053    /* Reduce likelihood of collision with real buffers by placing the hole at
1054     * the top of the 4G area. This will have to be dealt with for real
1055     * eventually by blocking off that area from the VM.
1056     */
1057    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
1058    PUSH_DATA (push, 0xff << 24);
1059
1060    if (screen->eng3d->oclass < GM107_3D_CLASS) {
1061       ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1062                            &screen->poly_cache);
1063       if (ret)
1064          FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
1065
1066       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
1067       PUSH_DATAh(push, screen->poly_cache->offset);
1068       PUSH_DATA (push, screen->poly_cache->offset);
1069       PUSH_DATA (push, 3);
1070    }
1071
1072    ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
1073                         &screen->txc);
1074    if (ret)
1075       FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
1076
1077    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
1078    PUSH_DATAh(push, screen->txc->offset);
1079    PUSH_DATA (push, screen->txc->offset);
1080    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
1081    if (screen->eng3d->oclass >= GM107_3D_CLASS) {
1082       screen->tic.maxwell = true;
1083       if (screen->eng3d->oclass == GM107_3D_CLASS) {
1084          screen->tic.maxwell =
1085             debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
1086          IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
1087       }
1088    }
1089
1090    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
1091    PUSH_DATAh(push, screen->txc->offset + 65536);
1092    PUSH_DATA (push, screen->txc->offset + 65536);
1093    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
1094
1095    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
1096    PUSH_DATA (push, 0);
1097    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
1098    PUSH_DATA (push, 0);
1099    PUSH_DATA (push, 0);
1100    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
1101    PUSH_DATA (push, 0x3f);
1102
1103    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
1104    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
1105    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
1106    for (i = 0; i < 8 * 2; ++i)
1107       PUSH_DATA(push, 0);
1108    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
1109    PUSH_DATA (push, 0);
1110    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
1111    PUSH_DATA (push, 0);
1112
1113    /* neither scissors, viewport nor stencil mask should affect clears */
1114    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
1115    PUSH_DATA (push, 0);
1116
1117    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
1118    PUSH_DATA (push, 1);
1119    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1120       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
1121       PUSH_DATAf(push, 0.0f);
1122       PUSH_DATAf(push, 1.0f);
1123    }
1124    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
1125    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
1126
1127    /* We use scissors instead of exact view volume clipping,
1128     * so they're always enabled.
1129     */
1130    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
1131       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
1132       PUSH_DATA (push, 1);
1133       PUSH_DATA (push, 8192 << 16);
1134       PUSH_DATA (push, 8192 << 16);
1135    }
1136
1137 #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
1138
1139    i = 0;
1140    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
1141    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
1142    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
1143    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
1144    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
1145    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
1146    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
1147    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
1148    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
1149    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT_COUNT, mme9097_draw_arrays_indirect_count);
1150    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
1151    MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
1152    MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
1153
1154    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
1155    PUSH_DATA (push, 1);
1156    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
1157    PUSH_DATA (push, 1);
1158    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
1159    PUSH_DATA (push, 0x40);
1160    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
1161    PUSH_DATA (push, 0);
1162    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
1163    PUSH_DATA (push, 0x30);
1164    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
1165    PUSH_DATA (push, 3);
1166    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
1167    PUSH_DATA (push, 0x20);
1168    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
1169    PUSH_DATA (push, 0x00);
1170    screen->save_state.patch_vertices = 3;
1171
1172    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
1173    PUSH_DATA (push, 0);
1174    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
1175    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
1176
1177    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
1178
1179    if (nvc0_screen_init_compute(screen))
1180       goto fail;
1181
1182    /* XXX: Compute and 3D are somehow aliased on Fermi. */
1183    for (i = 0; i < 5; ++i) {
1184       /* TIC and TSC entries for each unit (nve4+ only) */
1185       /* auxiliary constants (6 user clip planes, base instance id) */
1186       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
1187       PUSH_DATA (push, NVC0_CB_AUX_SIZE);
1188       PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1189       PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
1190       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
1191       PUSH_DATA (push, (15 << 4) | 1);
1192       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
1193          unsigned j;
1194          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
1195          PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
1196          for (j = 0; j < 8; ++j)
1197             PUSH_DATA(push, j);
1198       } else {
1199          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
1200          PUSH_DATA (push, 0x54);
1201       }
1202
1203       /* MS sample coordinate offsets: these do not work with _ALT modes ! */
1204       BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
1205       PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
1206       PUSH_DATA (push, 0); /* 0 */
1207       PUSH_DATA (push, 0);
1208       PUSH_DATA (push, 1); /* 1 */
1209       PUSH_DATA (push, 0);
1210       PUSH_DATA (push, 0); /* 2 */
1211       PUSH_DATA (push, 1);
1212       PUSH_DATA (push, 1); /* 3 */
1213       PUSH_DATA (push, 1);
1214       PUSH_DATA (push, 2); /* 4 */
1215       PUSH_DATA (push, 0);
1216       PUSH_DATA (push, 3); /* 5 */
1217       PUSH_DATA (push, 0);
1218       PUSH_DATA (push, 2); /* 6 */
1219       PUSH_DATA (push, 1);
1220       PUSH_DATA (push, 3); /* 7 */
1221       PUSH_DATA (push, 1);
1222    }
1223    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
1224    PUSH_DATA (push, 0);
1225
1226    PUSH_KICK (push);
1227
1228    screen->tic.entries = CALLOC(4096, sizeof(void *));
1229    screen->tsc.entries = screen->tic.entries + 2048;
1230
1231    if (!nvc0_blitter_create(screen))
1232       goto fail;
1233
1234    screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
1235    screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
1236
1237    nouveau_fence_new(&screen->base, &screen->base.fence.current);
1238
1239    return &screen->base;
1240
1241 fail:
1242    screen->base.base.context_create = NULL;
1243    return &screen->base;
1244 }
1245
1246 int
1247 nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
1248 {
1249    int i = screen->tic.next;
1250
1251    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1252       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1253
1254    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
1255
1256    if (screen->tic.entries[i])
1257       nv50_tic_entry(screen->tic.entries[i])->id = -1;
1258
1259    screen->tic.entries[i] = entry;
1260    return i;
1261 }
1262
1263 int
1264 nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
1265 {
1266    int i = screen->tsc.next;
1267
1268    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1269       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1270
1271    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
1272
1273    if (screen->tsc.entries[i])
1274       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1275
1276    screen->tsc.entries[i] = entry;
1277    return i;
1278 }