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nvc0: translate compute shaders at program creation
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_framebuffer.h"
25 #include "util/u_helpers.h"
26 #include "util/u_inlines.h"
27 #include "util/u_transfer.h"
28
29 #include "tgsi/tgsi_parse.h"
30
31 #include "nvc0/nvc0_stateobj.h"
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_query_hw.h"
34
35 #include "nvc0/nvc0_3d.xml.h"
36
37 #include "nouveau_gldefs.h"
38
39 static inline uint32_t
40 nvc0_colormask(unsigned mask)
41 {
42 uint32_t ret = 0;
43
44 if (mask & PIPE_MASK_R)
45 ret |= 0x0001;
46 if (mask & PIPE_MASK_G)
47 ret |= 0x0010;
48 if (mask & PIPE_MASK_B)
49 ret |= 0x0100;
50 if (mask & PIPE_MASK_A)
51 ret |= 0x1000;
52
53 return ret;
54 }
55
56 #define NVC0_BLEND_FACTOR_CASE(a, b) \
57 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
58
59 static inline uint32_t
60 nvc0_blend_fac(unsigned factor)
61 {
62 switch (factor) {
63 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
64 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
65 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
66 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
67 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
68 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
69 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
70 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
71 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
72 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
73 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
74 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
75 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
76 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
77 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
78 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
79 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
80 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
81 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
82 default:
83 return NV50_BLEND_FACTOR_ZERO;
84 }
85 }
86
87 static void *
88 nvc0_blend_state_create(struct pipe_context *pipe,
89 const struct pipe_blend_state *cso)
90 {
91 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
92 int i;
93 int r; /* reference */
94 uint8_t blend_en = 0;
95 bool indep_masks = false;
96 bool indep_funcs = false;
97
98 so->pipe = *cso;
99
100 /* check which states actually have differing values */
101 if (cso->independent_blend_enable) {
102 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
103 blend_en |= 1 << r;
104 for (i = r + 1; i < 8; ++i) {
105 if (!cso->rt[i].blend_enable)
106 continue;
107 blend_en |= 1 << i;
108 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
109 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
110 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
111 cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
112 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
113 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
114 indep_funcs = true;
115 break;
116 }
117 }
118 for (; i < 8; ++i)
119 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
120
121 for (i = 1; i < 8; ++i) {
122 if (cso->rt[i].colormask != cso->rt[0].colormask) {
123 indep_masks = true;
124 break;
125 }
126 }
127 } else {
128 r = 0;
129 if (cso->rt[0].blend_enable)
130 blend_en = 0xff;
131 }
132
133 if (cso->logicop_enable) {
134 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
135 SB_DATA (so, 1);
136 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
137
138 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
139 } else {
140 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
141
142 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
143 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
144 if (indep_funcs) {
145 for (i = 0; i < 8; ++i) {
146 if (cso->rt[i].blend_enable) {
147 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
148 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
149 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
150 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
151 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
152 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
153 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
154 }
155 }
156 } else
157 if (blend_en) {
158 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
159 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
160 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
161 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
162 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
163 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
164 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
165 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
166 }
167
168 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
169 if (indep_masks) {
170 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
171 for (i = 0; i < 8; ++i)
172 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
173 } else {
174 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
175 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
176 }
177 }
178
179 assert(so->size <= ARRAY_SIZE(so->state));
180 return so;
181 }
182
183 static void
184 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
185 {
186 struct nvc0_context *nvc0 = nvc0_context(pipe);
187
188 nvc0->blend = hwcso;
189 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND;
190 }
191
192 static void
193 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
194 {
195 FREE(hwcso);
196 }
197
198 /* NOTE: ignoring line_last_pixel */
199 static void *
200 nvc0_rasterizer_state_create(struct pipe_context *pipe,
201 const struct pipe_rasterizer_state *cso)
202 {
203 struct nvc0_rasterizer_stateobj *so;
204 uint32_t reg;
205
206 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
207 if (!so)
208 return NULL;
209 so->pipe = *cso;
210
211 /* Scissor enables are handled in scissor state, we will not want to
212 * always emit 16 commands, one for each scissor rectangle, here.
213 */
214
215 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
216 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
217
218 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
219 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
220 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
221
222 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
223
224 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
225 if (cso->line_smooth || cso->multisample)
226 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
227 else
228 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
229 SB_DATA (so, fui(cso->line_width));
230
231 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
232 if (cso->line_stipple_enable) {
233 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
234 SB_DATA (so, (cso->line_stipple_pattern << 8) |
235 cso->line_stipple_factor);
236
237 }
238
239 SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
240 if (!cso->point_size_per_vertex) {
241 SB_BEGIN_3D(so, POINT_SIZE, 1);
242 SB_DATA (so, fui(cso->point_size));
243 }
244
245 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
246 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
247 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
248
249 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
250 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
251 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
252 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
253
254 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
255 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
256 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
257 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
258 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
259
260 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
261 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
262 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
263 NVC0_3D_FRONT_FACE_CW);
264 switch (cso->cull_face) {
265 case PIPE_FACE_FRONT_AND_BACK:
266 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
267 break;
268 case PIPE_FACE_FRONT:
269 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
270 break;
271 case PIPE_FACE_BACK:
272 default:
273 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
274 break;
275 }
276
277 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
278 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
279 SB_DATA (so, cso->offset_point);
280 SB_DATA (so, cso->offset_line);
281 SB_DATA (so, cso->offset_tri);
282
283 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
284 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
285 SB_DATA (so, fui(cso->offset_scale));
286 if (!cso->offset_units_unscaled) {
287 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
288 SB_DATA (so, fui(cso->offset_units * 2.0f));
289 }
290 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
291 SB_DATA (so, fui(cso->offset_clamp));
292 }
293
294 if (cso->depth_clip)
295 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
296 else
297 reg =
298 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
299 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
300 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
301 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
302
303 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
304 SB_DATA (so, reg);
305
306 SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
307
308 SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
309
310 assert(so->size <= ARRAY_SIZE(so->state));
311 return (void *)so;
312 }
313
314 static void
315 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
316 {
317 struct nvc0_context *nvc0 = nvc0_context(pipe);
318
319 nvc0->rast = hwcso;
320 nvc0->dirty_3d |= NVC0_NEW_3D_RASTERIZER;
321 }
322
323 static void
324 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
325 {
326 FREE(hwcso);
327 }
328
329 static void *
330 nvc0_zsa_state_create(struct pipe_context *pipe,
331 const struct pipe_depth_stencil_alpha_state *cso)
332 {
333 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
334
335 so->pipe = *cso;
336
337 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
338 if (cso->depth.enabled) {
339 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
340 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
341 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
342 }
343
344 SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth.bounds_test);
345 if (cso->depth.bounds_test) {
346 SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
347 SB_DATA (so, fui(cso->depth.bounds_min));
348 SB_DATA (so, fui(cso->depth.bounds_max));
349 }
350
351 if (cso->stencil[0].enabled) {
352 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
353 SB_DATA (so, 1);
354 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
355 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
356 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
357 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
358 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
359 SB_DATA (so, cso->stencil[0].valuemask);
360 SB_DATA (so, cso->stencil[0].writemask);
361 } else {
362 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
363 }
364
365 if (cso->stencil[1].enabled) {
366 assert(cso->stencil[0].enabled);
367 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
368 SB_DATA (so, 1);
369 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
370 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
371 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
372 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
373 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
374 SB_DATA (so, cso->stencil[1].writemask);
375 SB_DATA (so, cso->stencil[1].valuemask);
376 } else
377 if (cso->stencil[0].enabled) {
378 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
379 }
380
381 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
382 if (cso->alpha.enabled) {
383 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
384 SB_DATA (so, fui(cso->alpha.ref_value));
385 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
386 }
387
388 assert(so->size <= ARRAY_SIZE(so->state));
389 return (void *)so;
390 }
391
392 static void
393 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
394 {
395 struct nvc0_context *nvc0 = nvc0_context(pipe);
396
397 nvc0->zsa = hwcso;
398 nvc0->dirty_3d |= NVC0_NEW_3D_ZSA;
399 }
400
401 static void
402 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
403 {
404 FREE(hwcso);
405 }
406
407 /* ====================== SAMPLERS AND TEXTURES ================================
408 */
409
410 #define NV50_TSC_WRAP_CASE(n) \
411 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
412
413 static void
414 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
415 {
416 unsigned s, i;
417
418 for (s = 0; s < 6; ++s)
419 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
420 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
421 nvc0_context(pipe)->samplers[s][i] = NULL;
422
423 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
424
425 FREE(hwcso);
426 }
427
428 static inline void
429 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0,
430 unsigned s,
431 unsigned nr, void **hwcso)
432 {
433 unsigned i;
434
435 for (i = 0; i < nr; ++i) {
436 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
437
438 if (hwcso[i] == old)
439 continue;
440 nvc0->samplers_dirty[s] |= 1 << i;
441
442 nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
443 if (old)
444 nvc0_screen_tsc_unlock(nvc0->screen, old);
445 }
446 for (; i < nvc0->num_samplers[s]; ++i) {
447 if (nvc0->samplers[s][i]) {
448 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
449 nvc0->samplers[s][i] = NULL;
450 }
451 }
452
453 nvc0->num_samplers[s] = nr;
454 }
455
456 static void
457 nvc0_bind_sampler_states(struct pipe_context *pipe,
458 enum pipe_shader_type shader,
459 unsigned start, unsigned nr, void **samplers)
460 {
461 const unsigned s = nvc0_shader_stage(shader);
462
463 assert(start == 0);
464 nvc0_stage_sampler_states_bind(nvc0_context(pipe), s, nr, samplers);
465
466 if (s == 5)
467 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
468 else
469 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
470 }
471
472
473 /* NOTE: only called when not referenced anywhere, won't be bound */
474 static void
475 nvc0_sampler_view_destroy(struct pipe_context *pipe,
476 struct pipe_sampler_view *view)
477 {
478 pipe_resource_reference(&view->texture, NULL);
479
480 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
481
482 FREE(nv50_tic_entry(view));
483 }
484
485 static inline void
486 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
487 unsigned nr,
488 struct pipe_sampler_view **views)
489 {
490 unsigned i;
491
492 for (i = 0; i < nr; ++i) {
493 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
494
495 if (views[i] == nvc0->textures[s][i])
496 continue;
497 nvc0->textures_dirty[s] |= 1 << i;
498
499 if (views[i] && views[i]->texture) {
500 struct pipe_resource *res = views[i]->texture;
501 if (res->target == PIPE_BUFFER &&
502 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
503 nvc0->textures_coherent[s] |= 1 << i;
504 else
505 nvc0->textures_coherent[s] &= ~(1 << i);
506 } else {
507 nvc0->textures_coherent[s] &= ~(1 << i);
508 }
509
510 if (old) {
511 if (s == 5)
512 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
513 else
514 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
515 nvc0_screen_tic_unlock(nvc0->screen, old);
516 }
517
518 pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
519 }
520
521 for (i = nr; i < nvc0->num_textures[s]; ++i) {
522 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
523 if (old) {
524 if (s == 5)
525 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
526 else
527 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
528 nvc0_screen_tic_unlock(nvc0->screen, old);
529 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
530 }
531 }
532
533 nvc0->num_textures[s] = nr;
534 }
535
536 static void
537 nvc0_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,
538 unsigned start, unsigned nr,
539 struct pipe_sampler_view **views)
540 {
541 const unsigned s = nvc0_shader_stage(shader);
542
543 assert(start == 0);
544 nvc0_stage_set_sampler_views(nvc0_context(pipe), s, nr, views);
545
546 if (s == 5)
547 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
548 else
549 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_TEXTURES;
550 }
551
552 /* ============================= SHADERS =======================================
553 */
554
555 static void *
556 nvc0_sp_state_create(struct pipe_context *pipe,
557 const struct pipe_shader_state *cso, unsigned type)
558 {
559 struct nvc0_program *prog;
560
561 prog = CALLOC_STRUCT(nvc0_program);
562 if (!prog)
563 return NULL;
564
565 prog->type = type;
566
567 if (cso->tokens)
568 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
569
570 if (cso->stream_output.num_outputs)
571 prog->pipe.stream_output = cso->stream_output;
572
573 prog->translated = nvc0_program_translate(
574 prog, nvc0_context(pipe)->screen->base.device->chipset,
575 &nouveau_context(pipe)->debug);
576
577 return (void *)prog;
578 }
579
580 static void
581 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
582 {
583 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
584
585 nvc0_program_destroy(nvc0_context(pipe), prog);
586
587 FREE((void *)prog->pipe.tokens);
588 FREE(prog);
589 }
590
591 static void *
592 nvc0_vp_state_create(struct pipe_context *pipe,
593 const struct pipe_shader_state *cso)
594 {
595 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
596 }
597
598 static void
599 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
600 {
601 struct nvc0_context *nvc0 = nvc0_context(pipe);
602
603 nvc0->vertprog = hwcso;
604 nvc0->dirty_3d |= NVC0_NEW_3D_VERTPROG;
605 }
606
607 static void *
608 nvc0_fp_state_create(struct pipe_context *pipe,
609 const struct pipe_shader_state *cso)
610 {
611 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
612 }
613
614 static void
615 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
616 {
617 struct nvc0_context *nvc0 = nvc0_context(pipe);
618
619 nvc0->fragprog = hwcso;
620 nvc0->dirty_3d |= NVC0_NEW_3D_FRAGPROG;
621 }
622
623 static void *
624 nvc0_gp_state_create(struct pipe_context *pipe,
625 const struct pipe_shader_state *cso)
626 {
627 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
628 }
629
630 static void
631 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
632 {
633 struct nvc0_context *nvc0 = nvc0_context(pipe);
634
635 nvc0->gmtyprog = hwcso;
636 nvc0->dirty_3d |= NVC0_NEW_3D_GMTYPROG;
637 }
638
639 static void *
640 nvc0_tcp_state_create(struct pipe_context *pipe,
641 const struct pipe_shader_state *cso)
642 {
643 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
644 }
645
646 static void
647 nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
648 {
649 struct nvc0_context *nvc0 = nvc0_context(pipe);
650
651 nvc0->tctlprog = hwcso;
652 nvc0->dirty_3d |= NVC0_NEW_3D_TCTLPROG;
653 }
654
655 static void *
656 nvc0_tep_state_create(struct pipe_context *pipe,
657 const struct pipe_shader_state *cso)
658 {
659 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
660 }
661
662 static void
663 nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
664 {
665 struct nvc0_context *nvc0 = nvc0_context(pipe);
666
667 nvc0->tevlprog = hwcso;
668 nvc0->dirty_3d |= NVC0_NEW_3D_TEVLPROG;
669 }
670
671 static void *
672 nvc0_cp_state_create(struct pipe_context *pipe,
673 const struct pipe_compute_state *cso)
674 {
675 struct nvc0_program *prog;
676
677 prog = CALLOC_STRUCT(nvc0_program);
678 if (!prog)
679 return NULL;
680 prog->type = PIPE_SHADER_COMPUTE;
681
682 prog->cp.smem_size = cso->req_local_mem;
683 prog->cp.lmem_size = cso->req_private_mem;
684 prog->parm_size = cso->req_input_mem;
685
686 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
687
688 prog->translated = nvc0_program_translate(
689 prog, nvc0_context(pipe)->screen->base.device->chipset,
690 &nouveau_context(pipe)->debug);
691
692 return (void *)prog;
693 }
694
695 static void
696 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
697 {
698 struct nvc0_context *nvc0 = nvc0_context(pipe);
699
700 nvc0->compprog = hwcso;
701 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
702 }
703
704 static void
705 nvc0_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
706 const struct pipe_constant_buffer *cb)
707 {
708 struct nvc0_context *nvc0 = nvc0_context(pipe);
709 struct pipe_resource *res = cb ? cb->buffer : NULL;
710 const unsigned s = nvc0_shader_stage(shader);
711 const unsigned i = index;
712
713 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
714 if (nvc0->constbuf[s][i].user)
715 nvc0->constbuf[s][i].u.buf = NULL;
716 else
717 if (nvc0->constbuf[s][i].u.buf)
718 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
719
720 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
721 } else {
722 if (nvc0->constbuf[s][i].user)
723 nvc0->constbuf[s][i].u.buf = NULL;
724 else
725 if (nvc0->constbuf[s][i].u.buf)
726 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_CB(s, i));
727
728 nvc0->dirty_3d |= NVC0_NEW_3D_CONSTBUF;
729 }
730 nvc0->constbuf_dirty[s] |= 1 << i;
731
732 if (nvc0->constbuf[s][i].u.buf)
733 nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
734 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
735
736 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
737 if (nvc0->constbuf[s][i].user) {
738 nvc0->constbuf[s][i].u.data = cb->user_buffer;
739 nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
740 nvc0->constbuf_valid[s] |= 1 << i;
741 nvc0->constbuf_coherent[s] &= ~(1 << i);
742 } else
743 if (cb) {
744 nvc0->constbuf[s][i].offset = cb->buffer_offset;
745 nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
746 nvc0->constbuf_valid[s] |= 1 << i;
747 if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
748 nvc0->constbuf_coherent[s] |= 1 << i;
749 else
750 nvc0->constbuf_coherent[s] &= ~(1 << i);
751 }
752 else {
753 nvc0->constbuf_valid[s] &= ~(1 << i);
754 nvc0->constbuf_coherent[s] &= ~(1 << i);
755 }
756 }
757
758 /* =============================================================================
759 */
760
761 static void
762 nvc0_set_blend_color(struct pipe_context *pipe,
763 const struct pipe_blend_color *bcol)
764 {
765 struct nvc0_context *nvc0 = nvc0_context(pipe);
766
767 nvc0->blend_colour = *bcol;
768 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND_COLOUR;
769 }
770
771 static void
772 nvc0_set_stencil_ref(struct pipe_context *pipe,
773 const struct pipe_stencil_ref *sr)
774 {
775 struct nvc0_context *nvc0 = nvc0_context(pipe);
776
777 nvc0->stencil_ref = *sr;
778 nvc0->dirty_3d |= NVC0_NEW_3D_STENCIL_REF;
779 }
780
781 static void
782 nvc0_set_clip_state(struct pipe_context *pipe,
783 const struct pipe_clip_state *clip)
784 {
785 struct nvc0_context *nvc0 = nvc0_context(pipe);
786
787 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
788
789 nvc0->dirty_3d |= NVC0_NEW_3D_CLIP;
790 }
791
792 static void
793 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
794 {
795 struct nvc0_context *nvc0 = nvc0_context(pipe);
796
797 nvc0->sample_mask = sample_mask;
798 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_MASK;
799 }
800
801 static void
802 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
803 {
804 struct nvc0_context *nvc0 = nvc0_context(pipe);
805
806 if (nvc0->min_samples != min_samples) {
807 nvc0->min_samples = min_samples;
808 nvc0->dirty_3d |= NVC0_NEW_3D_MIN_SAMPLES;
809 }
810 }
811
812 static void
813 nvc0_set_framebuffer_state(struct pipe_context *pipe,
814 const struct pipe_framebuffer_state *fb)
815 {
816 struct nvc0_context *nvc0 = nvc0_context(pipe);
817
818 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
819
820 util_copy_framebuffer_state(&nvc0->framebuffer, fb);
821
822 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER;
823 }
824
825 static void
826 nvc0_set_polygon_stipple(struct pipe_context *pipe,
827 const struct pipe_poly_stipple *stipple)
828 {
829 struct nvc0_context *nvc0 = nvc0_context(pipe);
830
831 nvc0->stipple = *stipple;
832 nvc0->dirty_3d |= NVC0_NEW_3D_STIPPLE;
833 }
834
835 static void
836 nvc0_set_scissor_states(struct pipe_context *pipe,
837 unsigned start_slot,
838 unsigned num_scissors,
839 const struct pipe_scissor_state *scissor)
840 {
841 struct nvc0_context *nvc0 = nvc0_context(pipe);
842 int i;
843
844 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
845 for (i = 0; i < num_scissors; i++) {
846 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
847 continue;
848 nvc0->scissors[start_slot + i] = scissor[i];
849 nvc0->scissors_dirty |= 1 << (start_slot + i);
850 nvc0->dirty_3d |= NVC0_NEW_3D_SCISSOR;
851 }
852 }
853
854 static void
855 nvc0_set_viewport_states(struct pipe_context *pipe,
856 unsigned start_slot,
857 unsigned num_viewports,
858 const struct pipe_viewport_state *vpt)
859 {
860 struct nvc0_context *nvc0 = nvc0_context(pipe);
861 int i;
862
863 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
864 for (i = 0; i < num_viewports; i++) {
865 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
866 continue;
867 nvc0->viewports[start_slot + i] = vpt[i];
868 nvc0->viewports_dirty |= 1 << (start_slot + i);
869 nvc0->dirty_3d |= NVC0_NEW_3D_VIEWPORT;
870 }
871
872 }
873
874 static void
875 nvc0_set_window_rectangles(struct pipe_context *pipe,
876 boolean include,
877 unsigned num_rectangles,
878 const struct pipe_scissor_state *rectangles)
879 {
880 struct nvc0_context *nvc0 = nvc0_context(pipe);
881
882 nvc0->window_rect.inclusive = include;
883 nvc0->window_rect.rects = MIN2(num_rectangles, NVC0_MAX_WINDOW_RECTANGLES);
884 memcpy(nvc0->window_rect.rect, rectangles,
885 sizeof(struct pipe_scissor_state) * nvc0->window_rect.rects);
886
887 nvc0->dirty_3d |= NVC0_NEW_3D_WINDOW_RECTS;
888 }
889
890 static void
891 nvc0_set_tess_state(struct pipe_context *pipe,
892 const float default_tess_outer[4],
893 const float default_tess_inner[2])
894 {
895 struct nvc0_context *nvc0 = nvc0_context(pipe);
896
897 memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
898 memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
899 nvc0->dirty_3d |= NVC0_NEW_3D_TESSFACTOR;
900 }
901
902 static void
903 nvc0_set_vertex_buffers(struct pipe_context *pipe,
904 unsigned start_slot, unsigned count,
905 const struct pipe_vertex_buffer *vb)
906 {
907 struct nvc0_context *nvc0 = nvc0_context(pipe);
908 unsigned i;
909
910 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX);
911 nvc0->dirty_3d |= NVC0_NEW_3D_ARRAYS;
912
913 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
914 start_slot, count);
915
916 if (!vb) {
917 nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
918 nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
919 nvc0->vtxbufs_coherent &= ~(((1ull << count) - 1) << start_slot);
920 return;
921 }
922
923 for (i = 0; i < count; ++i) {
924 unsigned dst_index = start_slot + i;
925
926 if (vb[i].user_buffer) {
927 nvc0->vbo_user |= 1 << dst_index;
928 if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
929 nvc0->constant_vbos |= 1 << dst_index;
930 else
931 nvc0->constant_vbos &= ~(1 << dst_index);
932 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
933 } else {
934 nvc0->vbo_user &= ~(1 << dst_index);
935 nvc0->constant_vbos &= ~(1 << dst_index);
936
937 if (vb[i].buffer &&
938 vb[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
939 nvc0->vtxbufs_coherent |= (1 << dst_index);
940 else
941 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
942 }
943 }
944 }
945
946 static void
947 nvc0_set_index_buffer(struct pipe_context *pipe,
948 const struct pipe_index_buffer *ib)
949 {
950 struct nvc0_context *nvc0 = nvc0_context(pipe);
951
952 if (nvc0->idxbuf.buffer)
953 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_IDX);
954
955 if (ib) {
956 pipe_resource_reference(&nvc0->idxbuf.buffer, ib->buffer);
957 nvc0->idxbuf.index_size = ib->index_size;
958 if (ib->buffer) {
959 nvc0->idxbuf.offset = ib->offset;
960 nvc0->dirty_3d |= NVC0_NEW_3D_IDXBUF;
961 } else {
962 nvc0->idxbuf.user_buffer = ib->user_buffer;
963 nvc0->dirty_3d &= ~NVC0_NEW_3D_IDXBUF;
964 }
965 } else {
966 nvc0->dirty_3d &= ~NVC0_NEW_3D_IDXBUF;
967 pipe_resource_reference(&nvc0->idxbuf.buffer, NULL);
968 }
969 }
970
971 static void
972 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
973 {
974 struct nvc0_context *nvc0 = nvc0_context(pipe);
975
976 nvc0->vertex = hwcso;
977 nvc0->dirty_3d |= NVC0_NEW_3D_VERTEX;
978 }
979
980 static struct pipe_stream_output_target *
981 nvc0_so_target_create(struct pipe_context *pipe,
982 struct pipe_resource *res,
983 unsigned offset, unsigned size)
984 {
985 struct nv04_resource *buf = (struct nv04_resource *)res;
986 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
987 if (!targ)
988 return NULL;
989
990 targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0);
991 if (!targ->pq) {
992 FREE(targ);
993 return NULL;
994 }
995 targ->clean = true;
996
997 targ->pipe.buffer_size = size;
998 targ->pipe.buffer_offset = offset;
999 targ->pipe.context = pipe;
1000 targ->pipe.buffer = NULL;
1001 pipe_resource_reference(&targ->pipe.buffer, res);
1002 pipe_reference_init(&targ->pipe.reference, 1);
1003
1004 assert(buf->base.target == PIPE_BUFFER);
1005 util_range_add(&buf->valid_buffer_range, offset, offset + size);
1006
1007 return &targ->pipe;
1008 }
1009
1010 static void
1011 nvc0_so_target_save_offset(struct pipe_context *pipe,
1012 struct pipe_stream_output_target *ptarg,
1013 unsigned index, bool *serialize)
1014 {
1015 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1016
1017 if (*serialize) {
1018 *serialize = false;
1019 PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
1020 IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
1021
1022 NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
1023 }
1024
1025 nvc0_query(targ->pq)->index = index;
1026 pipe->end_query(pipe, targ->pq);
1027 }
1028
1029 static void
1030 nvc0_so_target_destroy(struct pipe_context *pipe,
1031 struct pipe_stream_output_target *ptarg)
1032 {
1033 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1034 pipe->destroy_query(pipe, targ->pq);
1035 pipe_resource_reference(&targ->pipe.buffer, NULL);
1036 FREE(targ);
1037 }
1038
1039 static void
1040 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1041 unsigned num_targets,
1042 struct pipe_stream_output_target **targets,
1043 const unsigned *offsets)
1044 {
1045 struct nvc0_context *nvc0 = nvc0_context(pipe);
1046 unsigned i;
1047 bool serialize = true;
1048
1049 assert(num_targets <= 4);
1050
1051 for (i = 0; i < num_targets; ++i) {
1052 const bool changed = nvc0->tfbbuf[i] != targets[i];
1053 const bool append = (offsets[i] == ((unsigned)-1));
1054 if (!changed && append)
1055 continue;
1056 nvc0->tfbbuf_dirty |= 1 << i;
1057
1058 if (nvc0->tfbbuf[i] && changed)
1059 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1060
1061 if (targets[i] && !append)
1062 nvc0_so_target(targets[i])->clean = true;
1063
1064 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1065 }
1066 for (; i < nvc0->num_tfbbufs; ++i) {
1067 if (nvc0->tfbbuf[i]) {
1068 nvc0->tfbbuf_dirty |= 1 << i;
1069 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1070 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1071 }
1072 }
1073 nvc0->num_tfbbufs = num_targets;
1074
1075 if (nvc0->tfbbuf_dirty) {
1076 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TFB);
1077 nvc0->dirty_3d |= NVC0_NEW_3D_TFB_TARGETS;
1078 }
1079 }
1080
1081 static void
1082 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1083 unsigned start, unsigned nr,
1084 struct pipe_surface **psurfaces)
1085 {
1086 const unsigned end = start + nr;
1087 const unsigned mask = ((1 << nr) - 1) << start;
1088 unsigned i;
1089
1090 if (psurfaces) {
1091 for (i = start; i < end; ++i) {
1092 const unsigned p = i - start;
1093 if (psurfaces[p])
1094 nvc0->surfaces_valid[t] |= (1 << i);
1095 else
1096 nvc0->surfaces_valid[t] &= ~(1 << i);
1097 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1098 }
1099 } else {
1100 for (i = start; i < end; ++i)
1101 pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1102 nvc0->surfaces_valid[t] &= ~mask;
1103 }
1104 nvc0->surfaces_dirty[t] |= mask;
1105
1106 if (t == 0)
1107 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1108 else
1109 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1110 }
1111
1112 static void
1113 nvc0_set_compute_resources(struct pipe_context *pipe,
1114 unsigned start, unsigned nr,
1115 struct pipe_surface **resources)
1116 {
1117 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1118
1119 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1120 }
1121
1122 static bool
1123 nvc0_bind_images_range(struct nvc0_context *nvc0, const unsigned s,
1124 unsigned start, unsigned nr,
1125 const struct pipe_image_view *pimages)
1126 {
1127 const unsigned end = start + nr;
1128 unsigned mask = 0;
1129 unsigned i;
1130
1131 assert(s < 6);
1132
1133 if (pimages) {
1134 for (i = start; i < end; ++i) {
1135 struct pipe_image_view *img = &nvc0->images[s][i];
1136 const unsigned p = i - start;
1137
1138 if (img->resource == pimages[p].resource &&
1139 img->format == pimages[p].format &&
1140 img->access == pimages[p].access) {
1141 if (img->resource == NULL)
1142 continue;
1143 if (img->resource->target == PIPE_BUFFER &&
1144 img->u.buf.offset == pimages[p].u.buf.offset &&
1145 img->u.buf.size == pimages[p].u.buf.size)
1146 continue;
1147 if (img->resource->target != PIPE_BUFFER &&
1148 img->u.tex.first_layer == pimages[p].u.tex.first_layer &&
1149 img->u.tex.last_layer == pimages[p].u.tex.last_layer &&
1150 img->u.tex.level == pimages[p].u.tex.level)
1151 continue;
1152 }
1153
1154 mask |= (1 << i);
1155 if (pimages[p].resource)
1156 nvc0->images_valid[s] |= (1 << i);
1157 else
1158 nvc0->images_valid[s] &= ~(1 << i);
1159
1160 img->format = pimages[p].format;
1161 img->access = pimages[p].access;
1162 if (pimages[p].resource && pimages[p].resource->target == PIPE_BUFFER)
1163 img->u.buf = pimages[p].u.buf;
1164 else
1165 img->u.tex = pimages[p].u.tex;
1166
1167 pipe_resource_reference(
1168 &img->resource, pimages[p].resource);
1169
1170 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1171 if (nvc0->images_tic[s][i]) {
1172 struct nv50_tic_entry *old =
1173 nv50_tic_entry(nvc0->images_tic[s][i]);
1174 nvc0_screen_tic_unlock(nvc0->screen, old);
1175 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1176 }
1177
1178 nvc0->images_tic[s][i] =
1179 gm107_create_texture_view_from_image(&nvc0->base.pipe,
1180 &pimages[p]);
1181 }
1182 }
1183 if (!mask)
1184 return false;
1185 } else {
1186 mask = ((1 << nr) - 1) << start;
1187 if (!(nvc0->images_valid[s] & mask))
1188 return false;
1189 for (i = start; i < end; ++i) {
1190 pipe_resource_reference(&nvc0->images[s][i].resource, NULL);
1191 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1192 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->images_tic[s][i]);
1193 if (old) {
1194 nvc0_screen_tic_unlock(nvc0->screen, old);
1195 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1196 }
1197 }
1198 }
1199 nvc0->images_valid[s] &= ~mask;
1200 }
1201 nvc0->images_dirty[s] |= mask;
1202
1203 if (s == 5)
1204 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1205 else
1206 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1207
1208 return true;
1209 }
1210
1211 static void
1212 nvc0_set_shader_images(struct pipe_context *pipe,
1213 enum pipe_shader_type shader,
1214 unsigned start, unsigned nr,
1215 const struct pipe_image_view *images)
1216 {
1217 const unsigned s = nvc0_shader_stage(shader);
1218 if (!nvc0_bind_images_range(nvc0_context(pipe), s, start, nr, images))
1219 return;
1220
1221 if (s == 5)
1222 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1223 else
1224 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SURFACES;
1225 }
1226
1227 static bool
1228 nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t,
1229 unsigned start, unsigned nr,
1230 const struct pipe_shader_buffer *pbuffers)
1231 {
1232 const unsigned end = start + nr;
1233 unsigned mask = 0;
1234 unsigned i;
1235
1236 assert(t < 6);
1237
1238 if (pbuffers) {
1239 for (i = start; i < end; ++i) {
1240 struct pipe_shader_buffer *buf = &nvc0->buffers[t][i];
1241 const unsigned p = i - start;
1242 if (buf->buffer == pbuffers[p].buffer &&
1243 buf->buffer_offset == pbuffers[p].buffer_offset &&
1244 buf->buffer_size == pbuffers[p].buffer_size)
1245 continue;
1246
1247 mask |= (1 << i);
1248 if (pbuffers[p].buffer)
1249 nvc0->buffers_valid[t] |= (1 << i);
1250 else
1251 nvc0->buffers_valid[t] &= ~(1 << i);
1252 buf->buffer_offset = pbuffers[p].buffer_offset;
1253 buf->buffer_size = pbuffers[p].buffer_size;
1254 pipe_resource_reference(&buf->buffer, pbuffers[p].buffer);
1255 }
1256 if (!mask)
1257 return false;
1258 } else {
1259 mask = ((1 << nr) - 1) << start;
1260 if (!(nvc0->buffers_valid[t] & mask))
1261 return false;
1262 for (i = start; i < end; ++i)
1263 pipe_resource_reference(&nvc0->buffers[t][i].buffer, NULL);
1264 nvc0->buffers_valid[t] &= ~mask;
1265 }
1266 nvc0->buffers_dirty[t] |= mask;
1267
1268 if (t == 5)
1269 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF);
1270 else
1271 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BUF);
1272
1273 return true;
1274 }
1275
1276 static void
1277 nvc0_set_shader_buffers(struct pipe_context *pipe,
1278 enum pipe_shader_type shader,
1279 unsigned start, unsigned nr,
1280 const struct pipe_shader_buffer *buffers)
1281 {
1282 const unsigned s = nvc0_shader_stage(shader);
1283 if (!nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers))
1284 return;
1285
1286 if (s == 5)
1287 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_BUFFERS;
1288 else
1289 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_BUFFERS;
1290 }
1291
1292 static inline void
1293 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1294 {
1295 struct nv04_resource *buf = nv04_resource(res);
1296 if (buf) {
1297 uint64_t limit = (buf->address + buf->base.width0) - 1;
1298 if (limit < (1ULL << 32)) {
1299 *phandle = (uint32_t)buf->address;
1300 } else {
1301 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1302 "resource not contained within 32-bit address space !\n");
1303 *phandle = 0;
1304 }
1305 } else {
1306 *phandle = 0;
1307 }
1308 }
1309
1310 static void
1311 nvc0_set_global_bindings(struct pipe_context *pipe,
1312 unsigned start, unsigned nr,
1313 struct pipe_resource **resources,
1314 uint32_t **handles)
1315 {
1316 struct nvc0_context *nvc0 = nvc0_context(pipe);
1317 struct pipe_resource **ptr;
1318 unsigned i;
1319 const unsigned end = start + nr;
1320
1321 if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1322 const unsigned old_size = nvc0->global_residents.size;
1323 const unsigned req_size = end * sizeof(struct pipe_resource *);
1324 util_dynarray_resize(&nvc0->global_residents, req_size);
1325 memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1326 req_size - old_size);
1327 }
1328
1329 if (resources) {
1330 ptr = util_dynarray_element(
1331 &nvc0->global_residents, struct pipe_resource *, start);
1332 for (i = 0; i < nr; ++i) {
1333 pipe_resource_reference(&ptr[i], resources[i]);
1334 nvc0_set_global_handle(handles[i], resources[i]);
1335 }
1336 } else {
1337 ptr = util_dynarray_element(
1338 &nvc0->global_residents, struct pipe_resource *, start);
1339 for (i = 0; i < nr; ++i)
1340 pipe_resource_reference(&ptr[i], NULL);
1341 }
1342
1343 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1344
1345 nvc0->dirty_cp |= NVC0_NEW_CP_GLOBALS;
1346 }
1347
1348 void
1349 nvc0_init_state_functions(struct nvc0_context *nvc0)
1350 {
1351 struct pipe_context *pipe = &nvc0->base.pipe;
1352
1353 pipe->create_blend_state = nvc0_blend_state_create;
1354 pipe->bind_blend_state = nvc0_blend_state_bind;
1355 pipe->delete_blend_state = nvc0_blend_state_delete;
1356
1357 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1358 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1359 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1360
1361 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1362 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1363 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1364
1365 pipe->create_sampler_state = nv50_sampler_state_create;
1366 pipe->delete_sampler_state = nvc0_sampler_state_delete;
1367 pipe->bind_sampler_states = nvc0_bind_sampler_states;
1368
1369 pipe->create_sampler_view = nvc0_create_sampler_view;
1370 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1371 pipe->set_sampler_views = nvc0_set_sampler_views;
1372
1373 pipe->create_vs_state = nvc0_vp_state_create;
1374 pipe->create_fs_state = nvc0_fp_state_create;
1375 pipe->create_gs_state = nvc0_gp_state_create;
1376 pipe->create_tcs_state = nvc0_tcp_state_create;
1377 pipe->create_tes_state = nvc0_tep_state_create;
1378 pipe->bind_vs_state = nvc0_vp_state_bind;
1379 pipe->bind_fs_state = nvc0_fp_state_bind;
1380 pipe->bind_gs_state = nvc0_gp_state_bind;
1381 pipe->bind_tcs_state = nvc0_tcp_state_bind;
1382 pipe->bind_tes_state = nvc0_tep_state_bind;
1383 pipe->delete_vs_state = nvc0_sp_state_delete;
1384 pipe->delete_fs_state = nvc0_sp_state_delete;
1385 pipe->delete_gs_state = nvc0_sp_state_delete;
1386 pipe->delete_tcs_state = nvc0_sp_state_delete;
1387 pipe->delete_tes_state = nvc0_sp_state_delete;
1388
1389 pipe->create_compute_state = nvc0_cp_state_create;
1390 pipe->bind_compute_state = nvc0_cp_state_bind;
1391 pipe->delete_compute_state = nvc0_sp_state_delete;
1392
1393 pipe->set_blend_color = nvc0_set_blend_color;
1394 pipe->set_stencil_ref = nvc0_set_stencil_ref;
1395 pipe->set_clip_state = nvc0_set_clip_state;
1396 pipe->set_sample_mask = nvc0_set_sample_mask;
1397 pipe->set_min_samples = nvc0_set_min_samples;
1398 pipe->set_constant_buffer = nvc0_set_constant_buffer;
1399 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1400 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1401 pipe->set_scissor_states = nvc0_set_scissor_states;
1402 pipe->set_viewport_states = nvc0_set_viewport_states;
1403 pipe->set_window_rectangles = nvc0_set_window_rectangles;
1404 pipe->set_tess_state = nvc0_set_tess_state;
1405
1406 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1407 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1408 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1409
1410 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1411 pipe->set_index_buffer = nvc0_set_index_buffer;
1412
1413 pipe->create_stream_output_target = nvc0_so_target_create;
1414 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1415 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1416
1417 pipe->set_global_binding = nvc0_set_global_bindings;
1418 pipe->set_compute_resources = nvc0_set_compute_resources;
1419 pipe->set_shader_images = nvc0_set_shader_images;
1420 pipe->set_shader_buffers = nvc0_set_shader_buffers;
1421
1422 nvc0->sample_mask = ~0;
1423 nvc0->min_samples = 1;
1424 nvc0->default_tess_outer[0] =
1425 nvc0->default_tess_outer[1] =
1426 nvc0->default_tess_outer[2] =
1427 nvc0->default_tess_outer[3] = 1.0;
1428 nvc0->default_tess_inner[0] =
1429 nvc0->default_tess_inner[1] = 1.0;
1430 }