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nv50,nvc0: Remove duplicate logic from nvc0_set_framebuffer_state()
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_framebuffer.h"
25 #include "util/u_helpers.h"
26 #include "util/u_inlines.h"
27 #include "util/u_transfer.h"
28
29 #include "tgsi/tgsi_parse.h"
30
31 #include "nvc0/nvc0_stateobj.h"
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_query_hw.h"
34
35 #include "nvc0/nvc0_3d.xml.h"
36 #include "nv50/nv50_texture.xml.h"
37
38 #include "nouveau_gldefs.h"
39
40 static inline uint32_t
41 nvc0_colormask(unsigned mask)
42 {
43 uint32_t ret = 0;
44
45 if (mask & PIPE_MASK_R)
46 ret |= 0x0001;
47 if (mask & PIPE_MASK_G)
48 ret |= 0x0010;
49 if (mask & PIPE_MASK_B)
50 ret |= 0x0100;
51 if (mask & PIPE_MASK_A)
52 ret |= 0x1000;
53
54 return ret;
55 }
56
57 #define NVC0_BLEND_FACTOR_CASE(a, b) \
58 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
59
60 static inline uint32_t
61 nvc0_blend_fac(unsigned factor)
62 {
63 switch (factor) {
64 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
65 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
66 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
67 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
68 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
69 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
70 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
71 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
72 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
73 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
74 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
75 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
76 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
77 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
78 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
79 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
80 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
81 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
82 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
83 default:
84 return NV50_BLEND_FACTOR_ZERO;
85 }
86 }
87
88 static void *
89 nvc0_blend_state_create(struct pipe_context *pipe,
90 const struct pipe_blend_state *cso)
91 {
92 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
93 int i;
94 int r; /* reference */
95 uint8_t blend_en = 0;
96 bool indep_masks = false;
97 bool indep_funcs = false;
98
99 so->pipe = *cso;
100
101 /* check which states actually have differing values */
102 if (cso->independent_blend_enable) {
103 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
104 blend_en |= 1 << r;
105 for (i = r + 1; i < 8; ++i) {
106 if (!cso->rt[i].blend_enable)
107 continue;
108 blend_en |= 1 << i;
109 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
110 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
111 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
112 cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
113 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
114 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
115 indep_funcs = true;
116 break;
117 }
118 }
119 for (; i < 8; ++i)
120 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
121
122 for (i = 1; i < 8; ++i) {
123 if (cso->rt[i].colormask != cso->rt[0].colormask) {
124 indep_masks = true;
125 break;
126 }
127 }
128 } else {
129 r = 0;
130 if (cso->rt[0].blend_enable)
131 blend_en = 0xff;
132 }
133
134 if (cso->logicop_enable) {
135 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
136 SB_DATA (so, 1);
137 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
138
139 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
140 } else {
141 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
142
143 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
144 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
145 if (indep_funcs) {
146 for (i = 0; i < 8; ++i) {
147 if (cso->rt[i].blend_enable) {
148 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
149 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
150 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
151 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
152 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
153 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
154 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
155 }
156 }
157 } else
158 if (blend_en) {
159 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
160 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
161 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
162 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
163 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
164 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
165 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
166 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
167 }
168
169 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
170 if (indep_masks) {
171 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
172 for (i = 0; i < 8; ++i)
173 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
174 } else {
175 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
176 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
177 }
178 }
179
180 assert(so->size <= ARRAY_SIZE(so->state));
181 return so;
182 }
183
184 static void
185 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
186 {
187 struct nvc0_context *nvc0 = nvc0_context(pipe);
188
189 nvc0->blend = hwcso;
190 nvc0->dirty |= NVC0_NEW_BLEND;
191 }
192
193 static void
194 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
195 {
196 FREE(hwcso);
197 }
198
199 /* NOTE: ignoring line_last_pixel */
200 static void *
201 nvc0_rasterizer_state_create(struct pipe_context *pipe,
202 const struct pipe_rasterizer_state *cso)
203 {
204 struct nvc0_rasterizer_stateobj *so;
205 uint32_t reg;
206
207 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
208 if (!so)
209 return NULL;
210 so->pipe = *cso;
211
212 /* Scissor enables are handled in scissor state, we will not want to
213 * always emit 16 commands, one for each scissor rectangle, here.
214 */
215
216 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
217 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
218
219 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
220 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
221 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
222
223 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
224
225 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
226 if (cso->line_smooth || cso->multisample)
227 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
228 else
229 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
230 SB_DATA (so, fui(cso->line_width));
231
232 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
233 if (cso->line_stipple_enable) {
234 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
235 SB_DATA (so, (cso->line_stipple_pattern << 8) |
236 cso->line_stipple_factor);
237
238 }
239
240 SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
241 if (!cso->point_size_per_vertex) {
242 SB_BEGIN_3D(so, POINT_SIZE, 1);
243 SB_DATA (so, fui(cso->point_size));
244 }
245
246 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
247 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
248 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
249
250 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
251 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
252 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
253 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
254
255 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
256 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
257 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
258 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
259 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
260
261 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
262 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
263 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
264 NVC0_3D_FRONT_FACE_CW);
265 switch (cso->cull_face) {
266 case PIPE_FACE_FRONT_AND_BACK:
267 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
268 break;
269 case PIPE_FACE_FRONT:
270 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
271 break;
272 case PIPE_FACE_BACK:
273 default:
274 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
275 break;
276 }
277
278 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
279 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
280 SB_DATA (so, cso->offset_point);
281 SB_DATA (so, cso->offset_line);
282 SB_DATA (so, cso->offset_tri);
283
284 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
285 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
286 SB_DATA (so, fui(cso->offset_scale));
287 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
288 SB_DATA (so, fui(cso->offset_units * 2.0f));
289 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
290 SB_DATA (so, fui(cso->offset_clamp));
291 }
292
293 if (cso->depth_clip)
294 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
295 else
296 reg =
297 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
298 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
299 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
300 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
301
302 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
303 SB_DATA (so, reg);
304
305 SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
306
307 SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
308
309 assert(so->size <= ARRAY_SIZE(so->state));
310 return (void *)so;
311 }
312
313 static void
314 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
315 {
316 struct nvc0_context *nvc0 = nvc0_context(pipe);
317
318 nvc0->rast = hwcso;
319 nvc0->dirty |= NVC0_NEW_RASTERIZER;
320 }
321
322 static void
323 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
324 {
325 FREE(hwcso);
326 }
327
328 static void *
329 nvc0_zsa_state_create(struct pipe_context *pipe,
330 const struct pipe_depth_stencil_alpha_state *cso)
331 {
332 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
333
334 so->pipe = *cso;
335
336 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
337 if (cso->depth.enabled) {
338 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
339 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
340 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
341 }
342
343 SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth.bounds_test);
344 if (cso->depth.bounds_test) {
345 SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
346 SB_DATA (so, fui(cso->depth.bounds_min));
347 SB_DATA (so, fui(cso->depth.bounds_max));
348 }
349
350 if (cso->stencil[0].enabled) {
351 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
352 SB_DATA (so, 1);
353 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
354 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
355 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
356 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
357 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
358 SB_DATA (so, cso->stencil[0].valuemask);
359 SB_DATA (so, cso->stencil[0].writemask);
360 } else {
361 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
362 }
363
364 if (cso->stencil[1].enabled) {
365 assert(cso->stencil[0].enabled);
366 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
367 SB_DATA (so, 1);
368 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
369 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
370 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
371 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
372 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
373 SB_DATA (so, cso->stencil[1].writemask);
374 SB_DATA (so, cso->stencil[1].valuemask);
375 } else
376 if (cso->stencil[0].enabled) {
377 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
378 }
379
380 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
381 if (cso->alpha.enabled) {
382 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
383 SB_DATA (so, fui(cso->alpha.ref_value));
384 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
385 }
386
387 assert(so->size <= ARRAY_SIZE(so->state));
388 return (void *)so;
389 }
390
391 static void
392 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
393 {
394 struct nvc0_context *nvc0 = nvc0_context(pipe);
395
396 nvc0->zsa = hwcso;
397 nvc0->dirty |= NVC0_NEW_ZSA;
398 }
399
400 static void
401 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
402 {
403 FREE(hwcso);
404 }
405
406 /* ====================== SAMPLERS AND TEXTURES ================================
407 */
408
409 #define NV50_TSC_WRAP_CASE(n) \
410 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
411
412 static void
413 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
414 {
415 unsigned s, i;
416
417 for (s = 0; s < 5; ++s)
418 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
419 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
420 nvc0_context(pipe)->samplers[s][i] = NULL;
421
422 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
423
424 FREE(hwcso);
425 }
426
427 static inline void
428 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0, int s,
429 unsigned nr, void **hwcso)
430 {
431 unsigned i;
432
433 for (i = 0; i < nr; ++i) {
434 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
435
436 if (hwcso[i] == old)
437 continue;
438 nvc0->samplers_dirty[s] |= 1 << i;
439
440 nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
441 if (old)
442 nvc0_screen_tsc_unlock(nvc0->screen, old);
443 }
444 for (; i < nvc0->num_samplers[s]; ++i) {
445 if (nvc0->samplers[s][i]) {
446 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
447 nvc0->samplers[s][i] = NULL;
448 }
449 }
450
451 nvc0->num_samplers[s] = nr;
452
453 nvc0->dirty |= NVC0_NEW_SAMPLERS;
454 }
455
456 static void
457 nvc0_stage_sampler_states_bind_range(struct nvc0_context *nvc0,
458 const unsigned s,
459 unsigned start, unsigned nr, void **cso)
460 {
461 const unsigned end = start + nr;
462 int last_valid = -1;
463 unsigned i;
464
465 if (cso) {
466 for (i = start; i < end; ++i) {
467 const unsigned p = i - start;
468 if (cso[p])
469 last_valid = i;
470 if (cso[p] == nvc0->samplers[s][i])
471 continue;
472 nvc0->samplers_dirty[s] |= 1 << i;
473
474 if (nvc0->samplers[s][i])
475 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
476 nvc0->samplers[s][i] = cso[p];
477 }
478 } else {
479 for (i = start; i < end; ++i) {
480 if (nvc0->samplers[s][i]) {
481 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
482 nvc0->samplers[s][i] = NULL;
483 nvc0->samplers_dirty[s] |= 1 << i;
484 }
485 }
486 }
487
488 if (nvc0->num_samplers[s] <= end) {
489 if (last_valid < 0) {
490 for (i = start; i && !nvc0->samplers[s][i - 1]; --i);
491 nvc0->num_samplers[s] = i;
492 } else {
493 nvc0->num_samplers[s] = last_valid + 1;
494 }
495 }
496 }
497
498 static void
499 nvc0_bind_sampler_states(struct pipe_context *pipe, unsigned shader,
500 unsigned start, unsigned nr, void **s)
501 {
502 switch (shader) {
503 case PIPE_SHADER_VERTEX:
504 assert(start == 0);
505 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 0, nr, s);
506 break;
507 case PIPE_SHADER_TESS_CTRL:
508 assert(start == 0);
509 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 1, nr, s);
510 break;
511 case PIPE_SHADER_TESS_EVAL:
512 assert(start == 0);
513 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 2, nr, s);
514 break;
515 case PIPE_SHADER_GEOMETRY:
516 assert(start == 0);
517 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 3, nr, s);
518 break;
519 case PIPE_SHADER_FRAGMENT:
520 assert(start == 0);
521 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 4, nr, s);
522 break;
523 case PIPE_SHADER_COMPUTE:
524 nvc0_stage_sampler_states_bind_range(nvc0_context(pipe), 5,
525 start, nr, s);
526 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
527 break;
528 }
529 }
530
531
532 /* NOTE: only called when not referenced anywhere, won't be bound */
533 static void
534 nvc0_sampler_view_destroy(struct pipe_context *pipe,
535 struct pipe_sampler_view *view)
536 {
537 pipe_resource_reference(&view->texture, NULL);
538
539 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
540
541 FREE(nv50_tic_entry(view));
542 }
543
544 static inline void
545 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
546 unsigned nr,
547 struct pipe_sampler_view **views)
548 {
549 unsigned i;
550
551 for (i = 0; i < nr; ++i) {
552 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
553
554 if (views[i] == nvc0->textures[s][i])
555 continue;
556 nvc0->textures_dirty[s] |= 1 << i;
557
558 if (views[i] && views[i]->texture) {
559 struct pipe_resource *res = views[i]->texture;
560 if (res->target == PIPE_BUFFER &&
561 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
562 nvc0->textures_coherent[s] |= 1 << i;
563 else
564 nvc0->textures_coherent[s] &= ~(1 << i);
565 } else {
566 nvc0->textures_coherent[s] &= ~(1 << i);
567 }
568
569 if (old) {
570 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(s, i));
571 nvc0_screen_tic_unlock(nvc0->screen, old);
572 }
573
574 pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
575 }
576
577 for (i = nr; i < nvc0->num_textures[s]; ++i) {
578 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
579 if (old) {
580 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(s, i));
581 nvc0_screen_tic_unlock(nvc0->screen, old);
582 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
583 }
584 }
585
586 nvc0->num_textures[s] = nr;
587
588 nvc0->dirty |= NVC0_NEW_TEXTURES;
589 }
590
591 static void
592 nvc0_stage_set_sampler_views_range(struct nvc0_context *nvc0, const unsigned s,
593 unsigned start, unsigned nr,
594 struct pipe_sampler_view **views)
595 {
596 struct nouveau_bufctx *bctx = (s == 5) ? nvc0->bufctx_cp : nvc0->bufctx_3d;
597 const unsigned end = start + nr;
598 const unsigned bin = (s == 5) ? NVC0_BIND_CP_TEX(0) : NVC0_BIND_TEX(s, 0);
599 int last_valid = -1;
600 unsigned i;
601
602 if (views) {
603 for (i = start; i < end; ++i) {
604 const unsigned p = i - start;
605 if (views[p])
606 last_valid = i;
607 if (views[p] == nvc0->textures[s][i])
608 continue;
609 nvc0->textures_dirty[s] |= 1 << i;
610
611 if (views[p] && views[p]->texture) {
612 struct pipe_resource *res = views[p]->texture;
613 if (res->target == PIPE_BUFFER &&
614 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
615 nvc0->textures_coherent[s] |= 1 << i;
616 else
617 nvc0->textures_coherent[s] &= ~(1 << i);
618 } else {
619 nvc0->textures_coherent[s] &= ~(1 << i);
620 }
621
622 if (nvc0->textures[s][i]) {
623 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
624 nouveau_bufctx_reset(bctx, bin + i);
625 nvc0_screen_tic_unlock(nvc0->screen, old);
626 }
627 pipe_sampler_view_reference(&nvc0->textures[s][i], views[p]);
628 }
629 } else {
630 for (i = start; i < end; ++i) {
631 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
632 if (!old)
633 continue;
634 nvc0->textures_dirty[s] |= 1 << i;
635
636 nvc0_screen_tic_unlock(nvc0->screen, old);
637 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
638 nouveau_bufctx_reset(bctx, bin + i);
639 }
640 }
641
642 if (nvc0->num_textures[s] <= end) {
643 if (last_valid < 0) {
644 for (i = start; i && !nvc0->textures[s][i - 1]; --i);
645 nvc0->num_textures[s] = i;
646 } else {
647 nvc0->num_textures[s] = last_valid + 1;
648 }
649 }
650 }
651
652 static void
653 nvc0_set_sampler_views(struct pipe_context *pipe, unsigned shader,
654 unsigned start, unsigned nr,
655 struct pipe_sampler_view **views)
656 {
657 assert(start == 0);
658 switch (shader) {
659 case PIPE_SHADER_VERTEX:
660 nvc0_stage_set_sampler_views(nvc0_context(pipe), 0, nr, views);
661 break;
662 case PIPE_SHADER_TESS_CTRL:
663 nvc0_stage_set_sampler_views(nvc0_context(pipe), 1, nr, views);
664 break;
665 case PIPE_SHADER_TESS_EVAL:
666 nvc0_stage_set_sampler_views(nvc0_context(pipe), 2, nr, views);
667 break;
668 case PIPE_SHADER_GEOMETRY:
669 nvc0_stage_set_sampler_views(nvc0_context(pipe), 3, nr, views);
670 break;
671 case PIPE_SHADER_FRAGMENT:
672 nvc0_stage_set_sampler_views(nvc0_context(pipe), 4, nr, views);
673 break;
674 case PIPE_SHADER_COMPUTE:
675 nvc0_stage_set_sampler_views_range(nvc0_context(pipe), 5,
676 start, nr, views);
677 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
678 break;
679 default:
680 ;
681 }
682 }
683
684
685 /* ============================= SHADERS =======================================
686 */
687
688 static void *
689 nvc0_sp_state_create(struct pipe_context *pipe,
690 const struct pipe_shader_state *cso, unsigned type)
691 {
692 struct nvc0_program *prog;
693
694 prog = CALLOC_STRUCT(nvc0_program);
695 if (!prog)
696 return NULL;
697
698 prog->type = type;
699
700 if (cso->tokens)
701 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
702
703 if (cso->stream_output.num_outputs)
704 prog->pipe.stream_output = cso->stream_output;
705
706 prog->translated = nvc0_program_translate(
707 prog, nvc0_context(pipe)->screen->base.device->chipset,
708 &nouveau_context(pipe)->debug);
709
710 return (void *)prog;
711 }
712
713 static void
714 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
715 {
716 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
717
718 nvc0_program_destroy(nvc0_context(pipe), prog);
719
720 FREE((void *)prog->pipe.tokens);
721 FREE(prog);
722 }
723
724 static void *
725 nvc0_vp_state_create(struct pipe_context *pipe,
726 const struct pipe_shader_state *cso)
727 {
728 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
729 }
730
731 static void
732 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
733 {
734 struct nvc0_context *nvc0 = nvc0_context(pipe);
735
736 nvc0->vertprog = hwcso;
737 nvc0->dirty |= NVC0_NEW_VERTPROG;
738 }
739
740 static void *
741 nvc0_fp_state_create(struct pipe_context *pipe,
742 const struct pipe_shader_state *cso)
743 {
744 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
745 }
746
747 static void
748 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
749 {
750 struct nvc0_context *nvc0 = nvc0_context(pipe);
751
752 nvc0->fragprog = hwcso;
753 nvc0->dirty |= NVC0_NEW_FRAGPROG;
754 }
755
756 static void *
757 nvc0_gp_state_create(struct pipe_context *pipe,
758 const struct pipe_shader_state *cso)
759 {
760 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
761 }
762
763 static void
764 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
765 {
766 struct nvc0_context *nvc0 = nvc0_context(pipe);
767
768 nvc0->gmtyprog = hwcso;
769 nvc0->dirty |= NVC0_NEW_GMTYPROG;
770 }
771
772 static void *
773 nvc0_tcp_state_create(struct pipe_context *pipe,
774 const struct pipe_shader_state *cso)
775 {
776 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
777 }
778
779 static void
780 nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
781 {
782 struct nvc0_context *nvc0 = nvc0_context(pipe);
783
784 nvc0->tctlprog = hwcso;
785 nvc0->dirty |= NVC0_NEW_TCTLPROG;
786 }
787
788 static void *
789 nvc0_tep_state_create(struct pipe_context *pipe,
790 const struct pipe_shader_state *cso)
791 {
792 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
793 }
794
795 static void
796 nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
797 {
798 struct nvc0_context *nvc0 = nvc0_context(pipe);
799
800 nvc0->tevlprog = hwcso;
801 nvc0->dirty |= NVC0_NEW_TEVLPROG;
802 }
803
804 static void *
805 nvc0_cp_state_create(struct pipe_context *pipe,
806 const struct pipe_compute_state *cso)
807 {
808 struct nvc0_program *prog;
809
810 prog = CALLOC_STRUCT(nvc0_program);
811 if (!prog)
812 return NULL;
813 prog->type = PIPE_SHADER_COMPUTE;
814
815 prog->cp.smem_size = cso->req_local_mem;
816 prog->cp.lmem_size = cso->req_private_mem;
817 prog->parm_size = cso->req_input_mem;
818
819 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
820
821 return (void *)prog;
822 }
823
824 static void
825 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
826 {
827 struct nvc0_context *nvc0 = nvc0_context(pipe);
828
829 nvc0->compprog = hwcso;
830 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
831 }
832
833 static void
834 nvc0_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
835 struct pipe_constant_buffer *cb)
836 {
837 struct nvc0_context *nvc0 = nvc0_context(pipe);
838 struct pipe_resource *res = cb ? cb->buffer : NULL;
839 const unsigned s = nvc0_shader_stage(shader);
840 const unsigned i = index;
841
842 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
843 assert(!cb || !cb->user_buffer);
844 if (nvc0->constbuf[s][i].u.buf)
845 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
846
847 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
848 } else {
849 if (nvc0->constbuf[s][i].user)
850 nvc0->constbuf[s][i].u.buf = NULL;
851 else
852 if (nvc0->constbuf[s][i].u.buf)
853 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_CB(s, i));
854
855 nvc0->dirty |= NVC0_NEW_CONSTBUF;
856 }
857 nvc0->constbuf_dirty[s] |= 1 << i;
858
859 if (nvc0->constbuf[s][i].u.buf)
860 nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
861 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
862
863 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
864 if (nvc0->constbuf[s][i].user) {
865 nvc0->constbuf[s][i].u.data = cb->user_buffer;
866 nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
867 nvc0->constbuf_valid[s] |= 1 << i;
868 nvc0->constbuf_coherent[s] &= ~(1 << i);
869 } else
870 if (cb) {
871 nvc0->constbuf[s][i].offset = cb->buffer_offset;
872 nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
873 nvc0->constbuf_valid[s] |= 1 << i;
874 if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
875 nvc0->constbuf_coherent[s] |= 1 << i;
876 else
877 nvc0->constbuf_coherent[s] &= ~(1 << i);
878 }
879 else {
880 nvc0->constbuf_valid[s] &= ~(1 << i);
881 nvc0->constbuf_coherent[s] &= ~(1 << i);
882 }
883 }
884
885 /* =============================================================================
886 */
887
888 static void
889 nvc0_set_blend_color(struct pipe_context *pipe,
890 const struct pipe_blend_color *bcol)
891 {
892 struct nvc0_context *nvc0 = nvc0_context(pipe);
893
894 nvc0->blend_colour = *bcol;
895 nvc0->dirty |= NVC0_NEW_BLEND_COLOUR;
896 }
897
898 static void
899 nvc0_set_stencil_ref(struct pipe_context *pipe,
900 const struct pipe_stencil_ref *sr)
901 {
902 struct nvc0_context *nvc0 = nvc0_context(pipe);
903
904 nvc0->stencil_ref = *sr;
905 nvc0->dirty |= NVC0_NEW_STENCIL_REF;
906 }
907
908 static void
909 nvc0_set_clip_state(struct pipe_context *pipe,
910 const struct pipe_clip_state *clip)
911 {
912 struct nvc0_context *nvc0 = nvc0_context(pipe);
913
914 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
915
916 nvc0->dirty |= NVC0_NEW_CLIP;
917 }
918
919 static void
920 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
921 {
922 struct nvc0_context *nvc0 = nvc0_context(pipe);
923
924 nvc0->sample_mask = sample_mask;
925 nvc0->dirty |= NVC0_NEW_SAMPLE_MASK;
926 }
927
928 static void
929 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
930 {
931 struct nvc0_context *nvc0 = nvc0_context(pipe);
932
933 if (nvc0->min_samples != min_samples) {
934 nvc0->min_samples = min_samples;
935 nvc0->dirty |= NVC0_NEW_MIN_SAMPLES;
936 }
937 }
938
939 static void
940 nvc0_set_framebuffer_state(struct pipe_context *pipe,
941 const struct pipe_framebuffer_state *fb)
942 {
943 struct nvc0_context *nvc0 = nvc0_context(pipe);
944
945 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
946
947 util_copy_framebuffer_state(&nvc0->framebuffer, fb);
948
949 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
950 }
951
952 static void
953 nvc0_set_polygon_stipple(struct pipe_context *pipe,
954 const struct pipe_poly_stipple *stipple)
955 {
956 struct nvc0_context *nvc0 = nvc0_context(pipe);
957
958 nvc0->stipple = *stipple;
959 nvc0->dirty |= NVC0_NEW_STIPPLE;
960 }
961
962 static void
963 nvc0_set_scissor_states(struct pipe_context *pipe,
964 unsigned start_slot,
965 unsigned num_scissors,
966 const struct pipe_scissor_state *scissor)
967 {
968 struct nvc0_context *nvc0 = nvc0_context(pipe);
969 int i;
970
971 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
972 for (i = 0; i < num_scissors; i++) {
973 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
974 continue;
975 nvc0->scissors[start_slot + i] = scissor[i];
976 nvc0->scissors_dirty |= 1 << (start_slot + i);
977 nvc0->dirty |= NVC0_NEW_SCISSOR;
978 }
979 }
980
981 static void
982 nvc0_set_viewport_states(struct pipe_context *pipe,
983 unsigned start_slot,
984 unsigned num_viewports,
985 const struct pipe_viewport_state *vpt)
986 {
987 struct nvc0_context *nvc0 = nvc0_context(pipe);
988 int i;
989
990 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
991 for (i = 0; i < num_viewports; i++) {
992 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
993 continue;
994 nvc0->viewports[start_slot + i] = vpt[i];
995 nvc0->viewports_dirty |= 1 << (start_slot + i);
996 nvc0->dirty |= NVC0_NEW_VIEWPORT;
997 }
998
999 }
1000
1001 static void
1002 nvc0_set_tess_state(struct pipe_context *pipe,
1003 const float default_tess_outer[4],
1004 const float default_tess_inner[2])
1005 {
1006 struct nvc0_context *nvc0 = nvc0_context(pipe);
1007
1008 memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
1009 memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
1010 nvc0->dirty |= NVC0_NEW_TESSFACTOR;
1011 }
1012
1013 static void
1014 nvc0_set_vertex_buffers(struct pipe_context *pipe,
1015 unsigned start_slot, unsigned count,
1016 const struct pipe_vertex_buffer *vb)
1017 {
1018 struct nvc0_context *nvc0 = nvc0_context(pipe);
1019 unsigned i;
1020
1021 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX);
1022 nvc0->dirty |= NVC0_NEW_ARRAYS;
1023
1024 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
1025 start_slot, count);
1026
1027 if (!vb) {
1028 nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
1029 nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
1030 nvc0->vtxbufs_coherent &= ~(((1ull << count) - 1) << start_slot);
1031 return;
1032 }
1033
1034 for (i = 0; i < count; ++i) {
1035 unsigned dst_index = start_slot + i;
1036
1037 if (vb[i].user_buffer) {
1038 nvc0->vbo_user |= 1 << dst_index;
1039 if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
1040 nvc0->constant_vbos |= 1 << dst_index;
1041 else
1042 nvc0->constant_vbos &= ~(1 << dst_index);
1043 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1044 } else {
1045 nvc0->vbo_user &= ~(1 << dst_index);
1046 nvc0->constant_vbos &= ~(1 << dst_index);
1047
1048 if (vb[i].buffer &&
1049 vb[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1050 nvc0->vtxbufs_coherent |= (1 << dst_index);
1051 else
1052 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1053 }
1054 }
1055 }
1056
1057 static void
1058 nvc0_set_index_buffer(struct pipe_context *pipe,
1059 const struct pipe_index_buffer *ib)
1060 {
1061 struct nvc0_context *nvc0 = nvc0_context(pipe);
1062
1063 if (nvc0->idxbuf.buffer)
1064 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_IDX);
1065
1066 if (ib) {
1067 pipe_resource_reference(&nvc0->idxbuf.buffer, ib->buffer);
1068 nvc0->idxbuf.index_size = ib->index_size;
1069 if (ib->buffer) {
1070 nvc0->idxbuf.offset = ib->offset;
1071 nvc0->dirty |= NVC0_NEW_IDXBUF;
1072 } else {
1073 nvc0->idxbuf.user_buffer = ib->user_buffer;
1074 nvc0->dirty &= ~NVC0_NEW_IDXBUF;
1075 }
1076 } else {
1077 nvc0->dirty &= ~NVC0_NEW_IDXBUF;
1078 pipe_resource_reference(&nvc0->idxbuf.buffer, NULL);
1079 }
1080 }
1081
1082 static void
1083 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1084 {
1085 struct nvc0_context *nvc0 = nvc0_context(pipe);
1086
1087 nvc0->vertex = hwcso;
1088 nvc0->dirty |= NVC0_NEW_VERTEX;
1089 }
1090
1091 static struct pipe_stream_output_target *
1092 nvc0_so_target_create(struct pipe_context *pipe,
1093 struct pipe_resource *res,
1094 unsigned offset, unsigned size)
1095 {
1096 struct nv04_resource *buf = (struct nv04_resource *)res;
1097 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1098 if (!targ)
1099 return NULL;
1100
1101 targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0);
1102 if (!targ->pq) {
1103 FREE(targ);
1104 return NULL;
1105 }
1106 targ->clean = true;
1107
1108 targ->pipe.buffer_size = size;
1109 targ->pipe.buffer_offset = offset;
1110 targ->pipe.context = pipe;
1111 targ->pipe.buffer = NULL;
1112 pipe_resource_reference(&targ->pipe.buffer, res);
1113 pipe_reference_init(&targ->pipe.reference, 1);
1114
1115 assert(buf->base.target == PIPE_BUFFER);
1116 util_range_add(&buf->valid_buffer_range, offset, offset + size);
1117
1118 return &targ->pipe;
1119 }
1120
1121 static void
1122 nvc0_so_target_save_offset(struct pipe_context *pipe,
1123 struct pipe_stream_output_target *ptarg,
1124 unsigned index, bool *serialize)
1125 {
1126 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1127
1128 if (*serialize) {
1129 *serialize = false;
1130 PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
1131 IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
1132
1133 NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
1134 }
1135
1136 nvc0_query(targ->pq)->index = index;
1137 pipe->end_query(pipe, targ->pq);
1138 }
1139
1140 static void
1141 nvc0_so_target_destroy(struct pipe_context *pipe,
1142 struct pipe_stream_output_target *ptarg)
1143 {
1144 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1145 pipe->destroy_query(pipe, targ->pq);
1146 pipe_resource_reference(&targ->pipe.buffer, NULL);
1147 FREE(targ);
1148 }
1149
1150 static void
1151 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1152 unsigned num_targets,
1153 struct pipe_stream_output_target **targets,
1154 const unsigned *offsets)
1155 {
1156 struct nvc0_context *nvc0 = nvc0_context(pipe);
1157 unsigned i;
1158 bool serialize = true;
1159
1160 assert(num_targets <= 4);
1161
1162 for (i = 0; i < num_targets; ++i) {
1163 const bool changed = nvc0->tfbbuf[i] != targets[i];
1164 const bool append = (offsets[i] == ((unsigned)-1));
1165 if (!changed && append)
1166 continue;
1167 nvc0->tfbbuf_dirty |= 1 << i;
1168
1169 if (nvc0->tfbbuf[i] && changed)
1170 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1171
1172 if (targets[i] && !append)
1173 nvc0_so_target(targets[i])->clean = true;
1174
1175 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1176 }
1177 for (; i < nvc0->num_tfbbufs; ++i) {
1178 if (nvc0->tfbbuf[i]) {
1179 nvc0->tfbbuf_dirty |= 1 << i;
1180 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1181 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1182 }
1183 }
1184 nvc0->num_tfbbufs = num_targets;
1185
1186 if (nvc0->tfbbuf_dirty)
1187 nvc0->dirty |= NVC0_NEW_TFB_TARGETS;
1188 }
1189
1190 static void
1191 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1192 unsigned start, unsigned nr,
1193 struct pipe_surface **psurfaces)
1194 {
1195 const unsigned end = start + nr;
1196 const unsigned mask = ((1 << nr) - 1) << start;
1197 unsigned i;
1198
1199 if (psurfaces) {
1200 for (i = start; i < end; ++i) {
1201 const unsigned p = i - start;
1202 if (psurfaces[p])
1203 nvc0->surfaces_valid[t] |= (1 << i);
1204 else
1205 nvc0->surfaces_valid[t] &= ~(1 << i);
1206 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1207 }
1208 } else {
1209 for (i = start; i < end; ++i)
1210 pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1211 nvc0->surfaces_valid[t] &= ~mask;
1212 }
1213 nvc0->surfaces_dirty[t] |= mask;
1214
1215 if (t == 0)
1216 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_SUF);
1217 else
1218 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1219 }
1220
1221 static void
1222 nvc0_set_compute_resources(struct pipe_context *pipe,
1223 unsigned start, unsigned nr,
1224 struct pipe_surface **resources)
1225 {
1226 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1227
1228 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1229 }
1230
1231 static void
1232 nvc0_set_shader_images(struct pipe_context *pipe, unsigned shader,
1233 unsigned start_slot, unsigned count,
1234 struct pipe_image_view **views)
1235 {
1236 }
1237
1238 static void
1239 nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t,
1240 unsigned start, unsigned nr,
1241 struct pipe_shader_buffer *pbuffers)
1242 {
1243 const unsigned end = start + nr;
1244 const unsigned mask = ((1 << nr) - 1) << start;
1245 unsigned i;
1246
1247 assert(t < 5);
1248
1249 if (pbuffers) {
1250 for (i = start; i < end; ++i) {
1251 const unsigned p = i - start;
1252 if (pbuffers[p].buffer)
1253 nvc0->buffers_valid[t] |= (1 << i);
1254 else
1255 nvc0->buffers_valid[t] &= ~(1 << i);
1256 nvc0->buffers[t][i].buffer_offset = pbuffers[p].buffer_offset;
1257 nvc0->buffers[t][i].buffer_size = pbuffers[p].buffer_size;
1258 pipe_resource_reference(&nvc0->buffers[t][i].buffer, pbuffers[p].buffer);
1259 }
1260 } else {
1261 for (i = start; i < end; ++i)
1262 pipe_resource_reference(&nvc0->buffers[t][i].buffer, NULL);
1263 nvc0->buffers_valid[t] &= ~mask;
1264 }
1265 nvc0->buffers_dirty[t] |= mask;
1266
1267 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_BUF);
1268 }
1269
1270 static void
1271 nvc0_set_shader_buffers(struct pipe_context *pipe,
1272 unsigned shader,
1273 unsigned start, unsigned nr,
1274 struct pipe_shader_buffer *buffers)
1275 {
1276 const unsigned s = nvc0_shader_stage(shader);
1277 nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers);
1278
1279 nvc0_context(pipe)->dirty |= NVC0_NEW_BUFFERS;
1280 }
1281
1282 static inline void
1283 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1284 {
1285 struct nv04_resource *buf = nv04_resource(res);
1286 if (buf) {
1287 uint64_t limit = (buf->address + buf->base.width0) - 1;
1288 if (limit < (1ULL << 32)) {
1289 *phandle = (uint32_t)buf->address;
1290 } else {
1291 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1292 "resource not contained within 32-bit address space !\n");
1293 *phandle = 0;
1294 }
1295 } else {
1296 *phandle = 0;
1297 }
1298 }
1299
1300 static void
1301 nvc0_set_global_bindings(struct pipe_context *pipe,
1302 unsigned start, unsigned nr,
1303 struct pipe_resource **resources,
1304 uint32_t **handles)
1305 {
1306 struct nvc0_context *nvc0 = nvc0_context(pipe);
1307 struct pipe_resource **ptr;
1308 unsigned i;
1309 const unsigned end = start + nr;
1310
1311 if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1312 const unsigned old_size = nvc0->global_residents.size;
1313 const unsigned req_size = end * sizeof(struct pipe_resource *);
1314 util_dynarray_resize(&nvc0->global_residents, req_size);
1315 memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1316 req_size - old_size);
1317 }
1318
1319 if (resources) {
1320 ptr = util_dynarray_element(
1321 &nvc0->global_residents, struct pipe_resource *, start);
1322 for (i = 0; i < nr; ++i) {
1323 pipe_resource_reference(&ptr[i], resources[i]);
1324 nvc0_set_global_handle(handles[i], resources[i]);
1325 }
1326 } else {
1327 ptr = util_dynarray_element(
1328 &nvc0->global_residents, struct pipe_resource *, start);
1329 for (i = 0; i < nr; ++i)
1330 pipe_resource_reference(&ptr[i], NULL);
1331 }
1332
1333 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1334
1335 nvc0->dirty_cp = NVC0_NEW_CP_GLOBALS;
1336 }
1337
1338 void
1339 nvc0_init_state_functions(struct nvc0_context *nvc0)
1340 {
1341 struct pipe_context *pipe = &nvc0->base.pipe;
1342
1343 pipe->create_blend_state = nvc0_blend_state_create;
1344 pipe->bind_blend_state = nvc0_blend_state_bind;
1345 pipe->delete_blend_state = nvc0_blend_state_delete;
1346
1347 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1348 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1349 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1350
1351 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1352 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1353 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1354
1355 pipe->create_sampler_state = nv50_sampler_state_create;
1356 pipe->delete_sampler_state = nvc0_sampler_state_delete;
1357 pipe->bind_sampler_states = nvc0_bind_sampler_states;
1358
1359 pipe->create_sampler_view = nvc0_create_sampler_view;
1360 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1361 pipe->set_sampler_views = nvc0_set_sampler_views;
1362
1363 pipe->create_vs_state = nvc0_vp_state_create;
1364 pipe->create_fs_state = nvc0_fp_state_create;
1365 pipe->create_gs_state = nvc0_gp_state_create;
1366 pipe->create_tcs_state = nvc0_tcp_state_create;
1367 pipe->create_tes_state = nvc0_tep_state_create;
1368 pipe->bind_vs_state = nvc0_vp_state_bind;
1369 pipe->bind_fs_state = nvc0_fp_state_bind;
1370 pipe->bind_gs_state = nvc0_gp_state_bind;
1371 pipe->bind_tcs_state = nvc0_tcp_state_bind;
1372 pipe->bind_tes_state = nvc0_tep_state_bind;
1373 pipe->delete_vs_state = nvc0_sp_state_delete;
1374 pipe->delete_fs_state = nvc0_sp_state_delete;
1375 pipe->delete_gs_state = nvc0_sp_state_delete;
1376 pipe->delete_tcs_state = nvc0_sp_state_delete;
1377 pipe->delete_tes_state = nvc0_sp_state_delete;
1378
1379 pipe->create_compute_state = nvc0_cp_state_create;
1380 pipe->bind_compute_state = nvc0_cp_state_bind;
1381 pipe->delete_compute_state = nvc0_sp_state_delete;
1382
1383 pipe->set_blend_color = nvc0_set_blend_color;
1384 pipe->set_stencil_ref = nvc0_set_stencil_ref;
1385 pipe->set_clip_state = nvc0_set_clip_state;
1386 pipe->set_sample_mask = nvc0_set_sample_mask;
1387 pipe->set_min_samples = nvc0_set_min_samples;
1388 pipe->set_constant_buffer = nvc0_set_constant_buffer;
1389 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1390 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1391 pipe->set_scissor_states = nvc0_set_scissor_states;
1392 pipe->set_viewport_states = nvc0_set_viewport_states;
1393 pipe->set_tess_state = nvc0_set_tess_state;
1394
1395 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1396 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1397 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1398
1399 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1400 pipe->set_index_buffer = nvc0_set_index_buffer;
1401
1402 pipe->create_stream_output_target = nvc0_so_target_create;
1403 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1404 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1405
1406 pipe->set_global_binding = nvc0_set_global_bindings;
1407 pipe->set_compute_resources = nvc0_set_compute_resources;
1408 pipe->set_shader_images = nvc0_set_shader_images;
1409 pipe->set_shader_buffers = nvc0_set_shader_buffers;
1410
1411 nvc0->sample_mask = ~0;
1412 nvc0->min_samples = 1;
1413 nvc0->default_tess_outer[0] =
1414 nvc0->default_tess_outer[1] =
1415 nvc0->default_tess_outer[2] =
1416 nvc0->default_tess_outer[3] = 1.0;
1417 nvc0->default_tess_inner[0] =
1418 nvc0->default_tess_inner[1] = 1.0;
1419 }