projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
nv50,nvc0: optimize coherent buffer checking at draw time
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_helpers.h"
25 #include "util/u_inlines.h"
26 #include "util/u_transfer.h"
27
28 #include "tgsi/tgsi_parse.h"
29
30 #include "nvc0/nvc0_stateobj.h"
31 #include "nvc0/nvc0_context.h"
32 #include "nvc0/nvc0_query_hw.h"
33
34 #include "nvc0/nvc0_3d.xml.h"
35 #include "nv50/nv50_texture.xml.h"
36
37 #include "nouveau_gldefs.h"
38
39 static inline uint32_t
40 nvc0_colormask(unsigned mask)
41 {
42 uint32_t ret = 0;
43
44 if (mask & PIPE_MASK_R)
45 ret |= 0x0001;
46 if (mask & PIPE_MASK_G)
47 ret |= 0x0010;
48 if (mask & PIPE_MASK_B)
49 ret |= 0x0100;
50 if (mask & PIPE_MASK_A)
51 ret |= 0x1000;
52
53 return ret;
54 }
55
56 #define NVC0_BLEND_FACTOR_CASE(a, b) \
57 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
58
59 static inline uint32_t
60 nvc0_blend_fac(unsigned factor)
61 {
62 switch (factor) {
63 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
64 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
65 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
66 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
67 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
68 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
69 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
70 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
71 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
72 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
73 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
74 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
75 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
76 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
77 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
78 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
79 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
80 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
81 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
82 default:
83 return NV50_BLEND_FACTOR_ZERO;
84 }
85 }
86
87 static void *
88 nvc0_blend_state_create(struct pipe_context *pipe,
89 const struct pipe_blend_state *cso)
90 {
91 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
92 int i;
93 int r; /* reference */
94 uint8_t blend_en = 0;
95 bool indep_masks = false;
96 bool indep_funcs = false;
97
98 so->pipe = *cso;
99
100 /* check which states actually have differing values */
101 if (cso->independent_blend_enable) {
102 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
103 blend_en |= 1 << r;
104 for (i = r + 1; i < 8; ++i) {
105 if (!cso->rt[i].blend_enable)
106 continue;
107 blend_en |= 1 << i;
108 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
109 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
110 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
111 cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
112 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
113 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
114 indep_funcs = true;
115 break;
116 }
117 }
118 for (; i < 8; ++i)
119 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
120
121 for (i = 1; i < 8; ++i) {
122 if (cso->rt[i].colormask != cso->rt[0].colormask) {
123 indep_masks = true;
124 break;
125 }
126 }
127 } else {
128 r = 0;
129 if (cso->rt[0].blend_enable)
130 blend_en = 0xff;
131 }
132
133 if (cso->logicop_enable) {
134 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
135 SB_DATA (so, 1);
136 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
137
138 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
139 } else {
140 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
141
142 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
143 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
144 if (indep_funcs) {
145 for (i = 0; i < 8; ++i) {
146 if (cso->rt[i].blend_enable) {
147 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
148 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
149 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
150 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
151 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
152 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
153 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
154 }
155 }
156 } else
157 if (blend_en) {
158 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
159 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
160 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
161 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
162 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
163 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
164 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
165 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
166 }
167
168 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
169 if (indep_masks) {
170 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
171 for (i = 0; i < 8; ++i)
172 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
173 } else {
174 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
175 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
176 }
177 }
178
179 assert(so->size <= ARRAY_SIZE(so->state));
180 return so;
181 }
182
183 static void
184 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
185 {
186 struct nvc0_context *nvc0 = nvc0_context(pipe);
187
188 nvc0->blend = hwcso;
189 nvc0->dirty |= NVC0_NEW_BLEND;
190 }
191
192 static void
193 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
194 {
195 FREE(hwcso);
196 }
197
198 /* NOTE: ignoring line_last_pixel */
199 static void *
200 nvc0_rasterizer_state_create(struct pipe_context *pipe,
201 const struct pipe_rasterizer_state *cso)
202 {
203 struct nvc0_rasterizer_stateobj *so;
204 uint32_t reg;
205
206 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
207 if (!so)
208 return NULL;
209 so->pipe = *cso;
210
211 /* Scissor enables are handled in scissor state, we will not want to
212 * always emit 16 commands, one for each scissor rectangle, here.
213 */
214
215 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
216 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
217
218 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
219 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
220 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
221
222 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
223
224 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
225 if (cso->line_smooth || cso->multisample)
226 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
227 else
228 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
229 SB_DATA (so, fui(cso->line_width));
230
231 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
232 if (cso->line_stipple_enable) {
233 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
234 SB_DATA (so, (cso->line_stipple_pattern << 8) |
235 cso->line_stipple_factor);
236
237 }
238
239 SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
240 if (!cso->point_size_per_vertex) {
241 SB_BEGIN_3D(so, POINT_SIZE, 1);
242 SB_DATA (so, fui(cso->point_size));
243 }
244
245 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
246 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
247 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
248
249 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
250 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
251 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
252 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
253
254 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
255 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
256 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
257 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
258 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
259
260 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
261 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
262 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
263 NVC0_3D_FRONT_FACE_CW);
264 switch (cso->cull_face) {
265 case PIPE_FACE_FRONT_AND_BACK:
266 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
267 break;
268 case PIPE_FACE_FRONT:
269 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
270 break;
271 case PIPE_FACE_BACK:
272 default:
273 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
274 break;
275 }
276
277 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
278 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
279 SB_DATA (so, cso->offset_point);
280 SB_DATA (so, cso->offset_line);
281 SB_DATA (so, cso->offset_tri);
282
283 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
284 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
285 SB_DATA (so, fui(cso->offset_scale));
286 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
287 SB_DATA (so, fui(cso->offset_units * 2.0f));
288 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
289 SB_DATA (so, fui(cso->offset_clamp));
290 }
291
292 if (cso->depth_clip)
293 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
294 else
295 reg =
296 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
297 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
298 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
299 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
300
301 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
302 SB_DATA (so, reg);
303
304 SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
305
306 SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
307
308 assert(so->size <= ARRAY_SIZE(so->state));
309 return (void *)so;
310 }
311
312 static void
313 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
314 {
315 struct nvc0_context *nvc0 = nvc0_context(pipe);
316
317 nvc0->rast = hwcso;
318 nvc0->dirty |= NVC0_NEW_RASTERIZER;
319 }
320
321 static void
322 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
323 {
324 FREE(hwcso);
325 }
326
327 static void *
328 nvc0_zsa_state_create(struct pipe_context *pipe,
329 const struct pipe_depth_stencil_alpha_state *cso)
330 {
331 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
332
333 so->pipe = *cso;
334
335 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
336 if (cso->depth.enabled) {
337 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
338 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
339 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
340 }
341
342 SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth.bounds_test);
343 if (cso->depth.bounds_test) {
344 SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
345 SB_DATA (so, fui(cso->depth.bounds_min));
346 SB_DATA (so, fui(cso->depth.bounds_max));
347 }
348
349 if (cso->stencil[0].enabled) {
350 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
351 SB_DATA (so, 1);
352 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
353 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
354 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
355 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
356 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
357 SB_DATA (so, cso->stencil[0].valuemask);
358 SB_DATA (so, cso->stencil[0].writemask);
359 } else {
360 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
361 }
362
363 if (cso->stencil[1].enabled) {
364 assert(cso->stencil[0].enabled);
365 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
366 SB_DATA (so, 1);
367 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
368 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
369 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
370 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
371 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
372 SB_DATA (so, cso->stencil[1].writemask);
373 SB_DATA (so, cso->stencil[1].valuemask);
374 } else
375 if (cso->stencil[0].enabled) {
376 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
377 }
378
379 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
380 if (cso->alpha.enabled) {
381 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
382 SB_DATA (so, fui(cso->alpha.ref_value));
383 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
384 }
385
386 assert(so->size <= ARRAY_SIZE(so->state));
387 return (void *)so;
388 }
389
390 static void
391 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
392 {
393 struct nvc0_context *nvc0 = nvc0_context(pipe);
394
395 nvc0->zsa = hwcso;
396 nvc0->dirty |= NVC0_NEW_ZSA;
397 }
398
399 static void
400 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
401 {
402 FREE(hwcso);
403 }
404
405 /* ====================== SAMPLERS AND TEXTURES ================================
406 */
407
408 #define NV50_TSC_WRAP_CASE(n) \
409 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
410
411 static void
412 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
413 {
414 unsigned s, i;
415
416 for (s = 0; s < 5; ++s)
417 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
418 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
419 nvc0_context(pipe)->samplers[s][i] = NULL;
420
421 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
422
423 FREE(hwcso);
424 }
425
426 static inline void
427 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0, int s,
428 unsigned nr, void **hwcso)
429 {
430 unsigned i;
431
432 for (i = 0; i < nr; ++i) {
433 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
434
435 if (hwcso[i] == old)
436 continue;
437 nvc0->samplers_dirty[s] |= 1 << i;
438
439 nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
440 if (old)
441 nvc0_screen_tsc_unlock(nvc0->screen, old);
442 }
443 for (; i < nvc0->num_samplers[s]; ++i) {
444 if (nvc0->samplers[s][i]) {
445 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
446 nvc0->samplers[s][i] = NULL;
447 }
448 }
449
450 nvc0->num_samplers[s] = nr;
451
452 nvc0->dirty |= NVC0_NEW_SAMPLERS;
453 }
454
455 static void
456 nvc0_stage_sampler_states_bind_range(struct nvc0_context *nvc0,
457 const unsigned s,
458 unsigned start, unsigned nr, void **cso)
459 {
460 const unsigned end = start + nr;
461 int last_valid = -1;
462 unsigned i;
463
464 if (cso) {
465 for (i = start; i < end; ++i) {
466 const unsigned p = i - start;
467 if (cso[p])
468 last_valid = i;
469 if (cso[p] == nvc0->samplers[s][i])
470 continue;
471 nvc0->samplers_dirty[s] |= 1 << i;
472
473 if (nvc0->samplers[s][i])
474 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
475 nvc0->samplers[s][i] = cso[p];
476 }
477 } else {
478 for (i = start; i < end; ++i) {
479 if (nvc0->samplers[s][i]) {
480 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
481 nvc0->samplers[s][i] = NULL;
482 nvc0->samplers_dirty[s] |= 1 << i;
483 }
484 }
485 }
486
487 if (nvc0->num_samplers[s] <= end) {
488 if (last_valid < 0) {
489 for (i = start; i && !nvc0->samplers[s][i - 1]; --i);
490 nvc0->num_samplers[s] = i;
491 } else {
492 nvc0->num_samplers[s] = last_valid + 1;
493 }
494 }
495 }
496
497 static void
498 nvc0_bind_sampler_states(struct pipe_context *pipe, unsigned shader,
499 unsigned start, unsigned nr, void **s)
500 {
501 switch (shader) {
502 case PIPE_SHADER_VERTEX:
503 assert(start == 0);
504 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 0, nr, s);
505 break;
506 case PIPE_SHADER_TESS_CTRL:
507 assert(start == 0);
508 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 1, nr, s);
509 break;
510 case PIPE_SHADER_TESS_EVAL:
511 assert(start == 0);
512 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 2, nr, s);
513 break;
514 case PIPE_SHADER_GEOMETRY:
515 assert(start == 0);
516 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 3, nr, s);
517 break;
518 case PIPE_SHADER_FRAGMENT:
519 assert(start == 0);
520 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 4, nr, s);
521 break;
522 case PIPE_SHADER_COMPUTE:
523 nvc0_stage_sampler_states_bind_range(nvc0_context(pipe), 5,
524 start, nr, s);
525 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
526 break;
527 }
528 }
529
530
531 /* NOTE: only called when not referenced anywhere, won't be bound */
532 static void
533 nvc0_sampler_view_destroy(struct pipe_context *pipe,
534 struct pipe_sampler_view *view)
535 {
536 pipe_resource_reference(&view->texture, NULL);
537
538 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
539
540 FREE(nv50_tic_entry(view));
541 }
542
543 static inline void
544 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
545 unsigned nr,
546 struct pipe_sampler_view **views)
547 {
548 unsigned i;
549
550 for (i = 0; i < nr; ++i) {
551 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
552
553 if (views[i] == nvc0->textures[s][i])
554 continue;
555 nvc0->textures_dirty[s] |= 1 << i;
556
557 if (views[i] && views[i]->texture) {
558 struct pipe_resource *res = views[i]->texture;
559 if (res->target == PIPE_BUFFER &&
560 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
561 nvc0->textures_coherent[s] |= 1 << i;
562 else
563 nvc0->textures_coherent[s] &= ~(1 << i);
564 } else {
565 nvc0->textures_coherent[s] &= ~(1 << i);
566 }
567
568 if (old) {
569 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(s, i));
570 nvc0_screen_tic_unlock(nvc0->screen, old);
571 }
572
573 pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
574 }
575
576 for (i = nr; i < nvc0->num_textures[s]; ++i) {
577 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
578 if (old) {
579 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(s, i));
580 nvc0_screen_tic_unlock(nvc0->screen, old);
581 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
582 }
583 }
584
585 nvc0->num_textures[s] = nr;
586
587 nvc0->dirty |= NVC0_NEW_TEXTURES;
588 }
589
590 static void
591 nvc0_stage_set_sampler_views_range(struct nvc0_context *nvc0, const unsigned s,
592 unsigned start, unsigned nr,
593 struct pipe_sampler_view **views)
594 {
595 struct nouveau_bufctx *bctx = (s == 5) ? nvc0->bufctx_cp : nvc0->bufctx_3d;
596 const unsigned end = start + nr;
597 const unsigned bin = (s == 5) ? NVC0_BIND_CP_TEX(0) : NVC0_BIND_TEX(s, 0);
598 int last_valid = -1;
599 unsigned i;
600
601 if (views) {
602 for (i = start; i < end; ++i) {
603 const unsigned p = i - start;
604 if (views[p])
605 last_valid = i;
606 if (views[p] == nvc0->textures[s][i])
607 continue;
608 nvc0->textures_dirty[s] |= 1 << i;
609
610 if (views[p] && views[p]->texture) {
611 struct pipe_resource *res = views[p]->texture;
612 if (res->target == PIPE_BUFFER &&
613 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
614 nvc0->textures_coherent[s] |= 1 << i;
615 else
616 nvc0->textures_coherent[s] &= ~(1 << i);
617 } else {
618 nvc0->textures_coherent[s] &= ~(1 << i);
619 }
620
621 if (nvc0->textures[s][i]) {
622 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
623 nouveau_bufctx_reset(bctx, bin + i);
624 nvc0_screen_tic_unlock(nvc0->screen, old);
625 }
626 pipe_sampler_view_reference(&nvc0->textures[s][i], views[p]);
627 }
628 } else {
629 for (i = start; i < end; ++i) {
630 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
631 if (!old)
632 continue;
633 nvc0->textures_dirty[s] |= 1 << i;
634
635 nvc0_screen_tic_unlock(nvc0->screen, old);
636 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
637 nouveau_bufctx_reset(bctx, bin + i);
638 }
639 }
640
641 if (nvc0->num_textures[s] <= end) {
642 if (last_valid < 0) {
643 for (i = start; i && !nvc0->textures[s][i - 1]; --i);
644 nvc0->num_textures[s] = i;
645 } else {
646 nvc0->num_textures[s] = last_valid + 1;
647 }
648 }
649 }
650
651 static void
652 nvc0_set_sampler_views(struct pipe_context *pipe, unsigned shader,
653 unsigned start, unsigned nr,
654 struct pipe_sampler_view **views)
655 {
656 assert(start == 0);
657 switch (shader) {
658 case PIPE_SHADER_VERTEX:
659 nvc0_stage_set_sampler_views(nvc0_context(pipe), 0, nr, views);
660 break;
661 case PIPE_SHADER_TESS_CTRL:
662 nvc0_stage_set_sampler_views(nvc0_context(pipe), 1, nr, views);
663 break;
664 case PIPE_SHADER_TESS_EVAL:
665 nvc0_stage_set_sampler_views(nvc0_context(pipe), 2, nr, views);
666 break;
667 case PIPE_SHADER_GEOMETRY:
668 nvc0_stage_set_sampler_views(nvc0_context(pipe), 3, nr, views);
669 break;
670 case PIPE_SHADER_FRAGMENT:
671 nvc0_stage_set_sampler_views(nvc0_context(pipe), 4, nr, views);
672 break;
673 case PIPE_SHADER_COMPUTE:
674 nvc0_stage_set_sampler_views_range(nvc0_context(pipe), 5,
675 start, nr, views);
676 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
677 break;
678 default:
679 ;
680 }
681 }
682
683
684 /* ============================= SHADERS =======================================
685 */
686
687 static void *
688 nvc0_sp_state_create(struct pipe_context *pipe,
689 const struct pipe_shader_state *cso, unsigned type)
690 {
691 struct nvc0_program *prog;
692
693 prog = CALLOC_STRUCT(nvc0_program);
694 if (!prog)
695 return NULL;
696
697 prog->type = type;
698
699 if (cso->tokens)
700 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
701
702 if (cso->stream_output.num_outputs)
703 prog->pipe.stream_output = cso->stream_output;
704
705 prog->translated = nvc0_program_translate(
706 prog, nvc0_context(pipe)->screen->base.device->chipset,
707 &nouveau_context(pipe)->debug);
708
709 return (void *)prog;
710 }
711
712 static void
713 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
714 {
715 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
716
717 nvc0_program_destroy(nvc0_context(pipe), prog);
718
719 FREE((void *)prog->pipe.tokens);
720 FREE(prog);
721 }
722
723 static void *
724 nvc0_vp_state_create(struct pipe_context *pipe,
725 const struct pipe_shader_state *cso)
726 {
727 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
728 }
729
730 static void
731 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
732 {
733 struct nvc0_context *nvc0 = nvc0_context(pipe);
734
735 nvc0->vertprog = hwcso;
736 nvc0->dirty |= NVC0_NEW_VERTPROG;
737 }
738
739 static void *
740 nvc0_fp_state_create(struct pipe_context *pipe,
741 const struct pipe_shader_state *cso)
742 {
743 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
744 }
745
746 static void
747 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
748 {
749 struct nvc0_context *nvc0 = nvc0_context(pipe);
750
751 nvc0->fragprog = hwcso;
752 nvc0->dirty |= NVC0_NEW_FRAGPROG;
753 }
754
755 static void *
756 nvc0_gp_state_create(struct pipe_context *pipe,
757 const struct pipe_shader_state *cso)
758 {
759 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
760 }
761
762 static void
763 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
764 {
765 struct nvc0_context *nvc0 = nvc0_context(pipe);
766
767 nvc0->gmtyprog = hwcso;
768 nvc0->dirty |= NVC0_NEW_GMTYPROG;
769 }
770
771 static void *
772 nvc0_tcp_state_create(struct pipe_context *pipe,
773 const struct pipe_shader_state *cso)
774 {
775 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
776 }
777
778 static void
779 nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
780 {
781 struct nvc0_context *nvc0 = nvc0_context(pipe);
782
783 nvc0->tctlprog = hwcso;
784 nvc0->dirty |= NVC0_NEW_TCTLPROG;
785 }
786
787 static void *
788 nvc0_tep_state_create(struct pipe_context *pipe,
789 const struct pipe_shader_state *cso)
790 {
791 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
792 }
793
794 static void
795 nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
796 {
797 struct nvc0_context *nvc0 = nvc0_context(pipe);
798
799 nvc0->tevlprog = hwcso;
800 nvc0->dirty |= NVC0_NEW_TEVLPROG;
801 }
802
803 static void *
804 nvc0_cp_state_create(struct pipe_context *pipe,
805 const struct pipe_compute_state *cso)
806 {
807 struct nvc0_program *prog;
808
809 prog = CALLOC_STRUCT(nvc0_program);
810 if (!prog)
811 return NULL;
812 prog->type = PIPE_SHADER_COMPUTE;
813
814 prog->cp.smem_size = cso->req_local_mem;
815 prog->cp.lmem_size = cso->req_private_mem;
816 prog->parm_size = cso->req_input_mem;
817
818 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
819
820 return (void *)prog;
821 }
822
823 static void
824 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
825 {
826 struct nvc0_context *nvc0 = nvc0_context(pipe);
827
828 nvc0->compprog = hwcso;
829 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
830 }
831
832 static void
833 nvc0_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
834 struct pipe_constant_buffer *cb)
835 {
836 struct nvc0_context *nvc0 = nvc0_context(pipe);
837 struct pipe_resource *res = cb ? cb->buffer : NULL;
838 const unsigned s = nvc0_shader_stage(shader);
839 const unsigned i = index;
840
841 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
842 assert(!cb || !cb->user_buffer);
843 if (nvc0->constbuf[s][i].u.buf)
844 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
845
846 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
847 } else {
848 if (nvc0->constbuf[s][i].user)
849 nvc0->constbuf[s][i].u.buf = NULL;
850 else
851 if (nvc0->constbuf[s][i].u.buf)
852 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_CB(s, i));
853
854 nvc0->dirty |= NVC0_NEW_CONSTBUF;
855 }
856 nvc0->constbuf_dirty[s] |= 1 << i;
857
858 if (nvc0->constbuf[s][i].u.buf)
859 nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
860 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
861
862 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
863 if (nvc0->constbuf[s][i].user) {
864 nvc0->constbuf[s][i].u.data = cb->user_buffer;
865 nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
866 nvc0->constbuf_valid[s] |= 1 << i;
867 nvc0->constbuf_coherent[s] &= ~(1 << i);
868 } else
869 if (cb) {
870 nvc0->constbuf[s][i].offset = cb->buffer_offset;
871 nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
872 nvc0->constbuf_valid[s] |= 1 << i;
873 if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
874 nvc0->constbuf_coherent[s] |= 1 << i;
875 else
876 nvc0->constbuf_coherent[s] &= ~(1 << i);
877 }
878 else {
879 nvc0->constbuf_valid[s] &= ~(1 << i);
880 nvc0->constbuf_coherent[s] &= ~(1 << i);
881 }
882 }
883
884 /* =============================================================================
885 */
886
887 static void
888 nvc0_set_blend_color(struct pipe_context *pipe,
889 const struct pipe_blend_color *bcol)
890 {
891 struct nvc0_context *nvc0 = nvc0_context(pipe);
892
893 nvc0->blend_colour = *bcol;
894 nvc0->dirty |= NVC0_NEW_BLEND_COLOUR;
895 }
896
897 static void
898 nvc0_set_stencil_ref(struct pipe_context *pipe,
899 const struct pipe_stencil_ref *sr)
900 {
901 struct nvc0_context *nvc0 = nvc0_context(pipe);
902
903 nvc0->stencil_ref = *sr;
904 nvc0->dirty |= NVC0_NEW_STENCIL_REF;
905 }
906
907 static void
908 nvc0_set_clip_state(struct pipe_context *pipe,
909 const struct pipe_clip_state *clip)
910 {
911 struct nvc0_context *nvc0 = nvc0_context(pipe);
912
913 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
914
915 nvc0->dirty |= NVC0_NEW_CLIP;
916 }
917
918 static void
919 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
920 {
921 struct nvc0_context *nvc0 = nvc0_context(pipe);
922
923 nvc0->sample_mask = sample_mask;
924 nvc0->dirty |= NVC0_NEW_SAMPLE_MASK;
925 }
926
927 static void
928 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
929 {
930 struct nvc0_context *nvc0 = nvc0_context(pipe);
931
932 if (nvc0->min_samples != min_samples) {
933 nvc0->min_samples = min_samples;
934 nvc0->dirty |= NVC0_NEW_MIN_SAMPLES;
935 }
936 }
937
938 static void
939 nvc0_set_framebuffer_state(struct pipe_context *pipe,
940 const struct pipe_framebuffer_state *fb)
941 {
942 struct nvc0_context *nvc0 = nvc0_context(pipe);
943 unsigned i;
944
945 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
946
947 for (i = 0; i < fb->nr_cbufs; ++i)
948 pipe_surface_reference(&nvc0->framebuffer.cbufs[i], fb->cbufs[i]);
949 for (; i < nvc0->framebuffer.nr_cbufs; ++i)
950 pipe_surface_reference(&nvc0->framebuffer.cbufs[i], NULL);
951
952 nvc0->framebuffer.nr_cbufs = fb->nr_cbufs;
953
954 nvc0->framebuffer.width = fb->width;
955 nvc0->framebuffer.height = fb->height;
956
957 pipe_surface_reference(&nvc0->framebuffer.zsbuf, fb->zsbuf);
958
959 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
960 }
961
962 static void
963 nvc0_set_polygon_stipple(struct pipe_context *pipe,
964 const struct pipe_poly_stipple *stipple)
965 {
966 struct nvc0_context *nvc0 = nvc0_context(pipe);
967
968 nvc0->stipple = *stipple;
969 nvc0->dirty |= NVC0_NEW_STIPPLE;
970 }
971
972 static void
973 nvc0_set_scissor_states(struct pipe_context *pipe,
974 unsigned start_slot,
975 unsigned num_scissors,
976 const struct pipe_scissor_state *scissor)
977 {
978 struct nvc0_context *nvc0 = nvc0_context(pipe);
979 int i;
980
981 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
982 for (i = 0; i < num_scissors; i++) {
983 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
984 continue;
985 nvc0->scissors[start_slot + i] = scissor[i];
986 nvc0->scissors_dirty |= 1 << (start_slot + i);
987 nvc0->dirty |= NVC0_NEW_SCISSOR;
988 }
989 }
990
991 static void
992 nvc0_set_viewport_states(struct pipe_context *pipe,
993 unsigned start_slot,
994 unsigned num_viewports,
995 const struct pipe_viewport_state *vpt)
996 {
997 struct nvc0_context *nvc0 = nvc0_context(pipe);
998 int i;
999
1000 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
1001 for (i = 0; i < num_viewports; i++) {
1002 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
1003 continue;
1004 nvc0->viewports[start_slot + i] = vpt[i];
1005 nvc0->viewports_dirty |= 1 << (start_slot + i);
1006 nvc0->dirty |= NVC0_NEW_VIEWPORT;
1007 }
1008
1009 }
1010
1011 static void
1012 nvc0_set_tess_state(struct pipe_context *pipe,
1013 const float default_tess_outer[4],
1014 const float default_tess_inner[2])
1015 {
1016 struct nvc0_context *nvc0 = nvc0_context(pipe);
1017
1018 memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
1019 memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
1020 nvc0->dirty |= NVC0_NEW_TESSFACTOR;
1021 }
1022
1023 static void
1024 nvc0_set_vertex_buffers(struct pipe_context *pipe,
1025 unsigned start_slot, unsigned count,
1026 const struct pipe_vertex_buffer *vb)
1027 {
1028 struct nvc0_context *nvc0 = nvc0_context(pipe);
1029 unsigned i;
1030
1031 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX);
1032 nvc0->dirty |= NVC0_NEW_ARRAYS;
1033
1034 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
1035 start_slot, count);
1036
1037 if (!vb) {
1038 nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
1039 nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
1040 nvc0->vtxbufs_coherent &= ~(((1ull << count) - 1) << start_slot);
1041 return;
1042 }
1043
1044 for (i = 0; i < count; ++i) {
1045 unsigned dst_index = start_slot + i;
1046
1047 if (vb[i].user_buffer) {
1048 nvc0->vbo_user |= 1 << dst_index;
1049 if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
1050 nvc0->constant_vbos |= 1 << dst_index;
1051 else
1052 nvc0->constant_vbos &= ~(1 << dst_index);
1053 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1054 } else {
1055 nvc0->vbo_user &= ~(1 << dst_index);
1056 nvc0->constant_vbos &= ~(1 << dst_index);
1057
1058 if (vb[i].buffer &&
1059 vb[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1060 nvc0->vtxbufs_coherent |= (1 << dst_index);
1061 else
1062 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1063 }
1064 }
1065 }
1066
1067 static void
1068 nvc0_set_index_buffer(struct pipe_context *pipe,
1069 const struct pipe_index_buffer *ib)
1070 {
1071 struct nvc0_context *nvc0 = nvc0_context(pipe);
1072
1073 if (nvc0->idxbuf.buffer)
1074 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_IDX);
1075
1076 if (ib) {
1077 pipe_resource_reference(&nvc0->idxbuf.buffer, ib->buffer);
1078 nvc0->idxbuf.index_size = ib->index_size;
1079 if (ib->buffer) {
1080 nvc0->idxbuf.offset = ib->offset;
1081 nvc0->dirty |= NVC0_NEW_IDXBUF;
1082 } else {
1083 nvc0->idxbuf.user_buffer = ib->user_buffer;
1084 nvc0->dirty &= ~NVC0_NEW_IDXBUF;
1085 }
1086 } else {
1087 nvc0->dirty &= ~NVC0_NEW_IDXBUF;
1088 pipe_resource_reference(&nvc0->idxbuf.buffer, NULL);
1089 }
1090 }
1091
1092 static void
1093 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1094 {
1095 struct nvc0_context *nvc0 = nvc0_context(pipe);
1096
1097 nvc0->vertex = hwcso;
1098 nvc0->dirty |= NVC0_NEW_VERTEX;
1099 }
1100
1101 static struct pipe_stream_output_target *
1102 nvc0_so_target_create(struct pipe_context *pipe,
1103 struct pipe_resource *res,
1104 unsigned offset, unsigned size)
1105 {
1106 struct nv04_resource *buf = (struct nv04_resource *)res;
1107 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1108 if (!targ)
1109 return NULL;
1110
1111 targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0);
1112 if (!targ->pq) {
1113 FREE(targ);
1114 return NULL;
1115 }
1116 targ->clean = true;
1117
1118 targ->pipe.buffer_size = size;
1119 targ->pipe.buffer_offset = offset;
1120 targ->pipe.context = pipe;
1121 targ->pipe.buffer = NULL;
1122 pipe_resource_reference(&targ->pipe.buffer, res);
1123 pipe_reference_init(&targ->pipe.reference, 1);
1124
1125 assert(buf->base.target == PIPE_BUFFER);
1126 util_range_add(&buf->valid_buffer_range, offset, offset + size);
1127
1128 return &targ->pipe;
1129 }
1130
1131 static void
1132 nvc0_so_target_save_offset(struct pipe_context *pipe,
1133 struct pipe_stream_output_target *ptarg,
1134 unsigned index, bool *serialize)
1135 {
1136 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1137
1138 if (*serialize) {
1139 *serialize = false;
1140 PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
1141 IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
1142
1143 NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
1144 }
1145
1146 nvc0_query(targ->pq)->index = index;
1147 pipe->end_query(pipe, targ->pq);
1148 }
1149
1150 static void
1151 nvc0_so_target_destroy(struct pipe_context *pipe,
1152 struct pipe_stream_output_target *ptarg)
1153 {
1154 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1155 pipe->destroy_query(pipe, targ->pq);
1156 pipe_resource_reference(&targ->pipe.buffer, NULL);
1157 FREE(targ);
1158 }
1159
1160 static void
1161 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1162 unsigned num_targets,
1163 struct pipe_stream_output_target **targets,
1164 const unsigned *offsets)
1165 {
1166 struct nvc0_context *nvc0 = nvc0_context(pipe);
1167 unsigned i;
1168 bool serialize = true;
1169
1170 assert(num_targets <= 4);
1171
1172 for (i = 0; i < num_targets; ++i) {
1173 const bool changed = nvc0->tfbbuf[i] != targets[i];
1174 const bool append = (offsets[i] == ((unsigned)-1));
1175 if (!changed && append)
1176 continue;
1177 nvc0->tfbbuf_dirty |= 1 << i;
1178
1179 if (nvc0->tfbbuf[i] && changed)
1180 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1181
1182 if (targets[i] && !append)
1183 nvc0_so_target(targets[i])->clean = true;
1184
1185 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1186 }
1187 for (; i < nvc0->num_tfbbufs; ++i) {
1188 if (nvc0->tfbbuf[i]) {
1189 nvc0->tfbbuf_dirty |= 1 << i;
1190 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1191 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1192 }
1193 }
1194 nvc0->num_tfbbufs = num_targets;
1195
1196 if (nvc0->tfbbuf_dirty)
1197 nvc0->dirty |= NVC0_NEW_TFB_TARGETS;
1198 }
1199
1200 static void
1201 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1202 unsigned start, unsigned nr,
1203 struct pipe_surface **psurfaces)
1204 {
1205 const unsigned end = start + nr;
1206 const unsigned mask = ((1 << nr) - 1) << start;
1207 unsigned i;
1208
1209 if (psurfaces) {
1210 for (i = start; i < end; ++i) {
1211 const unsigned p = i - start;
1212 if (psurfaces[p])
1213 nvc0->surfaces_valid[t] |= (1 << i);
1214 else
1215 nvc0->surfaces_valid[t] &= ~(1 << i);
1216 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1217 }
1218 } else {
1219 for (i = start; i < end; ++i)
1220 pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1221 nvc0->surfaces_valid[t] &= ~mask;
1222 }
1223 nvc0->surfaces_dirty[t] |= mask;
1224
1225 if (t == 0)
1226 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_SUF);
1227 else
1228 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1229 }
1230
1231 static void
1232 nvc0_set_compute_resources(struct pipe_context *pipe,
1233 unsigned start, unsigned nr,
1234 struct pipe_surface **resources)
1235 {
1236 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1237
1238 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1239 }
1240
1241 static void
1242 nvc0_set_shader_images(struct pipe_context *pipe, unsigned shader,
1243 unsigned start_slot, unsigned count,
1244 struct pipe_image_view **views)
1245 {
1246 #if 0
1247 nvc0_bind_surfaces_range(nvc0_context(pipe), 0, start, nr, views);
1248
1249 nvc0_context(pipe)->dirty |= NVC0_NEW_SURFACES;
1250 #endif
1251 }
1252
1253 static inline void
1254 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1255 {
1256 struct nv04_resource *buf = nv04_resource(res);
1257 if (buf) {
1258 uint64_t limit = (buf->address + buf->base.width0) - 1;
1259 if (limit < (1ULL << 32)) {
1260 *phandle = (uint32_t)buf->address;
1261 } else {
1262 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1263 "resource not contained within 32-bit address space !\n");
1264 *phandle = 0;
1265 }
1266 } else {
1267 *phandle = 0;
1268 }
1269 }
1270
1271 static void
1272 nvc0_set_global_bindings(struct pipe_context *pipe,
1273 unsigned start, unsigned nr,
1274 struct pipe_resource **resources,
1275 uint32_t **handles)
1276 {
1277 struct nvc0_context *nvc0 = nvc0_context(pipe);
1278 struct pipe_resource **ptr;
1279 unsigned i;
1280 const unsigned end = start + nr;
1281
1282 if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1283 const unsigned old_size = nvc0->global_residents.size;
1284 const unsigned req_size = end * sizeof(struct pipe_resource *);
1285 util_dynarray_resize(&nvc0->global_residents, req_size);
1286 memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1287 req_size - old_size);
1288 }
1289
1290 if (resources) {
1291 ptr = util_dynarray_element(
1292 &nvc0->global_residents, struct pipe_resource *, start);
1293 for (i = 0; i < nr; ++i) {
1294 pipe_resource_reference(&ptr[i], resources[i]);
1295 nvc0_set_global_handle(handles[i], resources[i]);
1296 }
1297 } else {
1298 ptr = util_dynarray_element(
1299 &nvc0->global_residents, struct pipe_resource *, start);
1300 for (i = 0; i < nr; ++i)
1301 pipe_resource_reference(&ptr[i], NULL);
1302 }
1303
1304 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1305
1306 nvc0->dirty_cp = NVC0_NEW_CP_GLOBALS;
1307 }
1308
1309 void
1310 nvc0_init_state_functions(struct nvc0_context *nvc0)
1311 {
1312 struct pipe_context *pipe = &nvc0->base.pipe;
1313
1314 pipe->create_blend_state = nvc0_blend_state_create;
1315 pipe->bind_blend_state = nvc0_blend_state_bind;
1316 pipe->delete_blend_state = nvc0_blend_state_delete;
1317
1318 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1319 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1320 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1321
1322 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1323 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1324 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1325
1326 pipe->create_sampler_state = nv50_sampler_state_create;
1327 pipe->delete_sampler_state = nvc0_sampler_state_delete;
1328 pipe->bind_sampler_states = nvc0_bind_sampler_states;
1329
1330 pipe->create_sampler_view = nvc0_create_sampler_view;
1331 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1332 pipe->set_sampler_views = nvc0_set_sampler_views;
1333
1334 pipe->create_vs_state = nvc0_vp_state_create;
1335 pipe->create_fs_state = nvc0_fp_state_create;
1336 pipe->create_gs_state = nvc0_gp_state_create;
1337 pipe->create_tcs_state = nvc0_tcp_state_create;
1338 pipe->create_tes_state = nvc0_tep_state_create;
1339 pipe->bind_vs_state = nvc0_vp_state_bind;
1340 pipe->bind_fs_state = nvc0_fp_state_bind;
1341 pipe->bind_gs_state = nvc0_gp_state_bind;
1342 pipe->bind_tcs_state = nvc0_tcp_state_bind;
1343 pipe->bind_tes_state = nvc0_tep_state_bind;
1344 pipe->delete_vs_state = nvc0_sp_state_delete;
1345 pipe->delete_fs_state = nvc0_sp_state_delete;
1346 pipe->delete_gs_state = nvc0_sp_state_delete;
1347 pipe->delete_tcs_state = nvc0_sp_state_delete;
1348 pipe->delete_tes_state = nvc0_sp_state_delete;
1349
1350 pipe->create_compute_state = nvc0_cp_state_create;
1351 pipe->bind_compute_state = nvc0_cp_state_bind;
1352 pipe->delete_compute_state = nvc0_sp_state_delete;
1353
1354 pipe->set_blend_color = nvc0_set_blend_color;
1355 pipe->set_stencil_ref = nvc0_set_stencil_ref;
1356 pipe->set_clip_state = nvc0_set_clip_state;
1357 pipe->set_sample_mask = nvc0_set_sample_mask;
1358 pipe->set_min_samples = nvc0_set_min_samples;
1359 pipe->set_constant_buffer = nvc0_set_constant_buffer;
1360 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1361 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1362 pipe->set_scissor_states = nvc0_set_scissor_states;
1363 pipe->set_viewport_states = nvc0_set_viewport_states;
1364 pipe->set_tess_state = nvc0_set_tess_state;
1365
1366 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1367 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1368 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1369
1370 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1371 pipe->set_index_buffer = nvc0_set_index_buffer;
1372
1373 pipe->create_stream_output_target = nvc0_so_target_create;
1374 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1375 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1376
1377 pipe->set_global_binding = nvc0_set_global_bindings;
1378 pipe->set_compute_resources = nvc0_set_compute_resources;
1379 pipe->set_shader_images = nvc0_set_shader_images;
1380
1381 nvc0->sample_mask = ~0;
1382 nvc0->min_samples = 1;
1383 nvc0->default_tess_outer[0] =
1384 nvc0->default_tess_outer[1] =
1385 nvc0->default_tess_outer[2] =
1386 nvc0->default_tess_outer[3] = 1.0;
1387 nvc0->default_tess_inner[0] =
1388 nvc0->default_tess_inner[1] = 1.0;
1389 }