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nvc0: regenerate rnndb headers
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_helpers.h"
25 #include "util/u_inlines.h"
26 #include "util/u_transfer.h"
27
28 #include "tgsi/tgsi_parse.h"
29
30 #include "nvc0/nvc0_stateobj.h"
31 #include "nvc0/nvc0_context.h"
32
33 #include "nvc0/nvc0_3d.xml.h"
34 #include "nv50/nv50_texture.xml.h"
35
36 #include "nouveau_gldefs.h"
37
38 static INLINE uint32_t
39 nvc0_colormask(unsigned mask)
40 {
41 uint32_t ret = 0;
42
43 if (mask & PIPE_MASK_R)
44 ret |= 0x0001;
45 if (mask & PIPE_MASK_G)
46 ret |= 0x0010;
47 if (mask & PIPE_MASK_B)
48 ret |= 0x0100;
49 if (mask & PIPE_MASK_A)
50 ret |= 0x1000;
51
52 return ret;
53 }
54
55 #define NVC0_BLEND_FACTOR_CASE(a, b) \
56 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
57
58 static INLINE uint32_t
59 nvc0_blend_fac(unsigned factor)
60 {
61 switch (factor) {
62 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
63 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
64 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
65 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
66 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
67 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
68 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
69 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
70 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
71 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
72 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
73 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
74 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
75 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
76 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
77 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
78 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
79 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
80 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
81 default:
82 return NV50_BLEND_FACTOR_ZERO;
83 }
84 }
85
86 static void *
87 nvc0_blend_state_create(struct pipe_context *pipe,
88 const struct pipe_blend_state *cso)
89 {
90 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
91 int i;
92 int r; /* reference */
93 uint32_t ms;
94 uint8_t blend_en = 0;
95 boolean indep_masks = FALSE;
96 boolean indep_funcs = FALSE;
97
98 so->pipe = *cso;
99
100 /* check which states actually have differing values */
101 if (cso->independent_blend_enable) {
102 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
103 blend_en |= 1 << r;
104 for (i = r + 1; i < 8; ++i) {
105 if (!cso->rt[i].blend_enable)
106 continue;
107 blend_en |= 1 << i;
108 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
109 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
110 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
111 cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
112 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
113 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
114 indep_funcs = TRUE;
115 break;
116 }
117 }
118 for (; i < 8; ++i)
119 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
120
121 for (i = 1; i < 8; ++i) {
122 if (cso->rt[i].colormask != cso->rt[0].colormask) {
123 indep_masks = TRUE;
124 break;
125 }
126 }
127 } else {
128 r = 0;
129 if (cso->rt[0].blend_enable)
130 blend_en = 0xff;
131 }
132
133 if (cso->logicop_enable) {
134 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
135 SB_DATA (so, 1);
136 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
137
138 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
139 } else {
140 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
141
142 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
143 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
144 if (indep_funcs) {
145 for (i = 0; i < 8; ++i) {
146 if (cso->rt[i].blend_enable) {
147 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
148 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
149 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
150 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
151 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
152 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
153 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
154 }
155 }
156 } else
157 if (blend_en) {
158 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
159 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
160 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
161 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
162 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
163 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
164 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
165 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
166 }
167
168 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
169 if (indep_masks) {
170 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
171 for (i = 0; i < 8; ++i)
172 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
173 } else {
174 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
175 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
176 }
177 }
178
179 ms = 0;
180 if (cso->alpha_to_coverage)
181 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
182 if (cso->alpha_to_one)
183 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
184
185 SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
186 SB_DATA (so, ms);
187
188 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
189 return so;
190 }
191
192 static void
193 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
194 {
195 struct nvc0_context *nvc0 = nvc0_context(pipe);
196
197 nvc0->blend = hwcso;
198 nvc0->dirty |= NVC0_NEW_BLEND;
199 }
200
201 static void
202 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
203 {
204 FREE(hwcso);
205 }
206
207 /* NOTE: ignoring line_last_pixel */
208 static void *
209 nvc0_rasterizer_state_create(struct pipe_context *pipe,
210 const struct pipe_rasterizer_state *cso)
211 {
212 struct nvc0_rasterizer_stateobj *so;
213 uint32_t reg;
214
215 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
216 if (!so)
217 return NULL;
218 so->pipe = *cso;
219
220 /* Scissor enables are handled in scissor state, we will not want to
221 * always emit 16 commands, one for each scissor rectangle, here.
222 */
223
224 SB_BEGIN_3D(so, SHADE_MODEL, 1);
225 SB_DATA (so, cso->flatshade ? NVC0_3D_SHADE_MODEL_FLAT :
226 NVC0_3D_SHADE_MODEL_SMOOTH);
227 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
228 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
229
230 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
231 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
232 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
233
234 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
235
236 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
237 if (cso->line_smooth)
238 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
239 else
240 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
241 SB_DATA (so, fui(cso->line_width));
242
243 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
244 if (cso->line_stipple_enable) {
245 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
246 SB_DATA (so, (cso->line_stipple_pattern << 8) |
247 cso->line_stipple_factor);
248
249 }
250
251 SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
252 if (!cso->point_size_per_vertex) {
253 SB_BEGIN_3D(so, POINT_SIZE, 1);
254 SB_DATA (so, fui(cso->point_size));
255 }
256
257 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
258 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
259 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
260
261 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
262 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
263 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
264 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
265
266 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
267 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
268 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
269 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
270 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
271
272 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
273 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
274 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
275 NVC0_3D_FRONT_FACE_CW);
276 switch (cso->cull_face) {
277 case PIPE_FACE_FRONT_AND_BACK:
278 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
279 break;
280 case PIPE_FACE_FRONT:
281 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
282 break;
283 case PIPE_FACE_BACK:
284 default:
285 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
286 break;
287 }
288
289 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
290 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
291 SB_DATA (so, cso->offset_point);
292 SB_DATA (so, cso->offset_line);
293 SB_DATA (so, cso->offset_tri);
294
295 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
296 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
297 SB_DATA (so, fui(cso->offset_scale));
298 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
299 SB_DATA (so, fui(cso->offset_units * 2.0f));
300 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
301 SB_DATA (so, fui(cso->offset_clamp));
302 }
303
304 if (cso->depth_clip)
305 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
306 else
307 reg =
308 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
309 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
310 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
311 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
312
313 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
314 SB_DATA (so, reg);
315
316 SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
317
318 SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
319
320 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
321 return (void *)so;
322 }
323
324 static void
325 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
326 {
327 struct nvc0_context *nvc0 = nvc0_context(pipe);
328
329 nvc0->rast = hwcso;
330 nvc0->dirty |= NVC0_NEW_RASTERIZER;
331 }
332
333 static void
334 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
335 {
336 FREE(hwcso);
337 }
338
339 static void *
340 nvc0_zsa_state_create(struct pipe_context *pipe,
341 const struct pipe_depth_stencil_alpha_state *cso)
342 {
343 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
344
345 so->pipe = *cso;
346
347 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
348 if (cso->depth.enabled) {
349 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
350 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
351 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
352 }
353
354 if (cso->stencil[0].enabled) {
355 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
356 SB_DATA (so, 1);
357 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
358 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
359 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
360 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
361 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
362 SB_DATA (so, cso->stencil[0].valuemask);
363 SB_DATA (so, cso->stencil[0].writemask);
364 } else {
365 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
366 }
367
368 if (cso->stencil[1].enabled) {
369 assert(cso->stencil[0].enabled);
370 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
371 SB_DATA (so, 1);
372 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
373 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
374 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
375 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
376 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
377 SB_DATA (so, cso->stencil[1].writemask);
378 SB_DATA (so, cso->stencil[1].valuemask);
379 } else
380 if (cso->stencil[0].enabled) {
381 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
382 }
383
384 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
385 if (cso->alpha.enabled) {
386 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
387 SB_DATA (so, fui(cso->alpha.ref_value));
388 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
389 }
390
391 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
392 return (void *)so;
393 }
394
395 static void
396 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
397 {
398 struct nvc0_context *nvc0 = nvc0_context(pipe);
399
400 nvc0->zsa = hwcso;
401 nvc0->dirty |= NVC0_NEW_ZSA;
402 }
403
404 static void
405 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
406 {
407 FREE(hwcso);
408 }
409
410 /* ====================== SAMPLERS AND TEXTURES ================================
411 */
412
413 #define NV50_TSC_WRAP_CASE(n) \
414 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
415
416 static INLINE unsigned
417 nv50_tsc_wrap_mode(unsigned wrap)
418 {
419 switch (wrap) {
420 NV50_TSC_WRAP_CASE(REPEAT);
421 NV50_TSC_WRAP_CASE(MIRROR_REPEAT);
422 NV50_TSC_WRAP_CASE(CLAMP_TO_EDGE);
423 NV50_TSC_WRAP_CASE(CLAMP_TO_BORDER);
424 NV50_TSC_WRAP_CASE(CLAMP);
425 NV50_TSC_WRAP_CASE(MIRROR_CLAMP_TO_EDGE);
426 NV50_TSC_WRAP_CASE(MIRROR_CLAMP_TO_BORDER);
427 NV50_TSC_WRAP_CASE(MIRROR_CLAMP);
428 default:
429 NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
430 return NV50_TSC_WRAP_REPEAT;
431 }
432 }
433
434 static void
435 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
436 {
437 unsigned s, i;
438
439 for (s = 0; s < 5; ++s)
440 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
441 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
442 nvc0_context(pipe)->samplers[s][i] = NULL;
443
444 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
445
446 FREE(hwcso);
447 }
448
449 static INLINE void
450 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0, int s,
451 unsigned nr, void **hwcso)
452 {
453 unsigned i;
454
455 for (i = 0; i < nr; ++i) {
456 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
457
458 if (hwcso[i] == old)
459 continue;
460 nvc0->samplers_dirty[s] |= 1 << i;
461
462 nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
463 if (old)
464 nvc0_screen_tsc_unlock(nvc0->screen, old);
465 }
466 for (; i < nvc0->num_samplers[s]; ++i) {
467 if (nvc0->samplers[s][i]) {
468 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
469 nvc0->samplers[s][i] = NULL;
470 }
471 }
472
473 nvc0->num_samplers[s] = nr;
474
475 nvc0->dirty |= NVC0_NEW_SAMPLERS;
476 }
477
478 static void
479 nvc0_stage_sampler_states_bind_range(struct nvc0_context *nvc0,
480 const unsigned s,
481 unsigned start, unsigned nr, void **cso)
482 {
483 const unsigned end = start + nr;
484 int last_valid = -1;
485 unsigned i;
486
487 if (cso) {
488 for (i = start; i < end; ++i) {
489 const unsigned p = i - start;
490 if (cso[p])
491 last_valid = i;
492 if (cso[p] == nvc0->samplers[s][i])
493 continue;
494 nvc0->samplers_dirty[s] |= 1 << i;
495
496 if (nvc0->samplers[s][i])
497 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
498 nvc0->samplers[s][i] = cso[p];
499 }
500 } else {
501 for (i = start; i < end; ++i) {
502 if (nvc0->samplers[s][i]) {
503 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
504 nvc0->samplers[s][i] = NULL;
505 nvc0->samplers_dirty[s] |= 1 << i;
506 }
507 }
508 }
509
510 if (nvc0->num_samplers[s] <= end) {
511 if (last_valid < 0) {
512 for (i = start; i && !nvc0->samplers[s][i - 1]; --i);
513 nvc0->num_samplers[s] = i;
514 } else {
515 nvc0->num_samplers[s] = last_valid + 1;
516 }
517 }
518 }
519
520 static void
521 nvc0_bind_sampler_states(struct pipe_context *pipe, unsigned shader,
522 unsigned start, unsigned nr, void **s)
523 {
524 switch (shader) {
525 case PIPE_SHADER_VERTEX:
526 assert(start == 0);
527 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 0, nr, s);
528 break;
529 case PIPE_SHADER_GEOMETRY:
530 assert(start == 0);
531 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 3, nr, s);
532 break;
533 case PIPE_SHADER_FRAGMENT:
534 assert(start == 0);
535 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 4, nr, s);
536 break;
537 case PIPE_SHADER_COMPUTE:
538 nvc0_stage_sampler_states_bind_range(nvc0_context(pipe), 5,
539 start, nr, s);
540 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
541 break;
542 }
543 }
544
545
546 /* NOTE: only called when not referenced anywhere, won't be bound */
547 static void
548 nvc0_sampler_view_destroy(struct pipe_context *pipe,
549 struct pipe_sampler_view *view)
550 {
551 pipe_resource_reference(&view->texture, NULL);
552
553 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
554
555 FREE(nv50_tic_entry(view));
556 }
557
558 static INLINE void
559 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
560 unsigned nr,
561 struct pipe_sampler_view **views)
562 {
563 unsigned i;
564
565 for (i = 0; i < nr; ++i) {
566 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
567
568 if (views[i] == nvc0->textures[s][i])
569 continue;
570 nvc0->textures_dirty[s] |= 1 << i;
571
572 if (old) {
573 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(s, i));
574 nvc0_screen_tic_unlock(nvc0->screen, old);
575 }
576
577 pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
578 }
579
580 for (i = nr; i < nvc0->num_textures[s]; ++i) {
581 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
582 if (old) {
583 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(s, i));
584 nvc0_screen_tic_unlock(nvc0->screen, old);
585 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
586 }
587 }
588
589 nvc0->num_textures[s] = nr;
590
591 nvc0->dirty |= NVC0_NEW_TEXTURES;
592 }
593
594 static void
595 nvc0_stage_set_sampler_views_range(struct nvc0_context *nvc0, const unsigned s,
596 unsigned start, unsigned nr,
597 struct pipe_sampler_view **views)
598 {
599 struct nouveau_bufctx *bctx = (s == 5) ? nvc0->bufctx_cp : nvc0->bufctx_3d;
600 const unsigned end = start + nr;
601 const unsigned bin = (s == 5) ? NVC0_BIND_CP_TEX(0) : NVC0_BIND_TEX(s, 0);
602 int last_valid = -1;
603 unsigned i;
604
605 if (views) {
606 for (i = start; i < end; ++i) {
607 const unsigned p = i - start;
608 if (views[p])
609 last_valid = i;
610 if (views[p] == nvc0->textures[s][i])
611 continue;
612 nvc0->textures_dirty[s] |= 1 << i;
613
614 if (nvc0->textures[s][i]) {
615 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
616 nouveau_bufctx_reset(bctx, bin + i);
617 nvc0_screen_tic_unlock(nvc0->screen, old);
618 }
619 pipe_sampler_view_reference(&nvc0->textures[s][i], views[p]);
620 }
621 } else {
622 for (i = start; i < end; ++i) {
623 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
624 if (!old)
625 continue;
626 nvc0->textures_dirty[s] |= 1 << i;
627
628 nvc0_screen_tic_unlock(nvc0->screen, old);
629 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
630 nouveau_bufctx_reset(bctx, bin + i);
631 }
632 }
633
634 if (nvc0->num_textures[s] <= end) {
635 if (last_valid < 0) {
636 for (i = start; i && !nvc0->textures[s][i - 1]; --i);
637 nvc0->num_textures[s] = i;
638 } else {
639 nvc0->num_textures[s] = last_valid + 1;
640 }
641 }
642 }
643
644 static void
645 nvc0_set_sampler_views(struct pipe_context *pipe, unsigned shader,
646 unsigned start, unsigned nr,
647 struct pipe_sampler_view **views)
648 {
649 assert(start == 0);
650 switch (shader) {
651 case PIPE_SHADER_VERTEX:
652 nvc0_stage_set_sampler_views(nvc0_context(pipe), 0, nr, views);
653 break;
654 case PIPE_SHADER_GEOMETRY:
655 nvc0_stage_set_sampler_views(nvc0_context(pipe), 3, nr, views);
656 break;
657 case PIPE_SHADER_FRAGMENT:
658 nvc0_stage_set_sampler_views(nvc0_context(pipe), 4, nr, views);
659 break;
660 case PIPE_SHADER_COMPUTE:
661 nvc0_stage_set_sampler_views_range(nvc0_context(pipe), 5,
662 start, nr, views);
663 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
664 break;
665 default:
666 ;
667 }
668 }
669
670
671 /* ============================= SHADERS =======================================
672 */
673
674 static void *
675 nvc0_sp_state_create(struct pipe_context *pipe,
676 const struct pipe_shader_state *cso, unsigned type)
677 {
678 struct nvc0_program *prog;
679
680 prog = CALLOC_STRUCT(nvc0_program);
681 if (!prog)
682 return NULL;
683
684 prog->type = type;
685
686 if (cso->tokens)
687 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
688
689 if (cso->stream_output.num_outputs)
690 prog->pipe.stream_output = cso->stream_output;
691
692 return (void *)prog;
693 }
694
695 static void
696 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
697 {
698 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
699
700 nvc0_program_destroy(nvc0_context(pipe), prog);
701
702 FREE((void *)prog->pipe.tokens);
703 FREE(prog);
704 }
705
706 static void *
707 nvc0_vp_state_create(struct pipe_context *pipe,
708 const struct pipe_shader_state *cso)
709 {
710 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
711 }
712
713 static void
714 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
715 {
716 struct nvc0_context *nvc0 = nvc0_context(pipe);
717
718 nvc0->vertprog = hwcso;
719 nvc0->dirty |= NVC0_NEW_VERTPROG;
720 }
721
722 static void *
723 nvc0_fp_state_create(struct pipe_context *pipe,
724 const struct pipe_shader_state *cso)
725 {
726 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
727 }
728
729 static void
730 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
731 {
732 struct nvc0_context *nvc0 = nvc0_context(pipe);
733
734 nvc0->fragprog = hwcso;
735 nvc0->dirty |= NVC0_NEW_FRAGPROG;
736 }
737
738 static void *
739 nvc0_gp_state_create(struct pipe_context *pipe,
740 const struct pipe_shader_state *cso)
741 {
742 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
743 }
744
745 static void
746 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
747 {
748 struct nvc0_context *nvc0 = nvc0_context(pipe);
749
750 nvc0->gmtyprog = hwcso;
751 nvc0->dirty |= NVC0_NEW_GMTYPROG;
752 }
753
754 static void *
755 nvc0_cp_state_create(struct pipe_context *pipe,
756 const struct pipe_compute_state *cso)
757 {
758 struct nvc0_program *prog;
759
760 prog = CALLOC_STRUCT(nvc0_program);
761 if (!prog)
762 return NULL;
763 prog->type = PIPE_SHADER_COMPUTE;
764
765 prog->cp.smem_size = cso->req_local_mem;
766 prog->cp.lmem_size = cso->req_private_mem;
767 prog->parm_size = cso->req_input_mem;
768
769 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
770
771 return (void *)prog;
772 }
773
774 static void
775 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
776 {
777 struct nvc0_context *nvc0 = nvc0_context(pipe);
778
779 nvc0->compprog = hwcso;
780 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
781 }
782
783 static void
784 nvc0_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
785 struct pipe_constant_buffer *cb)
786 {
787 struct nvc0_context *nvc0 = nvc0_context(pipe);
788 struct pipe_resource *res = cb ? cb->buffer : NULL;
789 const unsigned s = nvc0_shader_stage(shader);
790 const unsigned i = index;
791
792 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
793 assert(!cb || !cb->user_buffer);
794 if (nvc0->constbuf[s][i].u.buf)
795 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
796
797 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
798 } else {
799 if (nvc0->constbuf[s][i].user)
800 nvc0->constbuf[s][i].u.buf = NULL;
801 else
802 if (nvc0->constbuf[s][i].u.buf)
803 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_CB(s, i));
804
805 nvc0->dirty |= NVC0_NEW_CONSTBUF;
806 }
807 nvc0->constbuf_dirty[s] |= 1 << i;
808
809 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
810
811 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? TRUE : FALSE;
812 if (nvc0->constbuf[s][i].user) {
813 nvc0->constbuf[s][i].u.data = cb->user_buffer;
814 nvc0->constbuf[s][i].size = cb->buffer_size;
815 nvc0->constbuf_valid[s] |= 1 << i;
816 } else
817 if (cb) {
818 nvc0->constbuf[s][i].offset = cb->buffer_offset;
819 nvc0->constbuf[s][i].size = align(cb->buffer_size, 0x100);
820 nvc0->constbuf_valid[s] |= 1 << i;
821 }
822 else {
823 nvc0->constbuf_valid[s] &= ~(1 << i);
824 }
825 }
826
827 /* =============================================================================
828 */
829
830 static void
831 nvc0_set_blend_color(struct pipe_context *pipe,
832 const struct pipe_blend_color *bcol)
833 {
834 struct nvc0_context *nvc0 = nvc0_context(pipe);
835
836 nvc0->blend_colour = *bcol;
837 nvc0->dirty |= NVC0_NEW_BLEND_COLOUR;
838 }
839
840 static void
841 nvc0_set_stencil_ref(struct pipe_context *pipe,
842 const struct pipe_stencil_ref *sr)
843 {
844 struct nvc0_context *nvc0 = nvc0_context(pipe);
845
846 nvc0->stencil_ref = *sr;
847 nvc0->dirty |= NVC0_NEW_STENCIL_REF;
848 }
849
850 static void
851 nvc0_set_clip_state(struct pipe_context *pipe,
852 const struct pipe_clip_state *clip)
853 {
854 struct nvc0_context *nvc0 = nvc0_context(pipe);
855
856 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
857
858 nvc0->dirty |= NVC0_NEW_CLIP;
859 }
860
861 static void
862 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
863 {
864 struct nvc0_context *nvc0 = nvc0_context(pipe);
865
866 nvc0->sample_mask = sample_mask;
867 nvc0->dirty |= NVC0_NEW_SAMPLE_MASK;
868 }
869
870 static void
871 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
872 {
873 struct nvc0_context *nvc0 = nvc0_context(pipe);
874
875 if (nvc0->min_samples != min_samples) {
876 nvc0->min_samples = min_samples;
877 nvc0->dirty |= NVC0_NEW_MIN_SAMPLES;
878 }
879 }
880
881 static void
882 nvc0_set_framebuffer_state(struct pipe_context *pipe,
883 const struct pipe_framebuffer_state *fb)
884 {
885 struct nvc0_context *nvc0 = nvc0_context(pipe);
886 unsigned i;
887
888 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
889
890 for (i = 0; i < fb->nr_cbufs; ++i)
891 pipe_surface_reference(&nvc0->framebuffer.cbufs[i], fb->cbufs[i]);
892 for (; i < nvc0->framebuffer.nr_cbufs; ++i)
893 pipe_surface_reference(&nvc0->framebuffer.cbufs[i], NULL);
894
895 nvc0->framebuffer.nr_cbufs = fb->nr_cbufs;
896
897 nvc0->framebuffer.width = fb->width;
898 nvc0->framebuffer.height = fb->height;
899
900 pipe_surface_reference(&nvc0->framebuffer.zsbuf, fb->zsbuf);
901
902 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
903 }
904
905 static void
906 nvc0_set_polygon_stipple(struct pipe_context *pipe,
907 const struct pipe_poly_stipple *stipple)
908 {
909 struct nvc0_context *nvc0 = nvc0_context(pipe);
910
911 nvc0->stipple = *stipple;
912 nvc0->dirty |= NVC0_NEW_STIPPLE;
913 }
914
915 static void
916 nvc0_set_scissor_states(struct pipe_context *pipe,
917 unsigned start_slot,
918 unsigned num_scissors,
919 const struct pipe_scissor_state *scissor)
920 {
921 struct nvc0_context *nvc0 = nvc0_context(pipe);
922 int i;
923
924 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
925 for (i = 0; i < num_scissors; i++) {
926 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
927 continue;
928 nvc0->scissors[start_slot + i] = scissor[i];
929 nvc0->scissors_dirty |= 1 << (start_slot + i);
930 nvc0->dirty |= NVC0_NEW_SCISSOR;
931 }
932 }
933
934 static void
935 nvc0_set_viewport_states(struct pipe_context *pipe,
936 unsigned start_slot,
937 unsigned num_viewports,
938 const struct pipe_viewport_state *vpt)
939 {
940 struct nvc0_context *nvc0 = nvc0_context(pipe);
941 int i;
942
943 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
944 for (i = 0; i < num_viewports; i++) {
945 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
946 continue;
947 nvc0->viewports[start_slot + i] = vpt[i];
948 nvc0->viewports_dirty |= 1 << (start_slot + i);
949 nvc0->dirty |= NVC0_NEW_VIEWPORT;
950 }
951
952 }
953
954 static void
955 nvc0_set_vertex_buffers(struct pipe_context *pipe,
956 unsigned start_slot, unsigned count,
957 const struct pipe_vertex_buffer *vb)
958 {
959 struct nvc0_context *nvc0 = nvc0_context(pipe);
960 unsigned i;
961
962 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
963 start_slot, count);
964
965 if (!vb) {
966 nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
967 nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
968 return;
969 }
970
971 for (i = 0; i < count; ++i) {
972 unsigned dst_index = start_slot + i;
973
974 if (vb[i].user_buffer) {
975 nvc0->vbo_user |= 1 << dst_index;
976 if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
977 nvc0->constant_vbos |= 1 << dst_index;
978 else
979 nvc0->constant_vbos &= ~(1 << dst_index);
980 } else {
981 nvc0->vbo_user &= ~(1 << dst_index);
982 nvc0->constant_vbos &= ~(1 << dst_index);
983 }
984 }
985
986 nvc0->dirty |= NVC0_NEW_ARRAYS;
987 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX);
988 }
989
990 static void
991 nvc0_set_index_buffer(struct pipe_context *pipe,
992 const struct pipe_index_buffer *ib)
993 {
994 struct nvc0_context *nvc0 = nvc0_context(pipe);
995
996 if (nvc0->idxbuf.buffer)
997 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_IDX);
998
999 if (ib) {
1000 pipe_resource_reference(&nvc0->idxbuf.buffer, ib->buffer);
1001 nvc0->idxbuf.index_size = ib->index_size;
1002 if (ib->buffer) {
1003 nvc0->idxbuf.offset = ib->offset;
1004 nvc0->dirty |= NVC0_NEW_IDXBUF;
1005 } else {
1006 nvc0->idxbuf.user_buffer = ib->user_buffer;
1007 nvc0->dirty &= ~NVC0_NEW_IDXBUF;
1008 }
1009 } else {
1010 nvc0->dirty &= ~NVC0_NEW_IDXBUF;
1011 pipe_resource_reference(&nvc0->idxbuf.buffer, NULL);
1012 }
1013 }
1014
1015 static void
1016 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1017 {
1018 struct nvc0_context *nvc0 = nvc0_context(pipe);
1019
1020 nvc0->vertex = hwcso;
1021 nvc0->dirty |= NVC0_NEW_VERTEX;
1022 }
1023
1024 static struct pipe_stream_output_target *
1025 nvc0_so_target_create(struct pipe_context *pipe,
1026 struct pipe_resource *res,
1027 unsigned offset, unsigned size)
1028 {
1029 struct nv04_resource *buf = (struct nv04_resource *)res;
1030 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1031 if (!targ)
1032 return NULL;
1033
1034 targ->pq = pipe->create_query(pipe, NVC0_QUERY_TFB_BUFFER_OFFSET, 0);
1035 if (!targ->pq) {
1036 FREE(targ);
1037 return NULL;
1038 }
1039 targ->clean = TRUE;
1040
1041 targ->pipe.buffer_size = size;
1042 targ->pipe.buffer_offset = offset;
1043 targ->pipe.context = pipe;
1044 targ->pipe.buffer = NULL;
1045 pipe_resource_reference(&targ->pipe.buffer, res);
1046 pipe_reference_init(&targ->pipe.reference, 1);
1047
1048 assert(buf->base.target == PIPE_BUFFER);
1049 util_range_add(&buf->valid_buffer_range, offset, offset + size);
1050
1051 return &targ->pipe;
1052 }
1053
1054 static void
1055 nvc0_so_target_destroy(struct pipe_context *pipe,
1056 struct pipe_stream_output_target *ptarg)
1057 {
1058 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1059 pipe->destroy_query(pipe, targ->pq);
1060 pipe_resource_reference(&targ->pipe.buffer, NULL);
1061 FREE(targ);
1062 }
1063
1064 static void
1065 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1066 unsigned num_targets,
1067 struct pipe_stream_output_target **targets,
1068 const unsigned *offsets)
1069 {
1070 struct nvc0_context *nvc0 = nvc0_context(pipe);
1071 unsigned i;
1072 boolean serialize = TRUE;
1073
1074 assert(num_targets <= 4);
1075
1076 for (i = 0; i < num_targets; ++i) {
1077 const boolean changed = nvc0->tfbbuf[i] != targets[i];
1078 const boolean append = (offsets[i] == ((unsigned)-1));
1079 if (!changed && append)
1080 continue;
1081 nvc0->tfbbuf_dirty |= 1 << i;
1082
1083 if (nvc0->tfbbuf[i] && changed)
1084 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1085
1086 if (targets[i] && !append)
1087 nvc0_so_target(targets[i])->clean = TRUE;
1088
1089 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1090 }
1091 for (; i < nvc0->num_tfbbufs; ++i) {
1092 nvc0->tfbbuf_dirty |= 1 << i;
1093 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1094 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1095 }
1096 nvc0->num_tfbbufs = num_targets;
1097
1098 if (nvc0->tfbbuf_dirty)
1099 nvc0->dirty |= NVC0_NEW_TFB_TARGETS;
1100 }
1101
1102 static void
1103 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1104 unsigned start, unsigned nr,
1105 struct pipe_surface **psurfaces)
1106 {
1107 const unsigned end = start + nr;
1108 const unsigned mask = ((1 << nr) - 1) << start;
1109 unsigned i;
1110
1111 if (psurfaces) {
1112 for (i = start; i < end; ++i) {
1113 const unsigned p = i - start;
1114 if (psurfaces[p])
1115 nvc0->surfaces_valid[t] |= (1 << i);
1116 else
1117 nvc0->surfaces_valid[t] &= ~(1 << i);
1118 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1119 }
1120 } else {
1121 for (i = start; i < end; ++i)
1122 pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1123 nvc0->surfaces_valid[t] &= ~mask;
1124 }
1125 nvc0->surfaces_dirty[t] |= mask;
1126
1127 if (t == 0)
1128 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_SUF);
1129 else
1130 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1131 }
1132
1133 static void
1134 nvc0_set_compute_resources(struct pipe_context *pipe,
1135 unsigned start, unsigned nr,
1136 struct pipe_surface **resources)
1137 {
1138 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1139
1140 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1141 }
1142
1143 static void
1144 nvc0_set_shader_resources(struct pipe_context *pipe,
1145 unsigned start, unsigned nr,
1146 struct pipe_surface **resources)
1147 {
1148 nvc0_bind_surfaces_range(nvc0_context(pipe), 0, start, nr, resources);
1149
1150 nvc0_context(pipe)->dirty |= NVC0_NEW_SURFACES;
1151 }
1152
1153 static INLINE void
1154 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1155 {
1156 struct nv04_resource *buf = nv04_resource(res);
1157 if (buf) {
1158 uint64_t limit = (buf->address + buf->base.width0) - 1;
1159 if (limit < (1ULL << 32)) {
1160 *phandle = (uint32_t)buf->address;
1161 } else {
1162 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1163 "resource not contained within 32-bit address space !\n");
1164 *phandle = 0;
1165 }
1166 } else {
1167 *phandle = 0;
1168 }
1169 }
1170
1171 static void
1172 nvc0_set_global_bindings(struct pipe_context *pipe,
1173 unsigned start, unsigned nr,
1174 struct pipe_resource **resources,
1175 uint32_t **handles)
1176 {
1177 struct nvc0_context *nvc0 = nvc0_context(pipe);
1178 struct pipe_resource **ptr;
1179 unsigned i;
1180 const unsigned end = start + nr;
1181
1182 if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1183 const unsigned old_size = nvc0->global_residents.size;
1184 const unsigned req_size = end * sizeof(struct pipe_resource *);
1185 util_dynarray_resize(&nvc0->global_residents, req_size);
1186 memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1187 req_size - old_size);
1188 }
1189
1190 if (resources) {
1191 ptr = util_dynarray_element(
1192 &nvc0->global_residents, struct pipe_resource *, start);
1193 for (i = 0; i < nr; ++i) {
1194 pipe_resource_reference(&ptr[i], resources[i]);
1195 nvc0_set_global_handle(handles[i], resources[i]);
1196 }
1197 } else {
1198 ptr = util_dynarray_element(
1199 &nvc0->global_residents, struct pipe_resource *, start);
1200 for (i = 0; i < nr; ++i)
1201 pipe_resource_reference(&ptr[i], NULL);
1202 }
1203
1204 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1205
1206 nvc0->dirty_cp = NVC0_NEW_CP_GLOBALS;
1207 }
1208
1209 void
1210 nvc0_init_state_functions(struct nvc0_context *nvc0)
1211 {
1212 struct pipe_context *pipe = &nvc0->base.pipe;
1213
1214 pipe->create_blend_state = nvc0_blend_state_create;
1215 pipe->bind_blend_state = nvc0_blend_state_bind;
1216 pipe->delete_blend_state = nvc0_blend_state_delete;
1217
1218 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1219 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1220 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1221
1222 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1223 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1224 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1225
1226 pipe->create_sampler_state = nv50_sampler_state_create;
1227 pipe->delete_sampler_state = nvc0_sampler_state_delete;
1228 pipe->bind_sampler_states = nvc0_bind_sampler_states;
1229
1230 pipe->create_sampler_view = nvc0_create_sampler_view;
1231 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1232 pipe->set_sampler_views = nvc0_set_sampler_views;
1233
1234 pipe->create_vs_state = nvc0_vp_state_create;
1235 pipe->create_fs_state = nvc0_fp_state_create;
1236 pipe->create_gs_state = nvc0_gp_state_create;
1237 pipe->bind_vs_state = nvc0_vp_state_bind;
1238 pipe->bind_fs_state = nvc0_fp_state_bind;
1239 pipe->bind_gs_state = nvc0_gp_state_bind;
1240 pipe->delete_vs_state = nvc0_sp_state_delete;
1241 pipe->delete_fs_state = nvc0_sp_state_delete;
1242 pipe->delete_gs_state = nvc0_sp_state_delete;
1243
1244 pipe->create_compute_state = nvc0_cp_state_create;
1245 pipe->bind_compute_state = nvc0_cp_state_bind;
1246 pipe->delete_compute_state = nvc0_sp_state_delete;
1247
1248 pipe->set_blend_color = nvc0_set_blend_color;
1249 pipe->set_stencil_ref = nvc0_set_stencil_ref;
1250 pipe->set_clip_state = nvc0_set_clip_state;
1251 pipe->set_sample_mask = nvc0_set_sample_mask;
1252 pipe->set_min_samples = nvc0_set_min_samples;
1253 pipe->set_constant_buffer = nvc0_set_constant_buffer;
1254 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1255 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1256 pipe->set_scissor_states = nvc0_set_scissor_states;
1257 pipe->set_viewport_states = nvc0_set_viewport_states;
1258
1259 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1260 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1261 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1262
1263 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1264 pipe->set_index_buffer = nvc0_set_index_buffer;
1265
1266 pipe->create_stream_output_target = nvc0_so_target_create;
1267 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1268 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1269
1270 pipe->set_global_binding = nvc0_set_global_bindings;
1271 pipe->set_compute_resources = nvc0_set_compute_resources;
1272 pipe->set_shader_resources = nvc0_set_shader_resources;
1273
1274 nvc0->sample_mask = ~0;
1275 nvc0->min_samples = 1;
1276 }