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nvc0: provide support for unscaled poly offset units
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_framebuffer.h"
25 #include "util/u_helpers.h"
26 #include "util/u_inlines.h"
27 #include "util/u_transfer.h"
28
29 #include "tgsi/tgsi_parse.h"
30
31 #include "nvc0/nvc0_stateobj.h"
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_query_hw.h"
34
35 #include "nvc0/nvc0_3d.xml.h"
36
37 #include "nouveau_gldefs.h"
38
39 static inline uint32_t
40 nvc0_colormask(unsigned mask)
41 {
42 uint32_t ret = 0;
43
44 if (mask & PIPE_MASK_R)
45 ret |= 0x0001;
46 if (mask & PIPE_MASK_G)
47 ret |= 0x0010;
48 if (mask & PIPE_MASK_B)
49 ret |= 0x0100;
50 if (mask & PIPE_MASK_A)
51 ret |= 0x1000;
52
53 return ret;
54 }
55
56 #define NVC0_BLEND_FACTOR_CASE(a, b) \
57 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
58
59 static inline uint32_t
60 nvc0_blend_fac(unsigned factor)
61 {
62 switch (factor) {
63 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
64 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
65 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
66 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
67 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
68 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
69 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
70 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
71 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
72 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
73 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
74 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
75 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
76 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
77 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
78 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
79 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
80 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
81 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
82 default:
83 return NV50_BLEND_FACTOR_ZERO;
84 }
85 }
86
87 static void *
88 nvc0_blend_state_create(struct pipe_context *pipe,
89 const struct pipe_blend_state *cso)
90 {
91 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
92 int i;
93 int r; /* reference */
94 uint8_t blend_en = 0;
95 bool indep_masks = false;
96 bool indep_funcs = false;
97
98 so->pipe = *cso;
99
100 /* check which states actually have differing values */
101 if (cso->independent_blend_enable) {
102 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
103 blend_en |= 1 << r;
104 for (i = r + 1; i < 8; ++i) {
105 if (!cso->rt[i].blend_enable)
106 continue;
107 blend_en |= 1 << i;
108 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
109 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
110 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
111 cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
112 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
113 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
114 indep_funcs = true;
115 break;
116 }
117 }
118 for (; i < 8; ++i)
119 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
120
121 for (i = 1; i < 8; ++i) {
122 if (cso->rt[i].colormask != cso->rt[0].colormask) {
123 indep_masks = true;
124 break;
125 }
126 }
127 } else {
128 r = 0;
129 if (cso->rt[0].blend_enable)
130 blend_en = 0xff;
131 }
132
133 if (cso->logicop_enable) {
134 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
135 SB_DATA (so, 1);
136 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
137
138 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
139 } else {
140 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
141
142 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
143 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
144 if (indep_funcs) {
145 for (i = 0; i < 8; ++i) {
146 if (cso->rt[i].blend_enable) {
147 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
148 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
149 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
150 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
151 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
152 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
153 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
154 }
155 }
156 } else
157 if (blend_en) {
158 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
159 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
160 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
161 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
162 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
163 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
164 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
165 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
166 }
167
168 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
169 if (indep_masks) {
170 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
171 for (i = 0; i < 8; ++i)
172 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
173 } else {
174 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
175 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
176 }
177 }
178
179 assert(so->size <= ARRAY_SIZE(so->state));
180 return so;
181 }
182
183 static void
184 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
185 {
186 struct nvc0_context *nvc0 = nvc0_context(pipe);
187
188 nvc0->blend = hwcso;
189 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND;
190 }
191
192 static void
193 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
194 {
195 FREE(hwcso);
196 }
197
198 /* NOTE: ignoring line_last_pixel */
199 static void *
200 nvc0_rasterizer_state_create(struct pipe_context *pipe,
201 const struct pipe_rasterizer_state *cso)
202 {
203 struct nvc0_rasterizer_stateobj *so;
204 uint32_t reg;
205
206 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
207 if (!so)
208 return NULL;
209 so->pipe = *cso;
210
211 /* Scissor enables are handled in scissor state, we will not want to
212 * always emit 16 commands, one for each scissor rectangle, here.
213 */
214
215 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
216 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
217
218 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
219 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
220 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
221
222 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
223
224 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
225 if (cso->line_smooth || cso->multisample)
226 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
227 else
228 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
229 SB_DATA (so, fui(cso->line_width));
230
231 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
232 if (cso->line_stipple_enable) {
233 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
234 SB_DATA (so, (cso->line_stipple_pattern << 8) |
235 cso->line_stipple_factor);
236
237 }
238
239 SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
240 if (!cso->point_size_per_vertex) {
241 SB_BEGIN_3D(so, POINT_SIZE, 1);
242 SB_DATA (so, fui(cso->point_size));
243 }
244
245 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
246 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
247 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
248
249 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
250 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
251 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
252 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
253
254 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
255 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
256 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
257 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
258 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
259
260 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
261 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
262 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
263 NVC0_3D_FRONT_FACE_CW);
264 switch (cso->cull_face) {
265 case PIPE_FACE_FRONT_AND_BACK:
266 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
267 break;
268 case PIPE_FACE_FRONT:
269 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
270 break;
271 case PIPE_FACE_BACK:
272 default:
273 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
274 break;
275 }
276
277 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
278 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
279 SB_DATA (so, cso->offset_point);
280 SB_DATA (so, cso->offset_line);
281 SB_DATA (so, cso->offset_tri);
282
283 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
284 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
285 SB_DATA (so, fui(cso->offset_scale));
286 if (!cso->offset_units_unscaled) {
287 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
288 SB_DATA (so, fui(cso->offset_units * 2.0f));
289 }
290 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
291 SB_DATA (so, fui(cso->offset_clamp));
292 }
293
294 if (cso->depth_clip)
295 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
296 else
297 reg =
298 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
299 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
300 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
301 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
302
303 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
304 SB_DATA (so, reg);
305
306 SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
307
308 SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
309
310 assert(so->size <= ARRAY_SIZE(so->state));
311 return (void *)so;
312 }
313
314 static void
315 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
316 {
317 struct nvc0_context *nvc0 = nvc0_context(pipe);
318
319 nvc0->rast = hwcso;
320 nvc0->dirty_3d |= NVC0_NEW_3D_RASTERIZER;
321 }
322
323 static void
324 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
325 {
326 FREE(hwcso);
327 }
328
329 static void *
330 nvc0_zsa_state_create(struct pipe_context *pipe,
331 const struct pipe_depth_stencil_alpha_state *cso)
332 {
333 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
334
335 so->pipe = *cso;
336
337 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
338 if (cso->depth.enabled) {
339 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
340 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
341 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
342 }
343
344 SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth.bounds_test);
345 if (cso->depth.bounds_test) {
346 SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
347 SB_DATA (so, fui(cso->depth.bounds_min));
348 SB_DATA (so, fui(cso->depth.bounds_max));
349 }
350
351 if (cso->stencil[0].enabled) {
352 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
353 SB_DATA (so, 1);
354 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
355 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
356 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
357 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
358 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
359 SB_DATA (so, cso->stencil[0].valuemask);
360 SB_DATA (so, cso->stencil[0].writemask);
361 } else {
362 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
363 }
364
365 if (cso->stencil[1].enabled) {
366 assert(cso->stencil[0].enabled);
367 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
368 SB_DATA (so, 1);
369 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
370 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
371 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
372 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
373 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
374 SB_DATA (so, cso->stencil[1].writemask);
375 SB_DATA (so, cso->stencil[1].valuemask);
376 } else
377 if (cso->stencil[0].enabled) {
378 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
379 }
380
381 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
382 if (cso->alpha.enabled) {
383 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
384 SB_DATA (so, fui(cso->alpha.ref_value));
385 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
386 }
387
388 assert(so->size <= ARRAY_SIZE(so->state));
389 return (void *)so;
390 }
391
392 static void
393 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
394 {
395 struct nvc0_context *nvc0 = nvc0_context(pipe);
396
397 nvc0->zsa = hwcso;
398 nvc0->dirty_3d |= NVC0_NEW_3D_ZSA;
399 }
400
401 static void
402 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
403 {
404 FREE(hwcso);
405 }
406
407 /* ====================== SAMPLERS AND TEXTURES ================================
408 */
409
410 #define NV50_TSC_WRAP_CASE(n) \
411 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
412
413 static void
414 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
415 {
416 unsigned s, i;
417
418 for (s = 0; s < 6; ++s)
419 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
420 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
421 nvc0_context(pipe)->samplers[s][i] = NULL;
422
423 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
424
425 FREE(hwcso);
426 }
427
428 static inline void
429 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0, int s,
430 unsigned nr, void **hwcso)
431 {
432 unsigned i;
433
434 for (i = 0; i < nr; ++i) {
435 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
436
437 if (hwcso[i] == old)
438 continue;
439 nvc0->samplers_dirty[s] |= 1 << i;
440
441 nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
442 if (old)
443 nvc0_screen_tsc_unlock(nvc0->screen, old);
444 }
445 for (; i < nvc0->num_samplers[s]; ++i) {
446 if (nvc0->samplers[s][i]) {
447 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
448 nvc0->samplers[s][i] = NULL;
449 }
450 }
451
452 nvc0->num_samplers[s] = nr;
453
454 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
455 }
456
457 static void
458 nvc0_stage_sampler_states_bind_range(struct nvc0_context *nvc0,
459 const unsigned s,
460 unsigned start, unsigned nr, void **cso)
461 {
462 const unsigned end = start + nr;
463 int last_valid = -1;
464 unsigned i;
465
466 if (cso) {
467 for (i = start; i < end; ++i) {
468 const unsigned p = i - start;
469 if (cso[p])
470 last_valid = i;
471 if (cso[p] == nvc0->samplers[s][i])
472 continue;
473 nvc0->samplers_dirty[s] |= 1 << i;
474
475 if (nvc0->samplers[s][i])
476 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
477 nvc0->samplers[s][i] = cso[p];
478 }
479 } else {
480 for (i = start; i < end; ++i) {
481 if (nvc0->samplers[s][i]) {
482 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
483 nvc0->samplers[s][i] = NULL;
484 nvc0->samplers_dirty[s] |= 1 << i;
485 }
486 }
487 }
488
489 if (nvc0->num_samplers[s] <= end) {
490 if (last_valid < 0) {
491 for (i = start; i && !nvc0->samplers[s][i - 1]; --i);
492 nvc0->num_samplers[s] = i;
493 } else {
494 nvc0->num_samplers[s] = last_valid + 1;
495 }
496 }
497 }
498
499 static void
500 nvc0_bind_sampler_states(struct pipe_context *pipe, unsigned shader,
501 unsigned start, unsigned nr, void **s)
502 {
503 switch (shader) {
504 case PIPE_SHADER_VERTEX:
505 assert(start == 0);
506 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 0, nr, s);
507 break;
508 case PIPE_SHADER_TESS_CTRL:
509 assert(start == 0);
510 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 1, nr, s);
511 break;
512 case PIPE_SHADER_TESS_EVAL:
513 assert(start == 0);
514 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 2, nr, s);
515 break;
516 case PIPE_SHADER_GEOMETRY:
517 assert(start == 0);
518 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 3, nr, s);
519 break;
520 case PIPE_SHADER_FRAGMENT:
521 assert(start == 0);
522 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 4, nr, s);
523 break;
524 case PIPE_SHADER_COMPUTE:
525 nvc0_stage_sampler_states_bind_range(nvc0_context(pipe), 5,
526 start, nr, s);
527 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
528 break;
529 }
530 }
531
532
533 /* NOTE: only called when not referenced anywhere, won't be bound */
534 static void
535 nvc0_sampler_view_destroy(struct pipe_context *pipe,
536 struct pipe_sampler_view *view)
537 {
538 pipe_resource_reference(&view->texture, NULL);
539
540 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
541
542 FREE(nv50_tic_entry(view));
543 }
544
545 static inline void
546 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
547 unsigned nr,
548 struct pipe_sampler_view **views)
549 {
550 unsigned i;
551
552 for (i = 0; i < nr; ++i) {
553 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
554
555 if (views[i] == nvc0->textures[s][i])
556 continue;
557 nvc0->textures_dirty[s] |= 1 << i;
558
559 if (views[i] && views[i]->texture) {
560 struct pipe_resource *res = views[i]->texture;
561 if (res->target == PIPE_BUFFER &&
562 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
563 nvc0->textures_coherent[s] |= 1 << i;
564 else
565 nvc0->textures_coherent[s] &= ~(1 << i);
566 } else {
567 nvc0->textures_coherent[s] &= ~(1 << i);
568 }
569
570 if (old) {
571 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
572 nvc0_screen_tic_unlock(nvc0->screen, old);
573 }
574
575 pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
576 }
577
578 for (i = nr; i < nvc0->num_textures[s]; ++i) {
579 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
580 if (old) {
581 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
582 nvc0_screen_tic_unlock(nvc0->screen, old);
583 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
584 }
585 }
586
587 nvc0->num_textures[s] = nr;
588
589 nvc0->dirty_3d |= NVC0_NEW_3D_TEXTURES;
590 }
591
592 static void
593 nvc0_stage_set_sampler_views_range(struct nvc0_context *nvc0, const unsigned s,
594 unsigned start, unsigned nr,
595 struct pipe_sampler_view **views)
596 {
597 struct nouveau_bufctx *bctx = (s == 5) ? nvc0->bufctx_cp : nvc0->bufctx_3d;
598 const unsigned end = start + nr;
599 const unsigned bin = (s == 5) ? NVC0_BIND_CP_TEX(0) : NVC0_BIND_3D_TEX(s, 0);
600 int last_valid = -1;
601 unsigned i;
602
603 if (views) {
604 for (i = start; i < end; ++i) {
605 const unsigned p = i - start;
606 if (views[p])
607 last_valid = i;
608 if (views[p] == nvc0->textures[s][i])
609 continue;
610 nvc0->textures_dirty[s] |= 1 << i;
611
612 if (views[p] && views[p]->texture) {
613 struct pipe_resource *res = views[p]->texture;
614 if (res->target == PIPE_BUFFER &&
615 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
616 nvc0->textures_coherent[s] |= 1 << i;
617 else
618 nvc0->textures_coherent[s] &= ~(1 << i);
619 } else {
620 nvc0->textures_coherent[s] &= ~(1 << i);
621 }
622
623 if (nvc0->textures[s][i]) {
624 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
625 nouveau_bufctx_reset(bctx, bin + i);
626 nvc0_screen_tic_unlock(nvc0->screen, old);
627 }
628 pipe_sampler_view_reference(&nvc0->textures[s][i], views[p]);
629 }
630 } else {
631 for (i = start; i < end; ++i) {
632 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
633 if (!old)
634 continue;
635 nvc0->textures_dirty[s] |= 1 << i;
636
637 nvc0_screen_tic_unlock(nvc0->screen, old);
638 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
639 nouveau_bufctx_reset(bctx, bin + i);
640 }
641 }
642
643 if (nvc0->num_textures[s] <= end) {
644 if (last_valid < 0) {
645 for (i = start; i && !nvc0->textures[s][i - 1]; --i);
646 nvc0->num_textures[s] = i;
647 } else {
648 nvc0->num_textures[s] = last_valid + 1;
649 }
650 }
651 }
652
653 static void
654 nvc0_set_sampler_views(struct pipe_context *pipe, unsigned shader,
655 unsigned start, unsigned nr,
656 struct pipe_sampler_view **views)
657 {
658 assert(start == 0);
659 switch (shader) {
660 case PIPE_SHADER_VERTEX:
661 nvc0_stage_set_sampler_views(nvc0_context(pipe), 0, nr, views);
662 break;
663 case PIPE_SHADER_TESS_CTRL:
664 nvc0_stage_set_sampler_views(nvc0_context(pipe), 1, nr, views);
665 break;
666 case PIPE_SHADER_TESS_EVAL:
667 nvc0_stage_set_sampler_views(nvc0_context(pipe), 2, nr, views);
668 break;
669 case PIPE_SHADER_GEOMETRY:
670 nvc0_stage_set_sampler_views(nvc0_context(pipe), 3, nr, views);
671 break;
672 case PIPE_SHADER_FRAGMENT:
673 nvc0_stage_set_sampler_views(nvc0_context(pipe), 4, nr, views);
674 break;
675 case PIPE_SHADER_COMPUTE:
676 nvc0_stage_set_sampler_views_range(nvc0_context(pipe), 5,
677 start, nr, views);
678 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
679 break;
680 default:
681 ;
682 }
683 }
684
685
686 /* ============================= SHADERS =======================================
687 */
688
689 static void *
690 nvc0_sp_state_create(struct pipe_context *pipe,
691 const struct pipe_shader_state *cso, unsigned type)
692 {
693 struct nvc0_program *prog;
694
695 prog = CALLOC_STRUCT(nvc0_program);
696 if (!prog)
697 return NULL;
698
699 prog->type = type;
700
701 if (cso->tokens)
702 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
703
704 if (cso->stream_output.num_outputs)
705 prog->pipe.stream_output = cso->stream_output;
706
707 prog->translated = nvc0_program_translate(
708 prog, nvc0_context(pipe)->screen->base.device->chipset,
709 &nouveau_context(pipe)->debug);
710
711 return (void *)prog;
712 }
713
714 static void
715 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
716 {
717 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
718
719 nvc0_program_destroy(nvc0_context(pipe), prog);
720
721 FREE((void *)prog->pipe.tokens);
722 FREE(prog);
723 }
724
725 static void *
726 nvc0_vp_state_create(struct pipe_context *pipe,
727 const struct pipe_shader_state *cso)
728 {
729 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
730 }
731
732 static void
733 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
734 {
735 struct nvc0_context *nvc0 = nvc0_context(pipe);
736
737 nvc0->vertprog = hwcso;
738 nvc0->dirty_3d |= NVC0_NEW_3D_VERTPROG;
739 }
740
741 static void *
742 nvc0_fp_state_create(struct pipe_context *pipe,
743 const struct pipe_shader_state *cso)
744 {
745 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
746 }
747
748 static void
749 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
750 {
751 struct nvc0_context *nvc0 = nvc0_context(pipe);
752
753 nvc0->fragprog = hwcso;
754 nvc0->dirty_3d |= NVC0_NEW_3D_FRAGPROG;
755 }
756
757 static void *
758 nvc0_gp_state_create(struct pipe_context *pipe,
759 const struct pipe_shader_state *cso)
760 {
761 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
762 }
763
764 static void
765 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
766 {
767 struct nvc0_context *nvc0 = nvc0_context(pipe);
768
769 nvc0->gmtyprog = hwcso;
770 nvc0->dirty_3d |= NVC0_NEW_3D_GMTYPROG;
771 }
772
773 static void *
774 nvc0_tcp_state_create(struct pipe_context *pipe,
775 const struct pipe_shader_state *cso)
776 {
777 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
778 }
779
780 static void
781 nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
782 {
783 struct nvc0_context *nvc0 = nvc0_context(pipe);
784
785 nvc0->tctlprog = hwcso;
786 nvc0->dirty_3d |= NVC0_NEW_3D_TCTLPROG;
787 }
788
789 static void *
790 nvc0_tep_state_create(struct pipe_context *pipe,
791 const struct pipe_shader_state *cso)
792 {
793 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
794 }
795
796 static void
797 nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
798 {
799 struct nvc0_context *nvc0 = nvc0_context(pipe);
800
801 nvc0->tevlprog = hwcso;
802 nvc0->dirty_3d |= NVC0_NEW_3D_TEVLPROG;
803 }
804
805 static void *
806 nvc0_cp_state_create(struct pipe_context *pipe,
807 const struct pipe_compute_state *cso)
808 {
809 struct nvc0_program *prog;
810
811 prog = CALLOC_STRUCT(nvc0_program);
812 if (!prog)
813 return NULL;
814 prog->type = PIPE_SHADER_COMPUTE;
815
816 prog->cp.smem_size = cso->req_local_mem;
817 prog->cp.lmem_size = cso->req_private_mem;
818 prog->parm_size = cso->req_input_mem;
819
820 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
821
822 return (void *)prog;
823 }
824
825 static void
826 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
827 {
828 struct nvc0_context *nvc0 = nvc0_context(pipe);
829
830 nvc0->compprog = hwcso;
831 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
832 }
833
834 static void
835 nvc0_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
836 const struct pipe_constant_buffer *cb)
837 {
838 struct nvc0_context *nvc0 = nvc0_context(pipe);
839 struct pipe_resource *res = cb ? cb->buffer : NULL;
840 const unsigned s = nvc0_shader_stage(shader);
841 const unsigned i = index;
842
843 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
844 if (nvc0->constbuf[s][i].user)
845 nvc0->constbuf[s][i].u.buf = NULL;
846 else
847 if (nvc0->constbuf[s][i].u.buf)
848 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
849
850 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
851 } else {
852 if (nvc0->constbuf[s][i].user)
853 nvc0->constbuf[s][i].u.buf = NULL;
854 else
855 if (nvc0->constbuf[s][i].u.buf)
856 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_CB(s, i));
857
858 nvc0->dirty_3d |= NVC0_NEW_3D_CONSTBUF;
859 }
860 nvc0->constbuf_dirty[s] |= 1 << i;
861
862 if (nvc0->constbuf[s][i].u.buf)
863 nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
864 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
865
866 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
867 if (nvc0->constbuf[s][i].user) {
868 nvc0->constbuf[s][i].u.data = cb->user_buffer;
869 nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
870 nvc0->constbuf_valid[s] |= 1 << i;
871 nvc0->constbuf_coherent[s] &= ~(1 << i);
872 } else
873 if (cb) {
874 nvc0->constbuf[s][i].offset = cb->buffer_offset;
875 nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
876 nvc0->constbuf_valid[s] |= 1 << i;
877 if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
878 nvc0->constbuf_coherent[s] |= 1 << i;
879 else
880 nvc0->constbuf_coherent[s] &= ~(1 << i);
881 }
882 else {
883 nvc0->constbuf_valid[s] &= ~(1 << i);
884 nvc0->constbuf_coherent[s] &= ~(1 << i);
885 }
886 }
887
888 /* =============================================================================
889 */
890
891 static void
892 nvc0_set_blend_color(struct pipe_context *pipe,
893 const struct pipe_blend_color *bcol)
894 {
895 struct nvc0_context *nvc0 = nvc0_context(pipe);
896
897 nvc0->blend_colour = *bcol;
898 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND_COLOUR;
899 }
900
901 static void
902 nvc0_set_stencil_ref(struct pipe_context *pipe,
903 const struct pipe_stencil_ref *sr)
904 {
905 struct nvc0_context *nvc0 = nvc0_context(pipe);
906
907 nvc0->stencil_ref = *sr;
908 nvc0->dirty_3d |= NVC0_NEW_3D_STENCIL_REF;
909 }
910
911 static void
912 nvc0_set_clip_state(struct pipe_context *pipe,
913 const struct pipe_clip_state *clip)
914 {
915 struct nvc0_context *nvc0 = nvc0_context(pipe);
916
917 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
918
919 nvc0->dirty_3d |= NVC0_NEW_3D_CLIP;
920 }
921
922 static void
923 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
924 {
925 struct nvc0_context *nvc0 = nvc0_context(pipe);
926
927 nvc0->sample_mask = sample_mask;
928 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_MASK;
929 }
930
931 static void
932 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
933 {
934 struct nvc0_context *nvc0 = nvc0_context(pipe);
935
936 if (nvc0->min_samples != min_samples) {
937 nvc0->min_samples = min_samples;
938 nvc0->dirty_3d |= NVC0_NEW_3D_MIN_SAMPLES;
939 }
940 }
941
942 static void
943 nvc0_set_framebuffer_state(struct pipe_context *pipe,
944 const struct pipe_framebuffer_state *fb)
945 {
946 struct nvc0_context *nvc0 = nvc0_context(pipe);
947
948 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
949
950 util_copy_framebuffer_state(&nvc0->framebuffer, fb);
951
952 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER;
953 }
954
955 static void
956 nvc0_set_polygon_stipple(struct pipe_context *pipe,
957 const struct pipe_poly_stipple *stipple)
958 {
959 struct nvc0_context *nvc0 = nvc0_context(pipe);
960
961 nvc0->stipple = *stipple;
962 nvc0->dirty_3d |= NVC0_NEW_3D_STIPPLE;
963 }
964
965 static void
966 nvc0_set_scissor_states(struct pipe_context *pipe,
967 unsigned start_slot,
968 unsigned num_scissors,
969 const struct pipe_scissor_state *scissor)
970 {
971 struct nvc0_context *nvc0 = nvc0_context(pipe);
972 int i;
973
974 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
975 for (i = 0; i < num_scissors; i++) {
976 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
977 continue;
978 nvc0->scissors[start_slot + i] = scissor[i];
979 nvc0->scissors_dirty |= 1 << (start_slot + i);
980 nvc0->dirty_3d |= NVC0_NEW_3D_SCISSOR;
981 }
982 }
983
984 static void
985 nvc0_set_viewport_states(struct pipe_context *pipe,
986 unsigned start_slot,
987 unsigned num_viewports,
988 const struct pipe_viewport_state *vpt)
989 {
990 struct nvc0_context *nvc0 = nvc0_context(pipe);
991 int i;
992
993 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
994 for (i = 0; i < num_viewports; i++) {
995 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
996 continue;
997 nvc0->viewports[start_slot + i] = vpt[i];
998 nvc0->viewports_dirty |= 1 << (start_slot + i);
999 nvc0->dirty_3d |= NVC0_NEW_3D_VIEWPORT;
1000 }
1001
1002 }
1003
1004 static void
1005 nvc0_set_window_rectangles(struct pipe_context *pipe,
1006 boolean include,
1007 unsigned num_rectangles,
1008 const struct pipe_scissor_state *rectangles)
1009 {
1010 struct nvc0_context *nvc0 = nvc0_context(pipe);
1011
1012 nvc0->window_rect.inclusive = include;
1013 nvc0->window_rect.rects = MIN2(num_rectangles, NVC0_MAX_WINDOW_RECTANGLES);
1014 memcpy(nvc0->window_rect.rect, rectangles,
1015 sizeof(struct pipe_scissor_state) * nvc0->window_rect.rects);
1016
1017 nvc0->dirty_3d |= NVC0_NEW_3D_WINDOW_RECTS;
1018 }
1019
1020 static void
1021 nvc0_set_tess_state(struct pipe_context *pipe,
1022 const float default_tess_outer[4],
1023 const float default_tess_inner[2])
1024 {
1025 struct nvc0_context *nvc0 = nvc0_context(pipe);
1026
1027 memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
1028 memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
1029 nvc0->dirty_3d |= NVC0_NEW_3D_TESSFACTOR;
1030 }
1031
1032 static void
1033 nvc0_set_vertex_buffers(struct pipe_context *pipe,
1034 unsigned start_slot, unsigned count,
1035 const struct pipe_vertex_buffer *vb)
1036 {
1037 struct nvc0_context *nvc0 = nvc0_context(pipe);
1038 unsigned i;
1039
1040 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX);
1041 nvc0->dirty_3d |= NVC0_NEW_3D_ARRAYS;
1042
1043 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
1044 start_slot, count);
1045
1046 if (!vb) {
1047 nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
1048 nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
1049 nvc0->vtxbufs_coherent &= ~(((1ull << count) - 1) << start_slot);
1050 return;
1051 }
1052
1053 for (i = 0; i < count; ++i) {
1054 unsigned dst_index = start_slot + i;
1055
1056 if (vb[i].user_buffer) {
1057 nvc0->vbo_user |= 1 << dst_index;
1058 if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
1059 nvc0->constant_vbos |= 1 << dst_index;
1060 else
1061 nvc0->constant_vbos &= ~(1 << dst_index);
1062 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1063 } else {
1064 nvc0->vbo_user &= ~(1 << dst_index);
1065 nvc0->constant_vbos &= ~(1 << dst_index);
1066
1067 if (vb[i].buffer &&
1068 vb[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1069 nvc0->vtxbufs_coherent |= (1 << dst_index);
1070 else
1071 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1072 }
1073 }
1074 }
1075
1076 static void
1077 nvc0_set_index_buffer(struct pipe_context *pipe,
1078 const struct pipe_index_buffer *ib)
1079 {
1080 struct nvc0_context *nvc0 = nvc0_context(pipe);
1081
1082 if (nvc0->idxbuf.buffer)
1083 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_IDX);
1084
1085 if (ib) {
1086 pipe_resource_reference(&nvc0->idxbuf.buffer, ib->buffer);
1087 nvc0->idxbuf.index_size = ib->index_size;
1088 if (ib->buffer) {
1089 nvc0->idxbuf.offset = ib->offset;
1090 nvc0->dirty_3d |= NVC0_NEW_3D_IDXBUF;
1091 } else {
1092 nvc0->idxbuf.user_buffer = ib->user_buffer;
1093 nvc0->dirty_3d &= ~NVC0_NEW_3D_IDXBUF;
1094 }
1095 } else {
1096 nvc0->dirty_3d &= ~NVC0_NEW_3D_IDXBUF;
1097 pipe_resource_reference(&nvc0->idxbuf.buffer, NULL);
1098 }
1099 }
1100
1101 static void
1102 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1103 {
1104 struct nvc0_context *nvc0 = nvc0_context(pipe);
1105
1106 nvc0->vertex = hwcso;
1107 nvc0->dirty_3d |= NVC0_NEW_3D_VERTEX;
1108 }
1109
1110 static struct pipe_stream_output_target *
1111 nvc0_so_target_create(struct pipe_context *pipe,
1112 struct pipe_resource *res,
1113 unsigned offset, unsigned size)
1114 {
1115 struct nv04_resource *buf = (struct nv04_resource *)res;
1116 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1117 if (!targ)
1118 return NULL;
1119
1120 targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0);
1121 if (!targ->pq) {
1122 FREE(targ);
1123 return NULL;
1124 }
1125 targ->clean = true;
1126
1127 targ->pipe.buffer_size = size;
1128 targ->pipe.buffer_offset = offset;
1129 targ->pipe.context = pipe;
1130 targ->pipe.buffer = NULL;
1131 pipe_resource_reference(&targ->pipe.buffer, res);
1132 pipe_reference_init(&targ->pipe.reference, 1);
1133
1134 assert(buf->base.target == PIPE_BUFFER);
1135 util_range_add(&buf->valid_buffer_range, offset, offset + size);
1136
1137 return &targ->pipe;
1138 }
1139
1140 static void
1141 nvc0_so_target_save_offset(struct pipe_context *pipe,
1142 struct pipe_stream_output_target *ptarg,
1143 unsigned index, bool *serialize)
1144 {
1145 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1146
1147 if (*serialize) {
1148 *serialize = false;
1149 PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
1150 IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
1151
1152 NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
1153 }
1154
1155 nvc0_query(targ->pq)->index = index;
1156 pipe->end_query(pipe, targ->pq);
1157 }
1158
1159 static void
1160 nvc0_so_target_destroy(struct pipe_context *pipe,
1161 struct pipe_stream_output_target *ptarg)
1162 {
1163 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1164 pipe->destroy_query(pipe, targ->pq);
1165 pipe_resource_reference(&targ->pipe.buffer, NULL);
1166 FREE(targ);
1167 }
1168
1169 static void
1170 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1171 unsigned num_targets,
1172 struct pipe_stream_output_target **targets,
1173 const unsigned *offsets)
1174 {
1175 struct nvc0_context *nvc0 = nvc0_context(pipe);
1176 unsigned i;
1177 bool serialize = true;
1178
1179 assert(num_targets <= 4);
1180
1181 for (i = 0; i < num_targets; ++i) {
1182 const bool changed = nvc0->tfbbuf[i] != targets[i];
1183 const bool append = (offsets[i] == ((unsigned)-1));
1184 if (!changed && append)
1185 continue;
1186 nvc0->tfbbuf_dirty |= 1 << i;
1187
1188 if (nvc0->tfbbuf[i] && changed)
1189 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1190
1191 if (targets[i] && !append)
1192 nvc0_so_target(targets[i])->clean = true;
1193
1194 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1195 }
1196 for (; i < nvc0->num_tfbbufs; ++i) {
1197 if (nvc0->tfbbuf[i]) {
1198 nvc0->tfbbuf_dirty |= 1 << i;
1199 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1200 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1201 }
1202 }
1203 nvc0->num_tfbbufs = num_targets;
1204
1205 if (nvc0->tfbbuf_dirty) {
1206 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TFB);
1207 nvc0->dirty_3d |= NVC0_NEW_3D_TFB_TARGETS;
1208 }
1209 }
1210
1211 static void
1212 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1213 unsigned start, unsigned nr,
1214 struct pipe_surface **psurfaces)
1215 {
1216 const unsigned end = start + nr;
1217 const unsigned mask = ((1 << nr) - 1) << start;
1218 unsigned i;
1219
1220 if (psurfaces) {
1221 for (i = start; i < end; ++i) {
1222 const unsigned p = i - start;
1223 if (psurfaces[p])
1224 nvc0->surfaces_valid[t] |= (1 << i);
1225 else
1226 nvc0->surfaces_valid[t] &= ~(1 << i);
1227 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1228 }
1229 } else {
1230 for (i = start; i < end; ++i)
1231 pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1232 nvc0->surfaces_valid[t] &= ~mask;
1233 }
1234 nvc0->surfaces_dirty[t] |= mask;
1235
1236 if (t == 0)
1237 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1238 else
1239 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1240 }
1241
1242 static void
1243 nvc0_set_compute_resources(struct pipe_context *pipe,
1244 unsigned start, unsigned nr,
1245 struct pipe_surface **resources)
1246 {
1247 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1248
1249 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1250 }
1251
1252 static bool
1253 nvc0_bind_images_range(struct nvc0_context *nvc0, const unsigned s,
1254 unsigned start, unsigned nr,
1255 const struct pipe_image_view *pimages)
1256 {
1257 const unsigned end = start + nr;
1258 unsigned mask = 0;
1259 unsigned i;
1260
1261 assert(s < 6);
1262
1263 if (pimages) {
1264 for (i = start; i < end; ++i) {
1265 struct pipe_image_view *img = &nvc0->images[s][i];
1266 const unsigned p = i - start;
1267
1268 if (img->resource == pimages[p].resource &&
1269 img->format == pimages[p].format &&
1270 img->access == pimages[p].access) {
1271 if (img->resource == NULL)
1272 continue;
1273 if (img->resource->target == PIPE_BUFFER &&
1274 img->u.buf.first_element == pimages[p].u.buf.first_element &&
1275 img->u.buf.last_element == pimages[p].u.buf.last_element)
1276 continue;
1277 if (img->resource->target != PIPE_BUFFER &&
1278 img->u.tex.first_layer == pimages[p].u.tex.first_layer &&
1279 img->u.tex.last_layer == pimages[p].u.tex.last_layer &&
1280 img->u.tex.level == pimages[p].u.tex.level)
1281 continue;
1282 }
1283
1284 mask |= (1 << i);
1285 if (pimages[p].resource)
1286 nvc0->images_valid[s] |= (1 << i);
1287 else
1288 nvc0->images_valid[s] &= ~(1 << i);
1289
1290 img->format = pimages[p].format;
1291 img->access = pimages[p].access;
1292 if (pimages[p].resource && pimages[p].resource->target == PIPE_BUFFER)
1293 img->u.buf = pimages[p].u.buf;
1294 else
1295 img->u.tex = pimages[p].u.tex;
1296
1297 pipe_resource_reference(
1298 &img->resource, pimages[p].resource);
1299 }
1300 if (!mask)
1301 return false;
1302 } else {
1303 mask = ((1 << nr) - 1) << start;
1304 if (!(nvc0->images_valid[s] & mask))
1305 return false;
1306 for (i = start; i < end; ++i)
1307 pipe_resource_reference(&nvc0->images[s][i].resource, NULL);
1308 nvc0->images_valid[s] &= ~mask;
1309 }
1310 nvc0->images_dirty[s] |= mask;
1311
1312 if (s == 5)
1313 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1314 else
1315 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1316
1317 return true;
1318 }
1319
1320 static void
1321 nvc0_set_shader_images(struct pipe_context *pipe, unsigned shader,
1322 unsigned start, unsigned nr,
1323 const struct pipe_image_view *images)
1324 {
1325 const unsigned s = nvc0_shader_stage(shader);
1326 if (!nvc0_bind_images_range(nvc0_context(pipe), s, start, nr, images))
1327 return;
1328
1329 if (s == 5)
1330 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1331 else
1332 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SURFACES;
1333 }
1334
1335 static bool
1336 nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t,
1337 unsigned start, unsigned nr,
1338 const struct pipe_shader_buffer *pbuffers)
1339 {
1340 const unsigned end = start + nr;
1341 unsigned mask = 0;
1342 unsigned i;
1343
1344 assert(t < 6);
1345
1346 if (pbuffers) {
1347 for (i = start; i < end; ++i) {
1348 struct pipe_shader_buffer *buf = &nvc0->buffers[t][i];
1349 const unsigned p = i - start;
1350 if (buf->buffer == pbuffers[p].buffer &&
1351 buf->buffer_offset == pbuffers[p].buffer_offset &&
1352 buf->buffer_size == pbuffers[p].buffer_size)
1353 continue;
1354
1355 mask |= (1 << i);
1356 if (pbuffers[p].buffer)
1357 nvc0->buffers_valid[t] |= (1 << i);
1358 else
1359 nvc0->buffers_valid[t] &= ~(1 << i);
1360 buf->buffer_offset = pbuffers[p].buffer_offset;
1361 buf->buffer_size = pbuffers[p].buffer_size;
1362 pipe_resource_reference(&buf->buffer, pbuffers[p].buffer);
1363 }
1364 if (!mask)
1365 return false;
1366 } else {
1367 mask = ((1 << nr) - 1) << start;
1368 if (!(nvc0->buffers_valid[t] & mask))
1369 return false;
1370 for (i = start; i < end; ++i)
1371 pipe_resource_reference(&nvc0->buffers[t][i].buffer, NULL);
1372 nvc0->buffers_valid[t] &= ~mask;
1373 }
1374 nvc0->buffers_dirty[t] |= mask;
1375
1376 if (t == 5)
1377 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF);
1378 else
1379 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BUF);
1380
1381 return true;
1382 }
1383
1384 static void
1385 nvc0_set_shader_buffers(struct pipe_context *pipe,
1386 unsigned shader,
1387 unsigned start, unsigned nr,
1388 const struct pipe_shader_buffer *buffers)
1389 {
1390 const unsigned s = nvc0_shader_stage(shader);
1391 if (!nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers))
1392 return;
1393
1394 if (s == 5)
1395 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_BUFFERS;
1396 else
1397 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_BUFFERS;
1398 }
1399
1400 static inline void
1401 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1402 {
1403 struct nv04_resource *buf = nv04_resource(res);
1404 if (buf) {
1405 uint64_t limit = (buf->address + buf->base.width0) - 1;
1406 if (limit < (1ULL << 32)) {
1407 *phandle = (uint32_t)buf->address;
1408 } else {
1409 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1410 "resource not contained within 32-bit address space !\n");
1411 *phandle = 0;
1412 }
1413 } else {
1414 *phandle = 0;
1415 }
1416 }
1417
1418 static void
1419 nvc0_set_global_bindings(struct pipe_context *pipe,
1420 unsigned start, unsigned nr,
1421 struct pipe_resource **resources,
1422 uint32_t **handles)
1423 {
1424 struct nvc0_context *nvc0 = nvc0_context(pipe);
1425 struct pipe_resource **ptr;
1426 unsigned i;
1427 const unsigned end = start + nr;
1428
1429 if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1430 const unsigned old_size = nvc0->global_residents.size;
1431 const unsigned req_size = end * sizeof(struct pipe_resource *);
1432 util_dynarray_resize(&nvc0->global_residents, req_size);
1433 memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1434 req_size - old_size);
1435 }
1436
1437 if (resources) {
1438 ptr = util_dynarray_element(
1439 &nvc0->global_residents, struct pipe_resource *, start);
1440 for (i = 0; i < nr; ++i) {
1441 pipe_resource_reference(&ptr[i], resources[i]);
1442 nvc0_set_global_handle(handles[i], resources[i]);
1443 }
1444 } else {
1445 ptr = util_dynarray_element(
1446 &nvc0->global_residents, struct pipe_resource *, start);
1447 for (i = 0; i < nr; ++i)
1448 pipe_resource_reference(&ptr[i], NULL);
1449 }
1450
1451 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1452
1453 nvc0->dirty_cp |= NVC0_NEW_CP_GLOBALS;
1454 }
1455
1456 void
1457 nvc0_init_state_functions(struct nvc0_context *nvc0)
1458 {
1459 struct pipe_context *pipe = &nvc0->base.pipe;
1460
1461 pipe->create_blend_state = nvc0_blend_state_create;
1462 pipe->bind_blend_state = nvc0_blend_state_bind;
1463 pipe->delete_blend_state = nvc0_blend_state_delete;
1464
1465 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1466 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1467 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1468
1469 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1470 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1471 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1472
1473 pipe->create_sampler_state = nv50_sampler_state_create;
1474 pipe->delete_sampler_state = nvc0_sampler_state_delete;
1475 pipe->bind_sampler_states = nvc0_bind_sampler_states;
1476
1477 pipe->create_sampler_view = nvc0_create_sampler_view;
1478 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1479 pipe->set_sampler_views = nvc0_set_sampler_views;
1480
1481 pipe->create_vs_state = nvc0_vp_state_create;
1482 pipe->create_fs_state = nvc0_fp_state_create;
1483 pipe->create_gs_state = nvc0_gp_state_create;
1484 pipe->create_tcs_state = nvc0_tcp_state_create;
1485 pipe->create_tes_state = nvc0_tep_state_create;
1486 pipe->bind_vs_state = nvc0_vp_state_bind;
1487 pipe->bind_fs_state = nvc0_fp_state_bind;
1488 pipe->bind_gs_state = nvc0_gp_state_bind;
1489 pipe->bind_tcs_state = nvc0_tcp_state_bind;
1490 pipe->bind_tes_state = nvc0_tep_state_bind;
1491 pipe->delete_vs_state = nvc0_sp_state_delete;
1492 pipe->delete_fs_state = nvc0_sp_state_delete;
1493 pipe->delete_gs_state = nvc0_sp_state_delete;
1494 pipe->delete_tcs_state = nvc0_sp_state_delete;
1495 pipe->delete_tes_state = nvc0_sp_state_delete;
1496
1497 pipe->create_compute_state = nvc0_cp_state_create;
1498 pipe->bind_compute_state = nvc0_cp_state_bind;
1499 pipe->delete_compute_state = nvc0_sp_state_delete;
1500
1501 pipe->set_blend_color = nvc0_set_blend_color;
1502 pipe->set_stencil_ref = nvc0_set_stencil_ref;
1503 pipe->set_clip_state = nvc0_set_clip_state;
1504 pipe->set_sample_mask = nvc0_set_sample_mask;
1505 pipe->set_min_samples = nvc0_set_min_samples;
1506 pipe->set_constant_buffer = nvc0_set_constant_buffer;
1507 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1508 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1509 pipe->set_scissor_states = nvc0_set_scissor_states;
1510 pipe->set_viewport_states = nvc0_set_viewport_states;
1511 pipe->set_window_rectangles = nvc0_set_window_rectangles;
1512 pipe->set_tess_state = nvc0_set_tess_state;
1513
1514 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1515 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1516 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1517
1518 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1519 pipe->set_index_buffer = nvc0_set_index_buffer;
1520
1521 pipe->create_stream_output_target = nvc0_so_target_create;
1522 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1523 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1524
1525 pipe->set_global_binding = nvc0_set_global_bindings;
1526 pipe->set_compute_resources = nvc0_set_compute_resources;
1527 pipe->set_shader_images = nvc0_set_shader_images;
1528 pipe->set_shader_buffers = nvc0_set_shader_buffers;
1529
1530 nvc0->sample_mask = ~0;
1531 nvc0->min_samples = 1;
1532 nvc0->default_tess_outer[0] =
1533 nvc0->default_tess_outer[1] =
1534 nvc0->default_tess_outer[2] =
1535 nvc0->default_tess_outer[3] = 1.0;
1536 nvc0->default_tess_inner[0] =
1537 nvc0->default_tess_inner[1] = 1.0;
1538 }