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nouveau: fix frees in unsupported IR error paths.
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_framebuffer.h"
25 #include "util/u_helpers.h"
26 #include "util/u_inlines.h"
27 #include "util/u_transfer.h"
28
29 #include "tgsi/tgsi_parse.h"
30 #include "compiler/nir/nir.h"
31
32 #include "nvc0/nvc0_stateobj.h"
33 #include "nvc0/nvc0_context.h"
34 #include "nvc0/nvc0_query_hw.h"
35
36 #include "nvc0/nvc0_3d.xml.h"
37
38 #include "nouveau_gldefs.h"
39
40 static inline uint32_t
41 nvc0_colormask(unsigned mask)
42 {
43 uint32_t ret = 0;
44
45 if (mask & PIPE_MASK_R)
46 ret |= 0x0001;
47 if (mask & PIPE_MASK_G)
48 ret |= 0x0010;
49 if (mask & PIPE_MASK_B)
50 ret |= 0x0100;
51 if (mask & PIPE_MASK_A)
52 ret |= 0x1000;
53
54 return ret;
55 }
56
57 #define NVC0_BLEND_FACTOR_CASE(a, b) \
58 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
59
60 static inline uint32_t
61 nvc0_blend_fac(unsigned factor)
62 {
63 switch (factor) {
64 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
65 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
66 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
67 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
68 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
69 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
70 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
71 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
72 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
73 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
74 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
75 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
76 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
77 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
78 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
79 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
80 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
81 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
82 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
83 default:
84 return NV50_BLEND_FACTOR_ZERO;
85 }
86 }
87
88 static void *
89 nvc0_blend_state_create(struct pipe_context *pipe,
90 const struct pipe_blend_state *cso)
91 {
92 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
93 int i;
94 int r; /* reference */
95 uint32_t ms;
96 uint8_t blend_en = 0;
97 bool indep_masks = false;
98 bool indep_funcs = false;
99
100 so->pipe = *cso;
101
102 /* check which states actually have differing values */
103 if (cso->independent_blend_enable) {
104 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
105 blend_en |= 1 << r;
106 for (i = r + 1; i < 8; ++i) {
107 if (!cso->rt[i].blend_enable)
108 continue;
109 blend_en |= 1 << i;
110 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
111 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
112 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
113 cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
114 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
115 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
116 indep_funcs = true;
117 break;
118 }
119 }
120 for (; i < 8; ++i)
121 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
122
123 for (i = 1; i < 8; ++i) {
124 if (cso->rt[i].colormask != cso->rt[0].colormask) {
125 indep_masks = true;
126 break;
127 }
128 }
129 } else {
130 r = 0;
131 if (cso->rt[0].blend_enable)
132 blend_en = 0xff;
133 }
134
135 if (cso->logicop_enable) {
136 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
137 SB_DATA (so, 1);
138 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
139
140 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
141 } else {
142 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
143
144 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
145 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
146 if (indep_funcs) {
147 for (i = 0; i < 8; ++i) {
148 if (cso->rt[i].blend_enable) {
149 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
150 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
151 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
152 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
153 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
154 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
155 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
156 }
157 }
158 } else
159 if (blend_en) {
160 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
161 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
162 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
163 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
164 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
165 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
166 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
167 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
168 }
169
170 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
171 if (indep_masks) {
172 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
173 for (i = 0; i < 8; ++i)
174 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
175 } else {
176 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
177 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
178 }
179 }
180
181 ms = 0;
182 if (cso->alpha_to_coverage)
183 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
184 if (cso->alpha_to_one)
185 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
186
187 SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
188 SB_DATA (so, ms);
189
190 assert(so->size <= ARRAY_SIZE(so->state));
191 return so;
192 }
193
194 static void
195 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
196 {
197 struct nvc0_context *nvc0 = nvc0_context(pipe);
198
199 nvc0->blend = hwcso;
200 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND;
201 }
202
203 static void
204 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
205 {
206 FREE(hwcso);
207 }
208
209 /* NOTE: ignoring line_last_pixel */
210 static void *
211 nvc0_rasterizer_state_create(struct pipe_context *pipe,
212 const struct pipe_rasterizer_state *cso)
213 {
214 struct nvc0_rasterizer_stateobj *so;
215 uint16_t class_3d = nouveau_screen(pipe->screen)->class_3d;
216 uint32_t reg;
217
218 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
219 if (!so)
220 return NULL;
221 so->pipe = *cso;
222
223 /* Scissor enables are handled in scissor state, we will not want to
224 * always emit 16 commands, one for each scissor rectangle, here.
225 */
226
227 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
228 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
229
230 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
231 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
232 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
233
234 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
235
236 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
237 /* On GM20x+, LINE_WIDTH_SMOOTH controls both aliased and smooth
238 * rendering and LINE_WIDTH_ALIASED seems to be ignored
239 */
240 if (cso->line_smooth || cso->multisample || class_3d >= GM200_3D_CLASS)
241 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
242 else
243 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
244 SB_DATA (so, fui(cso->line_width));
245
246 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
247 if (cso->line_stipple_enable) {
248 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
249 SB_DATA (so, (cso->line_stipple_pattern << 8) |
250 cso->line_stipple_factor);
251
252 }
253
254 SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
255 if (!cso->point_size_per_vertex) {
256 SB_BEGIN_3D(so, POINT_SIZE, 1);
257 SB_DATA (so, fui(cso->point_size));
258 }
259
260 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
261 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
262 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
263
264 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
265 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
266 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
267 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
268
269 if (class_3d >= GM200_3D_CLASS) {
270 SB_IMMED_3D(so, FILL_RECTANGLE,
271 cso->fill_front == PIPE_POLYGON_MODE_FILL_RECTANGLE ?
272 NVC0_3D_FILL_RECTANGLE_ENABLE : 0);
273 }
274
275 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
276 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
277 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
278 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
279 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
280
281 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
282 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
283 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
284 NVC0_3D_FRONT_FACE_CW);
285 switch (cso->cull_face) {
286 case PIPE_FACE_FRONT_AND_BACK:
287 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
288 break;
289 case PIPE_FACE_FRONT:
290 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
291 break;
292 case PIPE_FACE_BACK:
293 default:
294 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
295 break;
296 }
297
298 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
299 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
300 SB_DATA (so, cso->offset_point);
301 SB_DATA (so, cso->offset_line);
302 SB_DATA (so, cso->offset_tri);
303
304 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
305 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
306 SB_DATA (so, fui(cso->offset_scale));
307 if (!cso->offset_units_unscaled) {
308 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
309 SB_DATA (so, fui(cso->offset_units * 2.0f));
310 }
311 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
312 SB_DATA (so, fui(cso->offset_clamp));
313 }
314
315 if (cso->depth_clip_near)
316 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
317 else
318 reg =
319 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
320 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
321 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
322 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
323
324 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
325 SB_DATA (so, reg);
326
327 SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
328
329 SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
330
331 if (class_3d >= GM200_3D_CLASS) {
332 if (cso->conservative_raster_mode != PIPE_CONSERVATIVE_RASTER_OFF) {
333 bool post_snap = cso->conservative_raster_mode ==
334 PIPE_CONSERVATIVE_RASTER_POST_SNAP;
335 uint32_t state = cso->subpixel_precision_x;
336 state |= cso->subpixel_precision_y << 4;
337 state |= (uint32_t)(cso->conservative_raster_dilate * 4) << 8;
338 state |= (post_snap || class_3d < GP100_3D_CLASS) ? 1 << 10 : 0;
339 SB_IMMED_3D(so, MACRO_CONSERVATIVE_RASTER_STATE, state);
340 } else {
341 SB_IMMED_3D(so, CONSERVATIVE_RASTER, 0);
342 }
343 }
344
345 assert(so->size <= ARRAY_SIZE(so->state));
346 return (void *)so;
347 }
348
349 static void
350 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
351 {
352 struct nvc0_context *nvc0 = nvc0_context(pipe);
353
354 nvc0->rast = hwcso;
355 nvc0->dirty_3d |= NVC0_NEW_3D_RASTERIZER;
356 }
357
358 static void
359 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
360 {
361 FREE(hwcso);
362 }
363
364 static void *
365 nvc0_zsa_state_create(struct pipe_context *pipe,
366 const struct pipe_depth_stencil_alpha_state *cso)
367 {
368 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
369
370 so->pipe = *cso;
371
372 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
373 if (cso->depth.enabled) {
374 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
375 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
376 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
377 }
378
379 SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth.bounds_test);
380 if (cso->depth.bounds_test) {
381 SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
382 SB_DATA (so, fui(cso->depth.bounds_min));
383 SB_DATA (so, fui(cso->depth.bounds_max));
384 }
385
386 if (cso->stencil[0].enabled) {
387 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
388 SB_DATA (so, 1);
389 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
390 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
391 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
392 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
393 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
394 SB_DATA (so, cso->stencil[0].valuemask);
395 SB_DATA (so, cso->stencil[0].writemask);
396 } else {
397 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
398 }
399
400 if (cso->stencil[1].enabled) {
401 assert(cso->stencil[0].enabled);
402 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
403 SB_DATA (so, 1);
404 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
405 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
406 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
407 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
408 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
409 SB_DATA (so, cso->stencil[1].writemask);
410 SB_DATA (so, cso->stencil[1].valuemask);
411 } else
412 if (cso->stencil[0].enabled) {
413 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
414 }
415
416 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
417 if (cso->alpha.enabled) {
418 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
419 SB_DATA (so, fui(cso->alpha.ref_value));
420 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
421 }
422
423 assert(so->size <= ARRAY_SIZE(so->state));
424 return (void *)so;
425 }
426
427 static void
428 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
429 {
430 struct nvc0_context *nvc0 = nvc0_context(pipe);
431
432 nvc0->zsa = hwcso;
433 nvc0->dirty_3d |= NVC0_NEW_3D_ZSA;
434 }
435
436 static void
437 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
438 {
439 FREE(hwcso);
440 }
441
442 /* ====================== SAMPLERS AND TEXTURES ================================
443 */
444
445 #define NV50_TSC_WRAP_CASE(n) \
446 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
447
448 static void
449 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
450 {
451 unsigned s, i;
452
453 for (s = 0; s < 6; ++s)
454 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
455 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
456 nvc0_context(pipe)->samplers[s][i] = NULL;
457
458 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
459
460 FREE(hwcso);
461 }
462
463 static inline void
464 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0,
465 unsigned s,
466 unsigned nr, void **hwcso)
467 {
468 unsigned highest_found = 0;
469 unsigned i;
470
471 for (i = 0; i < nr; ++i) {
472 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
473
474 if (hwcso[i])
475 highest_found = i;
476
477 if (hwcso[i] == old)
478 continue;
479 nvc0->samplers_dirty[s] |= 1 << i;
480
481 nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
482 if (old)
483 nvc0_screen_tsc_unlock(nvc0->screen, old);
484 }
485 if (nr >= nvc0->num_samplers[s])
486 nvc0->num_samplers[s] = highest_found + 1;
487 }
488
489 static void
490 nvc0_bind_sampler_states(struct pipe_context *pipe,
491 enum pipe_shader_type shader,
492 unsigned start, unsigned nr, void **samplers)
493 {
494 const unsigned s = nvc0_shader_stage(shader);
495
496 assert(start == 0);
497 nvc0_stage_sampler_states_bind(nvc0_context(pipe), s, nr, samplers);
498
499 if (s == 5)
500 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
501 else
502 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
503 }
504
505
506 /* NOTE: only called when not referenced anywhere, won't be bound */
507 static void
508 nvc0_sampler_view_destroy(struct pipe_context *pipe,
509 struct pipe_sampler_view *view)
510 {
511 pipe_resource_reference(&view->texture, NULL);
512
513 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
514
515 FREE(nv50_tic_entry(view));
516 }
517
518 static inline void
519 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
520 unsigned nr,
521 struct pipe_sampler_view **views)
522 {
523 unsigned i;
524
525 for (i = 0; i < nr; ++i) {
526 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
527
528 if (views[i] == nvc0->textures[s][i])
529 continue;
530 nvc0->textures_dirty[s] |= 1 << i;
531
532 if (views[i] && views[i]->texture) {
533 struct pipe_resource *res = views[i]->texture;
534 if (res->target == PIPE_BUFFER &&
535 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
536 nvc0->textures_coherent[s] |= 1 << i;
537 else
538 nvc0->textures_coherent[s] &= ~(1 << i);
539 } else {
540 nvc0->textures_coherent[s] &= ~(1 << i);
541 }
542
543 if (old) {
544 if (s == 5)
545 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
546 else
547 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
548 nvc0_screen_tic_unlock(nvc0->screen, old);
549 }
550
551 pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
552 }
553
554 for (i = nr; i < nvc0->num_textures[s]; ++i) {
555 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
556 if (old) {
557 if (s == 5)
558 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
559 else
560 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
561 nvc0_screen_tic_unlock(nvc0->screen, old);
562 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
563 }
564 }
565
566 nvc0->num_textures[s] = nr;
567 }
568
569 static void
570 nvc0_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,
571 unsigned start, unsigned nr,
572 struct pipe_sampler_view **views)
573 {
574 const unsigned s = nvc0_shader_stage(shader);
575
576 assert(start == 0);
577 nvc0_stage_set_sampler_views(nvc0_context(pipe), s, nr, views);
578
579 if (s == 5)
580 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
581 else
582 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_TEXTURES;
583 }
584
585 /* ============================= SHADERS =======================================
586 */
587
588 static void *
589 nvc0_sp_state_create(struct pipe_context *pipe,
590 const struct pipe_shader_state *cso, unsigned type)
591 {
592 struct nvc0_program *prog;
593
594 prog = CALLOC_STRUCT(nvc0_program);
595 if (!prog)
596 return NULL;
597
598 prog->type = type;
599 prog->pipe.type = cso->type;
600
601 switch(cso->type) {
602 case PIPE_SHADER_IR_TGSI:
603 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
604 break;
605 case PIPE_SHADER_IR_NIR:
606 prog->pipe.ir.nir = cso->ir.nir;
607 break;
608 default:
609 assert(!"unsupported IR!");
610 free(prog);
611 return NULL;
612 }
613
614 if (cso->stream_output.num_outputs)
615 prog->pipe.stream_output = cso->stream_output;
616
617 prog->translated = nvc0_program_translate(
618 prog, nvc0_context(pipe)->screen->base.device->chipset,
619 &nouveau_context(pipe)->debug);
620
621 return (void *)prog;
622 }
623
624 static void
625 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
626 {
627 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
628
629 nvc0_program_destroy(nvc0_context(pipe), prog);
630
631 if (prog->pipe.type == PIPE_SHADER_IR_TGSI)
632 FREE((void *)prog->pipe.tokens);
633 else if (prog->pipe.type == PIPE_SHADER_IR_NIR)
634 ralloc_free(prog->pipe.ir.nir);
635 FREE(prog);
636 }
637
638 static void *
639 nvc0_vp_state_create(struct pipe_context *pipe,
640 const struct pipe_shader_state *cso)
641 {
642 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
643 }
644
645 static void
646 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
647 {
648 struct nvc0_context *nvc0 = nvc0_context(pipe);
649
650 nvc0->vertprog = hwcso;
651 nvc0->dirty_3d |= NVC0_NEW_3D_VERTPROG;
652 }
653
654 static void *
655 nvc0_fp_state_create(struct pipe_context *pipe,
656 const struct pipe_shader_state *cso)
657 {
658 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
659 }
660
661 static void
662 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
663 {
664 struct nvc0_context *nvc0 = nvc0_context(pipe);
665
666 nvc0->fragprog = hwcso;
667 nvc0->dirty_3d |= NVC0_NEW_3D_FRAGPROG;
668 }
669
670 static void *
671 nvc0_gp_state_create(struct pipe_context *pipe,
672 const struct pipe_shader_state *cso)
673 {
674 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
675 }
676
677 static void
678 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
679 {
680 struct nvc0_context *nvc0 = nvc0_context(pipe);
681
682 nvc0->gmtyprog = hwcso;
683 nvc0->dirty_3d |= NVC0_NEW_3D_GMTYPROG;
684 }
685
686 static void *
687 nvc0_tcp_state_create(struct pipe_context *pipe,
688 const struct pipe_shader_state *cso)
689 {
690 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
691 }
692
693 static void
694 nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
695 {
696 struct nvc0_context *nvc0 = nvc0_context(pipe);
697
698 nvc0->tctlprog = hwcso;
699 nvc0->dirty_3d |= NVC0_NEW_3D_TCTLPROG;
700 }
701
702 static void *
703 nvc0_tep_state_create(struct pipe_context *pipe,
704 const struct pipe_shader_state *cso)
705 {
706 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
707 }
708
709 static void
710 nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
711 {
712 struct nvc0_context *nvc0 = nvc0_context(pipe);
713
714 nvc0->tevlprog = hwcso;
715 nvc0->dirty_3d |= NVC0_NEW_3D_TEVLPROG;
716 }
717
718 static void *
719 nvc0_cp_state_create(struct pipe_context *pipe,
720 const struct pipe_compute_state *cso)
721 {
722 struct nvc0_program *prog;
723
724 prog = CALLOC_STRUCT(nvc0_program);
725 if (!prog)
726 return NULL;
727 prog->type = PIPE_SHADER_COMPUTE;
728 prog->pipe.type = cso->ir_type;
729
730 prog->cp.smem_size = cso->req_local_mem;
731 prog->cp.lmem_size = cso->req_private_mem;
732 prog->parm_size = cso->req_input_mem;
733
734 switch(cso->ir_type) {
735 case PIPE_SHADER_IR_TGSI:
736 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
737 break;
738 case PIPE_SHADER_IR_NIR:
739 prog->pipe.ir.nir = (nir_shader *)cso->prog;
740 break;
741 default:
742 assert(!"unsupported IR!");
743 free(prog);
744 return NULL;
745 }
746
747 prog->translated = nvc0_program_translate(
748 prog, nvc0_context(pipe)->screen->base.device->chipset,
749 &nouveau_context(pipe)->debug);
750
751 return (void *)prog;
752 }
753
754 static void
755 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
756 {
757 struct nvc0_context *nvc0 = nvc0_context(pipe);
758
759 nvc0->compprog = hwcso;
760 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
761 }
762
763 static void
764 nvc0_set_constant_buffer(struct pipe_context *pipe,
765 enum pipe_shader_type shader, uint index,
766 const struct pipe_constant_buffer *cb)
767 {
768 struct nvc0_context *nvc0 = nvc0_context(pipe);
769 struct pipe_resource *res = cb ? cb->buffer : NULL;
770 const unsigned s = nvc0_shader_stage(shader);
771 const unsigned i = index;
772
773 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
774 if (nvc0->constbuf[s][i].user)
775 nvc0->constbuf[s][i].u.buf = NULL;
776 else
777 if (nvc0->constbuf[s][i].u.buf)
778 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
779
780 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
781 } else {
782 if (nvc0->constbuf[s][i].user)
783 nvc0->constbuf[s][i].u.buf = NULL;
784 else
785 if (nvc0->constbuf[s][i].u.buf)
786 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_CB(s, i));
787
788 nvc0->dirty_3d |= NVC0_NEW_3D_CONSTBUF;
789 }
790 nvc0->constbuf_dirty[s] |= 1 << i;
791
792 if (nvc0->constbuf[s][i].u.buf)
793 nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
794 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
795
796 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
797 if (nvc0->constbuf[s][i].user) {
798 nvc0->constbuf[s][i].u.data = cb->user_buffer;
799 nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
800 nvc0->constbuf_valid[s] |= 1 << i;
801 nvc0->constbuf_coherent[s] &= ~(1 << i);
802 } else
803 if (cb) {
804 nvc0->constbuf[s][i].offset = cb->buffer_offset;
805 nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
806 nvc0->constbuf_valid[s] |= 1 << i;
807 if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
808 nvc0->constbuf_coherent[s] |= 1 << i;
809 else
810 nvc0->constbuf_coherent[s] &= ~(1 << i);
811 }
812 else {
813 nvc0->constbuf_valid[s] &= ~(1 << i);
814 nvc0->constbuf_coherent[s] &= ~(1 << i);
815 }
816 }
817
818 /* =============================================================================
819 */
820
821 static void
822 nvc0_set_blend_color(struct pipe_context *pipe,
823 const struct pipe_blend_color *bcol)
824 {
825 struct nvc0_context *nvc0 = nvc0_context(pipe);
826
827 nvc0->blend_colour = *bcol;
828 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND_COLOUR;
829 }
830
831 static void
832 nvc0_set_stencil_ref(struct pipe_context *pipe,
833 const struct pipe_stencil_ref *sr)
834 {
835 struct nvc0_context *nvc0 = nvc0_context(pipe);
836
837 nvc0->stencil_ref = *sr;
838 nvc0->dirty_3d |= NVC0_NEW_3D_STENCIL_REF;
839 }
840
841 static void
842 nvc0_set_clip_state(struct pipe_context *pipe,
843 const struct pipe_clip_state *clip)
844 {
845 struct nvc0_context *nvc0 = nvc0_context(pipe);
846
847 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
848
849 nvc0->dirty_3d |= NVC0_NEW_3D_CLIP;
850 }
851
852 static void
853 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
854 {
855 struct nvc0_context *nvc0 = nvc0_context(pipe);
856
857 nvc0->sample_mask = sample_mask;
858 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_MASK;
859 }
860
861 static void
862 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
863 {
864 struct nvc0_context *nvc0 = nvc0_context(pipe);
865
866 if (nvc0->min_samples != min_samples) {
867 nvc0->min_samples = min_samples;
868 nvc0->dirty_3d |= NVC0_NEW_3D_MIN_SAMPLES;
869 }
870 }
871
872 static void
873 nvc0_set_framebuffer_state(struct pipe_context *pipe,
874 const struct pipe_framebuffer_state *fb)
875 {
876 struct nvc0_context *nvc0 = nvc0_context(pipe);
877
878 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
879
880 util_copy_framebuffer_state(&nvc0->framebuffer, fb);
881
882 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER | NVC0_NEW_3D_SAMPLE_LOCATIONS |
883 NVC0_NEW_3D_TEXTURES;
884 nvc0->dirty_cp |= NVC0_NEW_CP_TEXTURES;
885 }
886
887 static void
888 nvc0_set_sample_locations(struct pipe_context *pipe,
889 size_t size, const uint8_t *locations)
890 {
891 struct nvc0_context *nvc0 = nvc0_context(pipe);
892
893 nvc0->sample_locations_enabled = size && locations;
894 if (size > sizeof(nvc0->sample_locations))
895 size = sizeof(nvc0->sample_locations);
896 memcpy(nvc0->sample_locations, locations, size);
897
898 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_LOCATIONS;
899 }
900
901 static void
902 nvc0_set_polygon_stipple(struct pipe_context *pipe,
903 const struct pipe_poly_stipple *stipple)
904 {
905 struct nvc0_context *nvc0 = nvc0_context(pipe);
906
907 nvc0->stipple = *stipple;
908 nvc0->dirty_3d |= NVC0_NEW_3D_STIPPLE;
909 }
910
911 static void
912 nvc0_set_scissor_states(struct pipe_context *pipe,
913 unsigned start_slot,
914 unsigned num_scissors,
915 const struct pipe_scissor_state *scissor)
916 {
917 struct nvc0_context *nvc0 = nvc0_context(pipe);
918 int i;
919
920 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
921 for (i = 0; i < num_scissors; i++) {
922 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
923 continue;
924 nvc0->scissors[start_slot + i] = scissor[i];
925 nvc0->scissors_dirty |= 1 << (start_slot + i);
926 nvc0->dirty_3d |= NVC0_NEW_3D_SCISSOR;
927 }
928 }
929
930 static void
931 nvc0_set_viewport_states(struct pipe_context *pipe,
932 unsigned start_slot,
933 unsigned num_viewports,
934 const struct pipe_viewport_state *vpt)
935 {
936 struct nvc0_context *nvc0 = nvc0_context(pipe);
937 int i;
938
939 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
940 for (i = 0; i < num_viewports; i++) {
941 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
942 continue;
943 nvc0->viewports[start_slot + i] = vpt[i];
944 nvc0->viewports_dirty |= 1 << (start_slot + i);
945 nvc0->dirty_3d |= NVC0_NEW_3D_VIEWPORT;
946 }
947
948 }
949
950 static void
951 nvc0_set_window_rectangles(struct pipe_context *pipe,
952 boolean include,
953 unsigned num_rectangles,
954 const struct pipe_scissor_state *rectangles)
955 {
956 struct nvc0_context *nvc0 = nvc0_context(pipe);
957
958 nvc0->window_rect.inclusive = include;
959 nvc0->window_rect.rects = MIN2(num_rectangles, NVC0_MAX_WINDOW_RECTANGLES);
960 memcpy(nvc0->window_rect.rect, rectangles,
961 sizeof(struct pipe_scissor_state) * nvc0->window_rect.rects);
962
963 nvc0->dirty_3d |= NVC0_NEW_3D_WINDOW_RECTS;
964 }
965
966 static void
967 nvc0_set_tess_state(struct pipe_context *pipe,
968 const float default_tess_outer[4],
969 const float default_tess_inner[2])
970 {
971 struct nvc0_context *nvc0 = nvc0_context(pipe);
972
973 memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
974 memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
975 nvc0->dirty_3d |= NVC0_NEW_3D_TESSFACTOR;
976 }
977
978 static void
979 nvc0_set_vertex_buffers(struct pipe_context *pipe,
980 unsigned start_slot, unsigned count,
981 const struct pipe_vertex_buffer *vb)
982 {
983 struct nvc0_context *nvc0 = nvc0_context(pipe);
984 unsigned i;
985
986 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX);
987 nvc0->dirty_3d |= NVC0_NEW_3D_ARRAYS;
988
989 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
990 start_slot, count);
991
992 if (!vb) {
993 nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
994 nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
995 nvc0->vtxbufs_coherent &= ~(((1ull << count) - 1) << start_slot);
996 return;
997 }
998
999 for (i = 0; i < count; ++i) {
1000 unsigned dst_index = start_slot + i;
1001
1002 if (vb[i].is_user_buffer) {
1003 nvc0->vbo_user |= 1 << dst_index;
1004 if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
1005 nvc0->constant_vbos |= 1 << dst_index;
1006 else
1007 nvc0->constant_vbos &= ~(1 << dst_index);
1008 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1009 } else {
1010 nvc0->vbo_user &= ~(1 << dst_index);
1011 nvc0->constant_vbos &= ~(1 << dst_index);
1012
1013 if (vb[i].buffer.resource &&
1014 vb[i].buffer.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1015 nvc0->vtxbufs_coherent |= (1 << dst_index);
1016 else
1017 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1018 }
1019 }
1020 }
1021
1022 static void
1023 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1024 {
1025 struct nvc0_context *nvc0 = nvc0_context(pipe);
1026
1027 nvc0->vertex = hwcso;
1028 nvc0->dirty_3d |= NVC0_NEW_3D_VERTEX;
1029 }
1030
1031 static struct pipe_stream_output_target *
1032 nvc0_so_target_create(struct pipe_context *pipe,
1033 struct pipe_resource *res,
1034 unsigned offset, unsigned size)
1035 {
1036 struct nv04_resource *buf = (struct nv04_resource *)res;
1037 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1038 if (!targ)
1039 return NULL;
1040
1041 targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0);
1042 if (!targ->pq) {
1043 FREE(targ);
1044 return NULL;
1045 }
1046 targ->clean = true;
1047
1048 targ->pipe.buffer_size = size;
1049 targ->pipe.buffer_offset = offset;
1050 targ->pipe.context = pipe;
1051 targ->pipe.buffer = NULL;
1052 pipe_resource_reference(&targ->pipe.buffer, res);
1053 pipe_reference_init(&targ->pipe.reference, 1);
1054
1055 assert(buf->base.target == PIPE_BUFFER);
1056 util_range_add(&buf->valid_buffer_range, offset, offset + size);
1057
1058 return &targ->pipe;
1059 }
1060
1061 static void
1062 nvc0_so_target_save_offset(struct pipe_context *pipe,
1063 struct pipe_stream_output_target *ptarg,
1064 unsigned index, bool *serialize)
1065 {
1066 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1067
1068 if (*serialize) {
1069 *serialize = false;
1070 PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
1071 IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
1072
1073 NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
1074 }
1075
1076 nvc0_query(targ->pq)->index = index;
1077 pipe->end_query(pipe, targ->pq);
1078 }
1079
1080 static void
1081 nvc0_so_target_destroy(struct pipe_context *pipe,
1082 struct pipe_stream_output_target *ptarg)
1083 {
1084 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1085 pipe->destroy_query(pipe, targ->pq);
1086 pipe_resource_reference(&targ->pipe.buffer, NULL);
1087 FREE(targ);
1088 }
1089
1090 static void
1091 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1092 unsigned num_targets,
1093 struct pipe_stream_output_target **targets,
1094 const unsigned *offsets)
1095 {
1096 struct nvc0_context *nvc0 = nvc0_context(pipe);
1097 unsigned i;
1098 bool serialize = true;
1099
1100 assert(num_targets <= 4);
1101
1102 for (i = 0; i < num_targets; ++i) {
1103 const bool changed = nvc0->tfbbuf[i] != targets[i];
1104 const bool append = (offsets[i] == ((unsigned)-1));
1105 if (!changed && append)
1106 continue;
1107 nvc0->tfbbuf_dirty |= 1 << i;
1108
1109 if (nvc0->tfbbuf[i] && changed)
1110 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1111
1112 if (targets[i] && !append)
1113 nvc0_so_target(targets[i])->clean = true;
1114
1115 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1116 }
1117 for (; i < nvc0->num_tfbbufs; ++i) {
1118 if (nvc0->tfbbuf[i]) {
1119 nvc0->tfbbuf_dirty |= 1 << i;
1120 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1121 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1122 }
1123 }
1124 nvc0->num_tfbbufs = num_targets;
1125
1126 if (nvc0->tfbbuf_dirty) {
1127 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TFB);
1128 nvc0->dirty_3d |= NVC0_NEW_3D_TFB_TARGETS;
1129 }
1130 }
1131
1132 static void
1133 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1134 unsigned start, unsigned nr,
1135 struct pipe_surface **psurfaces)
1136 {
1137 const unsigned end = start + nr;
1138 const unsigned mask = ((1 << nr) - 1) << start;
1139 unsigned i;
1140
1141 if (psurfaces) {
1142 for (i = start; i < end; ++i) {
1143 const unsigned p = i - start;
1144 if (psurfaces[p])
1145 nvc0->surfaces_valid[t] |= (1 << i);
1146 else
1147 nvc0->surfaces_valid[t] &= ~(1 << i);
1148 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1149 }
1150 } else {
1151 for (i = start; i < end; ++i)
1152 pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1153 nvc0->surfaces_valid[t] &= ~mask;
1154 }
1155 nvc0->surfaces_dirty[t] |= mask;
1156
1157 if (t == 0)
1158 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1159 else
1160 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1161 }
1162
1163 static void
1164 nvc0_set_compute_resources(struct pipe_context *pipe,
1165 unsigned start, unsigned nr,
1166 struct pipe_surface **resources)
1167 {
1168 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1169
1170 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1171 }
1172
1173 static bool
1174 nvc0_bind_images_range(struct nvc0_context *nvc0, const unsigned s,
1175 unsigned start, unsigned nr,
1176 const struct pipe_image_view *pimages)
1177 {
1178 const unsigned end = start + nr;
1179 unsigned mask = 0;
1180 unsigned i;
1181
1182 assert(s < 6);
1183
1184 if (pimages) {
1185 for (i = start; i < end; ++i) {
1186 struct pipe_image_view *img = &nvc0->images[s][i];
1187 const unsigned p = i - start;
1188
1189 if (img->resource == pimages[p].resource &&
1190 img->format == pimages[p].format &&
1191 img->access == pimages[p].access) {
1192 if (img->resource == NULL)
1193 continue;
1194 if (img->resource->target == PIPE_BUFFER &&
1195 img->u.buf.offset == pimages[p].u.buf.offset &&
1196 img->u.buf.size == pimages[p].u.buf.size)
1197 continue;
1198 if (img->resource->target != PIPE_BUFFER &&
1199 img->u.tex.first_layer == pimages[p].u.tex.first_layer &&
1200 img->u.tex.last_layer == pimages[p].u.tex.last_layer &&
1201 img->u.tex.level == pimages[p].u.tex.level)
1202 continue;
1203 }
1204
1205 mask |= (1 << i);
1206 if (pimages[p].resource)
1207 nvc0->images_valid[s] |= (1 << i);
1208 else
1209 nvc0->images_valid[s] &= ~(1 << i);
1210
1211 img->format = pimages[p].format;
1212 img->access = pimages[p].access;
1213 if (pimages[p].resource && pimages[p].resource->target == PIPE_BUFFER)
1214 img->u.buf = pimages[p].u.buf;
1215 else
1216 img->u.tex = pimages[p].u.tex;
1217
1218 pipe_resource_reference(
1219 &img->resource, pimages[p].resource);
1220
1221 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1222 if (nvc0->images_tic[s][i]) {
1223 struct nv50_tic_entry *old =
1224 nv50_tic_entry(nvc0->images_tic[s][i]);
1225 nvc0_screen_tic_unlock(nvc0->screen, old);
1226 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1227 }
1228
1229 nvc0->images_tic[s][i] =
1230 gm107_create_texture_view_from_image(&nvc0->base.pipe,
1231 &pimages[p]);
1232 }
1233 }
1234 if (!mask)
1235 return false;
1236 } else {
1237 mask = ((1 << nr) - 1) << start;
1238 if (!(nvc0->images_valid[s] & mask))
1239 return false;
1240 for (i = start; i < end; ++i) {
1241 pipe_resource_reference(&nvc0->images[s][i].resource, NULL);
1242 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1243 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->images_tic[s][i]);
1244 if (old) {
1245 nvc0_screen_tic_unlock(nvc0->screen, old);
1246 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1247 }
1248 }
1249 }
1250 nvc0->images_valid[s] &= ~mask;
1251 }
1252 nvc0->images_dirty[s] |= mask;
1253
1254 if (s == 5)
1255 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1256 else
1257 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1258
1259 return true;
1260 }
1261
1262 static void
1263 nvc0_set_shader_images(struct pipe_context *pipe,
1264 enum pipe_shader_type shader,
1265 unsigned start, unsigned nr,
1266 const struct pipe_image_view *images)
1267 {
1268 const unsigned s = nvc0_shader_stage(shader);
1269 if (!nvc0_bind_images_range(nvc0_context(pipe), s, start, nr, images))
1270 return;
1271
1272 if (s == 5)
1273 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1274 else
1275 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SURFACES;
1276 }
1277
1278 static bool
1279 nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t,
1280 unsigned start, unsigned nr,
1281 const struct pipe_shader_buffer *pbuffers)
1282 {
1283 const unsigned end = start + nr;
1284 unsigned mask = 0;
1285 unsigned i;
1286
1287 assert(t < 6);
1288
1289 if (pbuffers) {
1290 for (i = start; i < end; ++i) {
1291 struct pipe_shader_buffer *buf = &nvc0->buffers[t][i];
1292 const unsigned p = i - start;
1293 if (buf->buffer == pbuffers[p].buffer &&
1294 buf->buffer_offset == pbuffers[p].buffer_offset &&
1295 buf->buffer_size == pbuffers[p].buffer_size)
1296 continue;
1297
1298 mask |= (1 << i);
1299 if (pbuffers[p].buffer)
1300 nvc0->buffers_valid[t] |= (1 << i);
1301 else
1302 nvc0->buffers_valid[t] &= ~(1 << i);
1303 buf->buffer_offset = pbuffers[p].buffer_offset;
1304 buf->buffer_size = pbuffers[p].buffer_size;
1305 pipe_resource_reference(&buf->buffer, pbuffers[p].buffer);
1306 }
1307 if (!mask)
1308 return false;
1309 } else {
1310 mask = ((1 << nr) - 1) << start;
1311 if (!(nvc0->buffers_valid[t] & mask))
1312 return false;
1313 for (i = start; i < end; ++i)
1314 pipe_resource_reference(&nvc0->buffers[t][i].buffer, NULL);
1315 nvc0->buffers_valid[t] &= ~mask;
1316 }
1317 nvc0->buffers_dirty[t] |= mask;
1318
1319 if (t == 5)
1320 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF);
1321 else
1322 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BUF);
1323
1324 return true;
1325 }
1326
1327 static void
1328 nvc0_set_shader_buffers(struct pipe_context *pipe,
1329 enum pipe_shader_type shader,
1330 unsigned start, unsigned nr,
1331 const struct pipe_shader_buffer *buffers,
1332 unsigned writable_bitmask)
1333 {
1334 const unsigned s = nvc0_shader_stage(shader);
1335 if (!nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers))
1336 return;
1337
1338 if (s == 5)
1339 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_BUFFERS;
1340 else
1341 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_BUFFERS;
1342 }
1343
1344 static inline void
1345 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1346 {
1347 struct nv04_resource *buf = nv04_resource(res);
1348 if (buf) {
1349 uint64_t limit = (buf->address + buf->base.width0) - 1;
1350 if (limit < (1ULL << 32)) {
1351 *phandle = (uint32_t)buf->address;
1352 } else {
1353 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1354 "resource not contained within 32-bit address space !\n");
1355 *phandle = 0;
1356 }
1357 } else {
1358 *phandle = 0;
1359 }
1360 }
1361
1362 static void
1363 nvc0_set_global_bindings(struct pipe_context *pipe,
1364 unsigned start, unsigned nr,
1365 struct pipe_resource **resources,
1366 uint32_t **handles)
1367 {
1368 struct nvc0_context *nvc0 = nvc0_context(pipe);
1369 struct pipe_resource **ptr;
1370 unsigned i;
1371 const unsigned end = start + nr;
1372
1373 if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1374 const unsigned old_size = nvc0->global_residents.size;
1375 util_dynarray_resize(&nvc0->global_residents, struct pipe_resource *, end);
1376 memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1377 nvc0->global_residents.size - old_size);
1378 }
1379
1380 if (resources) {
1381 ptr = util_dynarray_element(
1382 &nvc0->global_residents, struct pipe_resource *, start);
1383 for (i = 0; i < nr; ++i) {
1384 pipe_resource_reference(&ptr[i], resources[i]);
1385 nvc0_set_global_handle(handles[i], resources[i]);
1386 }
1387 } else {
1388 ptr = util_dynarray_element(
1389 &nvc0->global_residents, struct pipe_resource *, start);
1390 for (i = 0; i < nr; ++i)
1391 pipe_resource_reference(&ptr[i], NULL);
1392 }
1393
1394 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1395
1396 nvc0->dirty_cp |= NVC0_NEW_CP_GLOBALS;
1397 }
1398
1399 void
1400 nvc0_init_state_functions(struct nvc0_context *nvc0)
1401 {
1402 struct pipe_context *pipe = &nvc0->base.pipe;
1403
1404 pipe->create_blend_state = nvc0_blend_state_create;
1405 pipe->bind_blend_state = nvc0_blend_state_bind;
1406 pipe->delete_blend_state = nvc0_blend_state_delete;
1407
1408 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1409 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1410 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1411
1412 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1413 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1414 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1415
1416 pipe->create_sampler_state = nv50_sampler_state_create;
1417 pipe->delete_sampler_state = nvc0_sampler_state_delete;
1418 pipe->bind_sampler_states = nvc0_bind_sampler_states;
1419
1420 pipe->create_sampler_view = nvc0_create_sampler_view;
1421 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1422 pipe->set_sampler_views = nvc0_set_sampler_views;
1423
1424 pipe->create_vs_state = nvc0_vp_state_create;
1425 pipe->create_fs_state = nvc0_fp_state_create;
1426 pipe->create_gs_state = nvc0_gp_state_create;
1427 pipe->create_tcs_state = nvc0_tcp_state_create;
1428 pipe->create_tes_state = nvc0_tep_state_create;
1429 pipe->bind_vs_state = nvc0_vp_state_bind;
1430 pipe->bind_fs_state = nvc0_fp_state_bind;
1431 pipe->bind_gs_state = nvc0_gp_state_bind;
1432 pipe->bind_tcs_state = nvc0_tcp_state_bind;
1433 pipe->bind_tes_state = nvc0_tep_state_bind;
1434 pipe->delete_vs_state = nvc0_sp_state_delete;
1435 pipe->delete_fs_state = nvc0_sp_state_delete;
1436 pipe->delete_gs_state = nvc0_sp_state_delete;
1437 pipe->delete_tcs_state = nvc0_sp_state_delete;
1438 pipe->delete_tes_state = nvc0_sp_state_delete;
1439
1440 pipe->create_compute_state = nvc0_cp_state_create;
1441 pipe->bind_compute_state = nvc0_cp_state_bind;
1442 pipe->delete_compute_state = nvc0_sp_state_delete;
1443
1444 pipe->set_blend_color = nvc0_set_blend_color;
1445 pipe->set_stencil_ref = nvc0_set_stencil_ref;
1446 pipe->set_clip_state = nvc0_set_clip_state;
1447 pipe->set_sample_mask = nvc0_set_sample_mask;
1448 pipe->set_min_samples = nvc0_set_min_samples;
1449 pipe->set_constant_buffer = nvc0_set_constant_buffer;
1450 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1451 pipe->set_sample_locations = nvc0_set_sample_locations;
1452 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1453 pipe->set_scissor_states = nvc0_set_scissor_states;
1454 pipe->set_viewport_states = nvc0_set_viewport_states;
1455 pipe->set_window_rectangles = nvc0_set_window_rectangles;
1456 pipe->set_tess_state = nvc0_set_tess_state;
1457
1458 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1459 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1460 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1461
1462 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1463
1464 pipe->create_stream_output_target = nvc0_so_target_create;
1465 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1466 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1467
1468 pipe->set_global_binding = nvc0_set_global_bindings;
1469 pipe->set_compute_resources = nvc0_set_compute_resources;
1470 pipe->set_shader_images = nvc0_set_shader_images;
1471 pipe->set_shader_buffers = nvc0_set_shader_buffers;
1472
1473 nvc0->sample_mask = ~0;
1474 nvc0->min_samples = 1;
1475 nvc0->default_tess_outer[0] =
1476 nvc0->default_tess_outer[1] =
1477 nvc0->default_tess_outer[2] =
1478 nvc0->default_tess_outer[3] = 1.0;
1479 nvc0->default_tess_inner[0] =
1480 nvc0->default_tess_inner[1] = 1.0;
1481 }