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Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_helpers.h"
25 #include "util/u_inlines.h"
26 #include "util/u_transfer.h"
27
28 #include "tgsi/tgsi_parse.h"
29
30 #include "nvc0/nvc0_stateobj.h"
31 #include "nvc0/nvc0_context.h"
32 #include "nvc0/nvc0_query_hw.h"
33
34 #include "nvc0/nvc0_3d.xml.h"
35 #include "nv50/nv50_texture.xml.h"
36
37 #include "nouveau_gldefs.h"
38
39 static inline uint32_t
40 nvc0_colormask(unsigned mask)
41 {
42 uint32_t ret = 0;
43
44 if (mask & PIPE_MASK_R)
45 ret |= 0x0001;
46 if (mask & PIPE_MASK_G)
47 ret |= 0x0010;
48 if (mask & PIPE_MASK_B)
49 ret |= 0x0100;
50 if (mask & PIPE_MASK_A)
51 ret |= 0x1000;
52
53 return ret;
54 }
55
56 #define NVC0_BLEND_FACTOR_CASE(a, b) \
57 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
58
59 static inline uint32_t
60 nvc0_blend_fac(unsigned factor)
61 {
62 switch (factor) {
63 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
64 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
65 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
66 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
67 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
68 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
69 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
70 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
71 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
72 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
73 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
74 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
75 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
76 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
77 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
78 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
79 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
80 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
81 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
82 default:
83 return NV50_BLEND_FACTOR_ZERO;
84 }
85 }
86
87 static void *
88 nvc0_blend_state_create(struct pipe_context *pipe,
89 const struct pipe_blend_state *cso)
90 {
91 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
92 int i;
93 int r; /* reference */
94 uint8_t blend_en = 0;
95 bool indep_masks = false;
96 bool indep_funcs = false;
97
98 so->pipe = *cso;
99
100 /* check which states actually have differing values */
101 if (cso->independent_blend_enable) {
102 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
103 blend_en |= 1 << r;
104 for (i = r + 1; i < 8; ++i) {
105 if (!cso->rt[i].blend_enable)
106 continue;
107 blend_en |= 1 << i;
108 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
109 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
110 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
111 cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
112 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
113 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
114 indep_funcs = true;
115 break;
116 }
117 }
118 for (; i < 8; ++i)
119 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
120
121 for (i = 1; i < 8; ++i) {
122 if (cso->rt[i].colormask != cso->rt[0].colormask) {
123 indep_masks = true;
124 break;
125 }
126 }
127 } else {
128 r = 0;
129 if (cso->rt[0].blend_enable)
130 blend_en = 0xff;
131 }
132
133 if (cso->logicop_enable) {
134 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
135 SB_DATA (so, 1);
136 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
137
138 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
139 } else {
140 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
141
142 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
143 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
144 if (indep_funcs) {
145 for (i = 0; i < 8; ++i) {
146 if (cso->rt[i].blend_enable) {
147 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
148 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
149 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
150 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
151 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
152 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
153 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
154 }
155 }
156 } else
157 if (blend_en) {
158 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
159 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
160 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
161 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
162 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
163 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
164 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
165 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
166 }
167
168 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
169 if (indep_masks) {
170 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
171 for (i = 0; i < 8; ++i)
172 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
173 } else {
174 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
175 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
176 }
177 }
178
179 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
180 return so;
181 }
182
183 static void
184 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
185 {
186 struct nvc0_context *nvc0 = nvc0_context(pipe);
187
188 nvc0->blend = hwcso;
189 nvc0->dirty |= NVC0_NEW_BLEND;
190 }
191
192 static void
193 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
194 {
195 FREE(hwcso);
196 }
197
198 /* NOTE: ignoring line_last_pixel */
199 static void *
200 nvc0_rasterizer_state_create(struct pipe_context *pipe,
201 const struct pipe_rasterizer_state *cso)
202 {
203 struct nvc0_rasterizer_stateobj *so;
204 uint32_t reg;
205
206 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
207 if (!so)
208 return NULL;
209 so->pipe = *cso;
210
211 /* Scissor enables are handled in scissor state, we will not want to
212 * always emit 16 commands, one for each scissor rectangle, here.
213 */
214
215 SB_BEGIN_3D(so, SHADE_MODEL, 1);
216 SB_DATA (so, cso->flatshade ? NVC0_3D_SHADE_MODEL_FLAT :
217 NVC0_3D_SHADE_MODEL_SMOOTH);
218 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
219 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
220
221 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
222 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
223 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
224
225 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
226
227 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
228 if (cso->line_smooth || cso->multisample)
229 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
230 else
231 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
232 SB_DATA (so, fui(cso->line_width));
233
234 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
235 if (cso->line_stipple_enable) {
236 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
237 SB_DATA (so, (cso->line_stipple_pattern << 8) |
238 cso->line_stipple_factor);
239
240 }
241
242 SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
243 if (!cso->point_size_per_vertex) {
244 SB_BEGIN_3D(so, POINT_SIZE, 1);
245 SB_DATA (so, fui(cso->point_size));
246 }
247
248 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
249 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
250 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
251
252 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
253 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
254 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
255 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
256
257 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
258 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
259 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
260 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
261 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
262
263 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
264 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
265 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
266 NVC0_3D_FRONT_FACE_CW);
267 switch (cso->cull_face) {
268 case PIPE_FACE_FRONT_AND_BACK:
269 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
270 break;
271 case PIPE_FACE_FRONT:
272 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
273 break;
274 case PIPE_FACE_BACK:
275 default:
276 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
277 break;
278 }
279
280 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
281 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
282 SB_DATA (so, cso->offset_point);
283 SB_DATA (so, cso->offset_line);
284 SB_DATA (so, cso->offset_tri);
285
286 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
287 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
288 SB_DATA (so, fui(cso->offset_scale));
289 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
290 SB_DATA (so, fui(cso->offset_units * 2.0f));
291 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
292 SB_DATA (so, fui(cso->offset_clamp));
293 }
294
295 if (cso->depth_clip)
296 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
297 else
298 reg =
299 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
300 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
301 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
302 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
303
304 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
305 SB_DATA (so, reg);
306
307 SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
308
309 SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
310
311 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
312 return (void *)so;
313 }
314
315 static void
316 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
317 {
318 struct nvc0_context *nvc0 = nvc0_context(pipe);
319
320 nvc0->rast = hwcso;
321 nvc0->dirty |= NVC0_NEW_RASTERIZER;
322 }
323
324 static void
325 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
326 {
327 FREE(hwcso);
328 }
329
330 static void *
331 nvc0_zsa_state_create(struct pipe_context *pipe,
332 const struct pipe_depth_stencil_alpha_state *cso)
333 {
334 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
335
336 so->pipe = *cso;
337
338 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
339 if (cso->depth.enabled) {
340 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
341 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
342 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
343 }
344
345 SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth.bounds_test);
346 if (cso->depth.bounds_test) {
347 SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
348 SB_DATA (so, fui(cso->depth.bounds_min));
349 SB_DATA (so, fui(cso->depth.bounds_max));
350 }
351
352 if (cso->stencil[0].enabled) {
353 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
354 SB_DATA (so, 1);
355 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
356 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
357 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
358 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
359 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
360 SB_DATA (so, cso->stencil[0].valuemask);
361 SB_DATA (so, cso->stencil[0].writemask);
362 } else {
363 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
364 }
365
366 if (cso->stencil[1].enabled) {
367 assert(cso->stencil[0].enabled);
368 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
369 SB_DATA (so, 1);
370 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
371 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
372 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
373 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
374 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
375 SB_DATA (so, cso->stencil[1].writemask);
376 SB_DATA (so, cso->stencil[1].valuemask);
377 } else
378 if (cso->stencil[0].enabled) {
379 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
380 }
381
382 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
383 if (cso->alpha.enabled) {
384 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
385 SB_DATA (so, fui(cso->alpha.ref_value));
386 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
387 }
388
389 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
390 return (void *)so;
391 }
392
393 static void
394 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
395 {
396 struct nvc0_context *nvc0 = nvc0_context(pipe);
397
398 nvc0->zsa = hwcso;
399 nvc0->dirty |= NVC0_NEW_ZSA;
400 }
401
402 static void
403 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
404 {
405 FREE(hwcso);
406 }
407
408 /* ====================== SAMPLERS AND TEXTURES ================================
409 */
410
411 #define NV50_TSC_WRAP_CASE(n) \
412 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
413
414 static void
415 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
416 {
417 unsigned s, i;
418
419 for (s = 0; s < 5; ++s)
420 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
421 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
422 nvc0_context(pipe)->samplers[s][i] = NULL;
423
424 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
425
426 FREE(hwcso);
427 }
428
429 static inline void
430 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0, int s,
431 unsigned nr, void **hwcso)
432 {
433 unsigned i;
434
435 for (i = 0; i < nr; ++i) {
436 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
437
438 if (hwcso[i] == old)
439 continue;
440 nvc0->samplers_dirty[s] |= 1 << i;
441
442 nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
443 if (old)
444 nvc0_screen_tsc_unlock(nvc0->screen, old);
445 }
446 for (; i < nvc0->num_samplers[s]; ++i) {
447 if (nvc0->samplers[s][i]) {
448 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
449 nvc0->samplers[s][i] = NULL;
450 }
451 }
452
453 nvc0->num_samplers[s] = nr;
454
455 nvc0->dirty |= NVC0_NEW_SAMPLERS;
456 }
457
458 static void
459 nvc0_stage_sampler_states_bind_range(struct nvc0_context *nvc0,
460 const unsigned s,
461 unsigned start, unsigned nr, void **cso)
462 {
463 const unsigned end = start + nr;
464 int last_valid = -1;
465 unsigned i;
466
467 if (cso) {
468 for (i = start; i < end; ++i) {
469 const unsigned p = i - start;
470 if (cso[p])
471 last_valid = i;
472 if (cso[p] == nvc0->samplers[s][i])
473 continue;
474 nvc0->samplers_dirty[s] |= 1 << i;
475
476 if (nvc0->samplers[s][i])
477 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
478 nvc0->samplers[s][i] = cso[p];
479 }
480 } else {
481 for (i = start; i < end; ++i) {
482 if (nvc0->samplers[s][i]) {
483 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
484 nvc0->samplers[s][i] = NULL;
485 nvc0->samplers_dirty[s] |= 1 << i;
486 }
487 }
488 }
489
490 if (nvc0->num_samplers[s] <= end) {
491 if (last_valid < 0) {
492 for (i = start; i && !nvc0->samplers[s][i - 1]; --i);
493 nvc0->num_samplers[s] = i;
494 } else {
495 nvc0->num_samplers[s] = last_valid + 1;
496 }
497 }
498 }
499
500 static void
501 nvc0_bind_sampler_states(struct pipe_context *pipe, unsigned shader,
502 unsigned start, unsigned nr, void **s)
503 {
504 switch (shader) {
505 case PIPE_SHADER_VERTEX:
506 assert(start == 0);
507 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 0, nr, s);
508 break;
509 case PIPE_SHADER_TESS_CTRL:
510 assert(start == 0);
511 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 1, nr, s);
512 break;
513 case PIPE_SHADER_TESS_EVAL:
514 assert(start == 0);
515 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 2, nr, s);
516 break;
517 case PIPE_SHADER_GEOMETRY:
518 assert(start == 0);
519 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 3, nr, s);
520 break;
521 case PIPE_SHADER_FRAGMENT:
522 assert(start == 0);
523 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 4, nr, s);
524 break;
525 case PIPE_SHADER_COMPUTE:
526 nvc0_stage_sampler_states_bind_range(nvc0_context(pipe), 5,
527 start, nr, s);
528 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
529 break;
530 }
531 }
532
533
534 /* NOTE: only called when not referenced anywhere, won't be bound */
535 static void
536 nvc0_sampler_view_destroy(struct pipe_context *pipe,
537 struct pipe_sampler_view *view)
538 {
539 pipe_resource_reference(&view->texture, NULL);
540
541 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
542
543 FREE(nv50_tic_entry(view));
544 }
545
546 static inline void
547 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
548 unsigned nr,
549 struct pipe_sampler_view **views)
550 {
551 unsigned i;
552
553 for (i = 0; i < nr; ++i) {
554 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
555
556 if (views[i] == nvc0->textures[s][i])
557 continue;
558 nvc0->textures_dirty[s] |= 1 << i;
559
560 if (old) {
561 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(s, i));
562 nvc0_screen_tic_unlock(nvc0->screen, old);
563 }
564
565 pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
566 }
567
568 for (i = nr; i < nvc0->num_textures[s]; ++i) {
569 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
570 if (old) {
571 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(s, i));
572 nvc0_screen_tic_unlock(nvc0->screen, old);
573 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
574 }
575 }
576
577 nvc0->num_textures[s] = nr;
578
579 nvc0->dirty |= NVC0_NEW_TEXTURES;
580 }
581
582 static void
583 nvc0_stage_set_sampler_views_range(struct nvc0_context *nvc0, const unsigned s,
584 unsigned start, unsigned nr,
585 struct pipe_sampler_view **views)
586 {
587 struct nouveau_bufctx *bctx = (s == 5) ? nvc0->bufctx_cp : nvc0->bufctx_3d;
588 const unsigned end = start + nr;
589 const unsigned bin = (s == 5) ? NVC0_BIND_CP_TEX(0) : NVC0_BIND_TEX(s, 0);
590 int last_valid = -1;
591 unsigned i;
592
593 if (views) {
594 for (i = start; i < end; ++i) {
595 const unsigned p = i - start;
596 if (views[p])
597 last_valid = i;
598 if (views[p] == nvc0->textures[s][i])
599 continue;
600 nvc0->textures_dirty[s] |= 1 << i;
601
602 if (nvc0->textures[s][i]) {
603 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
604 nouveau_bufctx_reset(bctx, bin + i);
605 nvc0_screen_tic_unlock(nvc0->screen, old);
606 }
607 pipe_sampler_view_reference(&nvc0->textures[s][i], views[p]);
608 }
609 } else {
610 for (i = start; i < end; ++i) {
611 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
612 if (!old)
613 continue;
614 nvc0->textures_dirty[s] |= 1 << i;
615
616 nvc0_screen_tic_unlock(nvc0->screen, old);
617 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
618 nouveau_bufctx_reset(bctx, bin + i);
619 }
620 }
621
622 if (nvc0->num_textures[s] <= end) {
623 if (last_valid < 0) {
624 for (i = start; i && !nvc0->textures[s][i - 1]; --i);
625 nvc0->num_textures[s] = i;
626 } else {
627 nvc0->num_textures[s] = last_valid + 1;
628 }
629 }
630 }
631
632 static void
633 nvc0_set_sampler_views(struct pipe_context *pipe, unsigned shader,
634 unsigned start, unsigned nr,
635 struct pipe_sampler_view **views)
636 {
637 assert(start == 0);
638 switch (shader) {
639 case PIPE_SHADER_VERTEX:
640 nvc0_stage_set_sampler_views(nvc0_context(pipe), 0, nr, views);
641 break;
642 case PIPE_SHADER_TESS_CTRL:
643 nvc0_stage_set_sampler_views(nvc0_context(pipe), 1, nr, views);
644 break;
645 case PIPE_SHADER_TESS_EVAL:
646 nvc0_stage_set_sampler_views(nvc0_context(pipe), 2, nr, views);
647 break;
648 case PIPE_SHADER_GEOMETRY:
649 nvc0_stage_set_sampler_views(nvc0_context(pipe), 3, nr, views);
650 break;
651 case PIPE_SHADER_FRAGMENT:
652 nvc0_stage_set_sampler_views(nvc0_context(pipe), 4, nr, views);
653 break;
654 case PIPE_SHADER_COMPUTE:
655 nvc0_stage_set_sampler_views_range(nvc0_context(pipe), 5,
656 start, nr, views);
657 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
658 break;
659 default:
660 ;
661 }
662 }
663
664
665 /* ============================= SHADERS =======================================
666 */
667
668 static void *
669 nvc0_sp_state_create(struct pipe_context *pipe,
670 const struct pipe_shader_state *cso, unsigned type)
671 {
672 struct nvc0_program *prog;
673
674 prog = CALLOC_STRUCT(nvc0_program);
675 if (!prog)
676 return NULL;
677
678 prog->type = type;
679
680 if (cso->tokens)
681 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
682
683 if (cso->stream_output.num_outputs)
684 prog->pipe.stream_output = cso->stream_output;
685
686 return (void *)prog;
687 }
688
689 static void
690 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
691 {
692 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
693
694 nvc0_program_destroy(nvc0_context(pipe), prog);
695
696 FREE((void *)prog->pipe.tokens);
697 FREE(prog);
698 }
699
700 static void *
701 nvc0_vp_state_create(struct pipe_context *pipe,
702 const struct pipe_shader_state *cso)
703 {
704 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
705 }
706
707 static void
708 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
709 {
710 struct nvc0_context *nvc0 = nvc0_context(pipe);
711
712 nvc0->vertprog = hwcso;
713 nvc0->dirty |= NVC0_NEW_VERTPROG;
714 }
715
716 static void *
717 nvc0_fp_state_create(struct pipe_context *pipe,
718 const struct pipe_shader_state *cso)
719 {
720 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
721 }
722
723 static void
724 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
725 {
726 struct nvc0_context *nvc0 = nvc0_context(pipe);
727
728 nvc0->fragprog = hwcso;
729 nvc0->dirty |= NVC0_NEW_FRAGPROG;
730 }
731
732 static void *
733 nvc0_gp_state_create(struct pipe_context *pipe,
734 const struct pipe_shader_state *cso)
735 {
736 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
737 }
738
739 static void
740 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
741 {
742 struct nvc0_context *nvc0 = nvc0_context(pipe);
743
744 nvc0->gmtyprog = hwcso;
745 nvc0->dirty |= NVC0_NEW_GMTYPROG;
746 }
747
748 static void *
749 nvc0_tcp_state_create(struct pipe_context *pipe,
750 const struct pipe_shader_state *cso)
751 {
752 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
753 }
754
755 static void
756 nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
757 {
758 struct nvc0_context *nvc0 = nvc0_context(pipe);
759
760 nvc0->tctlprog = hwcso;
761 nvc0->dirty |= NVC0_NEW_TCTLPROG;
762 }
763
764 static void *
765 nvc0_tep_state_create(struct pipe_context *pipe,
766 const struct pipe_shader_state *cso)
767 {
768 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
769 }
770
771 static void
772 nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
773 {
774 struct nvc0_context *nvc0 = nvc0_context(pipe);
775
776 nvc0->tevlprog = hwcso;
777 nvc0->dirty |= NVC0_NEW_TEVLPROG;
778 }
779
780 static void *
781 nvc0_cp_state_create(struct pipe_context *pipe,
782 const struct pipe_compute_state *cso)
783 {
784 struct nvc0_program *prog;
785
786 prog = CALLOC_STRUCT(nvc0_program);
787 if (!prog)
788 return NULL;
789 prog->type = PIPE_SHADER_COMPUTE;
790
791 prog->cp.smem_size = cso->req_local_mem;
792 prog->cp.lmem_size = cso->req_private_mem;
793 prog->parm_size = cso->req_input_mem;
794
795 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
796
797 return (void *)prog;
798 }
799
800 static void
801 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
802 {
803 struct nvc0_context *nvc0 = nvc0_context(pipe);
804
805 nvc0->compprog = hwcso;
806 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
807 }
808
809 static void
810 nvc0_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
811 struct pipe_constant_buffer *cb)
812 {
813 struct nvc0_context *nvc0 = nvc0_context(pipe);
814 struct pipe_resource *res = cb ? cb->buffer : NULL;
815 const unsigned s = nvc0_shader_stage(shader);
816 const unsigned i = index;
817
818 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
819 assert(!cb || !cb->user_buffer);
820 if (nvc0->constbuf[s][i].u.buf)
821 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
822
823 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
824 } else {
825 if (nvc0->constbuf[s][i].user)
826 nvc0->constbuf[s][i].u.buf = NULL;
827 else
828 if (nvc0->constbuf[s][i].u.buf)
829 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_CB(s, i));
830
831 nvc0->dirty |= NVC0_NEW_CONSTBUF;
832 }
833 nvc0->constbuf_dirty[s] |= 1 << i;
834
835 if (nvc0->constbuf[s][i].u.buf)
836 nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
837 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
838
839 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
840 if (nvc0->constbuf[s][i].user) {
841 nvc0->constbuf[s][i].u.data = cb->user_buffer;
842 nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
843 nvc0->constbuf_valid[s] |= 1 << i;
844 } else
845 if (cb) {
846 nvc0->constbuf[s][i].offset = cb->buffer_offset;
847 nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
848 nvc0->constbuf_valid[s] |= 1 << i;
849 }
850 else {
851 nvc0->constbuf_valid[s] &= ~(1 << i);
852 }
853 }
854
855 /* =============================================================================
856 */
857
858 static void
859 nvc0_set_blend_color(struct pipe_context *pipe,
860 const struct pipe_blend_color *bcol)
861 {
862 struct nvc0_context *nvc0 = nvc0_context(pipe);
863
864 nvc0->blend_colour = *bcol;
865 nvc0->dirty |= NVC0_NEW_BLEND_COLOUR;
866 }
867
868 static void
869 nvc0_set_stencil_ref(struct pipe_context *pipe,
870 const struct pipe_stencil_ref *sr)
871 {
872 struct nvc0_context *nvc0 = nvc0_context(pipe);
873
874 nvc0->stencil_ref = *sr;
875 nvc0->dirty |= NVC0_NEW_STENCIL_REF;
876 }
877
878 static void
879 nvc0_set_clip_state(struct pipe_context *pipe,
880 const struct pipe_clip_state *clip)
881 {
882 struct nvc0_context *nvc0 = nvc0_context(pipe);
883
884 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
885
886 nvc0->dirty |= NVC0_NEW_CLIP;
887 }
888
889 static void
890 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
891 {
892 struct nvc0_context *nvc0 = nvc0_context(pipe);
893
894 nvc0->sample_mask = sample_mask;
895 nvc0->dirty |= NVC0_NEW_SAMPLE_MASK;
896 }
897
898 static void
899 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
900 {
901 struct nvc0_context *nvc0 = nvc0_context(pipe);
902
903 if (nvc0->min_samples != min_samples) {
904 nvc0->min_samples = min_samples;
905 nvc0->dirty |= NVC0_NEW_MIN_SAMPLES;
906 }
907 }
908
909 static void
910 nvc0_set_framebuffer_state(struct pipe_context *pipe,
911 const struct pipe_framebuffer_state *fb)
912 {
913 struct nvc0_context *nvc0 = nvc0_context(pipe);
914 unsigned i;
915
916 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
917
918 for (i = 0; i < fb->nr_cbufs; ++i)
919 pipe_surface_reference(&nvc0->framebuffer.cbufs[i], fb->cbufs[i]);
920 for (; i < nvc0->framebuffer.nr_cbufs; ++i)
921 pipe_surface_reference(&nvc0->framebuffer.cbufs[i], NULL);
922
923 nvc0->framebuffer.nr_cbufs = fb->nr_cbufs;
924
925 nvc0->framebuffer.width = fb->width;
926 nvc0->framebuffer.height = fb->height;
927
928 pipe_surface_reference(&nvc0->framebuffer.zsbuf, fb->zsbuf);
929
930 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
931 }
932
933 static void
934 nvc0_set_polygon_stipple(struct pipe_context *pipe,
935 const struct pipe_poly_stipple *stipple)
936 {
937 struct nvc0_context *nvc0 = nvc0_context(pipe);
938
939 nvc0->stipple = *stipple;
940 nvc0->dirty |= NVC0_NEW_STIPPLE;
941 }
942
943 static void
944 nvc0_set_scissor_states(struct pipe_context *pipe,
945 unsigned start_slot,
946 unsigned num_scissors,
947 const struct pipe_scissor_state *scissor)
948 {
949 struct nvc0_context *nvc0 = nvc0_context(pipe);
950 int i;
951
952 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
953 for (i = 0; i < num_scissors; i++) {
954 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
955 continue;
956 nvc0->scissors[start_slot + i] = scissor[i];
957 nvc0->scissors_dirty |= 1 << (start_slot + i);
958 nvc0->dirty |= NVC0_NEW_SCISSOR;
959 }
960 }
961
962 static void
963 nvc0_set_viewport_states(struct pipe_context *pipe,
964 unsigned start_slot,
965 unsigned num_viewports,
966 const struct pipe_viewport_state *vpt)
967 {
968 struct nvc0_context *nvc0 = nvc0_context(pipe);
969 int i;
970
971 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
972 for (i = 0; i < num_viewports; i++) {
973 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
974 continue;
975 nvc0->viewports[start_slot + i] = vpt[i];
976 nvc0->viewports_dirty |= 1 << (start_slot + i);
977 nvc0->dirty |= NVC0_NEW_VIEWPORT;
978 }
979
980 }
981
982 static void
983 nvc0_set_tess_state(struct pipe_context *pipe,
984 const float default_tess_outer[4],
985 const float default_tess_inner[2])
986 {
987 struct nvc0_context *nvc0 = nvc0_context(pipe);
988
989 memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
990 memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
991 nvc0->dirty |= NVC0_NEW_TESSFACTOR;
992 }
993
994 static void
995 nvc0_set_vertex_buffers(struct pipe_context *pipe,
996 unsigned start_slot, unsigned count,
997 const struct pipe_vertex_buffer *vb)
998 {
999 struct nvc0_context *nvc0 = nvc0_context(pipe);
1000 unsigned i;
1001
1002 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
1003 start_slot, count);
1004
1005 if (!vb) {
1006 nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
1007 nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
1008 return;
1009 }
1010
1011 for (i = 0; i < count; ++i) {
1012 unsigned dst_index = start_slot + i;
1013
1014 if (vb[i].user_buffer) {
1015 nvc0->vbo_user |= 1 << dst_index;
1016 if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
1017 nvc0->constant_vbos |= 1 << dst_index;
1018 else
1019 nvc0->constant_vbos &= ~(1 << dst_index);
1020 } else {
1021 nvc0->vbo_user &= ~(1 << dst_index);
1022 nvc0->constant_vbos &= ~(1 << dst_index);
1023 }
1024 }
1025
1026 nvc0->dirty |= NVC0_NEW_ARRAYS;
1027 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX);
1028 }
1029
1030 static void
1031 nvc0_set_index_buffer(struct pipe_context *pipe,
1032 const struct pipe_index_buffer *ib)
1033 {
1034 struct nvc0_context *nvc0 = nvc0_context(pipe);
1035
1036 if (nvc0->idxbuf.buffer)
1037 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_IDX);
1038
1039 if (ib) {
1040 pipe_resource_reference(&nvc0->idxbuf.buffer, ib->buffer);
1041 nvc0->idxbuf.index_size = ib->index_size;
1042 if (ib->buffer) {
1043 nvc0->idxbuf.offset = ib->offset;
1044 nvc0->dirty |= NVC0_NEW_IDXBUF;
1045 } else {
1046 nvc0->idxbuf.user_buffer = ib->user_buffer;
1047 nvc0->dirty &= ~NVC0_NEW_IDXBUF;
1048 }
1049 } else {
1050 nvc0->dirty &= ~NVC0_NEW_IDXBUF;
1051 pipe_resource_reference(&nvc0->idxbuf.buffer, NULL);
1052 }
1053 }
1054
1055 static void
1056 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1057 {
1058 struct nvc0_context *nvc0 = nvc0_context(pipe);
1059
1060 nvc0->vertex = hwcso;
1061 nvc0->dirty |= NVC0_NEW_VERTEX;
1062 }
1063
1064 static struct pipe_stream_output_target *
1065 nvc0_so_target_create(struct pipe_context *pipe,
1066 struct pipe_resource *res,
1067 unsigned offset, unsigned size)
1068 {
1069 struct nv04_resource *buf = (struct nv04_resource *)res;
1070 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1071 if (!targ)
1072 return NULL;
1073
1074 targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0);
1075 if (!targ->pq) {
1076 FREE(targ);
1077 return NULL;
1078 }
1079 targ->clean = true;
1080
1081 targ->pipe.buffer_size = size;
1082 targ->pipe.buffer_offset = offset;
1083 targ->pipe.context = pipe;
1084 targ->pipe.buffer = NULL;
1085 pipe_resource_reference(&targ->pipe.buffer, res);
1086 pipe_reference_init(&targ->pipe.reference, 1);
1087
1088 assert(buf->base.target == PIPE_BUFFER);
1089 util_range_add(&buf->valid_buffer_range, offset, offset + size);
1090
1091 return &targ->pipe;
1092 }
1093
1094 static void
1095 nvc0_so_target_save_offset(struct pipe_context *pipe,
1096 struct pipe_stream_output_target *ptarg,
1097 unsigned index, bool *serialize)
1098 {
1099 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1100
1101 if (*serialize) {
1102 *serialize = false;
1103 PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
1104 IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
1105
1106 NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
1107 }
1108
1109 nvc0_query(targ->pq)->index = index;
1110 pipe->end_query(pipe, targ->pq);
1111 }
1112
1113 static void
1114 nvc0_so_target_destroy(struct pipe_context *pipe,
1115 struct pipe_stream_output_target *ptarg)
1116 {
1117 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1118 pipe->destroy_query(pipe, targ->pq);
1119 pipe_resource_reference(&targ->pipe.buffer, NULL);
1120 FREE(targ);
1121 }
1122
1123 static void
1124 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1125 unsigned num_targets,
1126 struct pipe_stream_output_target **targets,
1127 const unsigned *offsets)
1128 {
1129 struct nvc0_context *nvc0 = nvc0_context(pipe);
1130 unsigned i;
1131 bool serialize = true;
1132
1133 assert(num_targets <= 4);
1134
1135 for (i = 0; i < num_targets; ++i) {
1136 const bool changed = nvc0->tfbbuf[i] != targets[i];
1137 const bool append = (offsets[i] == ((unsigned)-1));
1138 if (!changed && append)
1139 continue;
1140 nvc0->tfbbuf_dirty |= 1 << i;
1141
1142 if (nvc0->tfbbuf[i] && changed)
1143 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1144
1145 if (targets[i] && !append)
1146 nvc0_so_target(targets[i])->clean = true;
1147
1148 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1149 }
1150 for (; i < nvc0->num_tfbbufs; ++i) {
1151 if (nvc0->tfbbuf[i]) {
1152 nvc0->tfbbuf_dirty |= 1 << i;
1153 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1154 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1155 }
1156 }
1157 nvc0->num_tfbbufs = num_targets;
1158
1159 if (nvc0->tfbbuf_dirty)
1160 nvc0->dirty |= NVC0_NEW_TFB_TARGETS;
1161 }
1162
1163 static void
1164 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1165 unsigned start, unsigned nr,
1166 struct pipe_surface **psurfaces)
1167 {
1168 const unsigned end = start + nr;
1169 const unsigned mask = ((1 << nr) - 1) << start;
1170 unsigned i;
1171
1172 if (psurfaces) {
1173 for (i = start; i < end; ++i) {
1174 const unsigned p = i - start;
1175 if (psurfaces[p])
1176 nvc0->surfaces_valid[t] |= (1 << i);
1177 else
1178 nvc0->surfaces_valid[t] &= ~(1 << i);
1179 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1180 }
1181 } else {
1182 for (i = start; i < end; ++i)
1183 pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1184 nvc0->surfaces_valid[t] &= ~mask;
1185 }
1186 nvc0->surfaces_dirty[t] |= mask;
1187
1188 if (t == 0)
1189 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_SUF);
1190 else
1191 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1192 }
1193
1194 static void
1195 nvc0_set_compute_resources(struct pipe_context *pipe,
1196 unsigned start, unsigned nr,
1197 struct pipe_surface **resources)
1198 {
1199 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1200
1201 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1202 }
1203
1204 static void
1205 nvc0_set_shader_images(struct pipe_context *pipe, unsigned shader,
1206 unsigned start_slot, unsigned count,
1207 struct pipe_image_view **views)
1208 {
1209 #if 0
1210 nvc0_bind_surfaces_range(nvc0_context(pipe), 0, start, nr, views);
1211
1212 nvc0_context(pipe)->dirty |= NVC0_NEW_SURFACES;
1213 #endif
1214 }
1215
1216 static inline void
1217 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1218 {
1219 struct nv04_resource *buf = nv04_resource(res);
1220 if (buf) {
1221 uint64_t limit = (buf->address + buf->base.width0) - 1;
1222 if (limit < (1ULL << 32)) {
1223 *phandle = (uint32_t)buf->address;
1224 } else {
1225 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1226 "resource not contained within 32-bit address space !\n");
1227 *phandle = 0;
1228 }
1229 } else {
1230 *phandle = 0;
1231 }
1232 }
1233
1234 static void
1235 nvc0_set_global_bindings(struct pipe_context *pipe,
1236 unsigned start, unsigned nr,
1237 struct pipe_resource **resources,
1238 uint32_t **handles)
1239 {
1240 struct nvc0_context *nvc0 = nvc0_context(pipe);
1241 struct pipe_resource **ptr;
1242 unsigned i;
1243 const unsigned end = start + nr;
1244
1245 if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1246 const unsigned old_size = nvc0->global_residents.size;
1247 const unsigned req_size = end * sizeof(struct pipe_resource *);
1248 util_dynarray_resize(&nvc0->global_residents, req_size);
1249 memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1250 req_size - old_size);
1251 }
1252
1253 if (resources) {
1254 ptr = util_dynarray_element(
1255 &nvc0->global_residents, struct pipe_resource *, start);
1256 for (i = 0; i < nr; ++i) {
1257 pipe_resource_reference(&ptr[i], resources[i]);
1258 nvc0_set_global_handle(handles[i], resources[i]);
1259 }
1260 } else {
1261 ptr = util_dynarray_element(
1262 &nvc0->global_residents, struct pipe_resource *, start);
1263 for (i = 0; i < nr; ++i)
1264 pipe_resource_reference(&ptr[i], NULL);
1265 }
1266
1267 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1268
1269 nvc0->dirty_cp = NVC0_NEW_CP_GLOBALS;
1270 }
1271
1272 void
1273 nvc0_init_state_functions(struct nvc0_context *nvc0)
1274 {
1275 struct pipe_context *pipe = &nvc0->base.pipe;
1276
1277 pipe->create_blend_state = nvc0_blend_state_create;
1278 pipe->bind_blend_state = nvc0_blend_state_bind;
1279 pipe->delete_blend_state = nvc0_blend_state_delete;
1280
1281 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1282 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1283 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1284
1285 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1286 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1287 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1288
1289 pipe->create_sampler_state = nv50_sampler_state_create;
1290 pipe->delete_sampler_state = nvc0_sampler_state_delete;
1291 pipe->bind_sampler_states = nvc0_bind_sampler_states;
1292
1293 pipe->create_sampler_view = nvc0_create_sampler_view;
1294 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1295 pipe->set_sampler_views = nvc0_set_sampler_views;
1296
1297 pipe->create_vs_state = nvc0_vp_state_create;
1298 pipe->create_fs_state = nvc0_fp_state_create;
1299 pipe->create_gs_state = nvc0_gp_state_create;
1300 pipe->create_tcs_state = nvc0_tcp_state_create;
1301 pipe->create_tes_state = nvc0_tep_state_create;
1302 pipe->bind_vs_state = nvc0_vp_state_bind;
1303 pipe->bind_fs_state = nvc0_fp_state_bind;
1304 pipe->bind_gs_state = nvc0_gp_state_bind;
1305 pipe->bind_tcs_state = nvc0_tcp_state_bind;
1306 pipe->bind_tes_state = nvc0_tep_state_bind;
1307 pipe->delete_vs_state = nvc0_sp_state_delete;
1308 pipe->delete_fs_state = nvc0_sp_state_delete;
1309 pipe->delete_gs_state = nvc0_sp_state_delete;
1310 pipe->delete_tcs_state = nvc0_sp_state_delete;
1311 pipe->delete_tes_state = nvc0_sp_state_delete;
1312
1313 pipe->create_compute_state = nvc0_cp_state_create;
1314 pipe->bind_compute_state = nvc0_cp_state_bind;
1315 pipe->delete_compute_state = nvc0_sp_state_delete;
1316
1317 pipe->set_blend_color = nvc0_set_blend_color;
1318 pipe->set_stencil_ref = nvc0_set_stencil_ref;
1319 pipe->set_clip_state = nvc0_set_clip_state;
1320 pipe->set_sample_mask = nvc0_set_sample_mask;
1321 pipe->set_min_samples = nvc0_set_min_samples;
1322 pipe->set_constant_buffer = nvc0_set_constant_buffer;
1323 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1324 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1325 pipe->set_scissor_states = nvc0_set_scissor_states;
1326 pipe->set_viewport_states = nvc0_set_viewport_states;
1327 pipe->set_tess_state = nvc0_set_tess_state;
1328
1329 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1330 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1331 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1332
1333 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1334 pipe->set_index_buffer = nvc0_set_index_buffer;
1335
1336 pipe->create_stream_output_target = nvc0_so_target_create;
1337 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1338 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1339
1340 pipe->set_global_binding = nvc0_set_global_bindings;
1341 pipe->set_compute_resources = nvc0_set_compute_resources;
1342 pipe->set_shader_images = nvc0_set_shader_images;
1343
1344 nvc0->sample_mask = ~0;
1345 nvc0->min_samples = 1;
1346 nvc0->default_tess_outer[0] =
1347 nvc0->default_tess_outer[1] =
1348 nvc0->default_tess_outer[2] =
1349 nvc0->default_tess_outer[3] = 1.0;
1350 nvc0->default_tess_inner[0] =
1351 nvc0->default_tess_inner[1] = 1.0;
1352 }