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nvc0: add a memory barrier when there are persistent UBOs
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_helpers.h"
25 #include "util/u_inlines.h"
26 #include "util/u_transfer.h"
27
28 #include "tgsi/tgsi_parse.h"
29
30 #include "nvc0/nvc0_stateobj.h"
31 #include "nvc0/nvc0_context.h"
32
33 #include "nvc0/nvc0_3d.xml.h"
34 #include "nv50/nv50_texture.xml.h"
35
36 #include "nouveau_gldefs.h"
37
38 static INLINE uint32_t
39 nvc0_colormask(unsigned mask)
40 {
41 uint32_t ret = 0;
42
43 if (mask & PIPE_MASK_R)
44 ret |= 0x0001;
45 if (mask & PIPE_MASK_G)
46 ret |= 0x0010;
47 if (mask & PIPE_MASK_B)
48 ret |= 0x0100;
49 if (mask & PIPE_MASK_A)
50 ret |= 0x1000;
51
52 return ret;
53 }
54
55 #define NVC0_BLEND_FACTOR_CASE(a, b) \
56 case PIPE_BLENDFACTOR_##a: return NV50_3D_BLEND_FACTOR_##b
57
58 static INLINE uint32_t
59 nvc0_blend_fac(unsigned factor)
60 {
61 switch (factor) {
62 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
63 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
64 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
65 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
66 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
67 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
68 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
69 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
70 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
71 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
72 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
73 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
74 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
75 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
76 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
77 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
78 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
79 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
80 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
81 default:
82 return NV50_3D_BLEND_FACTOR_ZERO;
83 }
84 }
85
86 static void *
87 nvc0_blend_state_create(struct pipe_context *pipe,
88 const struct pipe_blend_state *cso)
89 {
90 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
91 int i;
92 int r; /* reference */
93 uint32_t ms;
94 uint8_t blend_en = 0;
95 boolean indep_masks = FALSE;
96 boolean indep_funcs = FALSE;
97
98 so->pipe = *cso;
99
100 /* check which states actually have differing values */
101 if (cso->independent_blend_enable) {
102 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
103 blend_en |= 1 << r;
104 for (i = r + 1; i < 8; ++i) {
105 if (!cso->rt[i].blend_enable)
106 continue;
107 blend_en |= 1 << i;
108 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
109 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
110 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
111 cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
112 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
113 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
114 indep_funcs = TRUE;
115 break;
116 }
117 }
118 for (; i < 8; ++i)
119 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
120
121 for (i = 1; i < 8; ++i) {
122 if (cso->rt[i].colormask != cso->rt[0].colormask) {
123 indep_masks = TRUE;
124 break;
125 }
126 }
127 } else {
128 r = 0;
129 if (cso->rt[0].blend_enable)
130 blend_en = 0xff;
131 }
132
133 if (cso->logicop_enable) {
134 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
135 SB_DATA (so, 1);
136 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
137
138 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
139 } else {
140 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
141
142 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
143 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
144 if (indep_funcs) {
145 for (i = 0; i < 8; ++i) {
146 if (cso->rt[i].blend_enable) {
147 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
148 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
149 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
150 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
151 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
152 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
153 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
154 }
155 }
156 } else
157 if (blend_en) {
158 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
159 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
160 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
161 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
162 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
163 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
164 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
165 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
166 }
167
168 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
169 if (indep_masks) {
170 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
171 for (i = 0; i < 8; ++i)
172 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
173 } else {
174 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
175 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
176 }
177 }
178
179 ms = 0;
180 if (cso->alpha_to_coverage)
181 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
182 if (cso->alpha_to_one)
183 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
184
185 SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
186 SB_DATA (so, ms);
187
188 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
189 return so;
190 }
191
192 static void
193 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
194 {
195 struct nvc0_context *nvc0 = nvc0_context(pipe);
196
197 nvc0->blend = hwcso;
198 nvc0->dirty |= NVC0_NEW_BLEND;
199 }
200
201 static void
202 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
203 {
204 FREE(hwcso);
205 }
206
207 /* NOTE: ignoring line_last_pixel, using FALSE (set on screen init) */
208 static void *
209 nvc0_rasterizer_state_create(struct pipe_context *pipe,
210 const struct pipe_rasterizer_state *cso)
211 {
212 struct nvc0_rasterizer_stateobj *so;
213 uint32_t reg;
214
215 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
216 if (!so)
217 return NULL;
218 so->pipe = *cso;
219
220 /* Scissor enables are handled in scissor state, we will not want to
221 * always emit 16 commands, one for each scissor rectangle, here.
222 */
223
224 SB_BEGIN_3D(so, SHADE_MODEL, 1);
225 SB_DATA (so, cso->flatshade ? NVC0_3D_SHADE_MODEL_FLAT :
226 NVC0_3D_SHADE_MODEL_SMOOTH);
227 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
228 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
229
230 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
231 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
232 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
233
234 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
235
236 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
237 if (cso->line_smooth)
238 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
239 else
240 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
241 SB_DATA (so, fui(cso->line_width));
242
243 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
244 if (cso->line_stipple_enable) {
245 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
246 SB_DATA (so, (cso->line_stipple_pattern << 8) |
247 cso->line_stipple_factor);
248
249 }
250
251 SB_IMMED_3D(so, VP_POINT_SIZE_EN, cso->point_size_per_vertex);
252 if (!cso->point_size_per_vertex) {
253 SB_BEGIN_3D(so, POINT_SIZE, 1);
254 SB_DATA (so, fui(cso->point_size));
255 }
256
257 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
258 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
259 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
260
261 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
262 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
263 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
264 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
265
266 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
267 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
268 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
269 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
270 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
271
272 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
273 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
274 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
275 NVC0_3D_FRONT_FACE_CW);
276 switch (cso->cull_face) {
277 case PIPE_FACE_FRONT_AND_BACK:
278 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
279 break;
280 case PIPE_FACE_FRONT:
281 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
282 break;
283 case PIPE_FACE_BACK:
284 default:
285 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
286 break;
287 }
288
289 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
290 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
291 SB_DATA (so, cso->offset_point);
292 SB_DATA (so, cso->offset_line);
293 SB_DATA (so, cso->offset_tri);
294
295 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
296 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
297 SB_DATA (so, fui(cso->offset_scale));
298 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
299 SB_DATA (so, fui(cso->offset_units * 2.0f));
300 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
301 SB_DATA (so, fui(cso->offset_clamp));
302 }
303
304 if (cso->depth_clip)
305 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
306 else
307 reg =
308 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
309 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
310 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
311 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
312
313 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
314 SB_DATA (so, reg);
315
316 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
317 return (void *)so;
318 }
319
320 static void
321 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
322 {
323 struct nvc0_context *nvc0 = nvc0_context(pipe);
324
325 nvc0->rast = hwcso;
326 nvc0->dirty |= NVC0_NEW_RASTERIZER;
327 }
328
329 static void
330 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
331 {
332 FREE(hwcso);
333 }
334
335 static void *
336 nvc0_zsa_state_create(struct pipe_context *pipe,
337 const struct pipe_depth_stencil_alpha_state *cso)
338 {
339 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
340
341 so->pipe = *cso;
342
343 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
344 if (cso->depth.enabled) {
345 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
346 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
347 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
348 }
349
350 if (cso->stencil[0].enabled) {
351 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
352 SB_DATA (so, 1);
353 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
354 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
355 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
356 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
357 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
358 SB_DATA (so, cso->stencil[0].valuemask);
359 SB_DATA (so, cso->stencil[0].writemask);
360 } else {
361 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
362 }
363
364 if (cso->stencil[1].enabled) {
365 assert(cso->stencil[0].enabled);
366 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
367 SB_DATA (so, 1);
368 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
369 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
370 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
371 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
372 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
373 SB_DATA (so, cso->stencil[1].writemask);
374 SB_DATA (so, cso->stencil[1].valuemask);
375 } else
376 if (cso->stencil[0].enabled) {
377 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
378 }
379
380 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
381 if (cso->alpha.enabled) {
382 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
383 SB_DATA (so, fui(cso->alpha.ref_value));
384 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
385 }
386
387 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
388 return (void *)so;
389 }
390
391 static void
392 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
393 {
394 struct nvc0_context *nvc0 = nvc0_context(pipe);
395
396 nvc0->zsa = hwcso;
397 nvc0->dirty |= NVC0_NEW_ZSA;
398 }
399
400 static void
401 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
402 {
403 FREE(hwcso);
404 }
405
406 /* ====================== SAMPLERS AND TEXTURES ================================
407 */
408
409 #define NV50_TSC_WRAP_CASE(n) \
410 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
411
412 static INLINE unsigned
413 nv50_tsc_wrap_mode(unsigned wrap)
414 {
415 switch (wrap) {
416 NV50_TSC_WRAP_CASE(REPEAT);
417 NV50_TSC_WRAP_CASE(MIRROR_REPEAT);
418 NV50_TSC_WRAP_CASE(CLAMP_TO_EDGE);
419 NV50_TSC_WRAP_CASE(CLAMP_TO_BORDER);
420 NV50_TSC_WRAP_CASE(CLAMP);
421 NV50_TSC_WRAP_CASE(MIRROR_CLAMP_TO_EDGE);
422 NV50_TSC_WRAP_CASE(MIRROR_CLAMP_TO_BORDER);
423 NV50_TSC_WRAP_CASE(MIRROR_CLAMP);
424 default:
425 NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
426 return NV50_TSC_WRAP_REPEAT;
427 }
428 }
429
430 static void
431 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
432 {
433 unsigned s, i;
434
435 for (s = 0; s < 5; ++s)
436 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
437 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
438 nvc0_context(pipe)->samplers[s][i] = NULL;
439
440 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
441
442 FREE(hwcso);
443 }
444
445 static INLINE void
446 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0, int s,
447 unsigned nr, void **hwcso)
448 {
449 unsigned i;
450
451 for (i = 0; i < nr; ++i) {
452 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
453
454 if (hwcso[i] == old)
455 continue;
456 nvc0->samplers_dirty[s] |= 1 << i;
457
458 nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
459 if (old)
460 nvc0_screen_tsc_unlock(nvc0->screen, old);
461 }
462 for (; i < nvc0->num_samplers[s]; ++i) {
463 if (nvc0->samplers[s][i]) {
464 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
465 nvc0->samplers[s][i] = NULL;
466 }
467 }
468
469 nvc0->num_samplers[s] = nr;
470
471 nvc0->dirty |= NVC0_NEW_SAMPLERS;
472 }
473
474 static void
475 nvc0_stage_sampler_states_bind_range(struct nvc0_context *nvc0,
476 const unsigned s,
477 unsigned start, unsigned nr, void **cso)
478 {
479 const unsigned end = start + nr;
480 int last_valid = -1;
481 unsigned i;
482
483 if (cso) {
484 for (i = start; i < end; ++i) {
485 const unsigned p = i - start;
486 if (cso[p])
487 last_valid = i;
488 if (cso[p] == nvc0->samplers[s][i])
489 continue;
490 nvc0->samplers_dirty[s] |= 1 << i;
491
492 if (nvc0->samplers[s][i])
493 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
494 nvc0->samplers[s][i] = cso[p];
495 }
496 } else {
497 for (i = start; i < end; ++i) {
498 if (nvc0->samplers[s][i]) {
499 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
500 nvc0->samplers[s][i] = NULL;
501 nvc0->samplers_dirty[s] |= 1 << i;
502 }
503 }
504 }
505
506 if (nvc0->num_samplers[s] <= end) {
507 if (last_valid < 0) {
508 for (i = start; i && !nvc0->samplers[s][i - 1]; --i);
509 nvc0->num_samplers[s] = i;
510 } else {
511 nvc0->num_samplers[s] = last_valid + 1;
512 }
513 }
514 }
515
516 static void
517 nvc0_bind_sampler_states(struct pipe_context *pipe, unsigned shader,
518 unsigned start, unsigned nr, void **s)
519 {
520 switch (shader) {
521 case PIPE_SHADER_VERTEX:
522 assert(start == 0);
523 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 0, nr, s);
524 break;
525 case PIPE_SHADER_GEOMETRY:
526 assert(start == 0);
527 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 3, nr, s);
528 break;
529 case PIPE_SHADER_FRAGMENT:
530 assert(start == 0);
531 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 4, nr, s);
532 break;
533 case PIPE_SHADER_COMPUTE:
534 nvc0_stage_sampler_states_bind_range(nvc0_context(pipe), 5,
535 start, nr, s);
536 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
537 break;
538 }
539 }
540
541
542 /* NOTE: only called when not referenced anywhere, won't be bound */
543 static void
544 nvc0_sampler_view_destroy(struct pipe_context *pipe,
545 struct pipe_sampler_view *view)
546 {
547 pipe_resource_reference(&view->texture, NULL);
548
549 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
550
551 FREE(nv50_tic_entry(view));
552 }
553
554 static INLINE void
555 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
556 unsigned nr,
557 struct pipe_sampler_view **views)
558 {
559 unsigned i;
560
561 for (i = 0; i < nr; ++i) {
562 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
563
564 if (views[i] == nvc0->textures[s][i])
565 continue;
566 nvc0->textures_dirty[s] |= 1 << i;
567
568 if (old) {
569 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(s, i));
570 nvc0_screen_tic_unlock(nvc0->screen, old);
571 }
572
573 pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
574 }
575
576 for (i = nr; i < nvc0->num_textures[s]; ++i) {
577 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
578 if (old) {
579 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(s, i));
580 nvc0_screen_tic_unlock(nvc0->screen, old);
581 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
582 }
583 }
584
585 nvc0->num_textures[s] = nr;
586
587 nvc0->dirty |= NVC0_NEW_TEXTURES;
588 }
589
590 static void
591 nvc0_stage_set_sampler_views_range(struct nvc0_context *nvc0, const unsigned s,
592 unsigned start, unsigned nr,
593 struct pipe_sampler_view **views)
594 {
595 struct nouveau_bufctx *bctx = (s == 5) ? nvc0->bufctx_cp : nvc0->bufctx_3d;
596 const unsigned end = start + nr;
597 const unsigned bin = (s == 5) ? NVC0_BIND_CP_TEX(0) : NVC0_BIND_TEX(s, 0);
598 int last_valid = -1;
599 unsigned i;
600
601 if (views) {
602 for (i = start; i < end; ++i) {
603 const unsigned p = i - start;
604 if (views[p])
605 last_valid = i;
606 if (views[p] == nvc0->textures[s][i])
607 continue;
608 nvc0->textures_dirty[s] |= 1 << i;
609
610 if (nvc0->textures[s][i]) {
611 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
612 nouveau_bufctx_reset(bctx, bin + i);
613 nvc0_screen_tic_unlock(nvc0->screen, old);
614 }
615 pipe_sampler_view_reference(&nvc0->textures[s][i], views[p]);
616 }
617 } else {
618 for (i = start; i < end; ++i) {
619 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
620 if (!old)
621 continue;
622 nvc0->textures_dirty[s] |= 1 << i;
623
624 nvc0_screen_tic_unlock(nvc0->screen, old);
625 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
626 nouveau_bufctx_reset(bctx, bin + i);
627 }
628 }
629
630 if (nvc0->num_textures[s] <= end) {
631 if (last_valid < 0) {
632 for (i = start; i && !nvc0->textures[s][i - 1]; --i);
633 nvc0->num_textures[s] = i;
634 } else {
635 nvc0->num_textures[s] = last_valid + 1;
636 }
637 }
638 }
639
640 static void
641 nvc0_set_sampler_views(struct pipe_context *pipe, unsigned shader,
642 unsigned start, unsigned nr,
643 struct pipe_sampler_view **views)
644 {
645 assert(start == 0);
646 switch (shader) {
647 case PIPE_SHADER_VERTEX:
648 nvc0_stage_set_sampler_views(nvc0_context(pipe), 0, nr, views);
649 break;
650 case PIPE_SHADER_GEOMETRY:
651 nvc0_stage_set_sampler_views(nvc0_context(pipe), 3, nr, views);
652 break;
653 case PIPE_SHADER_FRAGMENT:
654 nvc0_stage_set_sampler_views(nvc0_context(pipe), 4, nr, views);
655 break;
656 case PIPE_SHADER_COMPUTE:
657 nvc0_stage_set_sampler_views_range(nvc0_context(pipe), 5,
658 start, nr, views);
659 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
660 break;
661 default:
662 ;
663 }
664 }
665
666
667 /* ============================= SHADERS =======================================
668 */
669
670 static void *
671 nvc0_sp_state_create(struct pipe_context *pipe,
672 const struct pipe_shader_state *cso, unsigned type)
673 {
674 struct nvc0_program *prog;
675
676 prog = CALLOC_STRUCT(nvc0_program);
677 if (!prog)
678 return NULL;
679
680 prog->type = type;
681
682 if (cso->tokens)
683 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
684
685 if (cso->stream_output.num_outputs)
686 prog->pipe.stream_output = cso->stream_output;
687
688 return (void *)prog;
689 }
690
691 static void
692 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
693 {
694 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
695
696 nvc0_program_destroy(nvc0_context(pipe), prog);
697
698 FREE((void *)prog->pipe.tokens);
699 FREE(prog);
700 }
701
702 static void *
703 nvc0_vp_state_create(struct pipe_context *pipe,
704 const struct pipe_shader_state *cso)
705 {
706 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
707 }
708
709 static void
710 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
711 {
712 struct nvc0_context *nvc0 = nvc0_context(pipe);
713
714 nvc0->vertprog = hwcso;
715 nvc0->dirty |= NVC0_NEW_VERTPROG;
716 }
717
718 static void *
719 nvc0_fp_state_create(struct pipe_context *pipe,
720 const struct pipe_shader_state *cso)
721 {
722 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
723 }
724
725 static void
726 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
727 {
728 struct nvc0_context *nvc0 = nvc0_context(pipe);
729
730 nvc0->fragprog = hwcso;
731 nvc0->dirty |= NVC0_NEW_FRAGPROG;
732 }
733
734 static void *
735 nvc0_gp_state_create(struct pipe_context *pipe,
736 const struct pipe_shader_state *cso)
737 {
738 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
739 }
740
741 static void
742 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
743 {
744 struct nvc0_context *nvc0 = nvc0_context(pipe);
745
746 nvc0->gmtyprog = hwcso;
747 nvc0->dirty |= NVC0_NEW_GMTYPROG;
748 }
749
750 static void *
751 nvc0_cp_state_create(struct pipe_context *pipe,
752 const struct pipe_compute_state *cso)
753 {
754 struct nvc0_program *prog;
755
756 prog = CALLOC_STRUCT(nvc0_program);
757 if (!prog)
758 return NULL;
759 prog->type = PIPE_SHADER_COMPUTE;
760
761 prog->cp.smem_size = cso->req_local_mem;
762 prog->cp.lmem_size = cso->req_private_mem;
763 prog->parm_size = cso->req_input_mem;
764
765 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
766
767 return (void *)prog;
768 }
769
770 static void
771 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
772 {
773 struct nvc0_context *nvc0 = nvc0_context(pipe);
774
775 nvc0->compprog = hwcso;
776 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
777 }
778
779 static void
780 nvc0_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
781 struct pipe_constant_buffer *cb)
782 {
783 struct nvc0_context *nvc0 = nvc0_context(pipe);
784 struct pipe_resource *res = cb ? cb->buffer : NULL;
785 const unsigned s = nvc0_shader_stage(shader);
786 const unsigned i = index;
787
788 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
789 assert(!cb || !cb->user_buffer);
790 if (nvc0->constbuf[s][i].u.buf)
791 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
792
793 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
794 } else {
795 if (nvc0->constbuf[s][i].user)
796 nvc0->constbuf[s][i].u.buf = NULL;
797 else
798 if (nvc0->constbuf[s][i].u.buf)
799 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_CB(s, i));
800
801 nvc0->dirty |= NVC0_NEW_CONSTBUF;
802 }
803 nvc0->constbuf_dirty[s] |= 1 << i;
804
805 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
806
807 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? TRUE : FALSE;
808 if (nvc0->constbuf[s][i].user) {
809 nvc0->constbuf[s][i].u.data = cb->user_buffer;
810 nvc0->constbuf[s][i].size = cb->buffer_size;
811 nvc0->constbuf_valid[s] |= 1 << i;
812 } else
813 if (cb) {
814 nvc0->constbuf[s][i].offset = cb->buffer_offset;
815 nvc0->constbuf[s][i].size = align(cb->buffer_size, 0x100);
816 nvc0->constbuf_valid[s] |= 1 << i;
817 }
818 else {
819 nvc0->constbuf_valid[s] &= ~(1 << i);
820 }
821 }
822
823 /* =============================================================================
824 */
825
826 static void
827 nvc0_set_blend_color(struct pipe_context *pipe,
828 const struct pipe_blend_color *bcol)
829 {
830 struct nvc0_context *nvc0 = nvc0_context(pipe);
831
832 nvc0->blend_colour = *bcol;
833 nvc0->dirty |= NVC0_NEW_BLEND_COLOUR;
834 }
835
836 static void
837 nvc0_set_stencil_ref(struct pipe_context *pipe,
838 const struct pipe_stencil_ref *sr)
839 {
840 struct nvc0_context *nvc0 = nvc0_context(pipe);
841
842 nvc0->stencil_ref = *sr;
843 nvc0->dirty |= NVC0_NEW_STENCIL_REF;
844 }
845
846 static void
847 nvc0_set_clip_state(struct pipe_context *pipe,
848 const struct pipe_clip_state *clip)
849 {
850 struct nvc0_context *nvc0 = nvc0_context(pipe);
851
852 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
853
854 nvc0->dirty |= NVC0_NEW_CLIP;
855 }
856
857 static void
858 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
859 {
860 struct nvc0_context *nvc0 = nvc0_context(pipe);
861
862 nvc0->sample_mask = sample_mask;
863 nvc0->dirty |= NVC0_NEW_SAMPLE_MASK;
864 }
865
866 static void
867 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
868 {
869 struct nvc0_context *nvc0 = nvc0_context(pipe);
870
871 if (nvc0->min_samples != min_samples) {
872 nvc0->min_samples = min_samples;
873 nvc0->dirty |= NVC0_NEW_MIN_SAMPLES;
874 }
875 }
876
877 static void
878 nvc0_set_framebuffer_state(struct pipe_context *pipe,
879 const struct pipe_framebuffer_state *fb)
880 {
881 struct nvc0_context *nvc0 = nvc0_context(pipe);
882 unsigned i;
883
884 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
885
886 for (i = 0; i < fb->nr_cbufs; ++i)
887 pipe_surface_reference(&nvc0->framebuffer.cbufs[i], fb->cbufs[i]);
888 for (; i < nvc0->framebuffer.nr_cbufs; ++i)
889 pipe_surface_reference(&nvc0->framebuffer.cbufs[i], NULL);
890
891 nvc0->framebuffer.nr_cbufs = fb->nr_cbufs;
892
893 nvc0->framebuffer.width = fb->width;
894 nvc0->framebuffer.height = fb->height;
895
896 pipe_surface_reference(&nvc0->framebuffer.zsbuf, fb->zsbuf);
897
898 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
899 }
900
901 static void
902 nvc0_set_polygon_stipple(struct pipe_context *pipe,
903 const struct pipe_poly_stipple *stipple)
904 {
905 struct nvc0_context *nvc0 = nvc0_context(pipe);
906
907 nvc0->stipple = *stipple;
908 nvc0->dirty |= NVC0_NEW_STIPPLE;
909 }
910
911 static void
912 nvc0_set_scissor_states(struct pipe_context *pipe,
913 unsigned start_slot,
914 unsigned num_scissors,
915 const struct pipe_scissor_state *scissor)
916 {
917 struct nvc0_context *nvc0 = nvc0_context(pipe);
918 int i;
919
920 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
921 for (i = 0; i < num_scissors; i++) {
922 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
923 continue;
924 nvc0->scissors[start_slot + i] = scissor[i];
925 nvc0->scissors_dirty |= 1 << (start_slot + i);
926 nvc0->dirty |= NVC0_NEW_SCISSOR;
927 }
928 }
929
930 static void
931 nvc0_set_viewport_states(struct pipe_context *pipe,
932 unsigned start_slot,
933 unsigned num_viewports,
934 const struct pipe_viewport_state *vpt)
935 {
936 struct nvc0_context *nvc0 = nvc0_context(pipe);
937 int i;
938
939 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
940 for (i = 0; i < num_viewports; i++) {
941 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
942 continue;
943 nvc0->viewports[start_slot + i] = vpt[i];
944 nvc0->viewports_dirty |= 1 << (start_slot + i);
945 nvc0->dirty |= NVC0_NEW_VIEWPORT;
946 }
947
948 }
949
950 static void
951 nvc0_set_vertex_buffers(struct pipe_context *pipe,
952 unsigned start_slot, unsigned count,
953 const struct pipe_vertex_buffer *vb)
954 {
955 struct nvc0_context *nvc0 = nvc0_context(pipe);
956 unsigned i;
957
958 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
959 start_slot, count);
960
961 if (!vb) {
962 nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
963 nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
964 return;
965 }
966
967 for (i = 0; i < count; ++i) {
968 unsigned dst_index = start_slot + i;
969
970 if (vb[i].user_buffer) {
971 nvc0->vbo_user |= 1 << dst_index;
972 if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
973 nvc0->constant_vbos |= 1 << dst_index;
974 else
975 nvc0->constant_vbos &= ~(1 << dst_index);
976 } else {
977 nvc0->vbo_user &= ~(1 << dst_index);
978 nvc0->constant_vbos &= ~(1 << dst_index);
979 }
980 }
981
982 nvc0->dirty |= NVC0_NEW_ARRAYS;
983 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX);
984 }
985
986 static void
987 nvc0_set_index_buffer(struct pipe_context *pipe,
988 const struct pipe_index_buffer *ib)
989 {
990 struct nvc0_context *nvc0 = nvc0_context(pipe);
991
992 if (nvc0->idxbuf.buffer)
993 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_IDX);
994
995 if (ib) {
996 pipe_resource_reference(&nvc0->idxbuf.buffer, ib->buffer);
997 nvc0->idxbuf.index_size = ib->index_size;
998 if (ib->buffer) {
999 nvc0->idxbuf.offset = ib->offset;
1000 nvc0->dirty |= NVC0_NEW_IDXBUF;
1001 } else {
1002 nvc0->idxbuf.user_buffer = ib->user_buffer;
1003 nvc0->dirty &= ~NVC0_NEW_IDXBUF;
1004 }
1005 } else {
1006 nvc0->dirty &= ~NVC0_NEW_IDXBUF;
1007 pipe_resource_reference(&nvc0->idxbuf.buffer, NULL);
1008 }
1009 }
1010
1011 static void
1012 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1013 {
1014 struct nvc0_context *nvc0 = nvc0_context(pipe);
1015
1016 nvc0->vertex = hwcso;
1017 nvc0->dirty |= NVC0_NEW_VERTEX;
1018 }
1019
1020 static struct pipe_stream_output_target *
1021 nvc0_so_target_create(struct pipe_context *pipe,
1022 struct pipe_resource *res,
1023 unsigned offset, unsigned size)
1024 {
1025 struct nv04_resource *buf = (struct nv04_resource *)res;
1026 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1027 if (!targ)
1028 return NULL;
1029
1030 targ->pq = pipe->create_query(pipe, NVC0_QUERY_TFB_BUFFER_OFFSET, 0);
1031 if (!targ->pq) {
1032 FREE(targ);
1033 return NULL;
1034 }
1035 targ->clean = TRUE;
1036
1037 targ->pipe.buffer_size = size;
1038 targ->pipe.buffer_offset = offset;
1039 targ->pipe.context = pipe;
1040 targ->pipe.buffer = NULL;
1041 pipe_resource_reference(&targ->pipe.buffer, res);
1042 pipe_reference_init(&targ->pipe.reference, 1);
1043
1044 assert(buf->base.target == PIPE_BUFFER);
1045 util_range_add(&buf->valid_buffer_range, offset, offset + size);
1046
1047 return &targ->pipe;
1048 }
1049
1050 static void
1051 nvc0_so_target_destroy(struct pipe_context *pipe,
1052 struct pipe_stream_output_target *ptarg)
1053 {
1054 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1055 pipe->destroy_query(pipe, targ->pq);
1056 pipe_resource_reference(&targ->pipe.buffer, NULL);
1057 FREE(targ);
1058 }
1059
1060 static void
1061 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1062 unsigned num_targets,
1063 struct pipe_stream_output_target **targets,
1064 const unsigned *offsets)
1065 {
1066 struct nvc0_context *nvc0 = nvc0_context(pipe);
1067 unsigned i;
1068 boolean serialize = TRUE;
1069
1070 assert(num_targets <= 4);
1071
1072 for (i = 0; i < num_targets; ++i) {
1073 const boolean changed = nvc0->tfbbuf[i] != targets[i];
1074 const boolean append = (offsets[i] == ((unsigned)-1));
1075 if (!changed && append)
1076 continue;
1077 nvc0->tfbbuf_dirty |= 1 << i;
1078
1079 if (nvc0->tfbbuf[i] && changed)
1080 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1081
1082 if (targets[i] && !append)
1083 nvc0_so_target(targets[i])->clean = TRUE;
1084
1085 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1086 }
1087 for (; i < nvc0->num_tfbbufs; ++i) {
1088 nvc0->tfbbuf_dirty |= 1 << i;
1089 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1090 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1091 }
1092 nvc0->num_tfbbufs = num_targets;
1093
1094 if (nvc0->tfbbuf_dirty)
1095 nvc0->dirty |= NVC0_NEW_TFB_TARGETS;
1096 }
1097
1098 static void
1099 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1100 unsigned start, unsigned nr,
1101 struct pipe_surface **psurfaces)
1102 {
1103 const unsigned end = start + nr;
1104 const unsigned mask = ((1 << nr) - 1) << start;
1105 unsigned i;
1106
1107 if (psurfaces) {
1108 for (i = start; i < end; ++i) {
1109 const unsigned p = i - start;
1110 if (psurfaces[p])
1111 nvc0->surfaces_valid[t] |= (1 << i);
1112 else
1113 nvc0->surfaces_valid[t] &= ~(1 << i);
1114 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1115 }
1116 } else {
1117 for (i = start; i < end; ++i)
1118 pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1119 nvc0->surfaces_valid[t] &= ~mask;
1120 }
1121 nvc0->surfaces_dirty[t] |= mask;
1122
1123 if (t == 0)
1124 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_SUF);
1125 else
1126 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1127 }
1128
1129 static void
1130 nvc0_set_compute_resources(struct pipe_context *pipe,
1131 unsigned start, unsigned nr,
1132 struct pipe_surface **resources)
1133 {
1134 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1135
1136 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1137 }
1138
1139 static void
1140 nvc0_set_shader_resources(struct pipe_context *pipe,
1141 unsigned start, unsigned nr,
1142 struct pipe_surface **resources)
1143 {
1144 nvc0_bind_surfaces_range(nvc0_context(pipe), 0, start, nr, resources);
1145
1146 nvc0_context(pipe)->dirty |= NVC0_NEW_SURFACES;
1147 }
1148
1149 static INLINE void
1150 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1151 {
1152 struct nv04_resource *buf = nv04_resource(res);
1153 if (buf) {
1154 uint64_t limit = (buf->address + buf->base.width0) - 1;
1155 if (limit < (1ULL << 32)) {
1156 *phandle = (uint32_t)buf->address;
1157 } else {
1158 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1159 "resource not contained within 32-bit address space !\n");
1160 *phandle = 0;
1161 }
1162 } else {
1163 *phandle = 0;
1164 }
1165 }
1166
1167 static void
1168 nvc0_set_global_bindings(struct pipe_context *pipe,
1169 unsigned start, unsigned nr,
1170 struct pipe_resource **resources,
1171 uint32_t **handles)
1172 {
1173 struct nvc0_context *nvc0 = nvc0_context(pipe);
1174 struct pipe_resource **ptr;
1175 unsigned i;
1176 const unsigned end = start + nr;
1177
1178 if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1179 const unsigned old_size = nvc0->global_residents.size;
1180 const unsigned req_size = end * sizeof(struct pipe_resource *);
1181 util_dynarray_resize(&nvc0->global_residents, req_size);
1182 memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1183 req_size - old_size);
1184 }
1185
1186 if (resources) {
1187 ptr = util_dynarray_element(
1188 &nvc0->global_residents, struct pipe_resource *, start);
1189 for (i = 0; i < nr; ++i) {
1190 pipe_resource_reference(&ptr[i], resources[i]);
1191 nvc0_set_global_handle(handles[i], resources[i]);
1192 }
1193 } else {
1194 ptr = util_dynarray_element(
1195 &nvc0->global_residents, struct pipe_resource *, start);
1196 for (i = 0; i < nr; ++i)
1197 pipe_resource_reference(&ptr[i], NULL);
1198 }
1199
1200 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1201
1202 nvc0->dirty_cp = NVC0_NEW_CP_GLOBALS;
1203 }
1204
1205 void
1206 nvc0_init_state_functions(struct nvc0_context *nvc0)
1207 {
1208 struct pipe_context *pipe = &nvc0->base.pipe;
1209
1210 pipe->create_blend_state = nvc0_blend_state_create;
1211 pipe->bind_blend_state = nvc0_blend_state_bind;
1212 pipe->delete_blend_state = nvc0_blend_state_delete;
1213
1214 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1215 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1216 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1217
1218 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1219 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1220 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1221
1222 pipe->create_sampler_state = nv50_sampler_state_create;
1223 pipe->delete_sampler_state = nvc0_sampler_state_delete;
1224 pipe->bind_sampler_states = nvc0_bind_sampler_states;
1225
1226 pipe->create_sampler_view = nvc0_create_sampler_view;
1227 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1228 pipe->set_sampler_views = nvc0_set_sampler_views;
1229
1230 pipe->create_vs_state = nvc0_vp_state_create;
1231 pipe->create_fs_state = nvc0_fp_state_create;
1232 pipe->create_gs_state = nvc0_gp_state_create;
1233 pipe->bind_vs_state = nvc0_vp_state_bind;
1234 pipe->bind_fs_state = nvc0_fp_state_bind;
1235 pipe->bind_gs_state = nvc0_gp_state_bind;
1236 pipe->delete_vs_state = nvc0_sp_state_delete;
1237 pipe->delete_fs_state = nvc0_sp_state_delete;
1238 pipe->delete_gs_state = nvc0_sp_state_delete;
1239
1240 pipe->create_compute_state = nvc0_cp_state_create;
1241 pipe->bind_compute_state = nvc0_cp_state_bind;
1242 pipe->delete_compute_state = nvc0_sp_state_delete;
1243
1244 pipe->set_blend_color = nvc0_set_blend_color;
1245 pipe->set_stencil_ref = nvc0_set_stencil_ref;
1246 pipe->set_clip_state = nvc0_set_clip_state;
1247 pipe->set_sample_mask = nvc0_set_sample_mask;
1248 pipe->set_min_samples = nvc0_set_min_samples;
1249 pipe->set_constant_buffer = nvc0_set_constant_buffer;
1250 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1251 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1252 pipe->set_scissor_states = nvc0_set_scissor_states;
1253 pipe->set_viewport_states = nvc0_set_viewport_states;
1254
1255 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1256 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1257 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1258
1259 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1260 pipe->set_index_buffer = nvc0_set_index_buffer;
1261
1262 pipe->create_stream_output_target = nvc0_so_target_create;
1263 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1264 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1265
1266 pipe->set_global_binding = nvc0_set_global_bindings;
1267 pipe->set_compute_resources = nvc0_set_compute_resources;
1268 pipe->set_shader_resources = nvc0_set_shader_resources;
1269
1270 nvc0->sample_mask = ~0;
1271 nvc0->min_samples = 1;
1272 }