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nvc0: fix line width on GM20x+
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_framebuffer.h"
25 #include "util/u_helpers.h"
26 #include "util/u_inlines.h"
27 #include "util/u_transfer.h"
28
29 #include "tgsi/tgsi_parse.h"
30
31 #include "nvc0/nvc0_stateobj.h"
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_query_hw.h"
34
35 #include "nvc0/nvc0_3d.xml.h"
36
37 #include "nouveau_gldefs.h"
38
39 static inline uint32_t
40 nvc0_colormask(unsigned mask)
41 {
42 uint32_t ret = 0;
43
44 if (mask & PIPE_MASK_R)
45 ret |= 0x0001;
46 if (mask & PIPE_MASK_G)
47 ret |= 0x0010;
48 if (mask & PIPE_MASK_B)
49 ret |= 0x0100;
50 if (mask & PIPE_MASK_A)
51 ret |= 0x1000;
52
53 return ret;
54 }
55
56 #define NVC0_BLEND_FACTOR_CASE(a, b) \
57 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
58
59 static inline uint32_t
60 nvc0_blend_fac(unsigned factor)
61 {
62 switch (factor) {
63 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
64 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
65 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
66 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
67 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
68 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
69 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
70 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
71 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
72 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
73 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
74 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
75 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
76 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
77 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
78 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
79 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
80 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
81 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
82 default:
83 return NV50_BLEND_FACTOR_ZERO;
84 }
85 }
86
87 static void *
88 nvc0_blend_state_create(struct pipe_context *pipe,
89 const struct pipe_blend_state *cso)
90 {
91 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
92 int i;
93 int r; /* reference */
94 uint32_t ms;
95 uint8_t blend_en = 0;
96 bool indep_masks = false;
97 bool indep_funcs = false;
98
99 so->pipe = *cso;
100
101 /* check which states actually have differing values */
102 if (cso->independent_blend_enable) {
103 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
104 blend_en |= 1 << r;
105 for (i = r + 1; i < 8; ++i) {
106 if (!cso->rt[i].blend_enable)
107 continue;
108 blend_en |= 1 << i;
109 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
110 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
111 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
112 cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
113 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
114 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
115 indep_funcs = true;
116 break;
117 }
118 }
119 for (; i < 8; ++i)
120 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
121
122 for (i = 1; i < 8; ++i) {
123 if (cso->rt[i].colormask != cso->rt[0].colormask) {
124 indep_masks = true;
125 break;
126 }
127 }
128 } else {
129 r = 0;
130 if (cso->rt[0].blend_enable)
131 blend_en = 0xff;
132 }
133
134 if (cso->logicop_enable) {
135 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
136 SB_DATA (so, 1);
137 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
138
139 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
140 } else {
141 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
142
143 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
144 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
145 if (indep_funcs) {
146 for (i = 0; i < 8; ++i) {
147 if (cso->rt[i].blend_enable) {
148 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
149 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
150 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
151 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
152 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
153 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
154 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
155 }
156 }
157 } else
158 if (blend_en) {
159 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
160 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
161 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
162 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
163 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
164 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
165 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
166 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
167 }
168
169 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
170 if (indep_masks) {
171 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
172 for (i = 0; i < 8; ++i)
173 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
174 } else {
175 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
176 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
177 }
178 }
179
180 ms = 0;
181 if (cso->alpha_to_coverage)
182 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
183 if (cso->alpha_to_one)
184 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
185
186 SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
187 SB_DATA (so, ms);
188
189 assert(so->size <= ARRAY_SIZE(so->state));
190 return so;
191 }
192
193 static void
194 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
195 {
196 struct nvc0_context *nvc0 = nvc0_context(pipe);
197
198 nvc0->blend = hwcso;
199 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND;
200 }
201
202 static void
203 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
204 {
205 FREE(hwcso);
206 }
207
208 /* NOTE: ignoring line_last_pixel */
209 static void *
210 nvc0_rasterizer_state_create(struct pipe_context *pipe,
211 const struct pipe_rasterizer_state *cso)
212 {
213 struct nvc0_rasterizer_stateobj *so;
214 uint16_t class_3d = nouveau_screen(pipe->screen)->class_3d;
215 uint32_t reg;
216
217 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
218 if (!so)
219 return NULL;
220 so->pipe = *cso;
221
222 /* Scissor enables are handled in scissor state, we will not want to
223 * always emit 16 commands, one for each scissor rectangle, here.
224 */
225
226 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
227 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
228
229 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
230 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
231 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
232
233 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
234
235 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
236 /* On GM20x+, LINE_WIDTH_SMOOTH controls both aliased and smooth
237 * rendering and LINE_WIDTH_ALIASED seems to be ignored
238 */
239 if (cso->line_smooth || cso->multisample || class_3d >= GM200_3D_CLASS)
240 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
241 else
242 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
243 SB_DATA (so, fui(cso->line_width));
244
245 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
246 if (cso->line_stipple_enable) {
247 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
248 SB_DATA (so, (cso->line_stipple_pattern << 8) |
249 cso->line_stipple_factor);
250
251 }
252
253 SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
254 if (!cso->point_size_per_vertex) {
255 SB_BEGIN_3D(so, POINT_SIZE, 1);
256 SB_DATA (so, fui(cso->point_size));
257 }
258
259 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
260 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
261 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
262
263 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
264 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
265 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
266 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
267
268 if (class_3d >= GM200_3D_CLASS) {
269 SB_IMMED_3D(so, FILL_RECTANGLE,
270 cso->fill_front == PIPE_POLYGON_MODE_FILL_RECTANGLE ?
271 NVC0_3D_FILL_RECTANGLE_ENABLE : 0);
272 }
273
274 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
275 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
276 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
277 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
278 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
279
280 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
281 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
282 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
283 NVC0_3D_FRONT_FACE_CW);
284 switch (cso->cull_face) {
285 case PIPE_FACE_FRONT_AND_BACK:
286 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
287 break;
288 case PIPE_FACE_FRONT:
289 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
290 break;
291 case PIPE_FACE_BACK:
292 default:
293 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
294 break;
295 }
296
297 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
298 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
299 SB_DATA (so, cso->offset_point);
300 SB_DATA (so, cso->offset_line);
301 SB_DATA (so, cso->offset_tri);
302
303 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
304 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
305 SB_DATA (so, fui(cso->offset_scale));
306 if (!cso->offset_units_unscaled) {
307 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
308 SB_DATA (so, fui(cso->offset_units * 2.0f));
309 }
310 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
311 SB_DATA (so, fui(cso->offset_clamp));
312 }
313
314 if (cso->depth_clip)
315 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
316 else
317 reg =
318 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
319 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
320 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
321 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
322
323 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
324 SB_DATA (so, reg);
325
326 SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
327
328 SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
329
330 assert(so->size <= ARRAY_SIZE(so->state));
331 return (void *)so;
332 }
333
334 static void
335 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
336 {
337 struct nvc0_context *nvc0 = nvc0_context(pipe);
338
339 nvc0->rast = hwcso;
340 nvc0->dirty_3d |= NVC0_NEW_3D_RASTERIZER;
341 }
342
343 static void
344 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
345 {
346 FREE(hwcso);
347 }
348
349 static void *
350 nvc0_zsa_state_create(struct pipe_context *pipe,
351 const struct pipe_depth_stencil_alpha_state *cso)
352 {
353 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
354
355 so->pipe = *cso;
356
357 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
358 if (cso->depth.enabled) {
359 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
360 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
361 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
362 }
363
364 SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth.bounds_test);
365 if (cso->depth.bounds_test) {
366 SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
367 SB_DATA (so, fui(cso->depth.bounds_min));
368 SB_DATA (so, fui(cso->depth.bounds_max));
369 }
370
371 if (cso->stencil[0].enabled) {
372 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
373 SB_DATA (so, 1);
374 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
375 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
376 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
377 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
378 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
379 SB_DATA (so, cso->stencil[0].valuemask);
380 SB_DATA (so, cso->stencil[0].writemask);
381 } else {
382 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
383 }
384
385 if (cso->stencil[1].enabled) {
386 assert(cso->stencil[0].enabled);
387 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
388 SB_DATA (so, 1);
389 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
390 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
391 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
392 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
393 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
394 SB_DATA (so, cso->stencil[1].writemask);
395 SB_DATA (so, cso->stencil[1].valuemask);
396 } else
397 if (cso->stencil[0].enabled) {
398 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
399 }
400
401 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
402 if (cso->alpha.enabled) {
403 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
404 SB_DATA (so, fui(cso->alpha.ref_value));
405 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
406 }
407
408 assert(so->size <= ARRAY_SIZE(so->state));
409 return (void *)so;
410 }
411
412 static void
413 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
414 {
415 struct nvc0_context *nvc0 = nvc0_context(pipe);
416
417 nvc0->zsa = hwcso;
418 nvc0->dirty_3d |= NVC0_NEW_3D_ZSA;
419 }
420
421 static void
422 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
423 {
424 FREE(hwcso);
425 }
426
427 /* ====================== SAMPLERS AND TEXTURES ================================
428 */
429
430 #define NV50_TSC_WRAP_CASE(n) \
431 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
432
433 static void
434 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
435 {
436 unsigned s, i;
437
438 for (s = 0; s < 6; ++s)
439 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
440 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
441 nvc0_context(pipe)->samplers[s][i] = NULL;
442
443 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
444
445 FREE(hwcso);
446 }
447
448 static inline void
449 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0,
450 unsigned s,
451 unsigned nr, void **hwcso)
452 {
453 unsigned i;
454
455 for (i = 0; i < nr; ++i) {
456 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
457
458 if (hwcso[i] == old)
459 continue;
460 nvc0->samplers_dirty[s] |= 1 << i;
461
462 nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
463 if (old)
464 nvc0_screen_tsc_unlock(nvc0->screen, old);
465 }
466 for (; i < nvc0->num_samplers[s]; ++i) {
467 if (nvc0->samplers[s][i]) {
468 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
469 nvc0->samplers[s][i] = NULL;
470 }
471 }
472
473 nvc0->num_samplers[s] = nr;
474 }
475
476 static void
477 nvc0_bind_sampler_states(struct pipe_context *pipe,
478 enum pipe_shader_type shader,
479 unsigned start, unsigned nr, void **samplers)
480 {
481 const unsigned s = nvc0_shader_stage(shader);
482
483 assert(start == 0);
484 nvc0_stage_sampler_states_bind(nvc0_context(pipe), s, nr, samplers);
485
486 if (s == 5)
487 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
488 else
489 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
490 }
491
492
493 /* NOTE: only called when not referenced anywhere, won't be bound */
494 static void
495 nvc0_sampler_view_destroy(struct pipe_context *pipe,
496 struct pipe_sampler_view *view)
497 {
498 pipe_resource_reference(&view->texture, NULL);
499
500 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
501
502 FREE(nv50_tic_entry(view));
503 }
504
505 static inline void
506 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
507 unsigned nr,
508 struct pipe_sampler_view **views)
509 {
510 unsigned i;
511
512 for (i = 0; i < nr; ++i) {
513 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
514
515 if (views[i] == nvc0->textures[s][i])
516 continue;
517 nvc0->textures_dirty[s] |= 1 << i;
518
519 if (views[i] && views[i]->texture) {
520 struct pipe_resource *res = views[i]->texture;
521 if (res->target == PIPE_BUFFER &&
522 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
523 nvc0->textures_coherent[s] |= 1 << i;
524 else
525 nvc0->textures_coherent[s] &= ~(1 << i);
526 } else {
527 nvc0->textures_coherent[s] &= ~(1 << i);
528 }
529
530 if (old) {
531 if (s == 5)
532 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
533 else
534 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
535 nvc0_screen_tic_unlock(nvc0->screen, old);
536 }
537
538 pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
539 }
540
541 for (i = nr; i < nvc0->num_textures[s]; ++i) {
542 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
543 if (old) {
544 if (s == 5)
545 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
546 else
547 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
548 nvc0_screen_tic_unlock(nvc0->screen, old);
549 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
550 }
551 }
552
553 nvc0->num_textures[s] = nr;
554 }
555
556 static void
557 nvc0_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,
558 unsigned start, unsigned nr,
559 struct pipe_sampler_view **views)
560 {
561 const unsigned s = nvc0_shader_stage(shader);
562
563 assert(start == 0);
564 nvc0_stage_set_sampler_views(nvc0_context(pipe), s, nr, views);
565
566 if (s == 5)
567 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
568 else
569 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_TEXTURES;
570 }
571
572 /* ============================= SHADERS =======================================
573 */
574
575 static void *
576 nvc0_sp_state_create(struct pipe_context *pipe,
577 const struct pipe_shader_state *cso, unsigned type)
578 {
579 struct nvc0_program *prog;
580
581 prog = CALLOC_STRUCT(nvc0_program);
582 if (!prog)
583 return NULL;
584
585 prog->type = type;
586
587 if (cso->tokens)
588 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
589
590 if (cso->stream_output.num_outputs)
591 prog->pipe.stream_output = cso->stream_output;
592
593 prog->translated = nvc0_program_translate(
594 prog, nvc0_context(pipe)->screen->base.device->chipset,
595 &nouveau_context(pipe)->debug);
596
597 return (void *)prog;
598 }
599
600 static void
601 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
602 {
603 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
604
605 nvc0_program_destroy(nvc0_context(pipe), prog);
606
607 FREE((void *)prog->pipe.tokens);
608 FREE(prog);
609 }
610
611 static void *
612 nvc0_vp_state_create(struct pipe_context *pipe,
613 const struct pipe_shader_state *cso)
614 {
615 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
616 }
617
618 static void
619 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
620 {
621 struct nvc0_context *nvc0 = nvc0_context(pipe);
622
623 nvc0->vertprog = hwcso;
624 nvc0->dirty_3d |= NVC0_NEW_3D_VERTPROG;
625 }
626
627 static void *
628 nvc0_fp_state_create(struct pipe_context *pipe,
629 const struct pipe_shader_state *cso)
630 {
631 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
632 }
633
634 static void
635 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
636 {
637 struct nvc0_context *nvc0 = nvc0_context(pipe);
638
639 nvc0->fragprog = hwcso;
640 nvc0->dirty_3d |= NVC0_NEW_3D_FRAGPROG;
641 }
642
643 static void *
644 nvc0_gp_state_create(struct pipe_context *pipe,
645 const struct pipe_shader_state *cso)
646 {
647 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
648 }
649
650 static void
651 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
652 {
653 struct nvc0_context *nvc0 = nvc0_context(pipe);
654
655 nvc0->gmtyprog = hwcso;
656 nvc0->dirty_3d |= NVC0_NEW_3D_GMTYPROG;
657 }
658
659 static void *
660 nvc0_tcp_state_create(struct pipe_context *pipe,
661 const struct pipe_shader_state *cso)
662 {
663 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
664 }
665
666 static void
667 nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
668 {
669 struct nvc0_context *nvc0 = nvc0_context(pipe);
670
671 nvc0->tctlprog = hwcso;
672 nvc0->dirty_3d |= NVC0_NEW_3D_TCTLPROG;
673 }
674
675 static void *
676 nvc0_tep_state_create(struct pipe_context *pipe,
677 const struct pipe_shader_state *cso)
678 {
679 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
680 }
681
682 static void
683 nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
684 {
685 struct nvc0_context *nvc0 = nvc0_context(pipe);
686
687 nvc0->tevlprog = hwcso;
688 nvc0->dirty_3d |= NVC0_NEW_3D_TEVLPROG;
689 }
690
691 static void *
692 nvc0_cp_state_create(struct pipe_context *pipe,
693 const struct pipe_compute_state *cso)
694 {
695 struct nvc0_program *prog;
696
697 prog = CALLOC_STRUCT(nvc0_program);
698 if (!prog)
699 return NULL;
700 prog->type = PIPE_SHADER_COMPUTE;
701
702 prog->cp.smem_size = cso->req_local_mem;
703 prog->cp.lmem_size = cso->req_private_mem;
704 prog->parm_size = cso->req_input_mem;
705
706 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
707
708 prog->translated = nvc0_program_translate(
709 prog, nvc0_context(pipe)->screen->base.device->chipset,
710 &nouveau_context(pipe)->debug);
711
712 return (void *)prog;
713 }
714
715 static void
716 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
717 {
718 struct nvc0_context *nvc0 = nvc0_context(pipe);
719
720 nvc0->compprog = hwcso;
721 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
722 }
723
724 static void
725 nvc0_set_constant_buffer(struct pipe_context *pipe,
726 enum pipe_shader_type shader, uint index,
727 const struct pipe_constant_buffer *cb)
728 {
729 struct nvc0_context *nvc0 = nvc0_context(pipe);
730 struct pipe_resource *res = cb ? cb->buffer : NULL;
731 const unsigned s = nvc0_shader_stage(shader);
732 const unsigned i = index;
733
734 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
735 if (nvc0->constbuf[s][i].user)
736 nvc0->constbuf[s][i].u.buf = NULL;
737 else
738 if (nvc0->constbuf[s][i].u.buf)
739 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
740
741 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
742 } else {
743 if (nvc0->constbuf[s][i].user)
744 nvc0->constbuf[s][i].u.buf = NULL;
745 else
746 if (nvc0->constbuf[s][i].u.buf)
747 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_CB(s, i));
748
749 nvc0->dirty_3d |= NVC0_NEW_3D_CONSTBUF;
750 }
751 nvc0->constbuf_dirty[s] |= 1 << i;
752
753 if (nvc0->constbuf[s][i].u.buf)
754 nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
755 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
756
757 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
758 if (nvc0->constbuf[s][i].user) {
759 nvc0->constbuf[s][i].u.data = cb->user_buffer;
760 nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
761 nvc0->constbuf_valid[s] |= 1 << i;
762 nvc0->constbuf_coherent[s] &= ~(1 << i);
763 } else
764 if (cb) {
765 nvc0->constbuf[s][i].offset = cb->buffer_offset;
766 nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
767 nvc0->constbuf_valid[s] |= 1 << i;
768 if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
769 nvc0->constbuf_coherent[s] |= 1 << i;
770 else
771 nvc0->constbuf_coherent[s] &= ~(1 << i);
772 }
773 else {
774 nvc0->constbuf_valid[s] &= ~(1 << i);
775 nvc0->constbuf_coherent[s] &= ~(1 << i);
776 }
777 }
778
779 /* =============================================================================
780 */
781
782 static void
783 nvc0_set_blend_color(struct pipe_context *pipe,
784 const struct pipe_blend_color *bcol)
785 {
786 struct nvc0_context *nvc0 = nvc0_context(pipe);
787
788 nvc0->blend_colour = *bcol;
789 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND_COLOUR;
790 }
791
792 static void
793 nvc0_set_stencil_ref(struct pipe_context *pipe,
794 const struct pipe_stencil_ref *sr)
795 {
796 struct nvc0_context *nvc0 = nvc0_context(pipe);
797
798 nvc0->stencil_ref = *sr;
799 nvc0->dirty_3d |= NVC0_NEW_3D_STENCIL_REF;
800 }
801
802 static void
803 nvc0_set_clip_state(struct pipe_context *pipe,
804 const struct pipe_clip_state *clip)
805 {
806 struct nvc0_context *nvc0 = nvc0_context(pipe);
807
808 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
809
810 nvc0->dirty_3d |= NVC0_NEW_3D_CLIP;
811 }
812
813 static void
814 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
815 {
816 struct nvc0_context *nvc0 = nvc0_context(pipe);
817
818 nvc0->sample_mask = sample_mask;
819 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_MASK;
820 }
821
822 static void
823 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
824 {
825 struct nvc0_context *nvc0 = nvc0_context(pipe);
826
827 if (nvc0->min_samples != min_samples) {
828 nvc0->min_samples = min_samples;
829 nvc0->dirty_3d |= NVC0_NEW_3D_MIN_SAMPLES;
830 }
831 }
832
833 static void
834 nvc0_set_framebuffer_state(struct pipe_context *pipe,
835 const struct pipe_framebuffer_state *fb)
836 {
837 struct nvc0_context *nvc0 = nvc0_context(pipe);
838
839 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
840
841 util_copy_framebuffer_state(&nvc0->framebuffer, fb);
842
843 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER;
844 }
845
846 static void
847 nvc0_set_polygon_stipple(struct pipe_context *pipe,
848 const struct pipe_poly_stipple *stipple)
849 {
850 struct nvc0_context *nvc0 = nvc0_context(pipe);
851
852 nvc0->stipple = *stipple;
853 nvc0->dirty_3d |= NVC0_NEW_3D_STIPPLE;
854 }
855
856 static void
857 nvc0_set_scissor_states(struct pipe_context *pipe,
858 unsigned start_slot,
859 unsigned num_scissors,
860 const struct pipe_scissor_state *scissor)
861 {
862 struct nvc0_context *nvc0 = nvc0_context(pipe);
863 int i;
864
865 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
866 for (i = 0; i < num_scissors; i++) {
867 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
868 continue;
869 nvc0->scissors[start_slot + i] = scissor[i];
870 nvc0->scissors_dirty |= 1 << (start_slot + i);
871 nvc0->dirty_3d |= NVC0_NEW_3D_SCISSOR;
872 }
873 }
874
875 static void
876 nvc0_set_viewport_states(struct pipe_context *pipe,
877 unsigned start_slot,
878 unsigned num_viewports,
879 const struct pipe_viewport_state *vpt)
880 {
881 struct nvc0_context *nvc0 = nvc0_context(pipe);
882 int i;
883
884 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
885 for (i = 0; i < num_viewports; i++) {
886 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
887 continue;
888 nvc0->viewports[start_slot + i] = vpt[i];
889 nvc0->viewports_dirty |= 1 << (start_slot + i);
890 nvc0->dirty_3d |= NVC0_NEW_3D_VIEWPORT;
891 }
892
893 }
894
895 static void
896 nvc0_set_window_rectangles(struct pipe_context *pipe,
897 boolean include,
898 unsigned num_rectangles,
899 const struct pipe_scissor_state *rectangles)
900 {
901 struct nvc0_context *nvc0 = nvc0_context(pipe);
902
903 nvc0->window_rect.inclusive = include;
904 nvc0->window_rect.rects = MIN2(num_rectangles, NVC0_MAX_WINDOW_RECTANGLES);
905 memcpy(nvc0->window_rect.rect, rectangles,
906 sizeof(struct pipe_scissor_state) * nvc0->window_rect.rects);
907
908 nvc0->dirty_3d |= NVC0_NEW_3D_WINDOW_RECTS;
909 }
910
911 static void
912 nvc0_set_tess_state(struct pipe_context *pipe,
913 const float default_tess_outer[4],
914 const float default_tess_inner[2])
915 {
916 struct nvc0_context *nvc0 = nvc0_context(pipe);
917
918 memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
919 memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
920 nvc0->dirty_3d |= NVC0_NEW_3D_TESSFACTOR;
921 }
922
923 static void
924 nvc0_set_vertex_buffers(struct pipe_context *pipe,
925 unsigned start_slot, unsigned count,
926 const struct pipe_vertex_buffer *vb)
927 {
928 struct nvc0_context *nvc0 = nvc0_context(pipe);
929 unsigned i;
930
931 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX);
932 nvc0->dirty_3d |= NVC0_NEW_3D_ARRAYS;
933
934 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
935 start_slot, count);
936
937 if (!vb) {
938 nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
939 nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
940 nvc0->vtxbufs_coherent &= ~(((1ull << count) - 1) << start_slot);
941 return;
942 }
943
944 for (i = 0; i < count; ++i) {
945 unsigned dst_index = start_slot + i;
946
947 if (vb[i].is_user_buffer) {
948 nvc0->vbo_user |= 1 << dst_index;
949 if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
950 nvc0->constant_vbos |= 1 << dst_index;
951 else
952 nvc0->constant_vbos &= ~(1 << dst_index);
953 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
954 } else {
955 nvc0->vbo_user &= ~(1 << dst_index);
956 nvc0->constant_vbos &= ~(1 << dst_index);
957
958 if (vb[i].buffer.resource &&
959 vb[i].buffer.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
960 nvc0->vtxbufs_coherent |= (1 << dst_index);
961 else
962 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
963 }
964 }
965 }
966
967 static void
968 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
969 {
970 struct nvc0_context *nvc0 = nvc0_context(pipe);
971
972 nvc0->vertex = hwcso;
973 nvc0->dirty_3d |= NVC0_NEW_3D_VERTEX;
974 }
975
976 static struct pipe_stream_output_target *
977 nvc0_so_target_create(struct pipe_context *pipe,
978 struct pipe_resource *res,
979 unsigned offset, unsigned size)
980 {
981 struct nv04_resource *buf = (struct nv04_resource *)res;
982 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
983 if (!targ)
984 return NULL;
985
986 targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0);
987 if (!targ->pq) {
988 FREE(targ);
989 return NULL;
990 }
991 targ->clean = true;
992
993 targ->pipe.buffer_size = size;
994 targ->pipe.buffer_offset = offset;
995 targ->pipe.context = pipe;
996 targ->pipe.buffer = NULL;
997 pipe_resource_reference(&targ->pipe.buffer, res);
998 pipe_reference_init(&targ->pipe.reference, 1);
999
1000 assert(buf->base.target == PIPE_BUFFER);
1001 util_range_add(&buf->valid_buffer_range, offset, offset + size);
1002
1003 return &targ->pipe;
1004 }
1005
1006 static void
1007 nvc0_so_target_save_offset(struct pipe_context *pipe,
1008 struct pipe_stream_output_target *ptarg,
1009 unsigned index, bool *serialize)
1010 {
1011 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1012
1013 if (*serialize) {
1014 *serialize = false;
1015 PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
1016 IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
1017
1018 NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
1019 }
1020
1021 nvc0_query(targ->pq)->index = index;
1022 pipe->end_query(pipe, targ->pq);
1023 }
1024
1025 static void
1026 nvc0_so_target_destroy(struct pipe_context *pipe,
1027 struct pipe_stream_output_target *ptarg)
1028 {
1029 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1030 pipe->destroy_query(pipe, targ->pq);
1031 pipe_resource_reference(&targ->pipe.buffer, NULL);
1032 FREE(targ);
1033 }
1034
1035 static void
1036 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1037 unsigned num_targets,
1038 struct pipe_stream_output_target **targets,
1039 const unsigned *offsets)
1040 {
1041 struct nvc0_context *nvc0 = nvc0_context(pipe);
1042 unsigned i;
1043 bool serialize = true;
1044
1045 assert(num_targets <= 4);
1046
1047 for (i = 0; i < num_targets; ++i) {
1048 const bool changed = nvc0->tfbbuf[i] != targets[i];
1049 const bool append = (offsets[i] == ((unsigned)-1));
1050 if (!changed && append)
1051 continue;
1052 nvc0->tfbbuf_dirty |= 1 << i;
1053
1054 if (nvc0->tfbbuf[i] && changed)
1055 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1056
1057 if (targets[i] && !append)
1058 nvc0_so_target(targets[i])->clean = true;
1059
1060 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1061 }
1062 for (; i < nvc0->num_tfbbufs; ++i) {
1063 if (nvc0->tfbbuf[i]) {
1064 nvc0->tfbbuf_dirty |= 1 << i;
1065 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1066 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1067 }
1068 }
1069 nvc0->num_tfbbufs = num_targets;
1070
1071 if (nvc0->tfbbuf_dirty) {
1072 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TFB);
1073 nvc0->dirty_3d |= NVC0_NEW_3D_TFB_TARGETS;
1074 }
1075 }
1076
1077 static void
1078 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1079 unsigned start, unsigned nr,
1080 struct pipe_surface **psurfaces)
1081 {
1082 const unsigned end = start + nr;
1083 const unsigned mask = ((1 << nr) - 1) << start;
1084 unsigned i;
1085
1086 if (psurfaces) {
1087 for (i = start; i < end; ++i) {
1088 const unsigned p = i - start;
1089 if (psurfaces[p])
1090 nvc0->surfaces_valid[t] |= (1 << i);
1091 else
1092 nvc0->surfaces_valid[t] &= ~(1 << i);
1093 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1094 }
1095 } else {
1096 for (i = start; i < end; ++i)
1097 pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1098 nvc0->surfaces_valid[t] &= ~mask;
1099 }
1100 nvc0->surfaces_dirty[t] |= mask;
1101
1102 if (t == 0)
1103 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1104 else
1105 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1106 }
1107
1108 static void
1109 nvc0_set_compute_resources(struct pipe_context *pipe,
1110 unsigned start, unsigned nr,
1111 struct pipe_surface **resources)
1112 {
1113 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1114
1115 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1116 }
1117
1118 static bool
1119 nvc0_bind_images_range(struct nvc0_context *nvc0, const unsigned s,
1120 unsigned start, unsigned nr,
1121 const struct pipe_image_view *pimages)
1122 {
1123 const unsigned end = start + nr;
1124 unsigned mask = 0;
1125 unsigned i;
1126
1127 assert(s < 6);
1128
1129 if (pimages) {
1130 for (i = start; i < end; ++i) {
1131 struct pipe_image_view *img = &nvc0->images[s][i];
1132 const unsigned p = i - start;
1133
1134 if (img->resource == pimages[p].resource &&
1135 img->format == pimages[p].format &&
1136 img->access == pimages[p].access) {
1137 if (img->resource == NULL)
1138 continue;
1139 if (img->resource->target == PIPE_BUFFER &&
1140 img->u.buf.offset == pimages[p].u.buf.offset &&
1141 img->u.buf.size == pimages[p].u.buf.size)
1142 continue;
1143 if (img->resource->target != PIPE_BUFFER &&
1144 img->u.tex.first_layer == pimages[p].u.tex.first_layer &&
1145 img->u.tex.last_layer == pimages[p].u.tex.last_layer &&
1146 img->u.tex.level == pimages[p].u.tex.level)
1147 continue;
1148 }
1149
1150 mask |= (1 << i);
1151 if (pimages[p].resource)
1152 nvc0->images_valid[s] |= (1 << i);
1153 else
1154 nvc0->images_valid[s] &= ~(1 << i);
1155
1156 img->format = pimages[p].format;
1157 img->access = pimages[p].access;
1158 if (pimages[p].resource && pimages[p].resource->target == PIPE_BUFFER)
1159 img->u.buf = pimages[p].u.buf;
1160 else
1161 img->u.tex = pimages[p].u.tex;
1162
1163 pipe_resource_reference(
1164 &img->resource, pimages[p].resource);
1165
1166 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1167 if (nvc0->images_tic[s][i]) {
1168 struct nv50_tic_entry *old =
1169 nv50_tic_entry(nvc0->images_tic[s][i]);
1170 nvc0_screen_tic_unlock(nvc0->screen, old);
1171 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1172 }
1173
1174 nvc0->images_tic[s][i] =
1175 gm107_create_texture_view_from_image(&nvc0->base.pipe,
1176 &pimages[p]);
1177 }
1178 }
1179 if (!mask)
1180 return false;
1181 } else {
1182 mask = ((1 << nr) - 1) << start;
1183 if (!(nvc0->images_valid[s] & mask))
1184 return false;
1185 for (i = start; i < end; ++i) {
1186 pipe_resource_reference(&nvc0->images[s][i].resource, NULL);
1187 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1188 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->images_tic[s][i]);
1189 if (old) {
1190 nvc0_screen_tic_unlock(nvc0->screen, old);
1191 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1192 }
1193 }
1194 }
1195 nvc0->images_valid[s] &= ~mask;
1196 }
1197 nvc0->images_dirty[s] |= mask;
1198
1199 if (s == 5)
1200 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1201 else
1202 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1203
1204 return true;
1205 }
1206
1207 static void
1208 nvc0_set_shader_images(struct pipe_context *pipe,
1209 enum pipe_shader_type shader,
1210 unsigned start, unsigned nr,
1211 const struct pipe_image_view *images)
1212 {
1213 const unsigned s = nvc0_shader_stage(shader);
1214 if (!nvc0_bind_images_range(nvc0_context(pipe), s, start, nr, images))
1215 return;
1216
1217 if (s == 5)
1218 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1219 else
1220 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SURFACES;
1221 }
1222
1223 static bool
1224 nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t,
1225 unsigned start, unsigned nr,
1226 const struct pipe_shader_buffer *pbuffers)
1227 {
1228 const unsigned end = start + nr;
1229 unsigned mask = 0;
1230 unsigned i;
1231
1232 assert(t < 6);
1233
1234 if (pbuffers) {
1235 for (i = start; i < end; ++i) {
1236 struct pipe_shader_buffer *buf = &nvc0->buffers[t][i];
1237 const unsigned p = i - start;
1238 if (buf->buffer == pbuffers[p].buffer &&
1239 buf->buffer_offset == pbuffers[p].buffer_offset &&
1240 buf->buffer_size == pbuffers[p].buffer_size)
1241 continue;
1242
1243 mask |= (1 << i);
1244 if (pbuffers[p].buffer)
1245 nvc0->buffers_valid[t] |= (1 << i);
1246 else
1247 nvc0->buffers_valid[t] &= ~(1 << i);
1248 buf->buffer_offset = pbuffers[p].buffer_offset;
1249 buf->buffer_size = pbuffers[p].buffer_size;
1250 pipe_resource_reference(&buf->buffer, pbuffers[p].buffer);
1251 }
1252 if (!mask)
1253 return false;
1254 } else {
1255 mask = ((1 << nr) - 1) << start;
1256 if (!(nvc0->buffers_valid[t] & mask))
1257 return false;
1258 for (i = start; i < end; ++i)
1259 pipe_resource_reference(&nvc0->buffers[t][i].buffer, NULL);
1260 nvc0->buffers_valid[t] &= ~mask;
1261 }
1262 nvc0->buffers_dirty[t] |= mask;
1263
1264 if (t == 5)
1265 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF);
1266 else
1267 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BUF);
1268
1269 return true;
1270 }
1271
1272 static void
1273 nvc0_set_shader_buffers(struct pipe_context *pipe,
1274 enum pipe_shader_type shader,
1275 unsigned start, unsigned nr,
1276 const struct pipe_shader_buffer *buffers)
1277 {
1278 const unsigned s = nvc0_shader_stage(shader);
1279 if (!nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers))
1280 return;
1281
1282 if (s == 5)
1283 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_BUFFERS;
1284 else
1285 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_BUFFERS;
1286 }
1287
1288 static inline void
1289 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1290 {
1291 struct nv04_resource *buf = nv04_resource(res);
1292 if (buf) {
1293 uint64_t limit = (buf->address + buf->base.width0) - 1;
1294 if (limit < (1ULL << 32)) {
1295 *phandle = (uint32_t)buf->address;
1296 } else {
1297 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1298 "resource not contained within 32-bit address space !\n");
1299 *phandle = 0;
1300 }
1301 } else {
1302 *phandle = 0;
1303 }
1304 }
1305
1306 static void
1307 nvc0_set_global_bindings(struct pipe_context *pipe,
1308 unsigned start, unsigned nr,
1309 struct pipe_resource **resources,
1310 uint32_t **handles)
1311 {
1312 struct nvc0_context *nvc0 = nvc0_context(pipe);
1313 struct pipe_resource **ptr;
1314 unsigned i;
1315 const unsigned end = start + nr;
1316
1317 if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1318 const unsigned old_size = nvc0->global_residents.size;
1319 const unsigned req_size = end * sizeof(struct pipe_resource *);
1320 util_dynarray_resize(&nvc0->global_residents, req_size);
1321 memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1322 req_size - old_size);
1323 }
1324
1325 if (resources) {
1326 ptr = util_dynarray_element(
1327 &nvc0->global_residents, struct pipe_resource *, start);
1328 for (i = 0; i < nr; ++i) {
1329 pipe_resource_reference(&ptr[i], resources[i]);
1330 nvc0_set_global_handle(handles[i], resources[i]);
1331 }
1332 } else {
1333 ptr = util_dynarray_element(
1334 &nvc0->global_residents, struct pipe_resource *, start);
1335 for (i = 0; i < nr; ++i)
1336 pipe_resource_reference(&ptr[i], NULL);
1337 }
1338
1339 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1340
1341 nvc0->dirty_cp |= NVC0_NEW_CP_GLOBALS;
1342 }
1343
1344 void
1345 nvc0_init_state_functions(struct nvc0_context *nvc0)
1346 {
1347 struct pipe_context *pipe = &nvc0->base.pipe;
1348
1349 pipe->create_blend_state = nvc0_blend_state_create;
1350 pipe->bind_blend_state = nvc0_blend_state_bind;
1351 pipe->delete_blend_state = nvc0_blend_state_delete;
1352
1353 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1354 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1355 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1356
1357 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1358 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1359 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1360
1361 pipe->create_sampler_state = nv50_sampler_state_create;
1362 pipe->delete_sampler_state = nvc0_sampler_state_delete;
1363 pipe->bind_sampler_states = nvc0_bind_sampler_states;
1364
1365 pipe->create_sampler_view = nvc0_create_sampler_view;
1366 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1367 pipe->set_sampler_views = nvc0_set_sampler_views;
1368
1369 pipe->create_vs_state = nvc0_vp_state_create;
1370 pipe->create_fs_state = nvc0_fp_state_create;
1371 pipe->create_gs_state = nvc0_gp_state_create;
1372 pipe->create_tcs_state = nvc0_tcp_state_create;
1373 pipe->create_tes_state = nvc0_tep_state_create;
1374 pipe->bind_vs_state = nvc0_vp_state_bind;
1375 pipe->bind_fs_state = nvc0_fp_state_bind;
1376 pipe->bind_gs_state = nvc0_gp_state_bind;
1377 pipe->bind_tcs_state = nvc0_tcp_state_bind;
1378 pipe->bind_tes_state = nvc0_tep_state_bind;
1379 pipe->delete_vs_state = nvc0_sp_state_delete;
1380 pipe->delete_fs_state = nvc0_sp_state_delete;
1381 pipe->delete_gs_state = nvc0_sp_state_delete;
1382 pipe->delete_tcs_state = nvc0_sp_state_delete;
1383 pipe->delete_tes_state = nvc0_sp_state_delete;
1384
1385 pipe->create_compute_state = nvc0_cp_state_create;
1386 pipe->bind_compute_state = nvc0_cp_state_bind;
1387 pipe->delete_compute_state = nvc0_sp_state_delete;
1388
1389 pipe->set_blend_color = nvc0_set_blend_color;
1390 pipe->set_stencil_ref = nvc0_set_stencil_ref;
1391 pipe->set_clip_state = nvc0_set_clip_state;
1392 pipe->set_sample_mask = nvc0_set_sample_mask;
1393 pipe->set_min_samples = nvc0_set_min_samples;
1394 pipe->set_constant_buffer = nvc0_set_constant_buffer;
1395 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1396 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1397 pipe->set_scissor_states = nvc0_set_scissor_states;
1398 pipe->set_viewport_states = nvc0_set_viewport_states;
1399 pipe->set_window_rectangles = nvc0_set_window_rectangles;
1400 pipe->set_tess_state = nvc0_set_tess_state;
1401
1402 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1403 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1404 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1405
1406 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1407
1408 pipe->create_stream_output_target = nvc0_so_target_create;
1409 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1410 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1411
1412 pipe->set_global_binding = nvc0_set_global_bindings;
1413 pipe->set_compute_resources = nvc0_set_compute_resources;
1414 pipe->set_shader_images = nvc0_set_shader_images;
1415 pipe->set_shader_buffers = nvc0_set_shader_buffers;
1416
1417 nvc0->sample_mask = ~0;
1418 nvc0->min_samples = 1;
1419 nvc0->default_tess_outer[0] =
1420 nvc0->default_tess_outer[1] =
1421 nvc0->default_tess_outer[2] =
1422 nvc0->default_tess_outer[3] = 1.0;
1423 nvc0->default_tess_inner[0] =
1424 nvc0->default_tess_inner[1] = 1.0;
1425 }