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nvc0: undo overzealous enum usage
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_framebuffer.h"
25 #include "util/u_helpers.h"
26 #include "util/u_inlines.h"
27 #include "util/u_transfer.h"
28
29 #include "tgsi/tgsi_parse.h"
30
31 #include "nvc0/nvc0_stateobj.h"
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_query_hw.h"
34
35 #include "nvc0/nvc0_3d.xml.h"
36
37 #include "nouveau_gldefs.h"
38
39 static inline uint32_t
40 nvc0_colormask(unsigned mask)
41 {
42 uint32_t ret = 0;
43
44 if (mask & PIPE_MASK_R)
45 ret |= 0x0001;
46 if (mask & PIPE_MASK_G)
47 ret |= 0x0010;
48 if (mask & PIPE_MASK_B)
49 ret |= 0x0100;
50 if (mask & PIPE_MASK_A)
51 ret |= 0x1000;
52
53 return ret;
54 }
55
56 #define NVC0_BLEND_FACTOR_CASE(a, b) \
57 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
58
59 static inline uint32_t
60 nvc0_blend_fac(unsigned factor)
61 {
62 switch (factor) {
63 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
64 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
65 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
66 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
67 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
68 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
69 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
70 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
71 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
72 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
73 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
74 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
75 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
76 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
77 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
78 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
79 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
80 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
81 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
82 default:
83 return NV50_BLEND_FACTOR_ZERO;
84 }
85 }
86
87 static void *
88 nvc0_blend_state_create(struct pipe_context *pipe,
89 const struct pipe_blend_state *cso)
90 {
91 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
92 int i;
93 int r; /* reference */
94 uint8_t blend_en = 0;
95 bool indep_masks = false;
96 bool indep_funcs = false;
97
98 so->pipe = *cso;
99
100 /* check which states actually have differing values */
101 if (cso->independent_blend_enable) {
102 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
103 blend_en |= 1 << r;
104 for (i = r + 1; i < 8; ++i) {
105 if (!cso->rt[i].blend_enable)
106 continue;
107 blend_en |= 1 << i;
108 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
109 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
110 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
111 cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
112 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
113 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
114 indep_funcs = true;
115 break;
116 }
117 }
118 for (; i < 8; ++i)
119 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
120
121 for (i = 1; i < 8; ++i) {
122 if (cso->rt[i].colormask != cso->rt[0].colormask) {
123 indep_masks = true;
124 break;
125 }
126 }
127 } else {
128 r = 0;
129 if (cso->rt[0].blend_enable)
130 blend_en = 0xff;
131 }
132
133 if (cso->logicop_enable) {
134 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
135 SB_DATA (so, 1);
136 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
137
138 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
139 } else {
140 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
141
142 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
143 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
144 if (indep_funcs) {
145 for (i = 0; i < 8; ++i) {
146 if (cso->rt[i].blend_enable) {
147 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
148 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
149 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
150 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
151 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
152 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
153 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
154 }
155 }
156 } else
157 if (blend_en) {
158 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
159 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
160 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
161 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
162 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
163 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
164 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
165 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
166 }
167
168 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
169 if (indep_masks) {
170 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
171 for (i = 0; i < 8; ++i)
172 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
173 } else {
174 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
175 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
176 }
177 }
178
179 assert(so->size <= ARRAY_SIZE(so->state));
180 return so;
181 }
182
183 static void
184 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
185 {
186 struct nvc0_context *nvc0 = nvc0_context(pipe);
187
188 nvc0->blend = hwcso;
189 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND;
190 }
191
192 static void
193 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
194 {
195 FREE(hwcso);
196 }
197
198 /* NOTE: ignoring line_last_pixel */
199 static void *
200 nvc0_rasterizer_state_create(struct pipe_context *pipe,
201 const struct pipe_rasterizer_state *cso)
202 {
203 struct nvc0_rasterizer_stateobj *so;
204 uint32_t reg;
205
206 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
207 if (!so)
208 return NULL;
209 so->pipe = *cso;
210
211 /* Scissor enables are handled in scissor state, we will not want to
212 * always emit 16 commands, one for each scissor rectangle, here.
213 */
214
215 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
216 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
217
218 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
219 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
220 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
221
222 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
223
224 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
225 if (cso->line_smooth || cso->multisample)
226 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
227 else
228 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
229 SB_DATA (so, fui(cso->line_width));
230
231 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
232 if (cso->line_stipple_enable) {
233 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
234 SB_DATA (so, (cso->line_stipple_pattern << 8) |
235 cso->line_stipple_factor);
236
237 }
238
239 SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
240 if (!cso->point_size_per_vertex) {
241 SB_BEGIN_3D(so, POINT_SIZE, 1);
242 SB_DATA (so, fui(cso->point_size));
243 }
244
245 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
246 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
247 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
248
249 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
250 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
251 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
252 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
253
254 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
255 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
256 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
257 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
258 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
259
260 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
261 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
262 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
263 NVC0_3D_FRONT_FACE_CW);
264 switch (cso->cull_face) {
265 case PIPE_FACE_FRONT_AND_BACK:
266 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
267 break;
268 case PIPE_FACE_FRONT:
269 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
270 break;
271 case PIPE_FACE_BACK:
272 default:
273 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
274 break;
275 }
276
277 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
278 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
279 SB_DATA (so, cso->offset_point);
280 SB_DATA (so, cso->offset_line);
281 SB_DATA (so, cso->offset_tri);
282
283 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
284 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
285 SB_DATA (so, fui(cso->offset_scale));
286 if (!cso->offset_units_unscaled) {
287 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
288 SB_DATA (so, fui(cso->offset_units * 2.0f));
289 }
290 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
291 SB_DATA (so, fui(cso->offset_clamp));
292 }
293
294 if (cso->depth_clip)
295 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
296 else
297 reg =
298 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
299 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
300 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
301 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
302
303 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
304 SB_DATA (so, reg);
305
306 SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
307
308 SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
309
310 assert(so->size <= ARRAY_SIZE(so->state));
311 return (void *)so;
312 }
313
314 static void
315 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
316 {
317 struct nvc0_context *nvc0 = nvc0_context(pipe);
318
319 nvc0->rast = hwcso;
320 nvc0->dirty_3d |= NVC0_NEW_3D_RASTERIZER;
321 }
322
323 static void
324 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
325 {
326 FREE(hwcso);
327 }
328
329 static void *
330 nvc0_zsa_state_create(struct pipe_context *pipe,
331 const struct pipe_depth_stencil_alpha_state *cso)
332 {
333 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
334
335 so->pipe = *cso;
336
337 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
338 if (cso->depth.enabled) {
339 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
340 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
341 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
342 }
343
344 SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth.bounds_test);
345 if (cso->depth.bounds_test) {
346 SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
347 SB_DATA (so, fui(cso->depth.bounds_min));
348 SB_DATA (so, fui(cso->depth.bounds_max));
349 }
350
351 if (cso->stencil[0].enabled) {
352 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
353 SB_DATA (so, 1);
354 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
355 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
356 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
357 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
358 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
359 SB_DATA (so, cso->stencil[0].valuemask);
360 SB_DATA (so, cso->stencil[0].writemask);
361 } else {
362 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
363 }
364
365 if (cso->stencil[1].enabled) {
366 assert(cso->stencil[0].enabled);
367 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
368 SB_DATA (so, 1);
369 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
370 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
371 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
372 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
373 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
374 SB_DATA (so, cso->stencil[1].writemask);
375 SB_DATA (so, cso->stencil[1].valuemask);
376 } else
377 if (cso->stencil[0].enabled) {
378 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
379 }
380
381 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
382 if (cso->alpha.enabled) {
383 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
384 SB_DATA (so, fui(cso->alpha.ref_value));
385 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
386 }
387
388 assert(so->size <= ARRAY_SIZE(so->state));
389 return (void *)so;
390 }
391
392 static void
393 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
394 {
395 struct nvc0_context *nvc0 = nvc0_context(pipe);
396
397 nvc0->zsa = hwcso;
398 nvc0->dirty_3d |= NVC0_NEW_3D_ZSA;
399 }
400
401 static void
402 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
403 {
404 FREE(hwcso);
405 }
406
407 /* ====================== SAMPLERS AND TEXTURES ================================
408 */
409
410 #define NV50_TSC_WRAP_CASE(n) \
411 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
412
413 static void
414 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
415 {
416 unsigned s, i;
417
418 for (s = 0; s < 6; ++s)
419 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
420 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
421 nvc0_context(pipe)->samplers[s][i] = NULL;
422
423 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
424
425 FREE(hwcso);
426 }
427
428 static inline void
429 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0,
430 unsigned s,
431 unsigned nr, void **hwcso)
432 {
433 unsigned i;
434
435 for (i = 0; i < nr; ++i) {
436 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
437
438 if (hwcso[i] == old)
439 continue;
440 nvc0->samplers_dirty[s] |= 1 << i;
441
442 nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
443 if (old)
444 nvc0_screen_tsc_unlock(nvc0->screen, old);
445 }
446 for (; i < nvc0->num_samplers[s]; ++i) {
447 if (nvc0->samplers[s][i]) {
448 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
449 nvc0->samplers[s][i] = NULL;
450 }
451 }
452
453 nvc0->num_samplers[s] = nr;
454
455 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
456 }
457
458 static void
459 nvc0_stage_sampler_states_bind_range(struct nvc0_context *nvc0,
460 unsigned s,
461 unsigned start, unsigned nr, void **cso)
462 {
463 const unsigned end = start + nr;
464 int last_valid = -1;
465 unsigned i;
466
467 if (cso) {
468 for (i = start; i < end; ++i) {
469 const unsigned p = i - start;
470 if (cso[p])
471 last_valid = i;
472 if (cso[p] == nvc0->samplers[s][i])
473 continue;
474 nvc0->samplers_dirty[s] |= 1 << i;
475
476 if (nvc0->samplers[s][i])
477 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
478 nvc0->samplers[s][i] = cso[p];
479 }
480 } else {
481 for (i = start; i < end; ++i) {
482 if (nvc0->samplers[s][i]) {
483 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
484 nvc0->samplers[s][i] = NULL;
485 nvc0->samplers_dirty[s] |= 1 << i;
486 }
487 }
488 }
489
490 if (nvc0->num_samplers[s] <= end) {
491 if (last_valid < 0) {
492 for (i = start; i && !nvc0->samplers[s][i - 1]; --i);
493 nvc0->num_samplers[s] = i;
494 } else {
495 nvc0->num_samplers[s] = last_valid + 1;
496 }
497 }
498 }
499
500 static void
501 nvc0_bind_sampler_states(struct pipe_context *pipe,
502 enum pipe_shader_type shader,
503 unsigned start, unsigned nr, void **s)
504 {
505 switch (shader) {
506 case PIPE_SHADER_VERTEX:
507 assert(start == 0);
508 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 0, nr, s);
509 break;
510 case PIPE_SHADER_TESS_CTRL:
511 assert(start == 0);
512 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 1, nr, s);
513 break;
514 case PIPE_SHADER_TESS_EVAL:
515 assert(start == 0);
516 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 2, nr, s);
517 break;
518 case PIPE_SHADER_GEOMETRY:
519 assert(start == 0);
520 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 3, nr, s);
521 break;
522 case PIPE_SHADER_FRAGMENT:
523 assert(start == 0);
524 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 4, nr, s);
525 break;
526 case PIPE_SHADER_COMPUTE:
527 nvc0_stage_sampler_states_bind_range(nvc0_context(pipe), 5,
528 start, nr, s);
529 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
530 break;
531 default:
532 assert(!"unexpected shader type");
533 break;
534 }
535 }
536
537
538 /* NOTE: only called when not referenced anywhere, won't be bound */
539 static void
540 nvc0_sampler_view_destroy(struct pipe_context *pipe,
541 struct pipe_sampler_view *view)
542 {
543 pipe_resource_reference(&view->texture, NULL);
544
545 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
546
547 FREE(nv50_tic_entry(view));
548 }
549
550 static inline void
551 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
552 unsigned nr,
553 struct pipe_sampler_view **views)
554 {
555 unsigned i;
556
557 for (i = 0; i < nr; ++i) {
558 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
559
560 if (views[i] == nvc0->textures[s][i])
561 continue;
562 nvc0->textures_dirty[s] |= 1 << i;
563
564 if (views[i] && views[i]->texture) {
565 struct pipe_resource *res = views[i]->texture;
566 if (res->target == PIPE_BUFFER &&
567 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
568 nvc0->textures_coherent[s] |= 1 << i;
569 else
570 nvc0->textures_coherent[s] &= ~(1 << i);
571 } else {
572 nvc0->textures_coherent[s] &= ~(1 << i);
573 }
574
575 if (old) {
576 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
577 nvc0_screen_tic_unlock(nvc0->screen, old);
578 }
579
580 pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
581 }
582
583 for (i = nr; i < nvc0->num_textures[s]; ++i) {
584 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
585 if (old) {
586 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
587 nvc0_screen_tic_unlock(nvc0->screen, old);
588 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
589 }
590 }
591
592 nvc0->num_textures[s] = nr;
593
594 nvc0->dirty_3d |= NVC0_NEW_3D_TEXTURES;
595 }
596
597 static void
598 nvc0_stage_set_sampler_views_range(struct nvc0_context *nvc0, const unsigned s,
599 unsigned start, unsigned nr,
600 struct pipe_sampler_view **views)
601 {
602 struct nouveau_bufctx *bctx = (s == 5) ? nvc0->bufctx_cp : nvc0->bufctx_3d;
603 const unsigned end = start + nr;
604 const unsigned bin = (s == 5) ? NVC0_BIND_CP_TEX(0) : NVC0_BIND_3D_TEX(s, 0);
605 int last_valid = -1;
606 unsigned i;
607
608 if (views) {
609 for (i = start; i < end; ++i) {
610 const unsigned p = i - start;
611 if (views[p])
612 last_valid = i;
613 if (views[p] == nvc0->textures[s][i])
614 continue;
615 nvc0->textures_dirty[s] |= 1 << i;
616
617 if (views[p] && views[p]->texture) {
618 struct pipe_resource *res = views[p]->texture;
619 if (res->target == PIPE_BUFFER &&
620 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
621 nvc0->textures_coherent[s] |= 1 << i;
622 else
623 nvc0->textures_coherent[s] &= ~(1 << i);
624 } else {
625 nvc0->textures_coherent[s] &= ~(1 << i);
626 }
627
628 if (nvc0->textures[s][i]) {
629 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
630 nouveau_bufctx_reset(bctx, bin + i);
631 nvc0_screen_tic_unlock(nvc0->screen, old);
632 }
633 pipe_sampler_view_reference(&nvc0->textures[s][i], views[p]);
634 }
635 } else {
636 for (i = start; i < end; ++i) {
637 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
638 if (!old)
639 continue;
640 nvc0->textures_dirty[s] |= 1 << i;
641
642 nvc0_screen_tic_unlock(nvc0->screen, old);
643 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
644 nouveau_bufctx_reset(bctx, bin + i);
645 }
646 }
647
648 if (nvc0->num_textures[s] <= end) {
649 if (last_valid < 0) {
650 for (i = start; i && !nvc0->textures[s][i - 1]; --i);
651 nvc0->num_textures[s] = i;
652 } else {
653 nvc0->num_textures[s] = last_valid + 1;
654 }
655 }
656 }
657
658 static void
659 nvc0_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,
660 unsigned start, unsigned nr,
661 struct pipe_sampler_view **views)
662 {
663 assert(start == 0);
664 switch (shader) {
665 case PIPE_SHADER_VERTEX:
666 nvc0_stage_set_sampler_views(nvc0_context(pipe), 0, nr, views);
667 break;
668 case PIPE_SHADER_TESS_CTRL:
669 nvc0_stage_set_sampler_views(nvc0_context(pipe), 1, nr, views);
670 break;
671 case PIPE_SHADER_TESS_EVAL:
672 nvc0_stage_set_sampler_views(nvc0_context(pipe), 2, nr, views);
673 break;
674 case PIPE_SHADER_GEOMETRY:
675 nvc0_stage_set_sampler_views(nvc0_context(pipe), 3, nr, views);
676 break;
677 case PIPE_SHADER_FRAGMENT:
678 nvc0_stage_set_sampler_views(nvc0_context(pipe), 4, nr, views);
679 break;
680 case PIPE_SHADER_COMPUTE:
681 nvc0_stage_set_sampler_views_range(nvc0_context(pipe), 5,
682 start, nr, views);
683 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
684 break;
685 default:
686 ;
687 }
688 }
689
690
691 /* ============================= SHADERS =======================================
692 */
693
694 static void *
695 nvc0_sp_state_create(struct pipe_context *pipe,
696 const struct pipe_shader_state *cso, unsigned type)
697 {
698 struct nvc0_program *prog;
699
700 prog = CALLOC_STRUCT(nvc0_program);
701 if (!prog)
702 return NULL;
703
704 prog->type = type;
705
706 if (cso->tokens)
707 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
708
709 if (cso->stream_output.num_outputs)
710 prog->pipe.stream_output = cso->stream_output;
711
712 prog->translated = nvc0_program_translate(
713 prog, nvc0_context(pipe)->screen->base.device->chipset,
714 &nouveau_context(pipe)->debug);
715
716 return (void *)prog;
717 }
718
719 static void
720 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
721 {
722 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
723
724 nvc0_program_destroy(nvc0_context(pipe), prog);
725
726 FREE((void *)prog->pipe.tokens);
727 FREE(prog);
728 }
729
730 static void *
731 nvc0_vp_state_create(struct pipe_context *pipe,
732 const struct pipe_shader_state *cso)
733 {
734 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
735 }
736
737 static void
738 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
739 {
740 struct nvc0_context *nvc0 = nvc0_context(pipe);
741
742 nvc0->vertprog = hwcso;
743 nvc0->dirty_3d |= NVC0_NEW_3D_VERTPROG;
744 }
745
746 static void *
747 nvc0_fp_state_create(struct pipe_context *pipe,
748 const struct pipe_shader_state *cso)
749 {
750 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
751 }
752
753 static void
754 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
755 {
756 struct nvc0_context *nvc0 = nvc0_context(pipe);
757
758 nvc0->fragprog = hwcso;
759 nvc0->dirty_3d |= NVC0_NEW_3D_FRAGPROG;
760 }
761
762 static void *
763 nvc0_gp_state_create(struct pipe_context *pipe,
764 const struct pipe_shader_state *cso)
765 {
766 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
767 }
768
769 static void
770 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
771 {
772 struct nvc0_context *nvc0 = nvc0_context(pipe);
773
774 nvc0->gmtyprog = hwcso;
775 nvc0->dirty_3d |= NVC0_NEW_3D_GMTYPROG;
776 }
777
778 static void *
779 nvc0_tcp_state_create(struct pipe_context *pipe,
780 const struct pipe_shader_state *cso)
781 {
782 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
783 }
784
785 static void
786 nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
787 {
788 struct nvc0_context *nvc0 = nvc0_context(pipe);
789
790 nvc0->tctlprog = hwcso;
791 nvc0->dirty_3d |= NVC0_NEW_3D_TCTLPROG;
792 }
793
794 static void *
795 nvc0_tep_state_create(struct pipe_context *pipe,
796 const struct pipe_shader_state *cso)
797 {
798 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
799 }
800
801 static void
802 nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
803 {
804 struct nvc0_context *nvc0 = nvc0_context(pipe);
805
806 nvc0->tevlprog = hwcso;
807 nvc0->dirty_3d |= NVC0_NEW_3D_TEVLPROG;
808 }
809
810 static void *
811 nvc0_cp_state_create(struct pipe_context *pipe,
812 const struct pipe_compute_state *cso)
813 {
814 struct nvc0_program *prog;
815
816 prog = CALLOC_STRUCT(nvc0_program);
817 if (!prog)
818 return NULL;
819 prog->type = PIPE_SHADER_COMPUTE;
820
821 prog->cp.smem_size = cso->req_local_mem;
822 prog->cp.lmem_size = cso->req_private_mem;
823 prog->parm_size = cso->req_input_mem;
824
825 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
826
827 return (void *)prog;
828 }
829
830 static void
831 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
832 {
833 struct nvc0_context *nvc0 = nvc0_context(pipe);
834
835 nvc0->compprog = hwcso;
836 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
837 }
838
839 static void
840 nvc0_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
841 const struct pipe_constant_buffer *cb)
842 {
843 struct nvc0_context *nvc0 = nvc0_context(pipe);
844 struct pipe_resource *res = cb ? cb->buffer : NULL;
845 const unsigned s = nvc0_shader_stage(shader);
846 const unsigned i = index;
847
848 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
849 if (nvc0->constbuf[s][i].user)
850 nvc0->constbuf[s][i].u.buf = NULL;
851 else
852 if (nvc0->constbuf[s][i].u.buf)
853 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
854
855 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
856 } else {
857 if (nvc0->constbuf[s][i].user)
858 nvc0->constbuf[s][i].u.buf = NULL;
859 else
860 if (nvc0->constbuf[s][i].u.buf)
861 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_CB(s, i));
862
863 nvc0->dirty_3d |= NVC0_NEW_3D_CONSTBUF;
864 }
865 nvc0->constbuf_dirty[s] |= 1 << i;
866
867 if (nvc0->constbuf[s][i].u.buf)
868 nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
869 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
870
871 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
872 if (nvc0->constbuf[s][i].user) {
873 nvc0->constbuf[s][i].u.data = cb->user_buffer;
874 nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
875 nvc0->constbuf_valid[s] |= 1 << i;
876 nvc0->constbuf_coherent[s] &= ~(1 << i);
877 } else
878 if (cb) {
879 nvc0->constbuf[s][i].offset = cb->buffer_offset;
880 nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
881 nvc0->constbuf_valid[s] |= 1 << i;
882 if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
883 nvc0->constbuf_coherent[s] |= 1 << i;
884 else
885 nvc0->constbuf_coherent[s] &= ~(1 << i);
886 }
887 else {
888 nvc0->constbuf_valid[s] &= ~(1 << i);
889 nvc0->constbuf_coherent[s] &= ~(1 << i);
890 }
891 }
892
893 /* =============================================================================
894 */
895
896 static void
897 nvc0_set_blend_color(struct pipe_context *pipe,
898 const struct pipe_blend_color *bcol)
899 {
900 struct nvc0_context *nvc0 = nvc0_context(pipe);
901
902 nvc0->blend_colour = *bcol;
903 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND_COLOUR;
904 }
905
906 static void
907 nvc0_set_stencil_ref(struct pipe_context *pipe,
908 const struct pipe_stencil_ref *sr)
909 {
910 struct nvc0_context *nvc0 = nvc0_context(pipe);
911
912 nvc0->stencil_ref = *sr;
913 nvc0->dirty_3d |= NVC0_NEW_3D_STENCIL_REF;
914 }
915
916 static void
917 nvc0_set_clip_state(struct pipe_context *pipe,
918 const struct pipe_clip_state *clip)
919 {
920 struct nvc0_context *nvc0 = nvc0_context(pipe);
921
922 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
923
924 nvc0->dirty_3d |= NVC0_NEW_3D_CLIP;
925 }
926
927 static void
928 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
929 {
930 struct nvc0_context *nvc0 = nvc0_context(pipe);
931
932 nvc0->sample_mask = sample_mask;
933 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_MASK;
934 }
935
936 static void
937 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
938 {
939 struct nvc0_context *nvc0 = nvc0_context(pipe);
940
941 if (nvc0->min_samples != min_samples) {
942 nvc0->min_samples = min_samples;
943 nvc0->dirty_3d |= NVC0_NEW_3D_MIN_SAMPLES;
944 }
945 }
946
947 static void
948 nvc0_set_framebuffer_state(struct pipe_context *pipe,
949 const struct pipe_framebuffer_state *fb)
950 {
951 struct nvc0_context *nvc0 = nvc0_context(pipe);
952
953 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
954
955 util_copy_framebuffer_state(&nvc0->framebuffer, fb);
956
957 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER;
958 }
959
960 static void
961 nvc0_set_polygon_stipple(struct pipe_context *pipe,
962 const struct pipe_poly_stipple *stipple)
963 {
964 struct nvc0_context *nvc0 = nvc0_context(pipe);
965
966 nvc0->stipple = *stipple;
967 nvc0->dirty_3d |= NVC0_NEW_3D_STIPPLE;
968 }
969
970 static void
971 nvc0_set_scissor_states(struct pipe_context *pipe,
972 unsigned start_slot,
973 unsigned num_scissors,
974 const struct pipe_scissor_state *scissor)
975 {
976 struct nvc0_context *nvc0 = nvc0_context(pipe);
977 int i;
978
979 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
980 for (i = 0; i < num_scissors; i++) {
981 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
982 continue;
983 nvc0->scissors[start_slot + i] = scissor[i];
984 nvc0->scissors_dirty |= 1 << (start_slot + i);
985 nvc0->dirty_3d |= NVC0_NEW_3D_SCISSOR;
986 }
987 }
988
989 static void
990 nvc0_set_viewport_states(struct pipe_context *pipe,
991 unsigned start_slot,
992 unsigned num_viewports,
993 const struct pipe_viewport_state *vpt)
994 {
995 struct nvc0_context *nvc0 = nvc0_context(pipe);
996 int i;
997
998 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
999 for (i = 0; i < num_viewports; i++) {
1000 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
1001 continue;
1002 nvc0->viewports[start_slot + i] = vpt[i];
1003 nvc0->viewports_dirty |= 1 << (start_slot + i);
1004 nvc0->dirty_3d |= NVC0_NEW_3D_VIEWPORT;
1005 }
1006
1007 }
1008
1009 static void
1010 nvc0_set_window_rectangles(struct pipe_context *pipe,
1011 boolean include,
1012 unsigned num_rectangles,
1013 const struct pipe_scissor_state *rectangles)
1014 {
1015 struct nvc0_context *nvc0 = nvc0_context(pipe);
1016
1017 nvc0->window_rect.inclusive = include;
1018 nvc0->window_rect.rects = MIN2(num_rectangles, NVC0_MAX_WINDOW_RECTANGLES);
1019 memcpy(nvc0->window_rect.rect, rectangles,
1020 sizeof(struct pipe_scissor_state) * nvc0->window_rect.rects);
1021
1022 nvc0->dirty_3d |= NVC0_NEW_3D_WINDOW_RECTS;
1023 }
1024
1025 static void
1026 nvc0_set_tess_state(struct pipe_context *pipe,
1027 const float default_tess_outer[4],
1028 const float default_tess_inner[2])
1029 {
1030 struct nvc0_context *nvc0 = nvc0_context(pipe);
1031
1032 memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
1033 memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
1034 nvc0->dirty_3d |= NVC0_NEW_3D_TESSFACTOR;
1035 }
1036
1037 static void
1038 nvc0_set_vertex_buffers(struct pipe_context *pipe,
1039 unsigned start_slot, unsigned count,
1040 const struct pipe_vertex_buffer *vb)
1041 {
1042 struct nvc0_context *nvc0 = nvc0_context(pipe);
1043 unsigned i;
1044
1045 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX);
1046 nvc0->dirty_3d |= NVC0_NEW_3D_ARRAYS;
1047
1048 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
1049 start_slot, count);
1050
1051 if (!vb) {
1052 nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
1053 nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
1054 nvc0->vtxbufs_coherent &= ~(((1ull << count) - 1) << start_slot);
1055 return;
1056 }
1057
1058 for (i = 0; i < count; ++i) {
1059 unsigned dst_index = start_slot + i;
1060
1061 if (vb[i].user_buffer) {
1062 nvc0->vbo_user |= 1 << dst_index;
1063 if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
1064 nvc0->constant_vbos |= 1 << dst_index;
1065 else
1066 nvc0->constant_vbos &= ~(1 << dst_index);
1067 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1068 } else {
1069 nvc0->vbo_user &= ~(1 << dst_index);
1070 nvc0->constant_vbos &= ~(1 << dst_index);
1071
1072 if (vb[i].buffer &&
1073 vb[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1074 nvc0->vtxbufs_coherent |= (1 << dst_index);
1075 else
1076 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1077 }
1078 }
1079 }
1080
1081 static void
1082 nvc0_set_index_buffer(struct pipe_context *pipe,
1083 const struct pipe_index_buffer *ib)
1084 {
1085 struct nvc0_context *nvc0 = nvc0_context(pipe);
1086
1087 if (nvc0->idxbuf.buffer)
1088 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_IDX);
1089
1090 if (ib) {
1091 pipe_resource_reference(&nvc0->idxbuf.buffer, ib->buffer);
1092 nvc0->idxbuf.index_size = ib->index_size;
1093 if (ib->buffer) {
1094 nvc0->idxbuf.offset = ib->offset;
1095 nvc0->dirty_3d |= NVC0_NEW_3D_IDXBUF;
1096 } else {
1097 nvc0->idxbuf.user_buffer = ib->user_buffer;
1098 nvc0->dirty_3d &= ~NVC0_NEW_3D_IDXBUF;
1099 }
1100 } else {
1101 nvc0->dirty_3d &= ~NVC0_NEW_3D_IDXBUF;
1102 pipe_resource_reference(&nvc0->idxbuf.buffer, NULL);
1103 }
1104 }
1105
1106 static void
1107 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1108 {
1109 struct nvc0_context *nvc0 = nvc0_context(pipe);
1110
1111 nvc0->vertex = hwcso;
1112 nvc0->dirty_3d |= NVC0_NEW_3D_VERTEX;
1113 }
1114
1115 static struct pipe_stream_output_target *
1116 nvc0_so_target_create(struct pipe_context *pipe,
1117 struct pipe_resource *res,
1118 unsigned offset, unsigned size)
1119 {
1120 struct nv04_resource *buf = (struct nv04_resource *)res;
1121 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1122 if (!targ)
1123 return NULL;
1124
1125 targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0);
1126 if (!targ->pq) {
1127 FREE(targ);
1128 return NULL;
1129 }
1130 targ->clean = true;
1131
1132 targ->pipe.buffer_size = size;
1133 targ->pipe.buffer_offset = offset;
1134 targ->pipe.context = pipe;
1135 targ->pipe.buffer = NULL;
1136 pipe_resource_reference(&targ->pipe.buffer, res);
1137 pipe_reference_init(&targ->pipe.reference, 1);
1138
1139 assert(buf->base.target == PIPE_BUFFER);
1140 util_range_add(&buf->valid_buffer_range, offset, offset + size);
1141
1142 return &targ->pipe;
1143 }
1144
1145 static void
1146 nvc0_so_target_save_offset(struct pipe_context *pipe,
1147 struct pipe_stream_output_target *ptarg,
1148 unsigned index, bool *serialize)
1149 {
1150 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1151
1152 if (*serialize) {
1153 *serialize = false;
1154 PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
1155 IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
1156
1157 NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
1158 }
1159
1160 nvc0_query(targ->pq)->index = index;
1161 pipe->end_query(pipe, targ->pq);
1162 }
1163
1164 static void
1165 nvc0_so_target_destroy(struct pipe_context *pipe,
1166 struct pipe_stream_output_target *ptarg)
1167 {
1168 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1169 pipe->destroy_query(pipe, targ->pq);
1170 pipe_resource_reference(&targ->pipe.buffer, NULL);
1171 FREE(targ);
1172 }
1173
1174 static void
1175 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1176 unsigned num_targets,
1177 struct pipe_stream_output_target **targets,
1178 const unsigned *offsets)
1179 {
1180 struct nvc0_context *nvc0 = nvc0_context(pipe);
1181 unsigned i;
1182 bool serialize = true;
1183
1184 assert(num_targets <= 4);
1185
1186 for (i = 0; i < num_targets; ++i) {
1187 const bool changed = nvc0->tfbbuf[i] != targets[i];
1188 const bool append = (offsets[i] == ((unsigned)-1));
1189 if (!changed && append)
1190 continue;
1191 nvc0->tfbbuf_dirty |= 1 << i;
1192
1193 if (nvc0->tfbbuf[i] && changed)
1194 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1195
1196 if (targets[i] && !append)
1197 nvc0_so_target(targets[i])->clean = true;
1198
1199 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1200 }
1201 for (; i < nvc0->num_tfbbufs; ++i) {
1202 if (nvc0->tfbbuf[i]) {
1203 nvc0->tfbbuf_dirty |= 1 << i;
1204 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1205 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1206 }
1207 }
1208 nvc0->num_tfbbufs = num_targets;
1209
1210 if (nvc0->tfbbuf_dirty) {
1211 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TFB);
1212 nvc0->dirty_3d |= NVC0_NEW_3D_TFB_TARGETS;
1213 }
1214 }
1215
1216 static void
1217 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1218 unsigned start, unsigned nr,
1219 struct pipe_surface **psurfaces)
1220 {
1221 const unsigned end = start + nr;
1222 const unsigned mask = ((1 << nr) - 1) << start;
1223 unsigned i;
1224
1225 if (psurfaces) {
1226 for (i = start; i < end; ++i) {
1227 const unsigned p = i - start;
1228 if (psurfaces[p])
1229 nvc0->surfaces_valid[t] |= (1 << i);
1230 else
1231 nvc0->surfaces_valid[t] &= ~(1 << i);
1232 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1233 }
1234 } else {
1235 for (i = start; i < end; ++i)
1236 pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1237 nvc0->surfaces_valid[t] &= ~mask;
1238 }
1239 nvc0->surfaces_dirty[t] |= mask;
1240
1241 if (t == 0)
1242 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1243 else
1244 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1245 }
1246
1247 static void
1248 nvc0_set_compute_resources(struct pipe_context *pipe,
1249 unsigned start, unsigned nr,
1250 struct pipe_surface **resources)
1251 {
1252 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1253
1254 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1255 }
1256
1257 static bool
1258 nvc0_bind_images_range(struct nvc0_context *nvc0, const unsigned s,
1259 unsigned start, unsigned nr,
1260 const struct pipe_image_view *pimages)
1261 {
1262 const unsigned end = start + nr;
1263 unsigned mask = 0;
1264 unsigned i;
1265
1266 assert(s < 6);
1267
1268 if (pimages) {
1269 for (i = start; i < end; ++i) {
1270 struct pipe_image_view *img = &nvc0->images[s][i];
1271 const unsigned p = i - start;
1272
1273 if (img->resource == pimages[p].resource &&
1274 img->format == pimages[p].format &&
1275 img->access == pimages[p].access) {
1276 if (img->resource == NULL)
1277 continue;
1278 if (img->resource->target == PIPE_BUFFER &&
1279 img->u.buf.offset == pimages[p].u.buf.offset &&
1280 img->u.buf.size == pimages[p].u.buf.size)
1281 continue;
1282 if (img->resource->target != PIPE_BUFFER &&
1283 img->u.tex.first_layer == pimages[p].u.tex.first_layer &&
1284 img->u.tex.last_layer == pimages[p].u.tex.last_layer &&
1285 img->u.tex.level == pimages[p].u.tex.level)
1286 continue;
1287 }
1288
1289 mask |= (1 << i);
1290 if (pimages[p].resource)
1291 nvc0->images_valid[s] |= (1 << i);
1292 else
1293 nvc0->images_valid[s] &= ~(1 << i);
1294
1295 img->format = pimages[p].format;
1296 img->access = pimages[p].access;
1297 if (pimages[p].resource && pimages[p].resource->target == PIPE_BUFFER)
1298 img->u.buf = pimages[p].u.buf;
1299 else
1300 img->u.tex = pimages[p].u.tex;
1301
1302 pipe_resource_reference(
1303 &img->resource, pimages[p].resource);
1304
1305 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1306 if (nvc0->images_tic[s][i]) {
1307 struct nv50_tic_entry *old =
1308 nv50_tic_entry(nvc0->images_tic[s][i]);
1309 nvc0_screen_tic_unlock(nvc0->screen, old);
1310 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1311 }
1312
1313 nvc0->images_tic[s][i] =
1314 gm107_create_texture_view_from_image(&nvc0->base.pipe,
1315 &pimages[p]);
1316 }
1317 }
1318 if (!mask)
1319 return false;
1320 } else {
1321 mask = ((1 << nr) - 1) << start;
1322 if (!(nvc0->images_valid[s] & mask))
1323 return false;
1324 for (i = start; i < end; ++i) {
1325 pipe_resource_reference(&nvc0->images[s][i].resource, NULL);
1326 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1327 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->images_tic[s][i]);
1328 if (old) {
1329 nvc0_screen_tic_unlock(nvc0->screen, old);
1330 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1331 }
1332 }
1333 }
1334 nvc0->images_valid[s] &= ~mask;
1335 }
1336 nvc0->images_dirty[s] |= mask;
1337
1338 if (s == 5)
1339 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1340 else
1341 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1342
1343 return true;
1344 }
1345
1346 static void
1347 nvc0_set_shader_images(struct pipe_context *pipe,
1348 enum pipe_shader_type shader,
1349 unsigned start, unsigned nr,
1350 const struct pipe_image_view *images)
1351 {
1352 const unsigned s = nvc0_shader_stage(shader);
1353 if (!nvc0_bind_images_range(nvc0_context(pipe), s, start, nr, images))
1354 return;
1355
1356 if (s == 5)
1357 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1358 else
1359 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SURFACES;
1360 }
1361
1362 static bool
1363 nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t,
1364 unsigned start, unsigned nr,
1365 const struct pipe_shader_buffer *pbuffers)
1366 {
1367 const unsigned end = start + nr;
1368 unsigned mask = 0;
1369 unsigned i;
1370
1371 assert(t < 6);
1372
1373 if (pbuffers) {
1374 for (i = start; i < end; ++i) {
1375 struct pipe_shader_buffer *buf = &nvc0->buffers[t][i];
1376 const unsigned p = i - start;
1377 if (buf->buffer == pbuffers[p].buffer &&
1378 buf->buffer_offset == pbuffers[p].buffer_offset &&
1379 buf->buffer_size == pbuffers[p].buffer_size)
1380 continue;
1381
1382 mask |= (1 << i);
1383 if (pbuffers[p].buffer)
1384 nvc0->buffers_valid[t] |= (1 << i);
1385 else
1386 nvc0->buffers_valid[t] &= ~(1 << i);
1387 buf->buffer_offset = pbuffers[p].buffer_offset;
1388 buf->buffer_size = pbuffers[p].buffer_size;
1389 pipe_resource_reference(&buf->buffer, pbuffers[p].buffer);
1390 }
1391 if (!mask)
1392 return false;
1393 } else {
1394 mask = ((1 << nr) - 1) << start;
1395 if (!(nvc0->buffers_valid[t] & mask))
1396 return false;
1397 for (i = start; i < end; ++i)
1398 pipe_resource_reference(&nvc0->buffers[t][i].buffer, NULL);
1399 nvc0->buffers_valid[t] &= ~mask;
1400 }
1401 nvc0->buffers_dirty[t] |= mask;
1402
1403 if (t == 5)
1404 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF);
1405 else
1406 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BUF);
1407
1408 return true;
1409 }
1410
1411 static void
1412 nvc0_set_shader_buffers(struct pipe_context *pipe,
1413 enum pipe_shader_type shader,
1414 unsigned start, unsigned nr,
1415 const struct pipe_shader_buffer *buffers)
1416 {
1417 const unsigned s = nvc0_shader_stage(shader);
1418 if (!nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers))
1419 return;
1420
1421 if (s == 5)
1422 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_BUFFERS;
1423 else
1424 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_BUFFERS;
1425 }
1426
1427 static inline void
1428 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1429 {
1430 struct nv04_resource *buf = nv04_resource(res);
1431 if (buf) {
1432 uint64_t limit = (buf->address + buf->base.width0) - 1;
1433 if (limit < (1ULL << 32)) {
1434 *phandle = (uint32_t)buf->address;
1435 } else {
1436 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1437 "resource not contained within 32-bit address space !\n");
1438 *phandle = 0;
1439 }
1440 } else {
1441 *phandle = 0;
1442 }
1443 }
1444
1445 static void
1446 nvc0_set_global_bindings(struct pipe_context *pipe,
1447 unsigned start, unsigned nr,
1448 struct pipe_resource **resources,
1449 uint32_t **handles)
1450 {
1451 struct nvc0_context *nvc0 = nvc0_context(pipe);
1452 struct pipe_resource **ptr;
1453 unsigned i;
1454 const unsigned end = start + nr;
1455
1456 if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1457 const unsigned old_size = nvc0->global_residents.size;
1458 const unsigned req_size = end * sizeof(struct pipe_resource *);
1459 util_dynarray_resize(&nvc0->global_residents, req_size);
1460 memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1461 req_size - old_size);
1462 }
1463
1464 if (resources) {
1465 ptr = util_dynarray_element(
1466 &nvc0->global_residents, struct pipe_resource *, start);
1467 for (i = 0; i < nr; ++i) {
1468 pipe_resource_reference(&ptr[i], resources[i]);
1469 nvc0_set_global_handle(handles[i], resources[i]);
1470 }
1471 } else {
1472 ptr = util_dynarray_element(
1473 &nvc0->global_residents, struct pipe_resource *, start);
1474 for (i = 0; i < nr; ++i)
1475 pipe_resource_reference(&ptr[i], NULL);
1476 }
1477
1478 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1479
1480 nvc0->dirty_cp |= NVC0_NEW_CP_GLOBALS;
1481 }
1482
1483 void
1484 nvc0_init_state_functions(struct nvc0_context *nvc0)
1485 {
1486 struct pipe_context *pipe = &nvc0->base.pipe;
1487
1488 pipe->create_blend_state = nvc0_blend_state_create;
1489 pipe->bind_blend_state = nvc0_blend_state_bind;
1490 pipe->delete_blend_state = nvc0_blend_state_delete;
1491
1492 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1493 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1494 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1495
1496 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1497 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1498 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1499
1500 pipe->create_sampler_state = nv50_sampler_state_create;
1501 pipe->delete_sampler_state = nvc0_sampler_state_delete;
1502 pipe->bind_sampler_states = nvc0_bind_sampler_states;
1503
1504 pipe->create_sampler_view = nvc0_create_sampler_view;
1505 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1506 pipe->set_sampler_views = nvc0_set_sampler_views;
1507
1508 pipe->create_vs_state = nvc0_vp_state_create;
1509 pipe->create_fs_state = nvc0_fp_state_create;
1510 pipe->create_gs_state = nvc0_gp_state_create;
1511 pipe->create_tcs_state = nvc0_tcp_state_create;
1512 pipe->create_tes_state = nvc0_tep_state_create;
1513 pipe->bind_vs_state = nvc0_vp_state_bind;
1514 pipe->bind_fs_state = nvc0_fp_state_bind;
1515 pipe->bind_gs_state = nvc0_gp_state_bind;
1516 pipe->bind_tcs_state = nvc0_tcp_state_bind;
1517 pipe->bind_tes_state = nvc0_tep_state_bind;
1518 pipe->delete_vs_state = nvc0_sp_state_delete;
1519 pipe->delete_fs_state = nvc0_sp_state_delete;
1520 pipe->delete_gs_state = nvc0_sp_state_delete;
1521 pipe->delete_tcs_state = nvc0_sp_state_delete;
1522 pipe->delete_tes_state = nvc0_sp_state_delete;
1523
1524 pipe->create_compute_state = nvc0_cp_state_create;
1525 pipe->bind_compute_state = nvc0_cp_state_bind;
1526 pipe->delete_compute_state = nvc0_sp_state_delete;
1527
1528 pipe->set_blend_color = nvc0_set_blend_color;
1529 pipe->set_stencil_ref = nvc0_set_stencil_ref;
1530 pipe->set_clip_state = nvc0_set_clip_state;
1531 pipe->set_sample_mask = nvc0_set_sample_mask;
1532 pipe->set_min_samples = nvc0_set_min_samples;
1533 pipe->set_constant_buffer = nvc0_set_constant_buffer;
1534 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1535 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1536 pipe->set_scissor_states = nvc0_set_scissor_states;
1537 pipe->set_viewport_states = nvc0_set_viewport_states;
1538 pipe->set_window_rectangles = nvc0_set_window_rectangles;
1539 pipe->set_tess_state = nvc0_set_tess_state;
1540
1541 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1542 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1543 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1544
1545 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1546 pipe->set_index_buffer = nvc0_set_index_buffer;
1547
1548 pipe->create_stream_output_target = nvc0_so_target_create;
1549 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1550 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1551
1552 pipe->set_global_binding = nvc0_set_global_bindings;
1553 pipe->set_compute_resources = nvc0_set_compute_resources;
1554 pipe->set_shader_images = nvc0_set_shader_images;
1555 pipe->set_shader_buffers = nvc0_set_shader_buffers;
1556
1557 nvc0->sample_mask = ~0;
1558 nvc0->min_samples = 1;
1559 nvc0->default_tess_outer[0] =
1560 nvc0->default_tess_outer[1] =
1561 nvc0->default_tess_outer[2] =
1562 nvc0->default_tess_outer[3] = 1.0;
1563 nvc0->default_tess_inner[0] =
1564 nvc0->default_tess_inner[1] = 1.0;
1565 }