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Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_helpers.h"
25 #include "util/u_inlines.h"
26 #include "util/u_transfer.h"
27
28 #include "tgsi/tgsi_parse.h"
29
30 #include "nvc0/nvc0_stateobj.h"
31 #include "nvc0/nvc0_context.h"
32 #include "nvc0/nvc0_query_hw.h"
33
34 #include "nvc0/nvc0_3d.xml.h"
35 #include "nv50/nv50_texture.xml.h"
36
37 #include "nouveau_gldefs.h"
38
39 static inline uint32_t
40 nvc0_colormask(unsigned mask)
41 {
42 uint32_t ret = 0;
43
44 if (mask & PIPE_MASK_R)
45 ret |= 0x0001;
46 if (mask & PIPE_MASK_G)
47 ret |= 0x0010;
48 if (mask & PIPE_MASK_B)
49 ret |= 0x0100;
50 if (mask & PIPE_MASK_A)
51 ret |= 0x1000;
52
53 return ret;
54 }
55
56 #define NVC0_BLEND_FACTOR_CASE(a, b) \
57 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
58
59 static inline uint32_t
60 nvc0_blend_fac(unsigned factor)
61 {
62 switch (factor) {
63 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
64 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
65 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
66 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
67 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
68 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
69 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
70 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
71 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
72 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
73 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
74 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
75 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
76 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
77 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
78 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
79 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
80 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
81 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
82 default:
83 return NV50_BLEND_FACTOR_ZERO;
84 }
85 }
86
87 static void *
88 nvc0_blend_state_create(struct pipe_context *pipe,
89 const struct pipe_blend_state *cso)
90 {
91 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
92 int i;
93 int r; /* reference */
94 uint8_t blend_en = 0;
95 bool indep_masks = false;
96 bool indep_funcs = false;
97
98 so->pipe = *cso;
99
100 /* check which states actually have differing values */
101 if (cso->independent_blend_enable) {
102 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
103 blend_en |= 1 << r;
104 for (i = r + 1; i < 8; ++i) {
105 if (!cso->rt[i].blend_enable)
106 continue;
107 blend_en |= 1 << i;
108 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
109 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
110 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
111 cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
112 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
113 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
114 indep_funcs = true;
115 break;
116 }
117 }
118 for (; i < 8; ++i)
119 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
120
121 for (i = 1; i < 8; ++i) {
122 if (cso->rt[i].colormask != cso->rt[0].colormask) {
123 indep_masks = true;
124 break;
125 }
126 }
127 } else {
128 r = 0;
129 if (cso->rt[0].blend_enable)
130 blend_en = 0xff;
131 }
132
133 if (cso->logicop_enable) {
134 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
135 SB_DATA (so, 1);
136 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
137
138 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
139 } else {
140 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
141
142 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
143 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
144 if (indep_funcs) {
145 for (i = 0; i < 8; ++i) {
146 if (cso->rt[i].blend_enable) {
147 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
148 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
149 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
150 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
151 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
152 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
153 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
154 }
155 }
156 } else
157 if (blend_en) {
158 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
159 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
160 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
161 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
162 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
163 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
164 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
165 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
166 }
167
168 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
169 if (indep_masks) {
170 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
171 for (i = 0; i < 8; ++i)
172 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
173 } else {
174 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
175 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
176 }
177 }
178
179 assert(so->size <= ARRAY_SIZE(so->state));
180 return so;
181 }
182
183 static void
184 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
185 {
186 struct nvc0_context *nvc0 = nvc0_context(pipe);
187
188 nvc0->blend = hwcso;
189 nvc0->dirty |= NVC0_NEW_BLEND;
190 }
191
192 static void
193 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
194 {
195 FREE(hwcso);
196 }
197
198 /* NOTE: ignoring line_last_pixel */
199 static void *
200 nvc0_rasterizer_state_create(struct pipe_context *pipe,
201 const struct pipe_rasterizer_state *cso)
202 {
203 struct nvc0_rasterizer_stateobj *so;
204 uint32_t reg;
205
206 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
207 if (!so)
208 return NULL;
209 so->pipe = *cso;
210
211 /* Scissor enables are handled in scissor state, we will not want to
212 * always emit 16 commands, one for each scissor rectangle, here.
213 */
214
215 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
216 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
217
218 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
219 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
220 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
221
222 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
223
224 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
225 if (cso->line_smooth || cso->multisample)
226 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
227 else
228 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
229 SB_DATA (so, fui(cso->line_width));
230
231 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
232 if (cso->line_stipple_enable) {
233 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
234 SB_DATA (so, (cso->line_stipple_pattern << 8) |
235 cso->line_stipple_factor);
236
237 }
238
239 SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
240 if (!cso->point_size_per_vertex) {
241 SB_BEGIN_3D(so, POINT_SIZE, 1);
242 SB_DATA (so, fui(cso->point_size));
243 }
244
245 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
246 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
247 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
248
249 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
250 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
251 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
252 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
253
254 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
255 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
256 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
257 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
258 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
259
260 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
261 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
262 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
263 NVC0_3D_FRONT_FACE_CW);
264 switch (cso->cull_face) {
265 case PIPE_FACE_FRONT_AND_BACK:
266 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
267 break;
268 case PIPE_FACE_FRONT:
269 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
270 break;
271 case PIPE_FACE_BACK:
272 default:
273 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
274 break;
275 }
276
277 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
278 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
279 SB_DATA (so, cso->offset_point);
280 SB_DATA (so, cso->offset_line);
281 SB_DATA (so, cso->offset_tri);
282
283 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
284 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
285 SB_DATA (so, fui(cso->offset_scale));
286 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
287 SB_DATA (so, fui(cso->offset_units * 2.0f));
288 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
289 SB_DATA (so, fui(cso->offset_clamp));
290 }
291
292 if (cso->depth_clip)
293 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
294 else
295 reg =
296 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
297 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
298 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
299 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
300
301 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
302 SB_DATA (so, reg);
303
304 SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
305
306 SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
307
308 assert(so->size <= ARRAY_SIZE(so->state));
309 return (void *)so;
310 }
311
312 static void
313 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
314 {
315 struct nvc0_context *nvc0 = nvc0_context(pipe);
316
317 nvc0->rast = hwcso;
318 nvc0->dirty |= NVC0_NEW_RASTERIZER;
319 }
320
321 static void
322 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
323 {
324 FREE(hwcso);
325 }
326
327 static void *
328 nvc0_zsa_state_create(struct pipe_context *pipe,
329 const struct pipe_depth_stencil_alpha_state *cso)
330 {
331 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
332
333 so->pipe = *cso;
334
335 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
336 if (cso->depth.enabled) {
337 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
338 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
339 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
340 }
341
342 SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth.bounds_test);
343 if (cso->depth.bounds_test) {
344 SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
345 SB_DATA (so, fui(cso->depth.bounds_min));
346 SB_DATA (so, fui(cso->depth.bounds_max));
347 }
348
349 if (cso->stencil[0].enabled) {
350 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
351 SB_DATA (so, 1);
352 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
353 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
354 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
355 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
356 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
357 SB_DATA (so, cso->stencil[0].valuemask);
358 SB_DATA (so, cso->stencil[0].writemask);
359 } else {
360 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
361 }
362
363 if (cso->stencil[1].enabled) {
364 assert(cso->stencil[0].enabled);
365 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
366 SB_DATA (so, 1);
367 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
368 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
369 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
370 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
371 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
372 SB_DATA (so, cso->stencil[1].writemask);
373 SB_DATA (so, cso->stencil[1].valuemask);
374 } else
375 if (cso->stencil[0].enabled) {
376 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
377 }
378
379 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
380 if (cso->alpha.enabled) {
381 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
382 SB_DATA (so, fui(cso->alpha.ref_value));
383 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
384 }
385
386 assert(so->size <= ARRAY_SIZE(so->state));
387 return (void *)so;
388 }
389
390 static void
391 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
392 {
393 struct nvc0_context *nvc0 = nvc0_context(pipe);
394
395 nvc0->zsa = hwcso;
396 nvc0->dirty |= NVC0_NEW_ZSA;
397 }
398
399 static void
400 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
401 {
402 FREE(hwcso);
403 }
404
405 /* ====================== SAMPLERS AND TEXTURES ================================
406 */
407
408 #define NV50_TSC_WRAP_CASE(n) \
409 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
410
411 static void
412 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
413 {
414 unsigned s, i;
415
416 for (s = 0; s < 5; ++s)
417 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
418 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
419 nvc0_context(pipe)->samplers[s][i] = NULL;
420
421 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
422
423 FREE(hwcso);
424 }
425
426 static inline void
427 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0, int s,
428 unsigned nr, void **hwcso)
429 {
430 unsigned i;
431
432 for (i = 0; i < nr; ++i) {
433 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
434
435 if (hwcso[i] == old)
436 continue;
437 nvc0->samplers_dirty[s] |= 1 << i;
438
439 nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
440 if (old)
441 nvc0_screen_tsc_unlock(nvc0->screen, old);
442 }
443 for (; i < nvc0->num_samplers[s]; ++i) {
444 if (nvc0->samplers[s][i]) {
445 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
446 nvc0->samplers[s][i] = NULL;
447 }
448 }
449
450 nvc0->num_samplers[s] = nr;
451
452 nvc0->dirty |= NVC0_NEW_SAMPLERS;
453 }
454
455 static void
456 nvc0_stage_sampler_states_bind_range(struct nvc0_context *nvc0,
457 const unsigned s,
458 unsigned start, unsigned nr, void **cso)
459 {
460 const unsigned end = start + nr;
461 int last_valid = -1;
462 unsigned i;
463
464 if (cso) {
465 for (i = start; i < end; ++i) {
466 const unsigned p = i - start;
467 if (cso[p])
468 last_valid = i;
469 if (cso[p] == nvc0->samplers[s][i])
470 continue;
471 nvc0->samplers_dirty[s] |= 1 << i;
472
473 if (nvc0->samplers[s][i])
474 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
475 nvc0->samplers[s][i] = cso[p];
476 }
477 } else {
478 for (i = start; i < end; ++i) {
479 if (nvc0->samplers[s][i]) {
480 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
481 nvc0->samplers[s][i] = NULL;
482 nvc0->samplers_dirty[s] |= 1 << i;
483 }
484 }
485 }
486
487 if (nvc0->num_samplers[s] <= end) {
488 if (last_valid < 0) {
489 for (i = start; i && !nvc0->samplers[s][i - 1]; --i);
490 nvc0->num_samplers[s] = i;
491 } else {
492 nvc0->num_samplers[s] = last_valid + 1;
493 }
494 }
495 }
496
497 static void
498 nvc0_bind_sampler_states(struct pipe_context *pipe, unsigned shader,
499 unsigned start, unsigned nr, void **s)
500 {
501 switch (shader) {
502 case PIPE_SHADER_VERTEX:
503 assert(start == 0);
504 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 0, nr, s);
505 break;
506 case PIPE_SHADER_TESS_CTRL:
507 assert(start == 0);
508 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 1, nr, s);
509 break;
510 case PIPE_SHADER_TESS_EVAL:
511 assert(start == 0);
512 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 2, nr, s);
513 break;
514 case PIPE_SHADER_GEOMETRY:
515 assert(start == 0);
516 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 3, nr, s);
517 break;
518 case PIPE_SHADER_FRAGMENT:
519 assert(start == 0);
520 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 4, nr, s);
521 break;
522 case PIPE_SHADER_COMPUTE:
523 nvc0_stage_sampler_states_bind_range(nvc0_context(pipe), 5,
524 start, nr, s);
525 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
526 break;
527 }
528 }
529
530
531 /* NOTE: only called when not referenced anywhere, won't be bound */
532 static void
533 nvc0_sampler_view_destroy(struct pipe_context *pipe,
534 struct pipe_sampler_view *view)
535 {
536 pipe_resource_reference(&view->texture, NULL);
537
538 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
539
540 FREE(nv50_tic_entry(view));
541 }
542
543 static inline void
544 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
545 unsigned nr,
546 struct pipe_sampler_view **views)
547 {
548 unsigned i;
549
550 for (i = 0; i < nr; ++i) {
551 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
552
553 if (views[i] == nvc0->textures[s][i])
554 continue;
555 nvc0->textures_dirty[s] |= 1 << i;
556
557 if (old) {
558 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(s, i));
559 nvc0_screen_tic_unlock(nvc0->screen, old);
560 }
561
562 pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
563 }
564
565 for (i = nr; i < nvc0->num_textures[s]; ++i) {
566 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
567 if (old) {
568 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(s, i));
569 nvc0_screen_tic_unlock(nvc0->screen, old);
570 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
571 }
572 }
573
574 nvc0->num_textures[s] = nr;
575
576 nvc0->dirty |= NVC0_NEW_TEXTURES;
577 }
578
579 static void
580 nvc0_stage_set_sampler_views_range(struct nvc0_context *nvc0, const unsigned s,
581 unsigned start, unsigned nr,
582 struct pipe_sampler_view **views)
583 {
584 struct nouveau_bufctx *bctx = (s == 5) ? nvc0->bufctx_cp : nvc0->bufctx_3d;
585 const unsigned end = start + nr;
586 const unsigned bin = (s == 5) ? NVC0_BIND_CP_TEX(0) : NVC0_BIND_TEX(s, 0);
587 int last_valid = -1;
588 unsigned i;
589
590 if (views) {
591 for (i = start; i < end; ++i) {
592 const unsigned p = i - start;
593 if (views[p])
594 last_valid = i;
595 if (views[p] == nvc0->textures[s][i])
596 continue;
597 nvc0->textures_dirty[s] |= 1 << i;
598
599 if (nvc0->textures[s][i]) {
600 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
601 nouveau_bufctx_reset(bctx, bin + i);
602 nvc0_screen_tic_unlock(nvc0->screen, old);
603 }
604 pipe_sampler_view_reference(&nvc0->textures[s][i], views[p]);
605 }
606 } else {
607 for (i = start; i < end; ++i) {
608 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
609 if (!old)
610 continue;
611 nvc0->textures_dirty[s] |= 1 << i;
612
613 nvc0_screen_tic_unlock(nvc0->screen, old);
614 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
615 nouveau_bufctx_reset(bctx, bin + i);
616 }
617 }
618
619 if (nvc0->num_textures[s] <= end) {
620 if (last_valid < 0) {
621 for (i = start; i && !nvc0->textures[s][i - 1]; --i);
622 nvc0->num_textures[s] = i;
623 } else {
624 nvc0->num_textures[s] = last_valid + 1;
625 }
626 }
627 }
628
629 static void
630 nvc0_set_sampler_views(struct pipe_context *pipe, unsigned shader,
631 unsigned start, unsigned nr,
632 struct pipe_sampler_view **views)
633 {
634 assert(start == 0);
635 switch (shader) {
636 case PIPE_SHADER_VERTEX:
637 nvc0_stage_set_sampler_views(nvc0_context(pipe), 0, nr, views);
638 break;
639 case PIPE_SHADER_TESS_CTRL:
640 nvc0_stage_set_sampler_views(nvc0_context(pipe), 1, nr, views);
641 break;
642 case PIPE_SHADER_TESS_EVAL:
643 nvc0_stage_set_sampler_views(nvc0_context(pipe), 2, nr, views);
644 break;
645 case PIPE_SHADER_GEOMETRY:
646 nvc0_stage_set_sampler_views(nvc0_context(pipe), 3, nr, views);
647 break;
648 case PIPE_SHADER_FRAGMENT:
649 nvc0_stage_set_sampler_views(nvc0_context(pipe), 4, nr, views);
650 break;
651 case PIPE_SHADER_COMPUTE:
652 nvc0_stage_set_sampler_views_range(nvc0_context(pipe), 5,
653 start, nr, views);
654 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
655 break;
656 default:
657 ;
658 }
659 }
660
661
662 /* ============================= SHADERS =======================================
663 */
664
665 static void *
666 nvc0_sp_state_create(struct pipe_context *pipe,
667 const struct pipe_shader_state *cso, unsigned type)
668 {
669 struct nvc0_program *prog;
670
671 prog = CALLOC_STRUCT(nvc0_program);
672 if (!prog)
673 return NULL;
674
675 prog->type = type;
676
677 if (cso->tokens)
678 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
679
680 if (cso->stream_output.num_outputs)
681 prog->pipe.stream_output = cso->stream_output;
682
683 prog->translated = nvc0_program_translate(
684 prog, nvc0_context(pipe)->screen->base.device->chipset,
685 &nouveau_context(pipe)->debug);
686
687 return (void *)prog;
688 }
689
690 static void
691 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
692 {
693 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
694
695 nvc0_program_destroy(nvc0_context(pipe), prog);
696
697 FREE((void *)prog->pipe.tokens);
698 FREE(prog);
699 }
700
701 static void *
702 nvc0_vp_state_create(struct pipe_context *pipe,
703 const struct pipe_shader_state *cso)
704 {
705 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
706 }
707
708 static void
709 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
710 {
711 struct nvc0_context *nvc0 = nvc0_context(pipe);
712
713 nvc0->vertprog = hwcso;
714 nvc0->dirty |= NVC0_NEW_VERTPROG;
715 }
716
717 static void *
718 nvc0_fp_state_create(struct pipe_context *pipe,
719 const struct pipe_shader_state *cso)
720 {
721 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
722 }
723
724 static void
725 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
726 {
727 struct nvc0_context *nvc0 = nvc0_context(pipe);
728
729 nvc0->fragprog = hwcso;
730 nvc0->dirty |= NVC0_NEW_FRAGPROG;
731 }
732
733 static void *
734 nvc0_gp_state_create(struct pipe_context *pipe,
735 const struct pipe_shader_state *cso)
736 {
737 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
738 }
739
740 static void
741 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
742 {
743 struct nvc0_context *nvc0 = nvc0_context(pipe);
744
745 nvc0->gmtyprog = hwcso;
746 nvc0->dirty |= NVC0_NEW_GMTYPROG;
747 }
748
749 static void *
750 nvc0_tcp_state_create(struct pipe_context *pipe,
751 const struct pipe_shader_state *cso)
752 {
753 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
754 }
755
756 static void
757 nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
758 {
759 struct nvc0_context *nvc0 = nvc0_context(pipe);
760
761 nvc0->tctlprog = hwcso;
762 nvc0->dirty |= NVC0_NEW_TCTLPROG;
763 }
764
765 static void *
766 nvc0_tep_state_create(struct pipe_context *pipe,
767 const struct pipe_shader_state *cso)
768 {
769 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
770 }
771
772 static void
773 nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
774 {
775 struct nvc0_context *nvc0 = nvc0_context(pipe);
776
777 nvc0->tevlprog = hwcso;
778 nvc0->dirty |= NVC0_NEW_TEVLPROG;
779 }
780
781 static void *
782 nvc0_cp_state_create(struct pipe_context *pipe,
783 const struct pipe_compute_state *cso)
784 {
785 struct nvc0_program *prog;
786
787 prog = CALLOC_STRUCT(nvc0_program);
788 if (!prog)
789 return NULL;
790 prog->type = PIPE_SHADER_COMPUTE;
791
792 prog->cp.smem_size = cso->req_local_mem;
793 prog->cp.lmem_size = cso->req_private_mem;
794 prog->parm_size = cso->req_input_mem;
795
796 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
797
798 return (void *)prog;
799 }
800
801 static void
802 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
803 {
804 struct nvc0_context *nvc0 = nvc0_context(pipe);
805
806 nvc0->compprog = hwcso;
807 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
808 }
809
810 static void
811 nvc0_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
812 struct pipe_constant_buffer *cb)
813 {
814 struct nvc0_context *nvc0 = nvc0_context(pipe);
815 struct pipe_resource *res = cb ? cb->buffer : NULL;
816 const unsigned s = nvc0_shader_stage(shader);
817 const unsigned i = index;
818
819 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
820 assert(!cb || !cb->user_buffer);
821 if (nvc0->constbuf[s][i].u.buf)
822 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
823
824 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
825 } else {
826 if (nvc0->constbuf[s][i].user)
827 nvc0->constbuf[s][i].u.buf = NULL;
828 else
829 if (nvc0->constbuf[s][i].u.buf)
830 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_CB(s, i));
831
832 nvc0->dirty |= NVC0_NEW_CONSTBUF;
833 }
834 nvc0->constbuf_dirty[s] |= 1 << i;
835
836 if (nvc0->constbuf[s][i].u.buf)
837 nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
838 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
839
840 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
841 if (nvc0->constbuf[s][i].user) {
842 nvc0->constbuf[s][i].u.data = cb->user_buffer;
843 nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
844 nvc0->constbuf_valid[s] |= 1 << i;
845 } else
846 if (cb) {
847 nvc0->constbuf[s][i].offset = cb->buffer_offset;
848 nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
849 nvc0->constbuf_valid[s] |= 1 << i;
850 }
851 else {
852 nvc0->constbuf_valid[s] &= ~(1 << i);
853 }
854 }
855
856 /* =============================================================================
857 */
858
859 static void
860 nvc0_set_blend_color(struct pipe_context *pipe,
861 const struct pipe_blend_color *bcol)
862 {
863 struct nvc0_context *nvc0 = nvc0_context(pipe);
864
865 nvc0->blend_colour = *bcol;
866 nvc0->dirty |= NVC0_NEW_BLEND_COLOUR;
867 }
868
869 static void
870 nvc0_set_stencil_ref(struct pipe_context *pipe,
871 const struct pipe_stencil_ref *sr)
872 {
873 struct nvc0_context *nvc0 = nvc0_context(pipe);
874
875 nvc0->stencil_ref = *sr;
876 nvc0->dirty |= NVC0_NEW_STENCIL_REF;
877 }
878
879 static void
880 nvc0_set_clip_state(struct pipe_context *pipe,
881 const struct pipe_clip_state *clip)
882 {
883 struct nvc0_context *nvc0 = nvc0_context(pipe);
884
885 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
886
887 nvc0->dirty |= NVC0_NEW_CLIP;
888 }
889
890 static void
891 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
892 {
893 struct nvc0_context *nvc0 = nvc0_context(pipe);
894
895 nvc0->sample_mask = sample_mask;
896 nvc0->dirty |= NVC0_NEW_SAMPLE_MASK;
897 }
898
899 static void
900 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
901 {
902 struct nvc0_context *nvc0 = nvc0_context(pipe);
903
904 if (nvc0->min_samples != min_samples) {
905 nvc0->min_samples = min_samples;
906 nvc0->dirty |= NVC0_NEW_MIN_SAMPLES;
907 }
908 }
909
910 static void
911 nvc0_set_framebuffer_state(struct pipe_context *pipe,
912 const struct pipe_framebuffer_state *fb)
913 {
914 struct nvc0_context *nvc0 = nvc0_context(pipe);
915 unsigned i;
916
917 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
918
919 for (i = 0; i < fb->nr_cbufs; ++i)
920 pipe_surface_reference(&nvc0->framebuffer.cbufs[i], fb->cbufs[i]);
921 for (; i < nvc0->framebuffer.nr_cbufs; ++i)
922 pipe_surface_reference(&nvc0->framebuffer.cbufs[i], NULL);
923
924 nvc0->framebuffer.nr_cbufs = fb->nr_cbufs;
925
926 nvc0->framebuffer.width = fb->width;
927 nvc0->framebuffer.height = fb->height;
928
929 pipe_surface_reference(&nvc0->framebuffer.zsbuf, fb->zsbuf);
930
931 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
932 }
933
934 static void
935 nvc0_set_polygon_stipple(struct pipe_context *pipe,
936 const struct pipe_poly_stipple *stipple)
937 {
938 struct nvc0_context *nvc0 = nvc0_context(pipe);
939
940 nvc0->stipple = *stipple;
941 nvc0->dirty |= NVC0_NEW_STIPPLE;
942 }
943
944 static void
945 nvc0_set_scissor_states(struct pipe_context *pipe,
946 unsigned start_slot,
947 unsigned num_scissors,
948 const struct pipe_scissor_state *scissor)
949 {
950 struct nvc0_context *nvc0 = nvc0_context(pipe);
951 int i;
952
953 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
954 for (i = 0; i < num_scissors; i++) {
955 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
956 continue;
957 nvc0->scissors[start_slot + i] = scissor[i];
958 nvc0->scissors_dirty |= 1 << (start_slot + i);
959 nvc0->dirty |= NVC0_NEW_SCISSOR;
960 }
961 }
962
963 static void
964 nvc0_set_viewport_states(struct pipe_context *pipe,
965 unsigned start_slot,
966 unsigned num_viewports,
967 const struct pipe_viewport_state *vpt)
968 {
969 struct nvc0_context *nvc0 = nvc0_context(pipe);
970 int i;
971
972 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
973 for (i = 0; i < num_viewports; i++) {
974 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
975 continue;
976 nvc0->viewports[start_slot + i] = vpt[i];
977 nvc0->viewports_dirty |= 1 << (start_slot + i);
978 nvc0->dirty |= NVC0_NEW_VIEWPORT;
979 }
980
981 }
982
983 static void
984 nvc0_set_tess_state(struct pipe_context *pipe,
985 const float default_tess_outer[4],
986 const float default_tess_inner[2])
987 {
988 struct nvc0_context *nvc0 = nvc0_context(pipe);
989
990 memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
991 memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
992 nvc0->dirty |= NVC0_NEW_TESSFACTOR;
993 }
994
995 static void
996 nvc0_set_vertex_buffers(struct pipe_context *pipe,
997 unsigned start_slot, unsigned count,
998 const struct pipe_vertex_buffer *vb)
999 {
1000 struct nvc0_context *nvc0 = nvc0_context(pipe);
1001 unsigned i;
1002
1003 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX);
1004 nvc0->dirty |= NVC0_NEW_ARRAYS;
1005
1006 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
1007 start_slot, count);
1008
1009 if (!vb) {
1010 nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
1011 nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
1012 return;
1013 }
1014
1015 for (i = 0; i < count; ++i) {
1016 unsigned dst_index = start_slot + i;
1017
1018 if (vb[i].user_buffer) {
1019 nvc0->vbo_user |= 1 << dst_index;
1020 if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
1021 nvc0->constant_vbos |= 1 << dst_index;
1022 else
1023 nvc0->constant_vbos &= ~(1 << dst_index);
1024 } else {
1025 nvc0->vbo_user &= ~(1 << dst_index);
1026 nvc0->constant_vbos &= ~(1 << dst_index);
1027 }
1028 }
1029 }
1030
1031 static void
1032 nvc0_set_index_buffer(struct pipe_context *pipe,
1033 const struct pipe_index_buffer *ib)
1034 {
1035 struct nvc0_context *nvc0 = nvc0_context(pipe);
1036
1037 if (nvc0->idxbuf.buffer)
1038 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_IDX);
1039
1040 if (ib) {
1041 pipe_resource_reference(&nvc0->idxbuf.buffer, ib->buffer);
1042 nvc0->idxbuf.index_size = ib->index_size;
1043 if (ib->buffer) {
1044 nvc0->idxbuf.offset = ib->offset;
1045 nvc0->dirty |= NVC0_NEW_IDXBUF;
1046 } else {
1047 nvc0->idxbuf.user_buffer = ib->user_buffer;
1048 nvc0->dirty &= ~NVC0_NEW_IDXBUF;
1049 }
1050 } else {
1051 nvc0->dirty &= ~NVC0_NEW_IDXBUF;
1052 pipe_resource_reference(&nvc0->idxbuf.buffer, NULL);
1053 }
1054 }
1055
1056 static void
1057 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1058 {
1059 struct nvc0_context *nvc0 = nvc0_context(pipe);
1060
1061 nvc0->vertex = hwcso;
1062 nvc0->dirty |= NVC0_NEW_VERTEX;
1063 }
1064
1065 static struct pipe_stream_output_target *
1066 nvc0_so_target_create(struct pipe_context *pipe,
1067 struct pipe_resource *res,
1068 unsigned offset, unsigned size)
1069 {
1070 struct nv04_resource *buf = (struct nv04_resource *)res;
1071 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1072 if (!targ)
1073 return NULL;
1074
1075 targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0);
1076 if (!targ->pq) {
1077 FREE(targ);
1078 return NULL;
1079 }
1080 targ->clean = true;
1081
1082 targ->pipe.buffer_size = size;
1083 targ->pipe.buffer_offset = offset;
1084 targ->pipe.context = pipe;
1085 targ->pipe.buffer = NULL;
1086 pipe_resource_reference(&targ->pipe.buffer, res);
1087 pipe_reference_init(&targ->pipe.reference, 1);
1088
1089 assert(buf->base.target == PIPE_BUFFER);
1090 util_range_add(&buf->valid_buffer_range, offset, offset + size);
1091
1092 return &targ->pipe;
1093 }
1094
1095 static void
1096 nvc0_so_target_save_offset(struct pipe_context *pipe,
1097 struct pipe_stream_output_target *ptarg,
1098 unsigned index, bool *serialize)
1099 {
1100 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1101
1102 if (*serialize) {
1103 *serialize = false;
1104 PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
1105 IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
1106
1107 NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
1108 }
1109
1110 nvc0_query(targ->pq)->index = index;
1111 pipe->end_query(pipe, targ->pq);
1112 }
1113
1114 static void
1115 nvc0_so_target_destroy(struct pipe_context *pipe,
1116 struct pipe_stream_output_target *ptarg)
1117 {
1118 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1119 pipe->destroy_query(pipe, targ->pq);
1120 pipe_resource_reference(&targ->pipe.buffer, NULL);
1121 FREE(targ);
1122 }
1123
1124 static void
1125 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1126 unsigned num_targets,
1127 struct pipe_stream_output_target **targets,
1128 const unsigned *offsets)
1129 {
1130 struct nvc0_context *nvc0 = nvc0_context(pipe);
1131 unsigned i;
1132 bool serialize = true;
1133
1134 assert(num_targets <= 4);
1135
1136 for (i = 0; i < num_targets; ++i) {
1137 const bool changed = nvc0->tfbbuf[i] != targets[i];
1138 const bool append = (offsets[i] == ((unsigned)-1));
1139 if (!changed && append)
1140 continue;
1141 nvc0->tfbbuf_dirty |= 1 << i;
1142
1143 if (nvc0->tfbbuf[i] && changed)
1144 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1145
1146 if (targets[i] && !append)
1147 nvc0_so_target(targets[i])->clean = true;
1148
1149 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1150 }
1151 for (; i < nvc0->num_tfbbufs; ++i) {
1152 if (nvc0->tfbbuf[i]) {
1153 nvc0->tfbbuf_dirty |= 1 << i;
1154 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1155 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1156 }
1157 }
1158 nvc0->num_tfbbufs = num_targets;
1159
1160 if (nvc0->tfbbuf_dirty)
1161 nvc0->dirty |= NVC0_NEW_TFB_TARGETS;
1162 }
1163
1164 static void
1165 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1166 unsigned start, unsigned nr,
1167 struct pipe_surface **psurfaces)
1168 {
1169 const unsigned end = start + nr;
1170 const unsigned mask = ((1 << nr) - 1) << start;
1171 unsigned i;
1172
1173 if (psurfaces) {
1174 for (i = start; i < end; ++i) {
1175 const unsigned p = i - start;
1176 if (psurfaces[p])
1177 nvc0->surfaces_valid[t] |= (1 << i);
1178 else
1179 nvc0->surfaces_valid[t] &= ~(1 << i);
1180 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1181 }
1182 } else {
1183 for (i = start; i < end; ++i)
1184 pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1185 nvc0->surfaces_valid[t] &= ~mask;
1186 }
1187 nvc0->surfaces_dirty[t] |= mask;
1188
1189 if (t == 0)
1190 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_SUF);
1191 else
1192 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1193 }
1194
1195 static void
1196 nvc0_set_compute_resources(struct pipe_context *pipe,
1197 unsigned start, unsigned nr,
1198 struct pipe_surface **resources)
1199 {
1200 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1201
1202 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1203 }
1204
1205 static void
1206 nvc0_set_shader_images(struct pipe_context *pipe, unsigned shader,
1207 unsigned start_slot, unsigned count,
1208 struct pipe_image_view **views)
1209 {
1210 #if 0
1211 nvc0_bind_surfaces_range(nvc0_context(pipe), 0, start, nr, views);
1212
1213 nvc0_context(pipe)->dirty |= NVC0_NEW_SURFACES;
1214 #endif
1215 }
1216
1217 static inline void
1218 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1219 {
1220 struct nv04_resource *buf = nv04_resource(res);
1221 if (buf) {
1222 uint64_t limit = (buf->address + buf->base.width0) - 1;
1223 if (limit < (1ULL << 32)) {
1224 *phandle = (uint32_t)buf->address;
1225 } else {
1226 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1227 "resource not contained within 32-bit address space !\n");
1228 *phandle = 0;
1229 }
1230 } else {
1231 *phandle = 0;
1232 }
1233 }
1234
1235 static void
1236 nvc0_set_global_bindings(struct pipe_context *pipe,
1237 unsigned start, unsigned nr,
1238 struct pipe_resource **resources,
1239 uint32_t **handles)
1240 {
1241 struct nvc0_context *nvc0 = nvc0_context(pipe);
1242 struct pipe_resource **ptr;
1243 unsigned i;
1244 const unsigned end = start + nr;
1245
1246 if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1247 const unsigned old_size = nvc0->global_residents.size;
1248 const unsigned req_size = end * sizeof(struct pipe_resource *);
1249 util_dynarray_resize(&nvc0->global_residents, req_size);
1250 memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1251 req_size - old_size);
1252 }
1253
1254 if (resources) {
1255 ptr = util_dynarray_element(
1256 &nvc0->global_residents, struct pipe_resource *, start);
1257 for (i = 0; i < nr; ++i) {
1258 pipe_resource_reference(&ptr[i], resources[i]);
1259 nvc0_set_global_handle(handles[i], resources[i]);
1260 }
1261 } else {
1262 ptr = util_dynarray_element(
1263 &nvc0->global_residents, struct pipe_resource *, start);
1264 for (i = 0; i < nr; ++i)
1265 pipe_resource_reference(&ptr[i], NULL);
1266 }
1267
1268 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1269
1270 nvc0->dirty_cp = NVC0_NEW_CP_GLOBALS;
1271 }
1272
1273 void
1274 nvc0_init_state_functions(struct nvc0_context *nvc0)
1275 {
1276 struct pipe_context *pipe = &nvc0->base.pipe;
1277
1278 pipe->create_blend_state = nvc0_blend_state_create;
1279 pipe->bind_blend_state = nvc0_blend_state_bind;
1280 pipe->delete_blend_state = nvc0_blend_state_delete;
1281
1282 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1283 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1284 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1285
1286 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1287 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1288 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1289
1290 pipe->create_sampler_state = nv50_sampler_state_create;
1291 pipe->delete_sampler_state = nvc0_sampler_state_delete;
1292 pipe->bind_sampler_states = nvc0_bind_sampler_states;
1293
1294 pipe->create_sampler_view = nvc0_create_sampler_view;
1295 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1296 pipe->set_sampler_views = nvc0_set_sampler_views;
1297
1298 pipe->create_vs_state = nvc0_vp_state_create;
1299 pipe->create_fs_state = nvc0_fp_state_create;
1300 pipe->create_gs_state = nvc0_gp_state_create;
1301 pipe->create_tcs_state = nvc0_tcp_state_create;
1302 pipe->create_tes_state = nvc0_tep_state_create;
1303 pipe->bind_vs_state = nvc0_vp_state_bind;
1304 pipe->bind_fs_state = nvc0_fp_state_bind;
1305 pipe->bind_gs_state = nvc0_gp_state_bind;
1306 pipe->bind_tcs_state = nvc0_tcp_state_bind;
1307 pipe->bind_tes_state = nvc0_tep_state_bind;
1308 pipe->delete_vs_state = nvc0_sp_state_delete;
1309 pipe->delete_fs_state = nvc0_sp_state_delete;
1310 pipe->delete_gs_state = nvc0_sp_state_delete;
1311 pipe->delete_tcs_state = nvc0_sp_state_delete;
1312 pipe->delete_tes_state = nvc0_sp_state_delete;
1313
1314 pipe->create_compute_state = nvc0_cp_state_create;
1315 pipe->bind_compute_state = nvc0_cp_state_bind;
1316 pipe->delete_compute_state = nvc0_sp_state_delete;
1317
1318 pipe->set_blend_color = nvc0_set_blend_color;
1319 pipe->set_stencil_ref = nvc0_set_stencil_ref;
1320 pipe->set_clip_state = nvc0_set_clip_state;
1321 pipe->set_sample_mask = nvc0_set_sample_mask;
1322 pipe->set_min_samples = nvc0_set_min_samples;
1323 pipe->set_constant_buffer = nvc0_set_constant_buffer;
1324 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1325 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1326 pipe->set_scissor_states = nvc0_set_scissor_states;
1327 pipe->set_viewport_states = nvc0_set_viewport_states;
1328 pipe->set_tess_state = nvc0_set_tess_state;
1329
1330 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1331 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1332 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1333
1334 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1335 pipe->set_index_buffer = nvc0_set_index_buffer;
1336
1337 pipe->create_stream_output_target = nvc0_so_target_create;
1338 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1339 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1340
1341 pipe->set_global_binding = nvc0_set_global_bindings;
1342 pipe->set_compute_resources = nvc0_set_compute_resources;
1343 pipe->set_shader_images = nvc0_set_shader_images;
1344
1345 nvc0->sample_mask = ~0;
1346 nvc0->min_samples = 1;
1347 nvc0->default_tess_outer[0] =
1348 nvc0->default_tess_outer[1] =
1349 nvc0->default_tess_outer[2] =
1350 nvc0->default_tess_outer[3] = 1.0;
1351 nvc0->default_tess_inner[0] =
1352 nvc0->default_tess_inner[1] = 1.0;
1353 }