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nvc0: preliminary tess support
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_helpers.h"
25 #include "util/u_inlines.h"
26 #include "util/u_transfer.h"
27
28 #include "tgsi/tgsi_parse.h"
29
30 #include "nvc0/nvc0_stateobj.h"
31 #include "nvc0/nvc0_context.h"
32
33 #include "nvc0/nvc0_3d.xml.h"
34 #include "nv50/nv50_texture.xml.h"
35
36 #include "nouveau_gldefs.h"
37
38 static inline uint32_t
39 nvc0_colormask(unsigned mask)
40 {
41 uint32_t ret = 0;
42
43 if (mask & PIPE_MASK_R)
44 ret |= 0x0001;
45 if (mask & PIPE_MASK_G)
46 ret |= 0x0010;
47 if (mask & PIPE_MASK_B)
48 ret |= 0x0100;
49 if (mask & PIPE_MASK_A)
50 ret |= 0x1000;
51
52 return ret;
53 }
54
55 #define NVC0_BLEND_FACTOR_CASE(a, b) \
56 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
57
58 static inline uint32_t
59 nvc0_blend_fac(unsigned factor)
60 {
61 switch (factor) {
62 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
63 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
64 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
65 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
66 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
67 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
68 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
69 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
70 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
71 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
72 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
73 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
74 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
75 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
76 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
77 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
78 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
79 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
80 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
81 default:
82 return NV50_BLEND_FACTOR_ZERO;
83 }
84 }
85
86 static void *
87 nvc0_blend_state_create(struct pipe_context *pipe,
88 const struct pipe_blend_state *cso)
89 {
90 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
91 int i;
92 int r; /* reference */
93 uint32_t ms;
94 uint8_t blend_en = 0;
95 bool indep_masks = false;
96 bool indep_funcs = false;
97
98 so->pipe = *cso;
99
100 /* check which states actually have differing values */
101 if (cso->independent_blend_enable) {
102 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
103 blend_en |= 1 << r;
104 for (i = r + 1; i < 8; ++i) {
105 if (!cso->rt[i].blend_enable)
106 continue;
107 blend_en |= 1 << i;
108 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
109 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
110 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
111 cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
112 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
113 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
114 indep_funcs = true;
115 break;
116 }
117 }
118 for (; i < 8; ++i)
119 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
120
121 for (i = 1; i < 8; ++i) {
122 if (cso->rt[i].colormask != cso->rt[0].colormask) {
123 indep_masks = true;
124 break;
125 }
126 }
127 } else {
128 r = 0;
129 if (cso->rt[0].blend_enable)
130 blend_en = 0xff;
131 }
132
133 if (cso->logicop_enable) {
134 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
135 SB_DATA (so, 1);
136 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
137
138 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
139 } else {
140 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
141
142 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
143 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
144 if (indep_funcs) {
145 for (i = 0; i < 8; ++i) {
146 if (cso->rt[i].blend_enable) {
147 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
148 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
149 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
150 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
151 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
152 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
153 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
154 }
155 }
156 } else
157 if (blend_en) {
158 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
159 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
160 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
161 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
162 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
163 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
164 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
165 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
166 }
167
168 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
169 if (indep_masks) {
170 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
171 for (i = 0; i < 8; ++i)
172 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
173 } else {
174 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
175 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
176 }
177 }
178
179 ms = 0;
180 if (cso->alpha_to_coverage)
181 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
182 if (cso->alpha_to_one)
183 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
184
185 SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
186 SB_DATA (so, ms);
187
188 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
189 return so;
190 }
191
192 static void
193 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
194 {
195 struct nvc0_context *nvc0 = nvc0_context(pipe);
196
197 nvc0->blend = hwcso;
198 nvc0->dirty |= NVC0_NEW_BLEND;
199 }
200
201 static void
202 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
203 {
204 FREE(hwcso);
205 }
206
207 /* NOTE: ignoring line_last_pixel */
208 static void *
209 nvc0_rasterizer_state_create(struct pipe_context *pipe,
210 const struct pipe_rasterizer_state *cso)
211 {
212 struct nvc0_rasterizer_stateobj *so;
213 uint32_t reg;
214
215 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
216 if (!so)
217 return NULL;
218 so->pipe = *cso;
219
220 /* Scissor enables are handled in scissor state, we will not want to
221 * always emit 16 commands, one for each scissor rectangle, here.
222 */
223
224 SB_BEGIN_3D(so, SHADE_MODEL, 1);
225 SB_DATA (so, cso->flatshade ? NVC0_3D_SHADE_MODEL_FLAT :
226 NVC0_3D_SHADE_MODEL_SMOOTH);
227 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
228 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
229
230 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
231 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
232 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
233
234 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
235
236 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
237 if (cso->line_smooth)
238 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
239 else
240 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
241 SB_DATA (so, fui(cso->line_width));
242
243 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
244 if (cso->line_stipple_enable) {
245 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
246 SB_DATA (so, (cso->line_stipple_pattern << 8) |
247 cso->line_stipple_factor);
248
249 }
250
251 SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
252 if (!cso->point_size_per_vertex) {
253 SB_BEGIN_3D(so, POINT_SIZE, 1);
254 SB_DATA (so, fui(cso->point_size));
255 }
256
257 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
258 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
259 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
260
261 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
262 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
263 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
264 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
265
266 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
267 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
268 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
269 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
270 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
271
272 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
273 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
274 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
275 NVC0_3D_FRONT_FACE_CW);
276 switch (cso->cull_face) {
277 case PIPE_FACE_FRONT_AND_BACK:
278 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
279 break;
280 case PIPE_FACE_FRONT:
281 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
282 break;
283 case PIPE_FACE_BACK:
284 default:
285 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
286 break;
287 }
288
289 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
290 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
291 SB_DATA (so, cso->offset_point);
292 SB_DATA (so, cso->offset_line);
293 SB_DATA (so, cso->offset_tri);
294
295 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
296 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
297 SB_DATA (so, fui(cso->offset_scale));
298 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
299 SB_DATA (so, fui(cso->offset_units * 2.0f));
300 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
301 SB_DATA (so, fui(cso->offset_clamp));
302 }
303
304 if (cso->depth_clip)
305 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
306 else
307 reg =
308 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
309 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
310 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
311 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
312
313 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
314 SB_DATA (so, reg);
315
316 SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
317
318 SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
319
320 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
321 return (void *)so;
322 }
323
324 static void
325 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
326 {
327 struct nvc0_context *nvc0 = nvc0_context(pipe);
328
329 nvc0->rast = hwcso;
330 nvc0->dirty |= NVC0_NEW_RASTERIZER;
331 }
332
333 static void
334 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
335 {
336 FREE(hwcso);
337 }
338
339 static void *
340 nvc0_zsa_state_create(struct pipe_context *pipe,
341 const struct pipe_depth_stencil_alpha_state *cso)
342 {
343 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
344
345 so->pipe = *cso;
346
347 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
348 if (cso->depth.enabled) {
349 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
350 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
351 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
352 }
353
354 if (cso->stencil[0].enabled) {
355 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
356 SB_DATA (so, 1);
357 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
358 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
359 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
360 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
361 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
362 SB_DATA (so, cso->stencil[0].valuemask);
363 SB_DATA (so, cso->stencil[0].writemask);
364 } else {
365 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
366 }
367
368 if (cso->stencil[1].enabled) {
369 assert(cso->stencil[0].enabled);
370 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
371 SB_DATA (so, 1);
372 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
373 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
374 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
375 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
376 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
377 SB_DATA (so, cso->stencil[1].writemask);
378 SB_DATA (so, cso->stencil[1].valuemask);
379 } else
380 if (cso->stencil[0].enabled) {
381 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
382 }
383
384 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
385 if (cso->alpha.enabled) {
386 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
387 SB_DATA (so, fui(cso->alpha.ref_value));
388 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
389 }
390
391 assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
392 return (void *)so;
393 }
394
395 static void
396 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
397 {
398 struct nvc0_context *nvc0 = nvc0_context(pipe);
399
400 nvc0->zsa = hwcso;
401 nvc0->dirty |= NVC0_NEW_ZSA;
402 }
403
404 static void
405 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
406 {
407 FREE(hwcso);
408 }
409
410 /* ====================== SAMPLERS AND TEXTURES ================================
411 */
412
413 #define NV50_TSC_WRAP_CASE(n) \
414 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
415
416 static void
417 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
418 {
419 unsigned s, i;
420
421 for (s = 0; s < 5; ++s)
422 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
423 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
424 nvc0_context(pipe)->samplers[s][i] = NULL;
425
426 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
427
428 FREE(hwcso);
429 }
430
431 static inline void
432 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0, int s,
433 unsigned nr, void **hwcso)
434 {
435 unsigned i;
436
437 for (i = 0; i < nr; ++i) {
438 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
439
440 if (hwcso[i] == old)
441 continue;
442 nvc0->samplers_dirty[s] |= 1 << i;
443
444 nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
445 if (old)
446 nvc0_screen_tsc_unlock(nvc0->screen, old);
447 }
448 for (; i < nvc0->num_samplers[s]; ++i) {
449 if (nvc0->samplers[s][i]) {
450 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
451 nvc0->samplers[s][i] = NULL;
452 }
453 }
454
455 nvc0->num_samplers[s] = nr;
456
457 nvc0->dirty |= NVC0_NEW_SAMPLERS;
458 }
459
460 static void
461 nvc0_stage_sampler_states_bind_range(struct nvc0_context *nvc0,
462 const unsigned s,
463 unsigned start, unsigned nr, void **cso)
464 {
465 const unsigned end = start + nr;
466 int last_valid = -1;
467 unsigned i;
468
469 if (cso) {
470 for (i = start; i < end; ++i) {
471 const unsigned p = i - start;
472 if (cso[p])
473 last_valid = i;
474 if (cso[p] == nvc0->samplers[s][i])
475 continue;
476 nvc0->samplers_dirty[s] |= 1 << i;
477
478 if (nvc0->samplers[s][i])
479 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
480 nvc0->samplers[s][i] = cso[p];
481 }
482 } else {
483 for (i = start; i < end; ++i) {
484 if (nvc0->samplers[s][i]) {
485 nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
486 nvc0->samplers[s][i] = NULL;
487 nvc0->samplers_dirty[s] |= 1 << i;
488 }
489 }
490 }
491
492 if (nvc0->num_samplers[s] <= end) {
493 if (last_valid < 0) {
494 for (i = start; i && !nvc0->samplers[s][i - 1]; --i);
495 nvc0->num_samplers[s] = i;
496 } else {
497 nvc0->num_samplers[s] = last_valid + 1;
498 }
499 }
500 }
501
502 static void
503 nvc0_bind_sampler_states(struct pipe_context *pipe, unsigned shader,
504 unsigned start, unsigned nr, void **s)
505 {
506 switch (shader) {
507 case PIPE_SHADER_VERTEX:
508 assert(start == 0);
509 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 0, nr, s);
510 break;
511 case PIPE_SHADER_TESS_CTRL:
512 assert(start == 0);
513 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 1, nr, s);
514 break;
515 case PIPE_SHADER_TESS_EVAL:
516 assert(start == 0);
517 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 2, nr, s);
518 break;
519 case PIPE_SHADER_GEOMETRY:
520 assert(start == 0);
521 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 3, nr, s);
522 break;
523 case PIPE_SHADER_FRAGMENT:
524 assert(start == 0);
525 nvc0_stage_sampler_states_bind(nvc0_context(pipe), 4, nr, s);
526 break;
527 case PIPE_SHADER_COMPUTE:
528 nvc0_stage_sampler_states_bind_range(nvc0_context(pipe), 5,
529 start, nr, s);
530 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
531 break;
532 }
533 }
534
535
536 /* NOTE: only called when not referenced anywhere, won't be bound */
537 static void
538 nvc0_sampler_view_destroy(struct pipe_context *pipe,
539 struct pipe_sampler_view *view)
540 {
541 pipe_resource_reference(&view->texture, NULL);
542
543 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
544
545 FREE(nv50_tic_entry(view));
546 }
547
548 static inline void
549 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
550 unsigned nr,
551 struct pipe_sampler_view **views)
552 {
553 unsigned i;
554
555 for (i = 0; i < nr; ++i) {
556 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
557
558 if (views[i] == nvc0->textures[s][i])
559 continue;
560 nvc0->textures_dirty[s] |= 1 << i;
561
562 if (old) {
563 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(s, i));
564 nvc0_screen_tic_unlock(nvc0->screen, old);
565 }
566
567 pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
568 }
569
570 for (i = nr; i < nvc0->num_textures[s]; ++i) {
571 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
572 if (old) {
573 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_TEX(s, i));
574 nvc0_screen_tic_unlock(nvc0->screen, old);
575 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
576 }
577 }
578
579 nvc0->num_textures[s] = nr;
580
581 nvc0->dirty |= NVC0_NEW_TEXTURES;
582 }
583
584 static void
585 nvc0_stage_set_sampler_views_range(struct nvc0_context *nvc0, const unsigned s,
586 unsigned start, unsigned nr,
587 struct pipe_sampler_view **views)
588 {
589 struct nouveau_bufctx *bctx = (s == 5) ? nvc0->bufctx_cp : nvc0->bufctx_3d;
590 const unsigned end = start + nr;
591 const unsigned bin = (s == 5) ? NVC0_BIND_CP_TEX(0) : NVC0_BIND_TEX(s, 0);
592 int last_valid = -1;
593 unsigned i;
594
595 if (views) {
596 for (i = start; i < end; ++i) {
597 const unsigned p = i - start;
598 if (views[p])
599 last_valid = i;
600 if (views[p] == nvc0->textures[s][i])
601 continue;
602 nvc0->textures_dirty[s] |= 1 << i;
603
604 if (nvc0->textures[s][i]) {
605 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
606 nouveau_bufctx_reset(bctx, bin + i);
607 nvc0_screen_tic_unlock(nvc0->screen, old);
608 }
609 pipe_sampler_view_reference(&nvc0->textures[s][i], views[p]);
610 }
611 } else {
612 for (i = start; i < end; ++i) {
613 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
614 if (!old)
615 continue;
616 nvc0->textures_dirty[s] |= 1 << i;
617
618 nvc0_screen_tic_unlock(nvc0->screen, old);
619 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
620 nouveau_bufctx_reset(bctx, bin + i);
621 }
622 }
623
624 if (nvc0->num_textures[s] <= end) {
625 if (last_valid < 0) {
626 for (i = start; i && !nvc0->textures[s][i - 1]; --i);
627 nvc0->num_textures[s] = i;
628 } else {
629 nvc0->num_textures[s] = last_valid + 1;
630 }
631 }
632 }
633
634 static void
635 nvc0_set_sampler_views(struct pipe_context *pipe, unsigned shader,
636 unsigned start, unsigned nr,
637 struct pipe_sampler_view **views)
638 {
639 assert(start == 0);
640 switch (shader) {
641 case PIPE_SHADER_VERTEX:
642 nvc0_stage_set_sampler_views(nvc0_context(pipe), 0, nr, views);
643 break;
644 case PIPE_SHADER_TESS_CTRL:
645 nvc0_stage_set_sampler_views(nvc0_context(pipe), 1, nr, views);
646 break;
647 case PIPE_SHADER_TESS_EVAL:
648 nvc0_stage_set_sampler_views(nvc0_context(pipe), 2, nr, views);
649 break;
650 case PIPE_SHADER_GEOMETRY:
651 nvc0_stage_set_sampler_views(nvc0_context(pipe), 3, nr, views);
652 break;
653 case PIPE_SHADER_FRAGMENT:
654 nvc0_stage_set_sampler_views(nvc0_context(pipe), 4, nr, views);
655 break;
656 case PIPE_SHADER_COMPUTE:
657 nvc0_stage_set_sampler_views_range(nvc0_context(pipe), 5,
658 start, nr, views);
659 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
660 break;
661 default:
662 ;
663 }
664 }
665
666
667 /* ============================= SHADERS =======================================
668 */
669
670 static void *
671 nvc0_sp_state_create(struct pipe_context *pipe,
672 const struct pipe_shader_state *cso, unsigned type)
673 {
674 struct nvc0_program *prog;
675
676 prog = CALLOC_STRUCT(nvc0_program);
677 if (!prog)
678 return NULL;
679
680 prog->type = type;
681
682 if (cso->tokens)
683 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
684
685 if (cso->stream_output.num_outputs)
686 prog->pipe.stream_output = cso->stream_output;
687
688 return (void *)prog;
689 }
690
691 static void
692 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
693 {
694 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
695
696 nvc0_program_destroy(nvc0_context(pipe), prog);
697
698 FREE((void *)prog->pipe.tokens);
699 FREE(prog);
700 }
701
702 static void *
703 nvc0_vp_state_create(struct pipe_context *pipe,
704 const struct pipe_shader_state *cso)
705 {
706 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
707 }
708
709 static void
710 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
711 {
712 struct nvc0_context *nvc0 = nvc0_context(pipe);
713
714 nvc0->vertprog = hwcso;
715 nvc0->dirty |= NVC0_NEW_VERTPROG;
716 }
717
718 static void *
719 nvc0_fp_state_create(struct pipe_context *pipe,
720 const struct pipe_shader_state *cso)
721 {
722 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
723 }
724
725 static void
726 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
727 {
728 struct nvc0_context *nvc0 = nvc0_context(pipe);
729
730 nvc0->fragprog = hwcso;
731 nvc0->dirty |= NVC0_NEW_FRAGPROG;
732 }
733
734 static void *
735 nvc0_gp_state_create(struct pipe_context *pipe,
736 const struct pipe_shader_state *cso)
737 {
738 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
739 }
740
741 static void
742 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
743 {
744 struct nvc0_context *nvc0 = nvc0_context(pipe);
745
746 nvc0->gmtyprog = hwcso;
747 nvc0->dirty |= NVC0_NEW_GMTYPROG;
748 }
749
750 static void *
751 nvc0_tcp_state_create(struct pipe_context *pipe,
752 const struct pipe_shader_state *cso)
753 {
754 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
755 }
756
757 static void
758 nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
759 {
760 struct nvc0_context *nvc0 = nvc0_context(pipe);
761
762 nvc0->tctlprog = hwcso;
763 nvc0->dirty |= NVC0_NEW_TCTLPROG;
764 }
765
766 static void *
767 nvc0_tep_state_create(struct pipe_context *pipe,
768 const struct pipe_shader_state *cso)
769 {
770 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
771 }
772
773 static void
774 nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
775 {
776 struct nvc0_context *nvc0 = nvc0_context(pipe);
777
778 nvc0->tevlprog = hwcso;
779 nvc0->dirty |= NVC0_NEW_TEVLPROG;
780 }
781
782 static void *
783 nvc0_cp_state_create(struct pipe_context *pipe,
784 const struct pipe_compute_state *cso)
785 {
786 struct nvc0_program *prog;
787
788 prog = CALLOC_STRUCT(nvc0_program);
789 if (!prog)
790 return NULL;
791 prog->type = PIPE_SHADER_COMPUTE;
792
793 prog->cp.smem_size = cso->req_local_mem;
794 prog->cp.lmem_size = cso->req_private_mem;
795 prog->parm_size = cso->req_input_mem;
796
797 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
798
799 return (void *)prog;
800 }
801
802 static void
803 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
804 {
805 struct nvc0_context *nvc0 = nvc0_context(pipe);
806
807 nvc0->compprog = hwcso;
808 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
809 }
810
811 static void
812 nvc0_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index,
813 struct pipe_constant_buffer *cb)
814 {
815 struct nvc0_context *nvc0 = nvc0_context(pipe);
816 struct pipe_resource *res = cb ? cb->buffer : NULL;
817 const unsigned s = nvc0_shader_stage(shader);
818 const unsigned i = index;
819
820 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
821 assert(!cb || !cb->user_buffer);
822 if (nvc0->constbuf[s][i].u.buf)
823 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
824
825 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
826 } else {
827 if (nvc0->constbuf[s][i].user)
828 nvc0->constbuf[s][i].u.buf = NULL;
829 else
830 if (nvc0->constbuf[s][i].u.buf)
831 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_CB(s, i));
832
833 nvc0->dirty |= NVC0_NEW_CONSTBUF;
834 }
835 nvc0->constbuf_dirty[s] |= 1 << i;
836
837 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
838
839 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
840 if (nvc0->constbuf[s][i].user) {
841 nvc0->constbuf[s][i].u.data = cb->user_buffer;
842 nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
843 nvc0->constbuf_valid[s] |= 1 << i;
844 } else
845 if (cb) {
846 nvc0->constbuf[s][i].offset = cb->buffer_offset;
847 nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
848 nvc0->constbuf_valid[s] |= 1 << i;
849 }
850 else {
851 nvc0->constbuf_valid[s] &= ~(1 << i);
852 }
853 }
854
855 /* =============================================================================
856 */
857
858 static void
859 nvc0_set_blend_color(struct pipe_context *pipe,
860 const struct pipe_blend_color *bcol)
861 {
862 struct nvc0_context *nvc0 = nvc0_context(pipe);
863
864 nvc0->blend_colour = *bcol;
865 nvc0->dirty |= NVC0_NEW_BLEND_COLOUR;
866 }
867
868 static void
869 nvc0_set_stencil_ref(struct pipe_context *pipe,
870 const struct pipe_stencil_ref *sr)
871 {
872 struct nvc0_context *nvc0 = nvc0_context(pipe);
873
874 nvc0->stencil_ref = *sr;
875 nvc0->dirty |= NVC0_NEW_STENCIL_REF;
876 }
877
878 static void
879 nvc0_set_clip_state(struct pipe_context *pipe,
880 const struct pipe_clip_state *clip)
881 {
882 struct nvc0_context *nvc0 = nvc0_context(pipe);
883
884 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
885
886 nvc0->dirty |= NVC0_NEW_CLIP;
887 }
888
889 static void
890 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
891 {
892 struct nvc0_context *nvc0 = nvc0_context(pipe);
893
894 nvc0->sample_mask = sample_mask;
895 nvc0->dirty |= NVC0_NEW_SAMPLE_MASK;
896 }
897
898 static void
899 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
900 {
901 struct nvc0_context *nvc0 = nvc0_context(pipe);
902
903 if (nvc0->min_samples != min_samples) {
904 nvc0->min_samples = min_samples;
905 nvc0->dirty |= NVC0_NEW_MIN_SAMPLES;
906 }
907 }
908
909 static void
910 nvc0_set_framebuffer_state(struct pipe_context *pipe,
911 const struct pipe_framebuffer_state *fb)
912 {
913 struct nvc0_context *nvc0 = nvc0_context(pipe);
914 unsigned i;
915
916 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_FB);
917
918 for (i = 0; i < fb->nr_cbufs; ++i)
919 pipe_surface_reference(&nvc0->framebuffer.cbufs[i], fb->cbufs[i]);
920 for (; i < nvc0->framebuffer.nr_cbufs; ++i)
921 pipe_surface_reference(&nvc0->framebuffer.cbufs[i], NULL);
922
923 nvc0->framebuffer.nr_cbufs = fb->nr_cbufs;
924
925 nvc0->framebuffer.width = fb->width;
926 nvc0->framebuffer.height = fb->height;
927
928 pipe_surface_reference(&nvc0->framebuffer.zsbuf, fb->zsbuf);
929
930 nvc0->dirty |= NVC0_NEW_FRAMEBUFFER;
931 }
932
933 static void
934 nvc0_set_polygon_stipple(struct pipe_context *pipe,
935 const struct pipe_poly_stipple *stipple)
936 {
937 struct nvc0_context *nvc0 = nvc0_context(pipe);
938
939 nvc0->stipple = *stipple;
940 nvc0->dirty |= NVC0_NEW_STIPPLE;
941 }
942
943 static void
944 nvc0_set_scissor_states(struct pipe_context *pipe,
945 unsigned start_slot,
946 unsigned num_scissors,
947 const struct pipe_scissor_state *scissor)
948 {
949 struct nvc0_context *nvc0 = nvc0_context(pipe);
950 int i;
951
952 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
953 for (i = 0; i < num_scissors; i++) {
954 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
955 continue;
956 nvc0->scissors[start_slot + i] = scissor[i];
957 nvc0->scissors_dirty |= 1 << (start_slot + i);
958 nvc0->dirty |= NVC0_NEW_SCISSOR;
959 }
960 }
961
962 static void
963 nvc0_set_viewport_states(struct pipe_context *pipe,
964 unsigned start_slot,
965 unsigned num_viewports,
966 const struct pipe_viewport_state *vpt)
967 {
968 struct nvc0_context *nvc0 = nvc0_context(pipe);
969 int i;
970
971 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
972 for (i = 0; i < num_viewports; i++) {
973 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
974 continue;
975 nvc0->viewports[start_slot + i] = vpt[i];
976 nvc0->viewports_dirty |= 1 << (start_slot + i);
977 nvc0->dirty |= NVC0_NEW_VIEWPORT;
978 }
979
980 }
981
982 static void
983 nvc0_set_vertex_buffers(struct pipe_context *pipe,
984 unsigned start_slot, unsigned count,
985 const struct pipe_vertex_buffer *vb)
986 {
987 struct nvc0_context *nvc0 = nvc0_context(pipe);
988 unsigned i;
989
990 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
991 start_slot, count);
992
993 if (!vb) {
994 nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
995 nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
996 return;
997 }
998
999 for (i = 0; i < count; ++i) {
1000 unsigned dst_index = start_slot + i;
1001
1002 if (vb[i].user_buffer) {
1003 nvc0->vbo_user |= 1 << dst_index;
1004 if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
1005 nvc0->constant_vbos |= 1 << dst_index;
1006 else
1007 nvc0->constant_vbos &= ~(1 << dst_index);
1008 } else {
1009 nvc0->vbo_user &= ~(1 << dst_index);
1010 nvc0->constant_vbos &= ~(1 << dst_index);
1011 }
1012 }
1013
1014 nvc0->dirty |= NVC0_NEW_ARRAYS;
1015 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX);
1016 }
1017
1018 static void
1019 nvc0_set_index_buffer(struct pipe_context *pipe,
1020 const struct pipe_index_buffer *ib)
1021 {
1022 struct nvc0_context *nvc0 = nvc0_context(pipe);
1023
1024 if (nvc0->idxbuf.buffer)
1025 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_IDX);
1026
1027 if (ib) {
1028 pipe_resource_reference(&nvc0->idxbuf.buffer, ib->buffer);
1029 nvc0->idxbuf.index_size = ib->index_size;
1030 if (ib->buffer) {
1031 nvc0->idxbuf.offset = ib->offset;
1032 nvc0->dirty |= NVC0_NEW_IDXBUF;
1033 } else {
1034 nvc0->idxbuf.user_buffer = ib->user_buffer;
1035 nvc0->dirty &= ~NVC0_NEW_IDXBUF;
1036 }
1037 } else {
1038 nvc0->dirty &= ~NVC0_NEW_IDXBUF;
1039 pipe_resource_reference(&nvc0->idxbuf.buffer, NULL);
1040 }
1041 }
1042
1043 static void
1044 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1045 {
1046 struct nvc0_context *nvc0 = nvc0_context(pipe);
1047
1048 nvc0->vertex = hwcso;
1049 nvc0->dirty |= NVC0_NEW_VERTEX;
1050 }
1051
1052 static struct pipe_stream_output_target *
1053 nvc0_so_target_create(struct pipe_context *pipe,
1054 struct pipe_resource *res,
1055 unsigned offset, unsigned size)
1056 {
1057 struct nv04_resource *buf = (struct nv04_resource *)res;
1058 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1059 if (!targ)
1060 return NULL;
1061
1062 targ->pq = pipe->create_query(pipe, NVC0_QUERY_TFB_BUFFER_OFFSET, 0);
1063 if (!targ->pq) {
1064 FREE(targ);
1065 return NULL;
1066 }
1067 targ->clean = true;
1068
1069 targ->pipe.buffer_size = size;
1070 targ->pipe.buffer_offset = offset;
1071 targ->pipe.context = pipe;
1072 targ->pipe.buffer = NULL;
1073 pipe_resource_reference(&targ->pipe.buffer, res);
1074 pipe_reference_init(&targ->pipe.reference, 1);
1075
1076 assert(buf->base.target == PIPE_BUFFER);
1077 util_range_add(&buf->valid_buffer_range, offset, offset + size);
1078
1079 return &targ->pipe;
1080 }
1081
1082 static void
1083 nvc0_so_target_destroy(struct pipe_context *pipe,
1084 struct pipe_stream_output_target *ptarg)
1085 {
1086 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1087 pipe->destroy_query(pipe, targ->pq);
1088 pipe_resource_reference(&targ->pipe.buffer, NULL);
1089 FREE(targ);
1090 }
1091
1092 static void
1093 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1094 unsigned num_targets,
1095 struct pipe_stream_output_target **targets,
1096 const unsigned *offsets)
1097 {
1098 struct nvc0_context *nvc0 = nvc0_context(pipe);
1099 unsigned i;
1100 bool serialize = true;
1101
1102 assert(num_targets <= 4);
1103
1104 for (i = 0; i < num_targets; ++i) {
1105 const bool changed = nvc0->tfbbuf[i] != targets[i];
1106 const bool append = (offsets[i] == ((unsigned)-1));
1107 if (!changed && append)
1108 continue;
1109 nvc0->tfbbuf_dirty |= 1 << i;
1110
1111 if (nvc0->tfbbuf[i] && changed)
1112 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1113
1114 if (targets[i] && !append)
1115 nvc0_so_target(targets[i])->clean = true;
1116
1117 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1118 }
1119 for (; i < nvc0->num_tfbbufs; ++i) {
1120 if (nvc0->tfbbuf[i]) {
1121 nvc0->tfbbuf_dirty |= 1 << i;
1122 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1123 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1124 }
1125 }
1126 nvc0->num_tfbbufs = num_targets;
1127
1128 if (nvc0->tfbbuf_dirty)
1129 nvc0->dirty |= NVC0_NEW_TFB_TARGETS;
1130 }
1131
1132 static void
1133 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1134 unsigned start, unsigned nr,
1135 struct pipe_surface **psurfaces)
1136 {
1137 const unsigned end = start + nr;
1138 const unsigned mask = ((1 << nr) - 1) << start;
1139 unsigned i;
1140
1141 if (psurfaces) {
1142 for (i = start; i < end; ++i) {
1143 const unsigned p = i - start;
1144 if (psurfaces[p])
1145 nvc0->surfaces_valid[t] |= (1 << i);
1146 else
1147 nvc0->surfaces_valid[t] &= ~(1 << i);
1148 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1149 }
1150 } else {
1151 for (i = start; i < end; ++i)
1152 pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1153 nvc0->surfaces_valid[t] &= ~mask;
1154 }
1155 nvc0->surfaces_dirty[t] |= mask;
1156
1157 if (t == 0)
1158 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_SUF);
1159 else
1160 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1161 }
1162
1163 static void
1164 nvc0_set_compute_resources(struct pipe_context *pipe,
1165 unsigned start, unsigned nr,
1166 struct pipe_surface **resources)
1167 {
1168 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1169
1170 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1171 }
1172
1173 static void
1174 nvc0_set_shader_images(struct pipe_context *pipe, unsigned shader,
1175 unsigned start_slot, unsigned count,
1176 struct pipe_image_view **views)
1177 {
1178 #if 0
1179 nvc0_bind_surfaces_range(nvc0_context(pipe), 0, start, nr, views);
1180
1181 nvc0_context(pipe)->dirty |= NVC0_NEW_SURFACES;
1182 #endif
1183 }
1184
1185 static inline void
1186 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1187 {
1188 struct nv04_resource *buf = nv04_resource(res);
1189 if (buf) {
1190 uint64_t limit = (buf->address + buf->base.width0) - 1;
1191 if (limit < (1ULL << 32)) {
1192 *phandle = (uint32_t)buf->address;
1193 } else {
1194 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1195 "resource not contained within 32-bit address space !\n");
1196 *phandle = 0;
1197 }
1198 } else {
1199 *phandle = 0;
1200 }
1201 }
1202
1203 static void
1204 nvc0_set_global_bindings(struct pipe_context *pipe,
1205 unsigned start, unsigned nr,
1206 struct pipe_resource **resources,
1207 uint32_t **handles)
1208 {
1209 struct nvc0_context *nvc0 = nvc0_context(pipe);
1210 struct pipe_resource **ptr;
1211 unsigned i;
1212 const unsigned end = start + nr;
1213
1214 if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1215 const unsigned old_size = nvc0->global_residents.size;
1216 const unsigned req_size = end * sizeof(struct pipe_resource *);
1217 util_dynarray_resize(&nvc0->global_residents, req_size);
1218 memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1219 req_size - old_size);
1220 }
1221
1222 if (resources) {
1223 ptr = util_dynarray_element(
1224 &nvc0->global_residents, struct pipe_resource *, start);
1225 for (i = 0; i < nr; ++i) {
1226 pipe_resource_reference(&ptr[i], resources[i]);
1227 nvc0_set_global_handle(handles[i], resources[i]);
1228 }
1229 } else {
1230 ptr = util_dynarray_element(
1231 &nvc0->global_residents, struct pipe_resource *, start);
1232 for (i = 0; i < nr; ++i)
1233 pipe_resource_reference(&ptr[i], NULL);
1234 }
1235
1236 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1237
1238 nvc0->dirty_cp = NVC0_NEW_CP_GLOBALS;
1239 }
1240
1241 void
1242 nvc0_init_state_functions(struct nvc0_context *nvc0)
1243 {
1244 struct pipe_context *pipe = &nvc0->base.pipe;
1245
1246 pipe->create_blend_state = nvc0_blend_state_create;
1247 pipe->bind_blend_state = nvc0_blend_state_bind;
1248 pipe->delete_blend_state = nvc0_blend_state_delete;
1249
1250 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1251 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1252 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1253
1254 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1255 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1256 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1257
1258 pipe->create_sampler_state = nv50_sampler_state_create;
1259 pipe->delete_sampler_state = nvc0_sampler_state_delete;
1260 pipe->bind_sampler_states = nvc0_bind_sampler_states;
1261
1262 pipe->create_sampler_view = nvc0_create_sampler_view;
1263 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1264 pipe->set_sampler_views = nvc0_set_sampler_views;
1265
1266 pipe->create_vs_state = nvc0_vp_state_create;
1267 pipe->create_fs_state = nvc0_fp_state_create;
1268 pipe->create_gs_state = nvc0_gp_state_create;
1269 pipe->create_tcs_state = nvc0_tcp_state_create;
1270 pipe->create_tes_state = nvc0_tep_state_create;
1271 pipe->bind_vs_state = nvc0_vp_state_bind;
1272 pipe->bind_fs_state = nvc0_fp_state_bind;
1273 pipe->bind_gs_state = nvc0_gp_state_bind;
1274 pipe->bind_tcs_state = nvc0_tcp_state_bind;
1275 pipe->bind_tes_state = nvc0_tep_state_bind;
1276 pipe->delete_vs_state = nvc0_sp_state_delete;
1277 pipe->delete_fs_state = nvc0_sp_state_delete;
1278 pipe->delete_gs_state = nvc0_sp_state_delete;
1279 pipe->delete_tcs_state = nvc0_sp_state_delete;
1280 pipe->delete_tes_state = nvc0_sp_state_delete;
1281
1282 pipe->create_compute_state = nvc0_cp_state_create;
1283 pipe->bind_compute_state = nvc0_cp_state_bind;
1284 pipe->delete_compute_state = nvc0_sp_state_delete;
1285
1286 pipe->set_blend_color = nvc0_set_blend_color;
1287 pipe->set_stencil_ref = nvc0_set_stencil_ref;
1288 pipe->set_clip_state = nvc0_set_clip_state;
1289 pipe->set_sample_mask = nvc0_set_sample_mask;
1290 pipe->set_min_samples = nvc0_set_min_samples;
1291 pipe->set_constant_buffer = nvc0_set_constant_buffer;
1292 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1293 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1294 pipe->set_scissor_states = nvc0_set_scissor_states;
1295 pipe->set_viewport_states = nvc0_set_viewport_states;
1296
1297 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1298 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1299 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1300
1301 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1302 pipe->set_index_buffer = nvc0_set_index_buffer;
1303
1304 pipe->create_stream_output_target = nvc0_so_target_create;
1305 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1306 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1307
1308 pipe->set_global_binding = nvc0_set_global_bindings;
1309 pipe->set_compute_resources = nvc0_set_compute_resources;
1310 pipe->set_shader_images = nvc0_set_shader_images;
1311
1312 nvc0->sample_mask = ~0;
1313 nvc0->min_samples = 1;
1314 }