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nv50,nvc0: Fix gallium nine regression regarding sampler bindings
[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_state.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_framebuffer.h"
25 #include "util/u_helpers.h"
26 #include "util/u_inlines.h"
27 #include "util/u_transfer.h"
28
29 #include "tgsi/tgsi_parse.h"
30
31 #include "nvc0/nvc0_stateobj.h"
32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_query_hw.h"
34
35 #include "nvc0/nvc0_3d.xml.h"
36
37 #include "nouveau_gldefs.h"
38
39 static inline uint32_t
40 nvc0_colormask(unsigned mask)
41 {
42 uint32_t ret = 0;
43
44 if (mask & PIPE_MASK_R)
45 ret |= 0x0001;
46 if (mask & PIPE_MASK_G)
47 ret |= 0x0010;
48 if (mask & PIPE_MASK_B)
49 ret |= 0x0100;
50 if (mask & PIPE_MASK_A)
51 ret |= 0x1000;
52
53 return ret;
54 }
55
56 #define NVC0_BLEND_FACTOR_CASE(a, b) \
57 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
58
59 static inline uint32_t
60 nvc0_blend_fac(unsigned factor)
61 {
62 switch (factor) {
63 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
64 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
65 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
66 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
67 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
68 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
69 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
70 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
71 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
72 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
73 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
74 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
75 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
76 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
77 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
78 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
79 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
80 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
81 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
82 default:
83 return NV50_BLEND_FACTOR_ZERO;
84 }
85 }
86
87 static void *
88 nvc0_blend_state_create(struct pipe_context *pipe,
89 const struct pipe_blend_state *cso)
90 {
91 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
92 int i;
93 int r; /* reference */
94 uint32_t ms;
95 uint8_t blend_en = 0;
96 bool indep_masks = false;
97 bool indep_funcs = false;
98
99 so->pipe = *cso;
100
101 /* check which states actually have differing values */
102 if (cso->independent_blend_enable) {
103 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
104 blend_en |= 1 << r;
105 for (i = r + 1; i < 8; ++i) {
106 if (!cso->rt[i].blend_enable)
107 continue;
108 blend_en |= 1 << i;
109 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
110 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
111 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
112 cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
113 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
114 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
115 indep_funcs = true;
116 break;
117 }
118 }
119 for (; i < 8; ++i)
120 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
121
122 for (i = 1; i < 8; ++i) {
123 if (cso->rt[i].colormask != cso->rt[0].colormask) {
124 indep_masks = true;
125 break;
126 }
127 }
128 } else {
129 r = 0;
130 if (cso->rt[0].blend_enable)
131 blend_en = 0xff;
132 }
133
134 if (cso->logicop_enable) {
135 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
136 SB_DATA (so, 1);
137 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
138
139 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
140 } else {
141 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
142
143 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
144 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
145 if (indep_funcs) {
146 for (i = 0; i < 8; ++i) {
147 if (cso->rt[i].blend_enable) {
148 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
149 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
150 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
151 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
152 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
153 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
154 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
155 }
156 }
157 } else
158 if (blend_en) {
159 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
160 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
161 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
162 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
163 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
164 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
165 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
166 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
167 }
168
169 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
170 if (indep_masks) {
171 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
172 for (i = 0; i < 8; ++i)
173 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
174 } else {
175 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
176 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
177 }
178 }
179
180 ms = 0;
181 if (cso->alpha_to_coverage)
182 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
183 if (cso->alpha_to_one)
184 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
185
186 SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
187 SB_DATA (so, ms);
188
189 assert(so->size <= ARRAY_SIZE(so->state));
190 return so;
191 }
192
193 static void
194 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
195 {
196 struct nvc0_context *nvc0 = nvc0_context(pipe);
197
198 nvc0->blend = hwcso;
199 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND;
200 }
201
202 static void
203 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
204 {
205 FREE(hwcso);
206 }
207
208 /* NOTE: ignoring line_last_pixel */
209 static void *
210 nvc0_rasterizer_state_create(struct pipe_context *pipe,
211 const struct pipe_rasterizer_state *cso)
212 {
213 struct nvc0_rasterizer_stateobj *so;
214 uint16_t class_3d = nouveau_screen(pipe->screen)->class_3d;
215 uint32_t reg;
216
217 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
218 if (!so)
219 return NULL;
220 so->pipe = *cso;
221
222 /* Scissor enables are handled in scissor state, we will not want to
223 * always emit 16 commands, one for each scissor rectangle, here.
224 */
225
226 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
227 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
228
229 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
230 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
231 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
232
233 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
234
235 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
236 /* On GM20x+, LINE_WIDTH_SMOOTH controls both aliased and smooth
237 * rendering and LINE_WIDTH_ALIASED seems to be ignored
238 */
239 if (cso->line_smooth || cso->multisample || class_3d >= GM200_3D_CLASS)
240 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
241 else
242 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
243 SB_DATA (so, fui(cso->line_width));
244
245 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
246 if (cso->line_stipple_enable) {
247 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
248 SB_DATA (so, (cso->line_stipple_pattern << 8) |
249 cso->line_stipple_factor);
250
251 }
252
253 SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
254 if (!cso->point_size_per_vertex) {
255 SB_BEGIN_3D(so, POINT_SIZE, 1);
256 SB_DATA (so, fui(cso->point_size));
257 }
258
259 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
260 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
261 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
262
263 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
264 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
265 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
266 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
267
268 if (class_3d >= GM200_3D_CLASS) {
269 SB_IMMED_3D(so, FILL_RECTANGLE,
270 cso->fill_front == PIPE_POLYGON_MODE_FILL_RECTANGLE ?
271 NVC0_3D_FILL_RECTANGLE_ENABLE : 0);
272 }
273
274 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
275 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
276 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
277 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
278 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
279
280 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
281 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
282 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
283 NVC0_3D_FRONT_FACE_CW);
284 switch (cso->cull_face) {
285 case PIPE_FACE_FRONT_AND_BACK:
286 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
287 break;
288 case PIPE_FACE_FRONT:
289 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
290 break;
291 case PIPE_FACE_BACK:
292 default:
293 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
294 break;
295 }
296
297 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
298 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
299 SB_DATA (so, cso->offset_point);
300 SB_DATA (so, cso->offset_line);
301 SB_DATA (so, cso->offset_tri);
302
303 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
304 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
305 SB_DATA (so, fui(cso->offset_scale));
306 if (!cso->offset_units_unscaled) {
307 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
308 SB_DATA (so, fui(cso->offset_units * 2.0f));
309 }
310 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
311 SB_DATA (so, fui(cso->offset_clamp));
312 }
313
314 if (cso->depth_clip_near)
315 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
316 else
317 reg =
318 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
319 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
320 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
321 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
322
323 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
324 SB_DATA (so, reg);
325
326 SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
327
328 SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
329
330 if (class_3d >= GM200_3D_CLASS) {
331 if (cso->conservative_raster_mode != PIPE_CONSERVATIVE_RASTER_OFF) {
332 bool post_snap = cso->conservative_raster_mode ==
333 PIPE_CONSERVATIVE_RASTER_POST_SNAP;
334 uint32_t state = cso->subpixel_precision_x;
335 state |= cso->subpixel_precision_y << 4;
336 state |= (uint32_t)(cso->conservative_raster_dilate * 4) << 8;
337 state |= (post_snap || class_3d < GP100_3D_CLASS) ? 1 << 10 : 0;
338 SB_IMMED_3D(so, MACRO_CONSERVATIVE_RASTER_STATE, state);
339 } else {
340 SB_IMMED_3D(so, CONSERVATIVE_RASTER, 0);
341 }
342 }
343
344 assert(so->size <= ARRAY_SIZE(so->state));
345 return (void *)so;
346 }
347
348 static void
349 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
350 {
351 struct nvc0_context *nvc0 = nvc0_context(pipe);
352
353 nvc0->rast = hwcso;
354 nvc0->dirty_3d |= NVC0_NEW_3D_RASTERIZER;
355 }
356
357 static void
358 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
359 {
360 FREE(hwcso);
361 }
362
363 static void *
364 nvc0_zsa_state_create(struct pipe_context *pipe,
365 const struct pipe_depth_stencil_alpha_state *cso)
366 {
367 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
368
369 so->pipe = *cso;
370
371 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
372 if (cso->depth.enabled) {
373 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
374 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
375 SB_DATA (so, nvgl_comparison_op(cso->depth.func));
376 }
377
378 SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth.bounds_test);
379 if (cso->depth.bounds_test) {
380 SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
381 SB_DATA (so, fui(cso->depth.bounds_min));
382 SB_DATA (so, fui(cso->depth.bounds_max));
383 }
384
385 if (cso->stencil[0].enabled) {
386 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
387 SB_DATA (so, 1);
388 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
389 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
390 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
391 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
392 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
393 SB_DATA (so, cso->stencil[0].valuemask);
394 SB_DATA (so, cso->stencil[0].writemask);
395 } else {
396 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
397 }
398
399 if (cso->stencil[1].enabled) {
400 assert(cso->stencil[0].enabled);
401 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
402 SB_DATA (so, 1);
403 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
404 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
405 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
406 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
407 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
408 SB_DATA (so, cso->stencil[1].writemask);
409 SB_DATA (so, cso->stencil[1].valuemask);
410 } else
411 if (cso->stencil[0].enabled) {
412 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
413 }
414
415 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
416 if (cso->alpha.enabled) {
417 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
418 SB_DATA (so, fui(cso->alpha.ref_value));
419 SB_DATA (so, nvgl_comparison_op(cso->alpha.func));
420 }
421
422 assert(so->size <= ARRAY_SIZE(so->state));
423 return (void *)so;
424 }
425
426 static void
427 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
428 {
429 struct nvc0_context *nvc0 = nvc0_context(pipe);
430
431 nvc0->zsa = hwcso;
432 nvc0->dirty_3d |= NVC0_NEW_3D_ZSA;
433 }
434
435 static void
436 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
437 {
438 FREE(hwcso);
439 }
440
441 /* ====================== SAMPLERS AND TEXTURES ================================
442 */
443
444 #define NV50_TSC_WRAP_CASE(n) \
445 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
446
447 static void
448 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
449 {
450 unsigned s, i;
451
452 for (s = 0; s < 6; ++s)
453 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
454 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
455 nvc0_context(pipe)->samplers[s][i] = NULL;
456
457 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
458
459 FREE(hwcso);
460 }
461
462 static inline void
463 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0,
464 unsigned s,
465 unsigned nr, void **hwcso)
466 {
467 unsigned highest_found = 0;
468 unsigned i;
469
470 for (i = 0; i < nr; ++i) {
471 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
472
473 if (hwcso[i])
474 highest_found = i;
475
476 if (hwcso[i] == old)
477 continue;
478 nvc0->samplers_dirty[s] |= 1 << i;
479
480 nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
481 if (old)
482 nvc0_screen_tsc_unlock(nvc0->screen, old);
483 }
484 if (nr >= nvc0->num_samplers[s])
485 nvc0->num_samplers[s] = highest_found + 1;
486 }
487
488 static void
489 nvc0_bind_sampler_states(struct pipe_context *pipe,
490 enum pipe_shader_type shader,
491 unsigned start, unsigned nr, void **samplers)
492 {
493 const unsigned s = nvc0_shader_stage(shader);
494
495 assert(start == 0);
496 nvc0_stage_sampler_states_bind(nvc0_context(pipe), s, nr, samplers);
497
498 if (s == 5)
499 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
500 else
501 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
502 }
503
504
505 /* NOTE: only called when not referenced anywhere, won't be bound */
506 static void
507 nvc0_sampler_view_destroy(struct pipe_context *pipe,
508 struct pipe_sampler_view *view)
509 {
510 pipe_resource_reference(&view->texture, NULL);
511
512 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
513
514 FREE(nv50_tic_entry(view));
515 }
516
517 static inline void
518 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
519 unsigned nr,
520 struct pipe_sampler_view **views)
521 {
522 unsigned i;
523
524 for (i = 0; i < nr; ++i) {
525 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
526
527 if (views[i] == nvc0->textures[s][i])
528 continue;
529 nvc0->textures_dirty[s] |= 1 << i;
530
531 if (views[i] && views[i]->texture) {
532 struct pipe_resource *res = views[i]->texture;
533 if (res->target == PIPE_BUFFER &&
534 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
535 nvc0->textures_coherent[s] |= 1 << i;
536 else
537 nvc0->textures_coherent[s] &= ~(1 << i);
538 } else {
539 nvc0->textures_coherent[s] &= ~(1 << i);
540 }
541
542 if (old) {
543 if (s == 5)
544 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
545 else
546 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
547 nvc0_screen_tic_unlock(nvc0->screen, old);
548 }
549
550 pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
551 }
552
553 for (i = nr; i < nvc0->num_textures[s]; ++i) {
554 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
555 if (old) {
556 if (s == 5)
557 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
558 else
559 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
560 nvc0_screen_tic_unlock(nvc0->screen, old);
561 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
562 }
563 }
564
565 nvc0->num_textures[s] = nr;
566 }
567
568 static void
569 nvc0_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,
570 unsigned start, unsigned nr,
571 struct pipe_sampler_view **views)
572 {
573 const unsigned s = nvc0_shader_stage(shader);
574
575 assert(start == 0);
576 nvc0_stage_set_sampler_views(nvc0_context(pipe), s, nr, views);
577
578 if (s == 5)
579 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
580 else
581 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_TEXTURES;
582 }
583
584 /* ============================= SHADERS =======================================
585 */
586
587 static void *
588 nvc0_sp_state_create(struct pipe_context *pipe,
589 const struct pipe_shader_state *cso, unsigned type)
590 {
591 struct nvc0_program *prog;
592
593 prog = CALLOC_STRUCT(nvc0_program);
594 if (!prog)
595 return NULL;
596
597 prog->type = type;
598
599 if (cso->tokens)
600 prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
601
602 if (cso->stream_output.num_outputs)
603 prog->pipe.stream_output = cso->stream_output;
604
605 prog->translated = nvc0_program_translate(
606 prog, nvc0_context(pipe)->screen->base.device->chipset,
607 &nouveau_context(pipe)->debug);
608
609 return (void *)prog;
610 }
611
612 static void
613 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
614 {
615 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
616
617 nvc0_program_destroy(nvc0_context(pipe), prog);
618
619 FREE((void *)prog->pipe.tokens);
620 FREE(prog);
621 }
622
623 static void *
624 nvc0_vp_state_create(struct pipe_context *pipe,
625 const struct pipe_shader_state *cso)
626 {
627 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
628 }
629
630 static void
631 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
632 {
633 struct nvc0_context *nvc0 = nvc0_context(pipe);
634
635 nvc0->vertprog = hwcso;
636 nvc0->dirty_3d |= NVC0_NEW_3D_VERTPROG;
637 }
638
639 static void *
640 nvc0_fp_state_create(struct pipe_context *pipe,
641 const struct pipe_shader_state *cso)
642 {
643 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
644 }
645
646 static void
647 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
648 {
649 struct nvc0_context *nvc0 = nvc0_context(pipe);
650
651 nvc0->fragprog = hwcso;
652 nvc0->dirty_3d |= NVC0_NEW_3D_FRAGPROG;
653 }
654
655 static void *
656 nvc0_gp_state_create(struct pipe_context *pipe,
657 const struct pipe_shader_state *cso)
658 {
659 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
660 }
661
662 static void
663 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
664 {
665 struct nvc0_context *nvc0 = nvc0_context(pipe);
666
667 nvc0->gmtyprog = hwcso;
668 nvc0->dirty_3d |= NVC0_NEW_3D_GMTYPROG;
669 }
670
671 static void *
672 nvc0_tcp_state_create(struct pipe_context *pipe,
673 const struct pipe_shader_state *cso)
674 {
675 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
676 }
677
678 static void
679 nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
680 {
681 struct nvc0_context *nvc0 = nvc0_context(pipe);
682
683 nvc0->tctlprog = hwcso;
684 nvc0->dirty_3d |= NVC0_NEW_3D_TCTLPROG;
685 }
686
687 static void *
688 nvc0_tep_state_create(struct pipe_context *pipe,
689 const struct pipe_shader_state *cso)
690 {
691 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
692 }
693
694 static void
695 nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
696 {
697 struct nvc0_context *nvc0 = nvc0_context(pipe);
698
699 nvc0->tevlprog = hwcso;
700 nvc0->dirty_3d |= NVC0_NEW_3D_TEVLPROG;
701 }
702
703 static void *
704 nvc0_cp_state_create(struct pipe_context *pipe,
705 const struct pipe_compute_state *cso)
706 {
707 struct nvc0_program *prog;
708
709 prog = CALLOC_STRUCT(nvc0_program);
710 if (!prog)
711 return NULL;
712 prog->type = PIPE_SHADER_COMPUTE;
713
714 prog->cp.smem_size = cso->req_local_mem;
715 prog->cp.lmem_size = cso->req_private_mem;
716 prog->parm_size = cso->req_input_mem;
717
718 prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
719
720 prog->translated = nvc0_program_translate(
721 prog, nvc0_context(pipe)->screen->base.device->chipset,
722 &nouveau_context(pipe)->debug);
723
724 return (void *)prog;
725 }
726
727 static void
728 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
729 {
730 struct nvc0_context *nvc0 = nvc0_context(pipe);
731
732 nvc0->compprog = hwcso;
733 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
734 }
735
736 static void
737 nvc0_set_constant_buffer(struct pipe_context *pipe,
738 enum pipe_shader_type shader, uint index,
739 const struct pipe_constant_buffer *cb)
740 {
741 struct nvc0_context *nvc0 = nvc0_context(pipe);
742 struct pipe_resource *res = cb ? cb->buffer : NULL;
743 const unsigned s = nvc0_shader_stage(shader);
744 const unsigned i = index;
745
746 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
747 if (nvc0->constbuf[s][i].user)
748 nvc0->constbuf[s][i].u.buf = NULL;
749 else
750 if (nvc0->constbuf[s][i].u.buf)
751 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
752
753 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
754 } else {
755 if (nvc0->constbuf[s][i].user)
756 nvc0->constbuf[s][i].u.buf = NULL;
757 else
758 if (nvc0->constbuf[s][i].u.buf)
759 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_CB(s, i));
760
761 nvc0->dirty_3d |= NVC0_NEW_3D_CONSTBUF;
762 }
763 nvc0->constbuf_dirty[s] |= 1 << i;
764
765 if (nvc0->constbuf[s][i].u.buf)
766 nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
767 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
768
769 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
770 if (nvc0->constbuf[s][i].user) {
771 nvc0->constbuf[s][i].u.data = cb->user_buffer;
772 nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
773 nvc0->constbuf_valid[s] |= 1 << i;
774 nvc0->constbuf_coherent[s] &= ~(1 << i);
775 } else
776 if (cb) {
777 nvc0->constbuf[s][i].offset = cb->buffer_offset;
778 nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
779 nvc0->constbuf_valid[s] |= 1 << i;
780 if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
781 nvc0->constbuf_coherent[s] |= 1 << i;
782 else
783 nvc0->constbuf_coherent[s] &= ~(1 << i);
784 }
785 else {
786 nvc0->constbuf_valid[s] &= ~(1 << i);
787 nvc0->constbuf_coherent[s] &= ~(1 << i);
788 }
789 }
790
791 /* =============================================================================
792 */
793
794 static void
795 nvc0_set_blend_color(struct pipe_context *pipe,
796 const struct pipe_blend_color *bcol)
797 {
798 struct nvc0_context *nvc0 = nvc0_context(pipe);
799
800 nvc0->blend_colour = *bcol;
801 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND_COLOUR;
802 }
803
804 static void
805 nvc0_set_stencil_ref(struct pipe_context *pipe,
806 const struct pipe_stencil_ref *sr)
807 {
808 struct nvc0_context *nvc0 = nvc0_context(pipe);
809
810 nvc0->stencil_ref = *sr;
811 nvc0->dirty_3d |= NVC0_NEW_3D_STENCIL_REF;
812 }
813
814 static void
815 nvc0_set_clip_state(struct pipe_context *pipe,
816 const struct pipe_clip_state *clip)
817 {
818 struct nvc0_context *nvc0 = nvc0_context(pipe);
819
820 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
821
822 nvc0->dirty_3d |= NVC0_NEW_3D_CLIP;
823 }
824
825 static void
826 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
827 {
828 struct nvc0_context *nvc0 = nvc0_context(pipe);
829
830 nvc0->sample_mask = sample_mask;
831 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_MASK;
832 }
833
834 static void
835 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
836 {
837 struct nvc0_context *nvc0 = nvc0_context(pipe);
838
839 if (nvc0->min_samples != min_samples) {
840 nvc0->min_samples = min_samples;
841 nvc0->dirty_3d |= NVC0_NEW_3D_MIN_SAMPLES;
842 }
843 }
844
845 static void
846 nvc0_set_framebuffer_state(struct pipe_context *pipe,
847 const struct pipe_framebuffer_state *fb)
848 {
849 struct nvc0_context *nvc0 = nvc0_context(pipe);
850
851 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
852
853 util_copy_framebuffer_state(&nvc0->framebuffer, fb);
854
855 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER | NVC0_NEW_3D_SAMPLE_LOCATIONS;
856 }
857
858 static void
859 nvc0_set_sample_locations(struct pipe_context *pipe,
860 size_t size, const uint8_t *locations)
861 {
862 struct nvc0_context *nvc0 = nvc0_context(pipe);
863
864 nvc0->sample_locations_enabled = size && locations;
865 if (size > sizeof(nvc0->sample_locations))
866 size = sizeof(nvc0->sample_locations);
867 memcpy(nvc0->sample_locations, locations, size);
868
869 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_LOCATIONS;
870 }
871
872 static void
873 nvc0_set_polygon_stipple(struct pipe_context *pipe,
874 const struct pipe_poly_stipple *stipple)
875 {
876 struct nvc0_context *nvc0 = nvc0_context(pipe);
877
878 nvc0->stipple = *stipple;
879 nvc0->dirty_3d |= NVC0_NEW_3D_STIPPLE;
880 }
881
882 static void
883 nvc0_set_scissor_states(struct pipe_context *pipe,
884 unsigned start_slot,
885 unsigned num_scissors,
886 const struct pipe_scissor_state *scissor)
887 {
888 struct nvc0_context *nvc0 = nvc0_context(pipe);
889 int i;
890
891 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
892 for (i = 0; i < num_scissors; i++) {
893 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
894 continue;
895 nvc0->scissors[start_slot + i] = scissor[i];
896 nvc0->scissors_dirty |= 1 << (start_slot + i);
897 nvc0->dirty_3d |= NVC0_NEW_3D_SCISSOR;
898 }
899 }
900
901 static void
902 nvc0_set_viewport_states(struct pipe_context *pipe,
903 unsigned start_slot,
904 unsigned num_viewports,
905 const struct pipe_viewport_state *vpt)
906 {
907 struct nvc0_context *nvc0 = nvc0_context(pipe);
908 int i;
909
910 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
911 for (i = 0; i < num_viewports; i++) {
912 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
913 continue;
914 nvc0->viewports[start_slot + i] = vpt[i];
915 nvc0->viewports_dirty |= 1 << (start_slot + i);
916 nvc0->dirty_3d |= NVC0_NEW_3D_VIEWPORT;
917 }
918
919 }
920
921 static void
922 nvc0_set_window_rectangles(struct pipe_context *pipe,
923 boolean include,
924 unsigned num_rectangles,
925 const struct pipe_scissor_state *rectangles)
926 {
927 struct nvc0_context *nvc0 = nvc0_context(pipe);
928
929 nvc0->window_rect.inclusive = include;
930 nvc0->window_rect.rects = MIN2(num_rectangles, NVC0_MAX_WINDOW_RECTANGLES);
931 memcpy(nvc0->window_rect.rect, rectangles,
932 sizeof(struct pipe_scissor_state) * nvc0->window_rect.rects);
933
934 nvc0->dirty_3d |= NVC0_NEW_3D_WINDOW_RECTS;
935 }
936
937 static void
938 nvc0_set_tess_state(struct pipe_context *pipe,
939 const float default_tess_outer[4],
940 const float default_tess_inner[2])
941 {
942 struct nvc0_context *nvc0 = nvc0_context(pipe);
943
944 memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
945 memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
946 nvc0->dirty_3d |= NVC0_NEW_3D_TESSFACTOR;
947 }
948
949 static void
950 nvc0_set_vertex_buffers(struct pipe_context *pipe,
951 unsigned start_slot, unsigned count,
952 const struct pipe_vertex_buffer *vb)
953 {
954 struct nvc0_context *nvc0 = nvc0_context(pipe);
955 unsigned i;
956
957 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX);
958 nvc0->dirty_3d |= NVC0_NEW_3D_ARRAYS;
959
960 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
961 start_slot, count);
962
963 if (!vb) {
964 nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
965 nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
966 nvc0->vtxbufs_coherent &= ~(((1ull << count) - 1) << start_slot);
967 return;
968 }
969
970 for (i = 0; i < count; ++i) {
971 unsigned dst_index = start_slot + i;
972
973 if (vb[i].is_user_buffer) {
974 nvc0->vbo_user |= 1 << dst_index;
975 if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
976 nvc0->constant_vbos |= 1 << dst_index;
977 else
978 nvc0->constant_vbos &= ~(1 << dst_index);
979 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
980 } else {
981 nvc0->vbo_user &= ~(1 << dst_index);
982 nvc0->constant_vbos &= ~(1 << dst_index);
983
984 if (vb[i].buffer.resource &&
985 vb[i].buffer.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
986 nvc0->vtxbufs_coherent |= (1 << dst_index);
987 else
988 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
989 }
990 }
991 }
992
993 static void
994 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
995 {
996 struct nvc0_context *nvc0 = nvc0_context(pipe);
997
998 nvc0->vertex = hwcso;
999 nvc0->dirty_3d |= NVC0_NEW_3D_VERTEX;
1000 }
1001
1002 static struct pipe_stream_output_target *
1003 nvc0_so_target_create(struct pipe_context *pipe,
1004 struct pipe_resource *res,
1005 unsigned offset, unsigned size)
1006 {
1007 struct nv04_resource *buf = (struct nv04_resource *)res;
1008 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1009 if (!targ)
1010 return NULL;
1011
1012 targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0);
1013 if (!targ->pq) {
1014 FREE(targ);
1015 return NULL;
1016 }
1017 targ->clean = true;
1018
1019 targ->pipe.buffer_size = size;
1020 targ->pipe.buffer_offset = offset;
1021 targ->pipe.context = pipe;
1022 targ->pipe.buffer = NULL;
1023 pipe_resource_reference(&targ->pipe.buffer, res);
1024 pipe_reference_init(&targ->pipe.reference, 1);
1025
1026 assert(buf->base.target == PIPE_BUFFER);
1027 util_range_add(&buf->valid_buffer_range, offset, offset + size);
1028
1029 return &targ->pipe;
1030 }
1031
1032 static void
1033 nvc0_so_target_save_offset(struct pipe_context *pipe,
1034 struct pipe_stream_output_target *ptarg,
1035 unsigned index, bool *serialize)
1036 {
1037 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1038
1039 if (*serialize) {
1040 *serialize = false;
1041 PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
1042 IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
1043
1044 NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
1045 }
1046
1047 nvc0_query(targ->pq)->index = index;
1048 pipe->end_query(pipe, targ->pq);
1049 }
1050
1051 static void
1052 nvc0_so_target_destroy(struct pipe_context *pipe,
1053 struct pipe_stream_output_target *ptarg)
1054 {
1055 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1056 pipe->destroy_query(pipe, targ->pq);
1057 pipe_resource_reference(&targ->pipe.buffer, NULL);
1058 FREE(targ);
1059 }
1060
1061 static void
1062 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1063 unsigned num_targets,
1064 struct pipe_stream_output_target **targets,
1065 const unsigned *offsets)
1066 {
1067 struct nvc0_context *nvc0 = nvc0_context(pipe);
1068 unsigned i;
1069 bool serialize = true;
1070
1071 assert(num_targets <= 4);
1072
1073 for (i = 0; i < num_targets; ++i) {
1074 const bool changed = nvc0->tfbbuf[i] != targets[i];
1075 const bool append = (offsets[i] == ((unsigned)-1));
1076 if (!changed && append)
1077 continue;
1078 nvc0->tfbbuf_dirty |= 1 << i;
1079
1080 if (nvc0->tfbbuf[i] && changed)
1081 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1082
1083 if (targets[i] && !append)
1084 nvc0_so_target(targets[i])->clean = true;
1085
1086 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1087 }
1088 for (; i < nvc0->num_tfbbufs; ++i) {
1089 if (nvc0->tfbbuf[i]) {
1090 nvc0->tfbbuf_dirty |= 1 << i;
1091 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1092 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1093 }
1094 }
1095 nvc0->num_tfbbufs = num_targets;
1096
1097 if (nvc0->tfbbuf_dirty) {
1098 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TFB);
1099 nvc0->dirty_3d |= NVC0_NEW_3D_TFB_TARGETS;
1100 }
1101 }
1102
1103 static void
1104 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1105 unsigned start, unsigned nr,
1106 struct pipe_surface **psurfaces)
1107 {
1108 const unsigned end = start + nr;
1109 const unsigned mask = ((1 << nr) - 1) << start;
1110 unsigned i;
1111
1112 if (psurfaces) {
1113 for (i = start; i < end; ++i) {
1114 const unsigned p = i - start;
1115 if (psurfaces[p])
1116 nvc0->surfaces_valid[t] |= (1 << i);
1117 else
1118 nvc0->surfaces_valid[t] &= ~(1 << i);
1119 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1120 }
1121 } else {
1122 for (i = start; i < end; ++i)
1123 pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1124 nvc0->surfaces_valid[t] &= ~mask;
1125 }
1126 nvc0->surfaces_dirty[t] |= mask;
1127
1128 if (t == 0)
1129 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1130 else
1131 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1132 }
1133
1134 static void
1135 nvc0_set_compute_resources(struct pipe_context *pipe,
1136 unsigned start, unsigned nr,
1137 struct pipe_surface **resources)
1138 {
1139 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1140
1141 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1142 }
1143
1144 static bool
1145 nvc0_bind_images_range(struct nvc0_context *nvc0, const unsigned s,
1146 unsigned start, unsigned nr,
1147 const struct pipe_image_view *pimages)
1148 {
1149 const unsigned end = start + nr;
1150 unsigned mask = 0;
1151 unsigned i;
1152
1153 assert(s < 6);
1154
1155 if (pimages) {
1156 for (i = start; i < end; ++i) {
1157 struct pipe_image_view *img = &nvc0->images[s][i];
1158 const unsigned p = i - start;
1159
1160 if (img->resource == pimages[p].resource &&
1161 img->format == pimages[p].format &&
1162 img->access == pimages[p].access) {
1163 if (img->resource == NULL)
1164 continue;
1165 if (img->resource->target == PIPE_BUFFER &&
1166 img->u.buf.offset == pimages[p].u.buf.offset &&
1167 img->u.buf.size == pimages[p].u.buf.size)
1168 continue;
1169 if (img->resource->target != PIPE_BUFFER &&
1170 img->u.tex.first_layer == pimages[p].u.tex.first_layer &&
1171 img->u.tex.last_layer == pimages[p].u.tex.last_layer &&
1172 img->u.tex.level == pimages[p].u.tex.level)
1173 continue;
1174 }
1175
1176 mask |= (1 << i);
1177 if (pimages[p].resource)
1178 nvc0->images_valid[s] |= (1 << i);
1179 else
1180 nvc0->images_valid[s] &= ~(1 << i);
1181
1182 img->format = pimages[p].format;
1183 img->access = pimages[p].access;
1184 if (pimages[p].resource && pimages[p].resource->target == PIPE_BUFFER)
1185 img->u.buf = pimages[p].u.buf;
1186 else
1187 img->u.tex = pimages[p].u.tex;
1188
1189 pipe_resource_reference(
1190 &img->resource, pimages[p].resource);
1191
1192 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1193 if (nvc0->images_tic[s][i]) {
1194 struct nv50_tic_entry *old =
1195 nv50_tic_entry(nvc0->images_tic[s][i]);
1196 nvc0_screen_tic_unlock(nvc0->screen, old);
1197 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1198 }
1199
1200 nvc0->images_tic[s][i] =
1201 gm107_create_texture_view_from_image(&nvc0->base.pipe,
1202 &pimages[p]);
1203 }
1204 }
1205 if (!mask)
1206 return false;
1207 } else {
1208 mask = ((1 << nr) - 1) << start;
1209 if (!(nvc0->images_valid[s] & mask))
1210 return false;
1211 for (i = start; i < end; ++i) {
1212 pipe_resource_reference(&nvc0->images[s][i].resource, NULL);
1213 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1214 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->images_tic[s][i]);
1215 if (old) {
1216 nvc0_screen_tic_unlock(nvc0->screen, old);
1217 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1218 }
1219 }
1220 }
1221 nvc0->images_valid[s] &= ~mask;
1222 }
1223 nvc0->images_dirty[s] |= mask;
1224
1225 if (s == 5)
1226 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1227 else
1228 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1229
1230 return true;
1231 }
1232
1233 static void
1234 nvc0_set_shader_images(struct pipe_context *pipe,
1235 enum pipe_shader_type shader,
1236 unsigned start, unsigned nr,
1237 const struct pipe_image_view *images)
1238 {
1239 const unsigned s = nvc0_shader_stage(shader);
1240 if (!nvc0_bind_images_range(nvc0_context(pipe), s, start, nr, images))
1241 return;
1242
1243 if (s == 5)
1244 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1245 else
1246 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SURFACES;
1247 }
1248
1249 static bool
1250 nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t,
1251 unsigned start, unsigned nr,
1252 const struct pipe_shader_buffer *pbuffers)
1253 {
1254 const unsigned end = start + nr;
1255 unsigned mask = 0;
1256 unsigned i;
1257
1258 assert(t < 6);
1259
1260 if (pbuffers) {
1261 for (i = start; i < end; ++i) {
1262 struct pipe_shader_buffer *buf = &nvc0->buffers[t][i];
1263 const unsigned p = i - start;
1264 if (buf->buffer == pbuffers[p].buffer &&
1265 buf->buffer_offset == pbuffers[p].buffer_offset &&
1266 buf->buffer_size == pbuffers[p].buffer_size)
1267 continue;
1268
1269 mask |= (1 << i);
1270 if (pbuffers[p].buffer)
1271 nvc0->buffers_valid[t] |= (1 << i);
1272 else
1273 nvc0->buffers_valid[t] &= ~(1 << i);
1274 buf->buffer_offset = pbuffers[p].buffer_offset;
1275 buf->buffer_size = pbuffers[p].buffer_size;
1276 pipe_resource_reference(&buf->buffer, pbuffers[p].buffer);
1277 }
1278 if (!mask)
1279 return false;
1280 } else {
1281 mask = ((1 << nr) - 1) << start;
1282 if (!(nvc0->buffers_valid[t] & mask))
1283 return false;
1284 for (i = start; i < end; ++i)
1285 pipe_resource_reference(&nvc0->buffers[t][i].buffer, NULL);
1286 nvc0->buffers_valid[t] &= ~mask;
1287 }
1288 nvc0->buffers_dirty[t] |= mask;
1289
1290 if (t == 5)
1291 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF);
1292 else
1293 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BUF);
1294
1295 return true;
1296 }
1297
1298 static void
1299 nvc0_set_shader_buffers(struct pipe_context *pipe,
1300 enum pipe_shader_type shader,
1301 unsigned start, unsigned nr,
1302 const struct pipe_shader_buffer *buffers)
1303 {
1304 const unsigned s = nvc0_shader_stage(shader);
1305 if (!nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers))
1306 return;
1307
1308 if (s == 5)
1309 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_BUFFERS;
1310 else
1311 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_BUFFERS;
1312 }
1313
1314 static inline void
1315 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1316 {
1317 struct nv04_resource *buf = nv04_resource(res);
1318 if (buf) {
1319 uint64_t limit = (buf->address + buf->base.width0) - 1;
1320 if (limit < (1ULL << 32)) {
1321 *phandle = (uint32_t)buf->address;
1322 } else {
1323 NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1324 "resource not contained within 32-bit address space !\n");
1325 *phandle = 0;
1326 }
1327 } else {
1328 *phandle = 0;
1329 }
1330 }
1331
1332 static void
1333 nvc0_set_global_bindings(struct pipe_context *pipe,
1334 unsigned start, unsigned nr,
1335 struct pipe_resource **resources,
1336 uint32_t **handles)
1337 {
1338 struct nvc0_context *nvc0 = nvc0_context(pipe);
1339 struct pipe_resource **ptr;
1340 unsigned i;
1341 const unsigned end = start + nr;
1342
1343 if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1344 const unsigned old_size = nvc0->global_residents.size;
1345 const unsigned req_size = end * sizeof(struct pipe_resource *);
1346 util_dynarray_resize(&nvc0->global_residents, req_size);
1347 memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1348 req_size - old_size);
1349 }
1350
1351 if (resources) {
1352 ptr = util_dynarray_element(
1353 &nvc0->global_residents, struct pipe_resource *, start);
1354 for (i = 0; i < nr; ++i) {
1355 pipe_resource_reference(&ptr[i], resources[i]);
1356 nvc0_set_global_handle(handles[i], resources[i]);
1357 }
1358 } else {
1359 ptr = util_dynarray_element(
1360 &nvc0->global_residents, struct pipe_resource *, start);
1361 for (i = 0; i < nr; ++i)
1362 pipe_resource_reference(&ptr[i], NULL);
1363 }
1364
1365 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1366
1367 nvc0->dirty_cp |= NVC0_NEW_CP_GLOBALS;
1368 }
1369
1370 void
1371 nvc0_init_state_functions(struct nvc0_context *nvc0)
1372 {
1373 struct pipe_context *pipe = &nvc0->base.pipe;
1374
1375 pipe->create_blend_state = nvc0_blend_state_create;
1376 pipe->bind_blend_state = nvc0_blend_state_bind;
1377 pipe->delete_blend_state = nvc0_blend_state_delete;
1378
1379 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1380 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1381 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1382
1383 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1384 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1385 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1386
1387 pipe->create_sampler_state = nv50_sampler_state_create;
1388 pipe->delete_sampler_state = nvc0_sampler_state_delete;
1389 pipe->bind_sampler_states = nvc0_bind_sampler_states;
1390
1391 pipe->create_sampler_view = nvc0_create_sampler_view;
1392 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1393 pipe->set_sampler_views = nvc0_set_sampler_views;
1394
1395 pipe->create_vs_state = nvc0_vp_state_create;
1396 pipe->create_fs_state = nvc0_fp_state_create;
1397 pipe->create_gs_state = nvc0_gp_state_create;
1398 pipe->create_tcs_state = nvc0_tcp_state_create;
1399 pipe->create_tes_state = nvc0_tep_state_create;
1400 pipe->bind_vs_state = nvc0_vp_state_bind;
1401 pipe->bind_fs_state = nvc0_fp_state_bind;
1402 pipe->bind_gs_state = nvc0_gp_state_bind;
1403 pipe->bind_tcs_state = nvc0_tcp_state_bind;
1404 pipe->bind_tes_state = nvc0_tep_state_bind;
1405 pipe->delete_vs_state = nvc0_sp_state_delete;
1406 pipe->delete_fs_state = nvc0_sp_state_delete;
1407 pipe->delete_gs_state = nvc0_sp_state_delete;
1408 pipe->delete_tcs_state = nvc0_sp_state_delete;
1409 pipe->delete_tes_state = nvc0_sp_state_delete;
1410
1411 pipe->create_compute_state = nvc0_cp_state_create;
1412 pipe->bind_compute_state = nvc0_cp_state_bind;
1413 pipe->delete_compute_state = nvc0_sp_state_delete;
1414
1415 pipe->set_blend_color = nvc0_set_blend_color;
1416 pipe->set_stencil_ref = nvc0_set_stencil_ref;
1417 pipe->set_clip_state = nvc0_set_clip_state;
1418 pipe->set_sample_mask = nvc0_set_sample_mask;
1419 pipe->set_min_samples = nvc0_set_min_samples;
1420 pipe->set_constant_buffer = nvc0_set_constant_buffer;
1421 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1422 pipe->set_sample_locations = nvc0_set_sample_locations;
1423 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1424 pipe->set_scissor_states = nvc0_set_scissor_states;
1425 pipe->set_viewport_states = nvc0_set_viewport_states;
1426 pipe->set_window_rectangles = nvc0_set_window_rectangles;
1427 pipe->set_tess_state = nvc0_set_tess_state;
1428
1429 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1430 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1431 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1432
1433 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1434
1435 pipe->create_stream_output_target = nvc0_so_target_create;
1436 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1437 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1438
1439 pipe->set_global_binding = nvc0_set_global_bindings;
1440 pipe->set_compute_resources = nvc0_set_compute_resources;
1441 pipe->set_shader_images = nvc0_set_shader_images;
1442 pipe->set_shader_buffers = nvc0_set_shader_buffers;
1443
1444 nvc0->sample_mask = ~0;
1445 nvc0->min_samples = 1;
1446 nvc0->default_tess_outer[0] =
1447 nvc0->default_tess_outer[1] =
1448 nvc0->default_tess_outer[2] =
1449 nvc0->default_tess_outer[3] = 1.0;
1450 nvc0->default_tess_inner[0] =
1451 nvc0->default_tess_inner[1] = 1.0;
1452 }