1 #include "nv10_context.h"
2 #include "nv10_state.h"
4 static void nv10_state_emit_blend(struct nv10_context
* nv10
)
6 struct nv10_blend_state
*b
= nv10
->blend
;
8 BEGIN_RING(celsius
, NV10TCL_DITHER_ENABLE
, 1);
9 OUT_RING (b
->d_enable
);
11 BEGIN_RING(celsius
, NV10TCL_BLEND_FUNC_ENABLE
, 3);
12 OUT_RING (b
->b_enable
);
13 OUT_RING (b
->b_srcfunc
);
14 OUT_RING (b
->b_dstfunc
);
16 BEGIN_RING(celsius
, NV10TCL_COLOR_MASK
, 1);
20 static void nv10_state_emit_blend_color(struct nv10_context
* nv10
)
22 struct pipe_blend_color
*c
= nv10
->blend_color
;
24 BEGIN_RING(celsius
, NV10TCL_BLEND_COLOR
, 1);
25 OUT_RING ((float_to_ubyte(c
->color
[3]) << 24)|
26 (float_to_ubyte(c
->color
[0]) << 16)|
27 (float_to_ubyte(c
->color
[1]) << 8) |
28 (float_to_ubyte(c
->color
[2]) << 0));
31 static void nv10_state_emit_rast(struct nv10_context
* nv10
)
33 struct nv10_rasterizer_state
*r
= nv10
->rast
;
35 BEGIN_RING(celsius
, NV10TCL_SHADE_MODEL
, 2);
36 OUT_RING (r
->shade_model
);
37 OUT_RING (r
->line_width
);
40 BEGIN_RING(celsius
, NV10TCL_POINT_SIZE
, 1);
41 OUT_RING (r
->point_size
);
43 BEGIN_RING(celsius
, NV10TCL_POLYGON_MODE_FRONT
, 2);
44 OUT_RING (r
->poly_mode_front
);
45 OUT_RING (r
->poly_mode_back
);
48 BEGIN_RING(celsius
, NV10TCL_CULL_FACE
, 2);
49 OUT_RING (r
->cull_face
);
50 OUT_RING (r
->front_face
);
52 BEGIN_RING(celsius
, NV10TCL_LINE_SMOOTH_ENABLE
, 2);
53 OUT_RING (r
->line_smooth_en
);
54 OUT_RING (r
->poly_smooth_en
);
56 BEGIN_RING(celsius
, NV10TCL_CULL_FACE_ENABLE
, 1);
57 OUT_RING (r
->cull_face_en
);
60 static void nv10_state_emit_dsa(struct nv10_context
* nv10
)
62 struct nv10_depth_stencil_alpha_state
*d
= nv10
->dsa
;
64 BEGIN_RING(celsius
, NV10TCL_DEPTH_FUNC
, 1);
65 OUT_RING (d
->depth
.func
);
67 BEGIN_RING(celsius
, NV10TCL_DEPTH_WRITE_ENABLE
, 1);
68 OUT_RING (d
->depth
.write_enable
);
70 BEGIN_RING(celsius
, NV10TCL_DEPTH_TEST_ENABLE
, 1);
71 OUT_RING (d
->depth
.test_enable
);
74 BEGIN_RING(celsius
, NV10TCL_STENCIL_ENABLE
, 1);
75 OUT_RING (d
->stencil
.enable
);
76 BEGIN_RING(celsius
, NV10TCL_STENCIL_MASK
, 7);
77 OUT_RINGp ((uint32_t *)&(d
->stencil
.wmask
), 7);
80 BEGIN_RING(celsius
, NV10TCL_ALPHA_FUNC_ENABLE
, 1);
81 OUT_RING (d
->alpha
.enabled
);
83 BEGIN_RING(celsius
, NV10TCL_ALPHA_FUNC_FUNC
, 1);
84 OUT_RING (d
->alpha
.func
);
86 BEGIN_RING(celsius
, NV10TCL_ALPHA_FUNC_REF
, 1);
87 OUT_RING (d
->alpha
.ref
);
90 static void nv10_state_emit_viewport(struct nv10_context
* nv10
)
94 static void nv10_state_emit_scissor(struct nv10_context
* nv10
)
96 // XXX this is so not working
97 /* struct pipe_scissor_state *s = nv10->scissor;
98 BEGIN_RING(celsius, NV10TCL_SCISSOR_HORIZ, 2);
99 OUT_RING (((s->maxx - s->minx) << 16) | s->minx);
100 OUT_RING (((s->maxy - s->miny) << 16) | s->miny);*/
103 static void nv10_state_emit_framebuffer(struct nv10_context
* nv10
)
105 struct pipe_framebuffer_state
* fb
= nv10
->framebuffer
;
106 struct nv04_surface
*rt
, *zeta
= NULL
;
107 uint32_t rt_format
, w
, h
;
108 int colour_format
= 0, zeta_format
= 0;
109 struct nv10_miptree
*nv10mt
= 0;
111 w
= fb
->cbufs
[0]->width
;
112 h
= fb
->cbufs
[0]->height
;
113 colour_format
= fb
->cbufs
[0]->format
;
114 rt
= (struct nv04_surface
*)fb
->cbufs
[0];
118 assert(w
== fb
->zsbuf
->width
);
119 assert(h
== fb
->zsbuf
->height
);
121 w
= fb
->zsbuf
->width
;
122 h
= fb
->zsbuf
->height
;
125 zeta_format
= fb
->zsbuf
->format
;
126 zeta
= (struct nv04_surface
*)fb
->zsbuf
;
129 rt_format
= NV10TCL_RT_FORMAT_TYPE_LINEAR
;
131 switch (colour_format
) {
132 case PIPE_FORMAT_A8R8G8B8_UNORM
:
134 rt_format
|= NV10TCL_RT_FORMAT_COLOR_A8R8G8B8
;
136 case PIPE_FORMAT_R5G6B5_UNORM
:
137 rt_format
|= NV10TCL_RT_FORMAT_COLOR_R5G6B5
;
144 BEGIN_RING(celsius
, NV10TCL_RT_PITCH
, 1);
145 OUT_RING (rt
->pitch
| (zeta
->pitch
<< 16));
147 BEGIN_RING(celsius
, NV10TCL_RT_PITCH
, 1);
148 OUT_RING (rt
->pitch
| (rt
->pitch
<< 16));
151 nv10mt
= (struct nv10_miptree
*)rt
->base
.texture
;
152 nv10
->rt
[0] = nv10mt
->buffer
;
156 nv10mt
= (struct nv10_miptree
*)zeta
->base
.texture
;
157 nv10
->zeta
= nv10mt
->buffer
;
160 BEGIN_RING(celsius
, NV10TCL_RT_HORIZ
, 3);
161 OUT_RING ((w
<< 16) | 0);
162 OUT_RING ((h
<< 16) | 0);
163 OUT_RING (rt_format
);
164 BEGIN_RING(celsius
, NV10TCL_VIEWPORT_CLIP_HORIZ(0), 2);
165 OUT_RING (((w
- 1) << 16) | 0 | 0x08000800);
166 OUT_RING (((h
- 1) << 16) | 0 | 0x08000800);
169 static void nv10_vertex_layout(struct nv10_context
*nv10
)
171 struct nv10_fragment_program
*fp
= nv10
->fragprog
.current
;
174 struct vertex_info vinfo
;
176 memset(&vinfo
, 0, sizeof(vinfo
));
178 for (i
= 0; i
< fp
->info
.num_inputs
; i
++) {
179 switch (fp
->info
.input_semantic_name
[i
]) {
180 case TGSI_SEMANTIC_POSITION
:
181 draw_emit_vertex_attr(&vinfo
, EMIT_4F
, INTERP_LINEAR
, src
++);
183 case TGSI_SEMANTIC_COLOR
:
184 draw_emit_vertex_attr(&vinfo
, EMIT_4F
, INTERP_LINEAR
, src
++);
187 case TGSI_SEMANTIC_GENERIC
:
188 draw_emit_vertex_attr(&vinfo
, EMIT_4F
, INTERP_PERSPECTIVE
, src
++);
190 case TGSI_SEMANTIC_FOG
:
191 draw_emit_vertex_attr(&vinfo
, EMIT_4F
, INTERP_PERSPECTIVE
, src
++);
195 draw_compute_vertex_size(&vinfo
);
199 nv10_emit_hw_state(struct nv10_context
*nv10
)
203 if (nv10
->dirty
& NV10_NEW_VERTPROG
) {
204 //nv10_vertprog_bind(nv10, nv10->vertprog.current);
205 nv10
->dirty
&= ~NV10_NEW_VERTPROG
;
208 if (nv10
->dirty
& NV10_NEW_FRAGPROG
) {
209 nv10_fragprog_bind(nv10
, nv10
->fragprog
.current
);
210 /*XXX: clear NV10_NEW_FRAGPROG if no new program uploaded */
211 nv10
->dirty_samplers
|= (1<<10);
212 nv10
->dirty_samplers
= 0;
215 if (nv10
->dirty_samplers
|| (nv10
->dirty
& NV10_NEW_FRAGPROG
)) {
216 nv10_fragtex_bind(nv10
);
217 nv10
->dirty
&= ~NV10_NEW_FRAGPROG
;
220 if (nv10
->dirty
& NV10_NEW_VTXARRAYS
) {
221 nv10
->dirty
&= ~NV10_NEW_VTXARRAYS
;
222 nv10_vertex_layout(nv10
);
223 nv10_vtxbuf_bind(nv10
);
226 if (nv10
->dirty
& NV10_NEW_BLEND
) {
227 nv10
->dirty
&= ~NV10_NEW_BLEND
;
228 nv10_state_emit_blend(nv10
);
231 if (nv10
->dirty
& NV10_NEW_BLENDCOL
) {
232 nv10
->dirty
&= ~NV10_NEW_BLENDCOL
;
233 nv10_state_emit_blend_color(nv10
);
236 if (nv10
->dirty
& NV10_NEW_RAST
) {
237 nv10
->dirty
&= ~NV10_NEW_RAST
;
238 nv10_state_emit_rast(nv10
);
241 if (nv10
->dirty
& NV10_NEW_DSA
) {
242 nv10
->dirty
&= ~NV10_NEW_DSA
;
243 nv10_state_emit_dsa(nv10
);
246 if (nv10
->dirty
& NV10_NEW_VIEWPORT
) {
247 nv10
->dirty
&= ~NV10_NEW_VIEWPORT
;
248 nv10_state_emit_viewport(nv10
);
251 if (nv10
->dirty
& NV10_NEW_SCISSOR
) {
252 nv10
->dirty
&= ~NV10_NEW_SCISSOR
;
253 nv10_state_emit_scissor(nv10
);
256 if (nv10
->dirty
& NV10_NEW_FRAMEBUFFER
) {
257 nv10
->dirty
&= ~NV10_NEW_FRAMEBUFFER
;
258 nv10_state_emit_framebuffer(nv10
);
261 /* Emit relocs for every referenced buffer.
262 * This is to ensure the bufmgr has an accurate idea of how
263 * the buffer is used. This isn't very efficient, but we don't
264 * seem to take a significant performance hit. Will be improved
265 * at some point. Vertex arrays are emitted by nv10_vbo.c
269 // XXX figre out who's who for NV10TCL_DMA_* and fill accordingly
270 // BEGIN_RING(celsius, NV10TCL_DMA_COLOR0, 1);
271 // OUT_RELOCo(nv10->rt[0], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
272 BEGIN_RING(celsius
, NV10TCL_COLOR_OFFSET
, 1);
273 OUT_RELOCl(nv10
->rt
[0], 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
277 // BEGIN_RING(celsius, NV10TCL_DMA_ZETA, 1);
278 // OUT_RELOCo(nv10->zeta, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
279 BEGIN_RING(celsius
, NV10TCL_ZETA_OFFSET
, 1);
280 OUT_RELOCl(nv10
->zeta
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
281 /* XXX for when we allocate LMA on nv17 */
282 /* BEGIN_RING(celsius, NV10TCL_LMA_DEPTH_BUFFER_OFFSET, 1);
283 OUT_RELOCl(nv10->zeta + lma_offset);*/
287 BEGIN_RING(celsius
, NV10TCL_DMA_VTXBUF0
, 1);
288 OUT_RELOCo(nv10
->rt
[0], NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
289 BEGIN_RING(celsius
, NV10TCL_COLOR_OFFSET
, 1);
290 OUT_RELOCl(nv10
->rt
[0], 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
);
293 for (i
= 0; i
< 2; i
++) {
294 if (!(nv10
->fp_samplers
& (1 << i
)))
296 BEGIN_RING(celsius
, NV10TCL_TX_OFFSET(i
), 1);
297 OUT_RELOCl(nv10
->tex
[i
].buffer
, 0, NOUVEAU_BO_VRAM
|
298 NOUVEAU_BO_GART
| NOUVEAU_BO_RD
);
299 BEGIN_RING(celsius
, NV10TCL_TX_FORMAT(i
), 1);
300 OUT_RELOCd(nv10
->tex
[i
].buffer
, nv10
->tex
[i
].format
,
301 NOUVEAU_BO_VRAM
| NOUVEAU_BO_GART
| NOUVEAU_BO_RD
|
302 NOUVEAU_BO_OR
, NV10TCL_TX_FORMAT_DMA0
,
303 NV10TCL_TX_FORMAT_DMA1
);