src/gallium/drivers/nv30/nv30_screen.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *
  24  */
  25
  26 #include "util/u_format.h"
  27 #include "util/u_format_s3tc.h"
  28
  29 #include "nouveau/nv_object.xml.h"
  30 #include "nouveau/nv_m2mf.xml.h"
  31 #include "nv30-40_3d.xml.h"
  32 #include "nv01_2d.xml.h"
  33
  34 #include "nouveau/nouveau_fence.h"
  35 #include "nv30_screen.h"
  36 #include "nv30_context.h"
  37 #include "nv30_resource.h"
  38 #include "nv30_format.h"
  39
  40 #define RANKINE_0397_CHIPSET 0x00000003
  41 #define RANKINE_0497_CHIPSET 0x000001e0
  42 #define RANKINE_0697_CHIPSET 0x00000010
  43 #define CURIE_4097_CHIPSET   0x00000baf
  44 #define CURIE_4497_CHIPSET   0x00005450
  45 #define CURIE_4497_CHIPSET6X 0x00000088
  46
  47 static int
  48 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  49 {
  50    struct nv30_screen *screen = nv30_screen(pscreen);
  51    struct nouveau_object *eng3d = screen->eng3d;
  52
  53    switch (param) {
  54    /* non-boolean capabilities */
  55    case PIPE_CAP_MAX_RENDER_TARGETS:
  56       return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
  57    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  58       return 13;
  59    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  60       return 10;
  61    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  62       return 13;
  63    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  64       return 16;
  65    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  66       return 120;
  67    /* supported capabilities */
  68    case PIPE_CAP_TWO_SIDED_STENCIL:
  69    case PIPE_CAP_ANISOTROPIC_FILTER:
  70    case PIPE_CAP_POINT_SPRITE:
  71    case PIPE_CAP_SCALED_RESOLVE:
  72    case PIPE_CAP_OCCLUSION_QUERY:
  73    case PIPE_CAP_QUERY_TIME_ELAPSED:
  74    case PIPE_CAP_QUERY_TIMESTAMP:
  75    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  76    case PIPE_CAP_TEXTURE_SWIZZLE:
  77    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  78    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  79    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  80    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  81    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  82    case PIPE_CAP_TGSI_TEXCOORD:
  83    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  84    case PIPE_CAP_USER_INDEX_BUFFERS:
  85       return 1;
  86    case PIPE_CAP_USER_VERTEX_BUFFERS:
  87       return 0;
  88    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  89       return 16;
  90    /* nv4x capabilities */
  91    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  92    case PIPE_CAP_NPOT_TEXTURES:
  93    case PIPE_CAP_CONDITIONAL_RENDER:
  94    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  95    case PIPE_CAP_PRIMITIVE_RESTART:
  96       return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
  97    /* unsupported */
  98    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  99    case PIPE_CAP_SM3:
 100    case PIPE_CAP_INDEP_BLEND_ENABLE:
 101    case PIPE_CAP_INDEP_BLEND_FUNC:
 102    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 103    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 104    case PIPE_CAP_TGSI_INSTANCEID:
 105    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
 106    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 107    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 108    case PIPE_CAP_MIN_TEXEL_OFFSET:
 109    case PIPE_CAP_MAX_TEXEL_OFFSET:
 110    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 111    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 112    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 113    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 114    case PIPE_CAP_TEXTURE_BARRIER:
 115    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 116    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 117    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 118    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 119    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 120    case PIPE_CAP_START_INSTANCE:
 121    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 122    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 123    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 124    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 125    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 126       return 0;
 127    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 128    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 129    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 130    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 131       return 1;
 132    default:
 133       debug_printf("unknown param %d\n", param);
 134       return 0;
 135    }
 136 }
 137
 138 static float
 139 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 140 {
 141    struct nv30_screen *screen = nv30_screen(pscreen);
 142    struct nouveau_object *eng3d = screen->eng3d;
 143
 144    switch (param) {
 145    case PIPE_CAPF_MAX_LINE_WIDTH:
 146    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 147       return 10.0;
 148    case PIPE_CAPF_MAX_POINT_WIDTH:
 149    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 150       return 64.0;
 151    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 152       return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
 153    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 154       return 15.0;
 155    default:
 156       debug_printf("unknown paramf %d\n", param);
 157       return 0;
 158    }
 159 }
 160
 161 static int
 162 nv30_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 163                              enum pipe_shader_cap param)
 164 {
 165    struct nv30_screen *screen = nv30_screen(pscreen);
 166    struct nouveau_object *eng3d = screen->eng3d;
 167
 168    switch (shader) {
 169    case PIPE_SHADER_VERTEX:
 170       switch (param) {
 171       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 172       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 173          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
 174       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 175       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 176          return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
 177       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 178          return 0;
 179       case PIPE_SHADER_CAP_MAX_INPUTS:
 180          return 16;
 181       case PIPE_SHADER_CAP_MAX_CONSTS:
 182          return (eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6);
 183       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 184          return 1;
 185       case PIPE_SHADER_CAP_MAX_TEMPS:
 186          return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
 187       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 188          return 0;
 189       case PIPE_SHADER_CAP_MAX_ADDRS:
 190          return 2;
 191       case PIPE_SHADER_CAP_MAX_PREDS:
 192       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 193       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 194       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 195       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 196       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 197       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 198       case PIPE_SHADER_CAP_SUBROUTINES:
 199       case PIPE_SHADER_CAP_INTEGERS:
 200          return 0;
 201       default:
 202          debug_printf("unknown vertex shader param %d\n", param);
 203          return 0;
 204       }
 205       break;
 206    case PIPE_SHADER_FRAGMENT:
 207       switch (param) {
 208       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 209       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 210       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 211       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 212          return 4096;
 213       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 214          return 0;
 215       case PIPE_SHADER_CAP_MAX_INPUTS:
 216          return (eng3d->oclass >= NV40_3D_CLASS) ? 12 : 10;
 217       case PIPE_SHADER_CAP_MAX_CONSTS:
 218          return (eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32;
 219       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 220          return 1;
 221       case PIPE_SHADER_CAP_MAX_TEMPS:
 222          return 32;
 223       case PIPE_SHADER_CAP_MAX_ADDRS:
 224          return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
 225       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 226          return 16;
 227       case PIPE_SHADER_CAP_MAX_PREDS:
 228       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 229       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 230       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 231       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 232       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 233       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 234       case PIPE_SHADER_CAP_SUBROUTINES:
 235          return 0;
 236       default:
 237          debug_printf("unknown fragment shader param %d\n", param);
 238          return 0;
 239       }
 240       break;
 241    default:
 242       return 0;
 243    }
 244 }
 245
 246 static boolean
 247 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
 248                                 enum pipe_format format,
 249                                 enum pipe_texture_target target,
 250                                 unsigned sample_count,
 251                                 unsigned bindings)
 252 {
 253    if (sample_count > 4)
 254       return FALSE;
 255    if (!(0x00000017 & (1 << sample_count)))
 256       return FALSE;
 257
 258    if (!util_format_is_supported(format, bindings)) {
 259       return FALSE;
 260    }
 261
 262    /* transfers & shared are always supported */
 263    bindings &= ~(PIPE_BIND_TRANSFER_READ |
 264                  PIPE_BIND_TRANSFER_WRITE |
 265                  PIPE_BIND_SHARED);
 266
 267    return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
 268 }
 269
 270 static void
 271 nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
 272 {
 273    struct nv30_screen *screen = nv30_screen(pscreen);
 274    struct nouveau_pushbuf *push = screen->base.pushbuf;
 275
 276    *sequence = ++screen->base.fence.sequence;
 277
 278    BEGIN_NV04(push, NV30_3D(FENCE_OFFSET), 2);
 279    PUSH_DATA (push, 0);
 280    PUSH_DATA (push, *sequence);
 281 }
 282
 283 static uint32_t
 284 nv30_screen_fence_update(struct pipe_screen *pscreen)
 285 {
 286    struct nv30_screen *screen = nv30_screen(pscreen);
 287    struct nv04_notify *fence = screen->fence->data;
 288    return *(uint32_t *)((char *)screen->notify->map + fence->offset);
 289 }
 290
 291 static void
 292 nv30_screen_destroy(struct pipe_screen *pscreen)
 293 {
 294    struct nv30_screen *screen = nv30_screen(pscreen);
 295
 296    if (screen->base.fence.current &&
 297        screen->base.fence.current->state >= NOUVEAU_FENCE_STATE_EMITTED) {
 298       nouveau_fence_wait(screen->base.fence.current);
 299       nouveau_fence_ref (NULL, &screen->base.fence.current);
 300    }
 301
 302    nouveau_object_del(&screen->query);
 303    nouveau_object_del(&screen->fence);
 304    nouveau_object_del(&screen->ntfy);
 305
 306    nouveau_object_del(&screen->sifm);
 307    nouveau_object_del(&screen->swzsurf);
 308    nouveau_object_del(&screen->surf2d);
 309    nouveau_object_del(&screen->m2mf);
 310    nouveau_object_del(&screen->eng3d);
 311    nouveau_object_del(&screen->null);
 312
 313    nouveau_screen_fini(&screen->base);
 314    FREE(screen);
 315 }
 316
 317 #define FAIL_SCREEN_INIT(str, err)                    \
 318    do {                                               \
 319       NOUVEAU_ERR(str, err);                          \
 320       nv30_screen_destroy(pscreen);                   \
 321       return NULL;                                    \
 322    } while(0)
 323
 324 struct pipe_screen *
 325 nv30_screen_create(struct nouveau_device *dev)
 326 {
 327    struct nv30_screen *screen = CALLOC_STRUCT(nv30_screen);
 328    struct pipe_screen *pscreen;
 329    struct nouveau_pushbuf *push;
 330    struct nv04_fifo *fifo;
 331    unsigned oclass = 0;
 332    int ret, i;
 333
 334    if (!screen)
 335       return NULL;
 336
 337    switch (dev->chipset & 0xf0) {
 338    case 0x30:
 339       if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
 340          oclass = NV30_3D_CLASS;
 341       else
 342       if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
 343          oclass = NV34_3D_CLASS;
 344       else
 345       if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 346          oclass = NV35_3D_CLASS;
 347       break;
 348    case 0x40:
 349       if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
 350          oclass = NV40_3D_CLASS;
 351       else
 352       if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
 353          oclass = NV44_3D_CLASS;
 354       break;
 355    case 0x60:
 356       if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
 357          oclass = NV44_3D_CLASS;
 358       break;
 359    default:
 360       break;
 361    }
 362
 363    if (!oclass) {
 364       NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
 365       FREE(screen);
 366       return NULL;
 367    }
 368
 369    pscreen = &screen->base.base;
 370    pscreen->destroy = nv30_screen_destroy;
 371    pscreen->get_param = nv30_screen_get_param;
 372    pscreen->get_paramf = nv30_screen_get_paramf;
 373    pscreen->get_shader_param = nv30_screen_get_shader_param;
 374    pscreen->context_create = nv30_context_create;
 375    pscreen->is_format_supported = nv30_screen_is_format_supported;
 376    nv30_resource_screen_init(pscreen);
 377
 378    screen->base.fence.emit = nv30_screen_fence_emit;
 379    screen->base.fence.update = nv30_screen_fence_update;
 380
 381    ret = nouveau_screen_init(&screen->base, dev);
 382    if (ret)
 383       FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
 384
 385    screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 386    screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
 387    if (oclass == NV40_3D_CLASS) {
 388       screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 389       screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
 390    }
 391
 392    fifo = screen->base.channel->data;
 393    push = screen->base.pushbuf;
 394    push->rsvd_kick = 16;
 395
 396    ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
 397                             NULL, 0, &screen->null);
 398    if (ret)
 399       FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
 400
 401    /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
 402     * this means that the address pointed at by the DMA object must
 403     * be 4KiB aligned, which means this object needs to be the first
 404     * one allocated on the channel.
 405     */
 406    ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
 407                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 408                             .length = 32 }, sizeof(struct nv04_notify),
 409                             &screen->fence);
 410    if (ret)
 411       FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
 412
 413    /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
 414    ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
 415                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 416                             .length = 32 }, sizeof(struct nv04_notify),
 417                             &screen->ntfy);
 418    if (ret)
 419       FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
 420
 421    /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
 422     * the remainder of the "notifier block" assigned by the kernel for
 423     * use as query objects
 424     */
 425    ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
 426                             NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
 427                             .length = 4096 - 128 }, sizeof(struct nv04_notify),
 428                             &screen->query);
 429    if (ret)
 430       FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
 431
 432    ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
 433    if (ret)
 434       FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
 435
 436    LIST_INITHEAD(&screen->queries);
 437
 438    /* Vertex program resources (code/data), currently 6 of the constant
 439     * slots are reserved to implement user clipping planes
 440     */
 441    if (oclass < NV40_3D_CLASS) {
 442       nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
 443       nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
 444    } else {
 445       nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
 446       nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
 447    }
 448
 449    ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
 450    if (ret == 0)
 451       nouveau_bo_map(screen->notify, 0, screen->base.client);
 452    if (ret)
 453       FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
 454
 455    ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
 456                             NULL, 0, &screen->eng3d);
 457    if (ret)
 458       FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
 459
 460    BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
 461    PUSH_DATA (push, screen->eng3d->handle);
 462    BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
 463    PUSH_DATA (push, screen->ntfy->handle);
 464    PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
 465    PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
 466    PUSH_DATA (push, fifo->vram);     /* COLOR1 */
 467    PUSH_DATA (push, screen->null->handle);  /* UNK190 */
 468    PUSH_DATA (push, fifo->vram);     /* COLOR0 */
 469    PUSH_DATA (push, fifo->vram);     /* ZETA */
 470    PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
 471    PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
 472    PUSH_DATA (push, screen->fence->handle);  /* FENCE */
 473    PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
 474    PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
 475    PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
 476    if (screen->eng3d->oclass < NV40_3D_CLASS) {
 477       BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
 478       PUSH_DATA (push, 0x00100000);
 479       BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
 480       PUSH_DATA (push, 3);
 481
 482       BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
 483       PUSH_DATA (push, 0);
 484       BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
 485       PUSH_DATA (push, fui(0.0));
 486       PUSH_DATA (push, fui(0.0));
 487       PUSH_DATA (push, fui(1.0));
 488       BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
 489       for (i = 0; i < 16; i++)
 490          PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
 491
 492       BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
 493       PUSH_DATA (push, 0);
 494    } else {
 495       BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
 496       PUSH_DATA (push, fifo->vram);
 497       PUSH_DATA (push, fifo->vram);  /* COLOR3 */
 498
 499       BEGIN_NV04(push, SUBC_3D(0x1450), 1);
 500       PUSH_DATA (push, 0x00000004);
 501
 502       BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
 503       PUSH_DATA (push, 0x00000010);
 504       PUSH_DATA (push, 0x01000100);
 505       PUSH_DATA (push, 0xff800006);
 506
 507       /* vtxprog output routing */
 508       BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
 509       PUSH_DATA (push, 0x06144321);
 510       BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
 511       PUSH_DATA (push, 0xedcba987);
 512       PUSH_DATA (push, 0x0000006f);
 513       BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
 514       PUSH_DATA (push, 0x00171615);
 515       BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
 516       PUSH_DATA (push, 0x001b1a19);
 517
 518       BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
 519       PUSH_DATA (push, 0x0020ffff);
 520       BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
 521       PUSH_DATA (push, 0x01d300d4);
 522
 523       BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
 524       PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 525    }
 526
 527    ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
 528                             NULL, 0, &screen->m2mf);
 529    if (ret)
 530       FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
 531
 532    BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
 533    PUSH_DATA (push, screen->m2mf->handle);
 534    BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
 535    PUSH_DATA (push, screen->ntfy->handle);
 536
 537    ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
 538                             NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
 539    if (ret)
 540       FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
 541
 542    BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
 543    PUSH_DATA (push, screen->surf2d->handle);
 544    BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
 545    PUSH_DATA (push, screen->ntfy->handle);
 546
 547    if (dev->chipset < 0x40)
 548       oclass = NV30_SURFACE_SWZ_CLASS;
 549    else
 550       oclass = NV40_SURFACE_SWZ_CLASS;
 551
 552    ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
 553                             NULL, 0, &screen->swzsurf);
 554    if (ret)
 555       FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
 556
 557    BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
 558    PUSH_DATA (push, screen->swzsurf->handle);
 559    BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
 560    PUSH_DATA (push, screen->ntfy->handle);
 561
 562    if (dev->chipset < 0x40)
 563       oclass = NV30_SIFM_CLASS;
 564    else
 565       oclass = NV40_SIFM_CLASS;
 566
 567    ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
 568                             NULL, 0, &screen->sifm);
 569    if (ret)
 570       FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
 571
 572    BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
 573    PUSH_DATA (push, screen->sifm->handle);
 574    BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
 575    PUSH_DATA (push, screen->ntfy->handle);
 576    BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
 577    PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
 578
 579    nouveau_pushbuf_kick(push, push->channel);
 580
 581    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 582    return pscreen;
 583 }