src/gallium/drivers/nv30/nv30_state_fb.c

   1 #include "nv30_context.h"
   2
   3 static boolean
   4 nv30_state_framebuffer_validate(struct nv30_context *nv30)
   5 {
   6         struct pipe_framebuffer_state *fb = &nv30->framebuffer;
   7         struct pipe_surface *rt[2], *zeta = NULL;
   8         uint32_t rt_enable, rt_format;
   9         int i, colour_format = 0, zeta_format = 0;
  10         struct nouveau_stateobj *so = so_new(64, 10);
  11         unsigned rt_flags = NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM;
  12         unsigned w = fb->width;
  13         unsigned h = fb->height;
  14
  15         rt_enable = 0;
  16         for (i = 0; i < fb->num_cbufs; i++) {
  17                 if (colour_format) {
  18                         assert(colour_format == fb->cbufs[i]->format);
  19                 } else {
  20                         colour_format = fb->cbufs[i]->format;
  21                         rt_enable |= (NV34TCL_RT_ENABLE_COLOR0 << i);
  22                         rt[i] = fb->cbufs[i];
  23                 }
  24         }
  25
  26         if (rt_enable & NV34TCL_RT_ENABLE_COLOR1)
  27                 rt_enable |= NV34TCL_RT_ENABLE_MRT;
  28
  29         if (fb->zsbuf) {
  30                 zeta_format = fb->zsbuf->format;
  31                 zeta = fb->zsbuf;
  32         }
  33
  34         rt_format = NV34TCL_RT_FORMAT_TYPE_LINEAR;
  35
  36         switch (colour_format) {
  37         case PIPE_FORMAT_A8R8G8B8_UNORM:
  38         case 0:
  39                 rt_format |= NV34TCL_RT_FORMAT_COLOR_A8R8G8B8;
  40                 break;
  41         case PIPE_FORMAT_R5G6B5_UNORM:
  42                 rt_format |= NV34TCL_RT_FORMAT_COLOR_R5G6B5;
  43                 break;
  44         default:
  45                 assert(0);
  46         }
  47
  48         switch (zeta_format) {
  49         case PIPE_FORMAT_Z16_UNORM:
  50                 rt_format |= NV34TCL_RT_FORMAT_ZETA_Z16;
  51                 break;
  52         case PIPE_FORMAT_Z24S8_UNORM:
  53         case 0:
  54                 rt_format |= NV34TCL_RT_FORMAT_ZETA_Z24S8;
  55                 break;
  56         default:
  57                 assert(0);
  58         }
  59
  60         if (rt_enable & NV34TCL_RT_ENABLE_COLOR0) {
  61                 uint32_t pitch = rt[0]->stride;
  62                 if (zeta) {
  63                         pitch |= (zeta->stride << 16);
  64                 } else {
  65                         pitch |= (pitch << 16);
  66                 }
  67
  68                 so_method(so, nv30->screen->rankine, NV34TCL_DMA_COLOR0, 1);
  69                 so_reloc (so, rt[0]->buffer, 0, rt_flags | NOUVEAU_BO_OR,
  70                           nv30->nvws->channel->vram->handle,
  71                           nv30->nvws->channel->gart->handle);
  72                 so_method(so, nv30->screen->rankine, NV34TCL_COLOR0_PITCH, 2);
  73                 so_data  (so, pitch);
  74                 so_reloc (so, rt[0]->buffer, rt[0]->offset, rt_flags |
  75                           NOUVEAU_BO_LOW, 0, 0);
  76         }
  77
  78         if (rt_enable & NV34TCL_RT_ENABLE_COLOR1) {
  79                 so_method(so, nv30->screen->rankine, NV34TCL_DMA_COLOR1, 1);
  80                 so_reloc (so, rt[1]->buffer, 0, rt_flags | NOUVEAU_BO_OR,
  81                           nv30->nvws->channel->vram->handle,
  82                           nv30->nvws->channel->gart->handle);
  83                 so_method(so, nv30->screen->rankine, NV34TCL_COLOR1_OFFSET, 2);
  84                 so_reloc (so, rt[1]->buffer, rt[1]->offset, rt_flags |
  85                           NOUVEAU_BO_LOW, 0, 0);
  86                 so_data  (so, rt[1]->stride);
  87         }
  88
  89         if (zeta_format) {
  90                 so_method(so, nv30->screen->rankine, NV34TCL_DMA_ZETA, 1);
  91                 so_reloc (so, zeta->buffer, 0, rt_flags | NOUVEAU_BO_OR,
  92                           nv30->nvws->channel->vram->handle,
  93                           nv30->nvws->channel->gart->handle);
  94                 so_method(so, nv30->screen->rankine, NV34TCL_ZETA_OFFSET, 1);
  95                 so_reloc (so, zeta->buffer, zeta->offset, rt_flags |
  96                           NOUVEAU_BO_LOW, 0, 0);
  97                 /* TODO: allocate LMA depth buffer */
  98         }
  99
 100         so_method(so, nv30->screen->rankine, NV34TCL_RT_ENABLE, 1);
 101         so_data  (so, rt_enable);
 102         so_method(so, nv30->screen->rankine, NV34TCL_RT_HORIZ, 3);
 103         so_data  (so, (w << 16) | 0);
 104         so_data  (so, (h << 16) | 0);
 105         so_data  (so, rt_format);
 106         so_method(so, nv30->screen->rankine, NV34TCL_VIEWPORT_HORIZ, 2);
 107         so_data  (so, (w << 16) | 0);
 108         so_data  (so, (h << 16) | 0);
 109         so_method(so, nv30->screen->rankine, NV34TCL_VIEWPORT_CLIP_HORIZ(0), 2);
 110         so_data  (so, ((w - 1) << 16) | 0);
 111         so_data  (so, ((h - 1) << 16) | 0);
 112         so_method(so, nv30->screen->rankine, 0x1d88, 1);
 113         so_data  (so, (1 << 12) | h);
 114         /* Wonder why this is needed, context should all be set to zero on init */
 115         so_method(so, nv30->screen->rankine, NV34TCL_VIEWPORT_TX_ORIGIN, 1);
 116         so_data  (so, 0);
 117
 118         so_ref(so, &nv30->state.hw[NV30_STATE_FB]);
 119         return TRUE;
 120 }
 121
 122 struct nv30_state_entry nv30_state_framebuffer = {
 123         .validate = nv30_state_framebuffer_validate,
 124         .dirty = {
 125                 .pipe = NV30_NEW_FB,
 126                 .hw = NV30_STATE_FB
 127         }
 128 };