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Merge branch 'mesa_7_5_branch'
[mesa.git] / src / gallium / drivers / nv40 / nv40_fragprog.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "pipe/p_inlines.h"
5
6 #include "pipe/p_shader_tokens.h"
7 #include "tgsi/tgsi_parse.h"
8 #include "tgsi/tgsi_util.h"
9
10 #include "nv40_context.h"
11
12 #define SWZ_X 0
13 #define SWZ_Y 1
14 #define SWZ_Z 2
15 #define SWZ_W 3
16 #define MASK_X 1
17 #define MASK_Y 2
18 #define MASK_Z 4
19 #define MASK_W 8
20 #define MASK_ALL (MASK_X|MASK_Y|MASK_Z|MASK_W)
21 #define DEF_SCALE NV40_FP_OP_DST_SCALE_1X
22 #define DEF_CTEST NV40_FP_OP_COND_TR
23 #include "nv40_shader.h"
24
25 #define swz(s,x,y,z,w) nv40_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w)
26 #define neg(s) nv40_sr_neg((s))
27 #define abs(s) nv40_sr_abs((s))
28 #define scale(s,v) nv40_sr_scale((s), NV40_FP_OP_DST_SCALE_##v)
29
30 #define MAX_CONSTS 128
31 #define MAX_IMM 32
32 struct nv40_fpc {
33 struct nv40_fragment_program *fp;
34
35 uint attrib_map[PIPE_MAX_SHADER_INPUTS];
36
37 unsigned r_temps;
38 unsigned r_temps_discard;
39 struct nv40_sreg r_result[PIPE_MAX_SHADER_OUTPUTS];
40 struct nv40_sreg *r_temp;
41
42 int num_regs;
43
44 unsigned inst_offset;
45 unsigned have_const;
46
47 struct {
48 int pipe;
49 float vals[4];
50 } consts[MAX_CONSTS];
51 int nr_consts;
52
53 struct nv40_sreg imm[MAX_IMM];
54 unsigned nr_imm;
55 };
56
57 static INLINE struct nv40_sreg
58 temp(struct nv40_fpc *fpc)
59 {
60 int idx = ffs(~fpc->r_temps) - 1;
61
62 if (idx < 0) {
63 NOUVEAU_ERR("out of temps!!\n");
64 assert(0);
65 return nv40_sr(NV40SR_TEMP, 0);
66 }
67
68 fpc->r_temps |= (1 << idx);
69 fpc->r_temps_discard |= (1 << idx);
70 return nv40_sr(NV40SR_TEMP, idx);
71 }
72
73 static INLINE void
74 release_temps(struct nv40_fpc *fpc)
75 {
76 fpc->r_temps &= ~fpc->r_temps_discard;
77 fpc->r_temps_discard = 0;
78 }
79
80 static INLINE struct nv40_sreg
81 constant(struct nv40_fpc *fpc, int pipe, float vals[4])
82 {
83 int idx;
84
85 if (fpc->nr_consts == MAX_CONSTS)
86 assert(0);
87 idx = fpc->nr_consts++;
88
89 fpc->consts[idx].pipe = pipe;
90 if (pipe == -1)
91 memcpy(fpc->consts[idx].vals, vals, 4 * sizeof(float));
92 return nv40_sr(NV40SR_CONST, idx);
93 }
94
95 #define arith(cc,s,o,d,m,s0,s1,s2) \
96 nv40_fp_arith((cc), (s), NV40_FP_OP_OPCODE_##o, \
97 (d), (m), (s0), (s1), (s2))
98 #define tex(cc,s,o,u,d,m,s0,s1,s2) \
99 nv40_fp_tex((cc), (s), NV40_FP_OP_OPCODE_##o, (u), \
100 (d), (m), (s0), none, none)
101
102 static void
103 grow_insns(struct nv40_fpc *fpc, int size)
104 {
105 struct nv40_fragment_program *fp = fpc->fp;
106
107 fp->insn_len += size;
108 fp->insn = realloc(fp->insn, sizeof(uint32_t) * fp->insn_len);
109 }
110
111 static void
112 emit_src(struct nv40_fpc *fpc, int pos, struct nv40_sreg src)
113 {
114 struct nv40_fragment_program *fp = fpc->fp;
115 uint32_t *hw = &fp->insn[fpc->inst_offset];
116 uint32_t sr = 0;
117
118 switch (src.type) {
119 case NV40SR_INPUT:
120 sr |= (NV40_FP_REG_TYPE_INPUT << NV40_FP_REG_TYPE_SHIFT);
121 hw[0] |= (src.index << NV40_FP_OP_INPUT_SRC_SHIFT);
122 break;
123 case NV40SR_OUTPUT:
124 sr |= NV40_FP_REG_SRC_HALF;
125 /* fall-through */
126 case NV40SR_TEMP:
127 sr |= (NV40_FP_REG_TYPE_TEMP << NV40_FP_REG_TYPE_SHIFT);
128 sr |= (src.index << NV40_FP_REG_SRC_SHIFT);
129 break;
130 case NV40SR_CONST:
131 if (!fpc->have_const) {
132 grow_insns(fpc, 4);
133 fpc->have_const = 1;
134 }
135
136 hw = &fp->insn[fpc->inst_offset];
137 if (fpc->consts[src.index].pipe >= 0) {
138 struct nv40_fragment_program_data *fpd;
139
140 fp->consts = realloc(fp->consts, ++fp->nr_consts *
141 sizeof(*fpd));
142 fpd = &fp->consts[fp->nr_consts - 1];
143 fpd->offset = fpc->inst_offset + 4;
144 fpd->index = fpc->consts[src.index].pipe;
145 memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4);
146 } else {
147 memcpy(&fp->insn[fpc->inst_offset + 4],
148 fpc->consts[src.index].vals,
149 sizeof(uint32_t) * 4);
150 }
151
152 sr |= (NV40_FP_REG_TYPE_CONST << NV40_FP_REG_TYPE_SHIFT);
153 break;
154 case NV40SR_NONE:
155 sr |= (NV40_FP_REG_TYPE_INPUT << NV40_FP_REG_TYPE_SHIFT);
156 break;
157 default:
158 assert(0);
159 }
160
161 if (src.negate)
162 sr |= NV40_FP_REG_NEGATE;
163
164 if (src.abs)
165 hw[1] |= (1 << (29 + pos));
166
167 sr |= ((src.swz[0] << NV40_FP_REG_SWZ_X_SHIFT) |
168 (src.swz[1] << NV40_FP_REG_SWZ_Y_SHIFT) |
169 (src.swz[2] << NV40_FP_REG_SWZ_Z_SHIFT) |
170 (src.swz[3] << NV40_FP_REG_SWZ_W_SHIFT));
171
172 hw[pos + 1] |= sr;
173 }
174
175 static void
176 emit_dst(struct nv40_fpc *fpc, struct nv40_sreg dst)
177 {
178 struct nv40_fragment_program *fp = fpc->fp;
179 uint32_t *hw = &fp->insn[fpc->inst_offset];
180
181 switch (dst.type) {
182 case NV40SR_TEMP:
183 if (fpc->num_regs < (dst.index + 1))
184 fpc->num_regs = dst.index + 1;
185 break;
186 case NV40SR_OUTPUT:
187 if (dst.index == 1) {
188 fp->fp_control |= 0xe;
189 } else {
190 hw[0] |= NV40_FP_OP_OUT_REG_HALF;
191 }
192 break;
193 case NV40SR_NONE:
194 hw[0] |= (1 << 30);
195 break;
196 default:
197 assert(0);
198 }
199
200 hw[0] |= (dst.index << NV40_FP_OP_OUT_REG_SHIFT);
201 }
202
203 static void
204 nv40_fp_arith(struct nv40_fpc *fpc, int sat, int op,
205 struct nv40_sreg dst, int mask,
206 struct nv40_sreg s0, struct nv40_sreg s1, struct nv40_sreg s2)
207 {
208 struct nv40_fragment_program *fp = fpc->fp;
209 uint32_t *hw;
210
211 fpc->inst_offset = fp->insn_len;
212 fpc->have_const = 0;
213 grow_insns(fpc, 4);
214 hw = &fp->insn[fpc->inst_offset];
215 memset(hw, 0, sizeof(uint32_t) * 4);
216
217 if (op == NV40_FP_OP_OPCODE_KIL)
218 fp->fp_control |= NV40TCL_FP_CONTROL_KIL;
219 hw[0] |= (op << NV40_FP_OP_OPCODE_SHIFT);
220 hw[0] |= (mask << NV40_FP_OP_OUTMASK_SHIFT);
221 hw[2] |= (dst.dst_scale << NV40_FP_OP_DST_SCALE_SHIFT);
222
223 if (sat)
224 hw[0] |= NV40_FP_OP_OUT_SAT;
225
226 if (dst.cc_update)
227 hw[0] |= NV40_FP_OP_COND_WRITE_ENABLE;
228 hw[1] |= (dst.cc_test << NV40_FP_OP_COND_SHIFT);
229 hw[1] |= ((dst.cc_swz[0] << NV40_FP_OP_COND_SWZ_X_SHIFT) |
230 (dst.cc_swz[1] << NV40_FP_OP_COND_SWZ_Y_SHIFT) |
231 (dst.cc_swz[2] << NV40_FP_OP_COND_SWZ_Z_SHIFT) |
232 (dst.cc_swz[3] << NV40_FP_OP_COND_SWZ_W_SHIFT));
233
234 emit_dst(fpc, dst);
235 emit_src(fpc, 0, s0);
236 emit_src(fpc, 1, s1);
237 emit_src(fpc, 2, s2);
238 }
239
240 static void
241 nv40_fp_tex(struct nv40_fpc *fpc, int sat, int op, int unit,
242 struct nv40_sreg dst, int mask,
243 struct nv40_sreg s0, struct nv40_sreg s1, struct nv40_sreg s2)
244 {
245 struct nv40_fragment_program *fp = fpc->fp;
246
247 nv40_fp_arith(fpc, sat, op, dst, mask, s0, s1, s2);
248
249 fp->insn[fpc->inst_offset] |= (unit << NV40_FP_OP_TEX_UNIT_SHIFT);
250 fp->samplers |= (1 << unit);
251 }
252
253 static INLINE struct nv40_sreg
254 tgsi_src(struct nv40_fpc *fpc, const struct tgsi_full_src_register *fsrc)
255 {
256 struct nv40_sreg src;
257
258 switch (fsrc->SrcRegister.File) {
259 case TGSI_FILE_INPUT:
260 src = nv40_sr(NV40SR_INPUT,
261 fpc->attrib_map[fsrc->SrcRegister.Index]);
262 break;
263 case TGSI_FILE_CONSTANT:
264 src = constant(fpc, fsrc->SrcRegister.Index, NULL);
265 break;
266 case TGSI_FILE_IMMEDIATE:
267 assert(fsrc->SrcRegister.Index < fpc->nr_imm);
268 src = fpc->imm[fsrc->SrcRegister.Index];
269 break;
270 case TGSI_FILE_TEMPORARY:
271 src = fpc->r_temp[fsrc->SrcRegister.Index];
272 break;
273 /* NV40 fragprog result regs are just temps, so this is simple */
274 case TGSI_FILE_OUTPUT:
275 src = fpc->r_result[fsrc->SrcRegister.Index];
276 break;
277 default:
278 NOUVEAU_ERR("bad src file\n");
279 break;
280 }
281
282 src.abs = fsrc->SrcRegisterExtMod.Absolute;
283 src.negate = fsrc->SrcRegister.Negate;
284 src.swz[0] = fsrc->SrcRegister.SwizzleX;
285 src.swz[1] = fsrc->SrcRegister.SwizzleY;
286 src.swz[2] = fsrc->SrcRegister.SwizzleZ;
287 src.swz[3] = fsrc->SrcRegister.SwizzleW;
288 return src;
289 }
290
291 static INLINE struct nv40_sreg
292 tgsi_dst(struct nv40_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
293 switch (fdst->DstRegister.File) {
294 case TGSI_FILE_OUTPUT:
295 return fpc->r_result[fdst->DstRegister.Index];
296 case TGSI_FILE_TEMPORARY:
297 return fpc->r_temp[fdst->DstRegister.Index];
298 case TGSI_FILE_NULL:
299 return nv40_sr(NV40SR_NONE, 0);
300 default:
301 NOUVEAU_ERR("bad dst file %d\n", fdst->DstRegister.File);
302 return nv40_sr(NV40SR_NONE, 0);
303 }
304 }
305
306 static INLINE int
307 tgsi_mask(uint tgsi)
308 {
309 int mask = 0;
310
311 if (tgsi & TGSI_WRITEMASK_X) mask |= MASK_X;
312 if (tgsi & TGSI_WRITEMASK_Y) mask |= MASK_Y;
313 if (tgsi & TGSI_WRITEMASK_Z) mask |= MASK_Z;
314 if (tgsi & TGSI_WRITEMASK_W) mask |= MASK_W;
315 return mask;
316 }
317
318 static boolean
319 src_native_swz(struct nv40_fpc *fpc, const struct tgsi_full_src_register *fsrc,
320 struct nv40_sreg *src)
321 {
322 const struct nv40_sreg none = nv40_sr(NV40SR_NONE, 0);
323 struct nv40_sreg tgsi = tgsi_src(fpc, fsrc);
324 uint mask = 0, zero_mask = 0, one_mask = 0, neg_mask = 0;
325 uint neg[4] = { fsrc->SrcRegisterExtSwz.NegateX,
326 fsrc->SrcRegisterExtSwz.NegateY,
327 fsrc->SrcRegisterExtSwz.NegateZ,
328 fsrc->SrcRegisterExtSwz.NegateW };
329 uint c;
330
331 for (c = 0; c < 4; c++) {
332 switch (tgsi_util_get_full_src_register_extswizzle(fsrc, c)) {
333 case TGSI_EXTSWIZZLE_X:
334 case TGSI_EXTSWIZZLE_Y:
335 case TGSI_EXTSWIZZLE_Z:
336 case TGSI_EXTSWIZZLE_W:
337 mask |= (1 << c);
338 break;
339 case TGSI_EXTSWIZZLE_ZERO:
340 zero_mask |= (1 << c);
341 tgsi.swz[c] = SWZ_X;
342 break;
343 case TGSI_EXTSWIZZLE_ONE:
344 one_mask |= (1 << c);
345 tgsi.swz[c] = SWZ_X;
346 break;
347 default:
348 assert(0);
349 }
350
351 if (!tgsi.negate && neg[c])
352 neg_mask |= (1 << c);
353 }
354
355 if (mask == MASK_ALL && !neg_mask)
356 return TRUE;
357
358 *src = temp(fpc);
359
360 if (mask)
361 arith(fpc, 0, MOV, *src, mask, tgsi, none, none);
362
363 if (zero_mask)
364 arith(fpc, 0, SFL, *src, zero_mask, *src, none, none);
365
366 if (one_mask)
367 arith(fpc, 0, STR, *src, one_mask, *src, none, none);
368
369 if (neg_mask) {
370 struct nv40_sreg one = temp(fpc);
371 arith(fpc, 0, STR, one, neg_mask, one, none, none);
372 arith(fpc, 0, MUL, *src, neg_mask, *src, neg(one), none);
373 }
374
375 return FALSE;
376 }
377
378 static boolean
379 nv40_fragprog_parse_instruction(struct nv40_fpc *fpc,
380 const struct tgsi_full_instruction *finst)
381 {
382 const struct nv40_sreg none = nv40_sr(NV40SR_NONE, 0);
383 struct nv40_sreg src[3], dst, tmp;
384 int mask, sat, unit;
385 int ai = -1, ci = -1, ii = -1;
386 int i;
387
388 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
389 return TRUE;
390
391 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
392 const struct tgsi_full_src_register *fsrc;
393
394 fsrc = &finst->FullSrcRegisters[i];
395 if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
396 src[i] = tgsi_src(fpc, fsrc);
397 }
398 }
399
400 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
401 const struct tgsi_full_src_register *fsrc;
402
403 fsrc = &finst->FullSrcRegisters[i];
404
405 switch (fsrc->SrcRegister.File) {
406 case TGSI_FILE_INPUT:
407 case TGSI_FILE_CONSTANT:
408 case TGSI_FILE_TEMPORARY:
409 if (!src_native_swz(fpc, fsrc, &src[i]))
410 continue;
411 break;
412 default:
413 break;
414 }
415
416 switch (fsrc->SrcRegister.File) {
417 case TGSI_FILE_INPUT:
418 if (ai == -1 || ai == fsrc->SrcRegister.Index) {
419 ai = fsrc->SrcRegister.Index;
420 src[i] = tgsi_src(fpc, fsrc);
421 } else {
422 src[i] = temp(fpc);
423 arith(fpc, 0, MOV, src[i], MASK_ALL,
424 tgsi_src(fpc, fsrc), none, none);
425 }
426 break;
427 case TGSI_FILE_CONSTANT:
428 if ((ci == -1 && ii == -1) ||
429 ci == fsrc->SrcRegister.Index) {
430 ci = fsrc->SrcRegister.Index;
431 src[i] = tgsi_src(fpc, fsrc);
432 } else {
433 src[i] = temp(fpc);
434 arith(fpc, 0, MOV, src[i], MASK_ALL,
435 tgsi_src(fpc, fsrc), none, none);
436 }
437 break;
438 case TGSI_FILE_IMMEDIATE:
439 if ((ci == -1 && ii == -1) ||
440 ii == fsrc->SrcRegister.Index) {
441 ii = fsrc->SrcRegister.Index;
442 src[i] = tgsi_src(fpc, fsrc);
443 } else {
444 src[i] = temp(fpc);
445 arith(fpc, 0, MOV, src[i], MASK_ALL,
446 tgsi_src(fpc, fsrc), none, none);
447 }
448 break;
449 case TGSI_FILE_TEMPORARY:
450 /* handled above */
451 break;
452 case TGSI_FILE_SAMPLER:
453 unit = fsrc->SrcRegister.Index;
454 break;
455 case TGSI_FILE_OUTPUT:
456 break;
457 default:
458 NOUVEAU_ERR("bad src file\n");
459 return FALSE;
460 }
461 }
462
463 dst = tgsi_dst(fpc, &finst->FullDstRegisters[0]);
464 mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
465 sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
466
467 switch (finst->Instruction.Opcode) {
468 case TGSI_OPCODE_ABS:
469 arith(fpc, sat, MOV, dst, mask, abs(src[0]), none, none);
470 break;
471 case TGSI_OPCODE_ADD:
472 arith(fpc, sat, ADD, dst, mask, src[0], src[1], none);
473 break;
474 case TGSI_OPCODE_CMP:
475 tmp = temp(fpc);
476 arith(fpc, sat, MOV, dst, mask, src[2], none, none);
477 tmp.cc_update = 1;
478 arith(fpc, 0, MOV, tmp, 0xf, src[0], none, none);
479 dst.cc_test = NV40_VP_INST_COND_LT;
480 arith(fpc, sat, MOV, dst, mask, src[1], none, none);
481 break;
482 case TGSI_OPCODE_COS:
483 arith(fpc, sat, COS, dst, mask, src[0], none, none);
484 break;
485 case TGSI_OPCODE_DDX:
486 if (mask & (MASK_Z | MASK_W)) {
487 tmp = temp(fpc);
488 arith(fpc, sat, DDX, tmp, MASK_X | MASK_Y,
489 swz(src[0], Z, W, Z, W), none, none);
490 arith(fpc, 0, MOV, tmp, MASK_Z | MASK_W,
491 swz(tmp, X, Y, X, Y), none, none);
492 arith(fpc, sat, DDX, tmp, MASK_X | MASK_Y, src[0],
493 none, none);
494 arith(fpc, 0, MOV, dst, mask, tmp, none, none);
495 } else {
496 arith(fpc, sat, DDX, dst, mask, src[0], none, none);
497 }
498 break;
499 case TGSI_OPCODE_DDY:
500 if (mask & (MASK_Z | MASK_W)) {
501 tmp = temp(fpc);
502 arith(fpc, sat, DDY, tmp, MASK_X | MASK_Y,
503 swz(src[0], Z, W, Z, W), none, none);
504 arith(fpc, 0, MOV, tmp, MASK_Z | MASK_W,
505 swz(tmp, X, Y, X, Y), none, none);
506 arith(fpc, sat, DDY, tmp, MASK_X | MASK_Y, src[0],
507 none, none);
508 arith(fpc, 0, MOV, dst, mask, tmp, none, none);
509 } else {
510 arith(fpc, sat, DDY, dst, mask, src[0], none, none);
511 }
512 break;
513 case TGSI_OPCODE_DP3:
514 arith(fpc, sat, DP3, dst, mask, src[0], src[1], none);
515 break;
516 case TGSI_OPCODE_DP4:
517 arith(fpc, sat, DP4, dst, mask, src[0], src[1], none);
518 break;
519 case TGSI_OPCODE_DPH:
520 tmp = temp(fpc);
521 arith(fpc, 0, DP3, tmp, MASK_X, src[0], src[1], none);
522 arith(fpc, sat, ADD, dst, mask, swz(tmp, X, X, X, X),
523 swz(src[1], W, W, W, W), none);
524 break;
525 case TGSI_OPCODE_DST:
526 arith(fpc, sat, DST, dst, mask, src[0], src[1], none);
527 break;
528 case TGSI_OPCODE_EX2:
529 arith(fpc, sat, EX2, dst, mask, src[0], none, none);
530 break;
531 case TGSI_OPCODE_FLR:
532 arith(fpc, sat, FLR, dst, mask, src[0], none, none);
533 break;
534 case TGSI_OPCODE_FRC:
535 arith(fpc, sat, FRC, dst, mask, src[0], none, none);
536 break;
537 case TGSI_OPCODE_KILP:
538 arith(fpc, 0, KIL, none, 0, none, none, none);
539 break;
540 case TGSI_OPCODE_KIL:
541 dst = nv40_sr(NV40SR_NONE, 0);
542 dst.cc_update = 1;
543 arith(fpc, 0, MOV, dst, MASK_ALL, src[0], none, none);
544 dst.cc_update = 0; dst.cc_test = NV40_FP_OP_COND_LT;
545 arith(fpc, 0, KIL, dst, 0, none, none, none);
546 break;
547 case TGSI_OPCODE_LG2:
548 arith(fpc, sat, LG2, dst, mask, src[0], none, none);
549 break;
550 // case TGSI_OPCODE_LIT:
551 case TGSI_OPCODE_LRP:
552 tmp = temp(fpc);
553 arith(fpc, 0, MAD, tmp, mask, neg(src[0]), src[2], src[2]);
554 arith(fpc, sat, MAD, dst, mask, src[0], src[1], tmp);
555 break;
556 case TGSI_OPCODE_MAD:
557 arith(fpc, sat, MAD, dst, mask, src[0], src[1], src[2]);
558 break;
559 case TGSI_OPCODE_MAX:
560 arith(fpc, sat, MAX, dst, mask, src[0], src[1], none);
561 break;
562 case TGSI_OPCODE_MIN:
563 arith(fpc, sat, MIN, dst, mask, src[0], src[1], none);
564 break;
565 case TGSI_OPCODE_MOV:
566 arith(fpc, sat, MOV, dst, mask, src[0], none, none);
567 break;
568 case TGSI_OPCODE_MUL:
569 arith(fpc, sat, MUL, dst, mask, src[0], src[1], none);
570 break;
571 case TGSI_OPCODE_NOISE1:
572 case TGSI_OPCODE_NOISE2:
573 case TGSI_OPCODE_NOISE3:
574 case TGSI_OPCODE_NOISE4:
575 arith(fpc, sat, SFL, dst, mask, none, none, none);
576 break;
577 case TGSI_OPCODE_POW:
578 tmp = temp(fpc);
579 arith(fpc, 0, LG2, tmp, MASK_X,
580 swz(src[0], X, X, X, X), none, none);
581 arith(fpc, 0, MUL, tmp, MASK_X, swz(tmp, X, X, X, X),
582 swz(src[1], X, X, X, X), none);
583 arith(fpc, sat, EX2, dst, mask,
584 swz(tmp, X, X, X, X), none, none);
585 break;
586 case TGSI_OPCODE_RCP:
587 arith(fpc, sat, RCP, dst, mask, src[0], none, none);
588 break;
589 case TGSI_OPCODE_RET:
590 assert(0);
591 break;
592 case TGSI_OPCODE_RFL:
593 tmp = temp(fpc);
594 arith(fpc, 0, DP3, tmp, MASK_X, src[0], src[0], none);
595 arith(fpc, 0, DP3, tmp, MASK_Y, src[0], src[1], none);
596 arith(fpc, 0, DIV, scale(tmp, 2X), MASK_Z,
597 swz(tmp, Y, Y, Y, Y), swz(tmp, X, X, X, X), none);
598 arith(fpc, sat, MAD, dst, mask,
599 swz(tmp, Z, Z, Z, Z), src[0], neg(src[1]));
600 break;
601 case TGSI_OPCODE_RSQ:
602 tmp = temp(fpc);
603 arith(fpc, 0, LG2, scale(tmp, INV_2X), MASK_X,
604 abs(swz(src[0], X, X, X, X)), none, none);
605 arith(fpc, sat, EX2, dst, mask,
606 neg(swz(tmp, X, X, X, X)), none, none);
607 break;
608 case TGSI_OPCODE_SCS:
609 if (mask & MASK_X) {
610 arith(fpc, sat, COS, dst, MASK_X,
611 swz(src[0], X, X, X, X), none, none);
612 }
613 if (mask & MASK_Y) {
614 arith(fpc, sat, SIN, dst, MASK_Y,
615 swz(src[0], X, X, X, X), none, none);
616 }
617 break;
618 case TGSI_OPCODE_SEQ:
619 arith(fpc, sat, SEQ, dst, mask, src[0], src[1], none);
620 break;
621 case TGSI_OPCODE_SFL:
622 arith(fpc, sat, SFL, dst, mask, src[0], src[1], none);
623 break;
624 case TGSI_OPCODE_SGE:
625 arith(fpc, sat, SGE, dst, mask, src[0], src[1], none);
626 break;
627 case TGSI_OPCODE_SGT:
628 arith(fpc, sat, SGT, dst, mask, src[0], src[1], none);
629 break;
630 case TGSI_OPCODE_SIN:
631 arith(fpc, sat, SIN, dst, mask, src[0], none, none);
632 break;
633 case TGSI_OPCODE_SLE:
634 arith(fpc, sat, SLE, dst, mask, src[0], src[1], none);
635 break;
636 case TGSI_OPCODE_SLT:
637 arith(fpc, sat, SLT, dst, mask, src[0], src[1], none);
638 break;
639 case TGSI_OPCODE_SNE:
640 arith(fpc, sat, SNE, dst, mask, src[0], src[1], none);
641 break;
642 case TGSI_OPCODE_STR:
643 arith(fpc, sat, STR, dst, mask, src[0], src[1], none);
644 break;
645 case TGSI_OPCODE_SUB:
646 arith(fpc, sat, ADD, dst, mask, src[0], neg(src[1]), none);
647 break;
648 case TGSI_OPCODE_TEX:
649 tex(fpc, sat, TEX, unit, dst, mask, src[0], none, none);
650 break;
651 case TGSI_OPCODE_TXB:
652 tex(fpc, sat, TXB, unit, dst, mask, src[0], none, none);
653 break;
654 case TGSI_OPCODE_TXP:
655 tex(fpc, sat, TXP, unit, dst, mask, src[0], none, none);
656 break;
657 case TGSI_OPCODE_XPD:
658 tmp = temp(fpc);
659 arith(fpc, 0, MUL, tmp, mask,
660 swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
661 arith(fpc, sat, MAD, dst, (mask & ~MASK_W),
662 swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
663 neg(tmp));
664 break;
665 default:
666 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
667 return FALSE;
668 }
669
670 release_temps(fpc);
671 return TRUE;
672 }
673
674 static boolean
675 nv40_fragprog_parse_decl_attrib(struct nv40_fpc *fpc,
676 const struct tgsi_full_declaration *fdec)
677 {
678 int hw;
679
680 switch (fdec->Semantic.SemanticName) {
681 case TGSI_SEMANTIC_POSITION:
682 hw = NV40_FP_OP_INPUT_SRC_POSITION;
683 break;
684 case TGSI_SEMANTIC_COLOR:
685 if (fdec->Semantic.SemanticIndex == 0) {
686 hw = NV40_FP_OP_INPUT_SRC_COL0;
687 } else
688 if (fdec->Semantic.SemanticIndex == 1) {
689 hw = NV40_FP_OP_INPUT_SRC_COL1;
690 } else {
691 NOUVEAU_ERR("bad colour semantic index\n");
692 return FALSE;
693 }
694 break;
695 case TGSI_SEMANTIC_FOG:
696 hw = NV40_FP_OP_INPUT_SRC_FOGC;
697 break;
698 case TGSI_SEMANTIC_GENERIC:
699 if (fdec->Semantic.SemanticIndex <= 7) {
700 hw = NV40_FP_OP_INPUT_SRC_TC(fdec->Semantic.
701 SemanticIndex);
702 } else {
703 NOUVEAU_ERR("bad generic semantic index\n");
704 return FALSE;
705 }
706 break;
707 default:
708 NOUVEAU_ERR("bad input semantic\n");
709 return FALSE;
710 }
711
712 fpc->attrib_map[fdec->DeclarationRange.First] = hw;
713 return TRUE;
714 }
715
716 static boolean
717 nv40_fragprog_parse_decl_output(struct nv40_fpc *fpc,
718 const struct tgsi_full_declaration *fdec)
719 {
720 unsigned idx = fdec->DeclarationRange.First;
721 unsigned hw;
722
723 switch (fdec->Semantic.SemanticName) {
724 case TGSI_SEMANTIC_POSITION:
725 hw = 1;
726 break;
727 case TGSI_SEMANTIC_COLOR:
728 switch (fdec->Semantic.SemanticIndex) {
729 case 0: hw = 0; break;
730 case 1: hw = 2; break;
731 case 2: hw = 3; break;
732 case 3: hw = 4; break;
733 default:
734 NOUVEAU_ERR("bad rcol index\n");
735 return FALSE;
736 }
737 break;
738 default:
739 NOUVEAU_ERR("bad output semantic\n");
740 return FALSE;
741 }
742
743 fpc->r_result[idx] = nv40_sr(NV40SR_OUTPUT, hw);
744 fpc->r_temps |= (1 << hw);
745 return TRUE;
746 }
747
748 static boolean
749 nv40_fragprog_prepare(struct nv40_fpc *fpc)
750 {
751 struct tgsi_parse_context p;
752 int high_temp = -1, i;
753
754 tgsi_parse_init(&p, fpc->fp->pipe.tokens);
755 while (!tgsi_parse_end_of_tokens(&p)) {
756 const union tgsi_full_token *tok = &p.FullToken;
757
758 tgsi_parse_token(&p);
759 switch(tok->Token.Type) {
760 case TGSI_TOKEN_TYPE_DECLARATION:
761 {
762 const struct tgsi_full_declaration *fdec;
763 fdec = &p.FullToken.FullDeclaration;
764 switch (fdec->Declaration.File) {
765 case TGSI_FILE_INPUT:
766 if (!nv40_fragprog_parse_decl_attrib(fpc, fdec))
767 goto out_err;
768 break;
769 case TGSI_FILE_OUTPUT:
770 if (!nv40_fragprog_parse_decl_output(fpc, fdec))
771 goto out_err;
772 break;
773 case TGSI_FILE_TEMPORARY:
774 if (fdec->DeclarationRange.Last > high_temp) {
775 high_temp =
776 fdec->DeclarationRange.Last;
777 }
778 break;
779 default:
780 break;
781 }
782 }
783 break;
784 case TGSI_TOKEN_TYPE_IMMEDIATE:
785 {
786 struct tgsi_full_immediate *imm;
787 float vals[4];
788
789 imm = &p.FullToken.FullImmediate;
790 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
791 assert(fpc->nr_imm < MAX_IMM);
792
793 vals[0] = imm->u[0].Float;
794 vals[1] = imm->u[1].Float;
795 vals[2] = imm->u[2].Float;
796 vals[3] = imm->u[3].Float;
797 fpc->imm[fpc->nr_imm++] = constant(fpc, -1, vals);
798 }
799 break;
800 default:
801 break;
802 }
803 }
804 tgsi_parse_free(&p);
805
806 if (++high_temp) {
807 fpc->r_temp = CALLOC(high_temp, sizeof(struct nv40_sreg));
808 for (i = 0; i < high_temp; i++)
809 fpc->r_temp[i] = temp(fpc);
810 fpc->r_temps_discard = 0;
811 }
812
813 return TRUE;
814
815 out_err:
816 if (fpc->r_temp)
817 FREE(fpc->r_temp);
818 tgsi_parse_free(&p);
819 return FALSE;
820 }
821
822 static void
823 nv40_fragprog_translate(struct nv40_context *nv40,
824 struct nv40_fragment_program *fp)
825 {
826 struct tgsi_parse_context parse;
827 struct nv40_fpc *fpc = NULL;
828
829 fpc = CALLOC(1, sizeof(struct nv40_fpc));
830 if (!fpc)
831 return;
832 fpc->fp = fp;
833 fpc->num_regs = 2;
834
835 if (!nv40_fragprog_prepare(fpc)) {
836 FREE(fpc);
837 return;
838 }
839
840 tgsi_parse_init(&parse, fp->pipe.tokens);
841
842 while (!tgsi_parse_end_of_tokens(&parse)) {
843 tgsi_parse_token(&parse);
844
845 switch (parse.FullToken.Token.Type) {
846 case TGSI_TOKEN_TYPE_INSTRUCTION:
847 {
848 const struct tgsi_full_instruction *finst;
849
850 finst = &parse.FullToken.FullInstruction;
851 if (!nv40_fragprog_parse_instruction(fpc, finst))
852 goto out_err;
853 }
854 break;
855 default:
856 break;
857 }
858 }
859
860 fp->fp_control |= fpc->num_regs << NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT;
861
862 /* Terminate final instruction */
863 fp->insn[fpc->inst_offset] |= 0x00000001;
864
865 /* Append NOP + END instruction, may or may not be necessary. */
866 fpc->inst_offset = fp->insn_len;
867 grow_insns(fpc, 4);
868 fp->insn[fpc->inst_offset + 0] = 0x00000001;
869 fp->insn[fpc->inst_offset + 1] = 0x00000000;
870 fp->insn[fpc->inst_offset + 2] = 0x00000000;
871 fp->insn[fpc->inst_offset + 3] = 0x00000000;
872
873 fp->translated = TRUE;
874 out_err:
875 tgsi_parse_free(&parse);
876 if (fpc->r_temp)
877 FREE(fpc->r_temp);
878 FREE(fpc);
879 }
880
881 static void
882 nv40_fragprog_upload(struct nv40_context *nv40,
883 struct nv40_fragment_program *fp)
884 {
885 struct pipe_screen *pscreen = nv40->pipe.screen;
886 const uint32_t le = 1;
887 uint32_t *map;
888 int i;
889
890 map = pipe_buffer_map(pscreen, fp->buffer, PIPE_BUFFER_USAGE_CPU_WRITE);
891
892 #if 0
893 for (i = 0; i < fp->insn_len; i++) {
894 fflush(stdout); fflush(stderr);
895 NOUVEAU_ERR("%d 0x%08x\n", i, fp->insn[i]);
896 fflush(stdout); fflush(stderr);
897 }
898 #endif
899
900 if ((*(const uint8_t *)&le)) {
901 for (i = 0; i < fp->insn_len; i++) {
902 map[i] = fp->insn[i];
903 }
904 } else {
905 /* Weird swapping for big-endian chips */
906 for (i = 0; i < fp->insn_len; i++) {
907 map[i] = ((fp->insn[i] & 0xffff) << 16) |
908 ((fp->insn[i] >> 16) & 0xffff);
909 }
910 }
911
912 pipe_buffer_unmap(pscreen, fp->buffer);
913 }
914
915 static boolean
916 nv40_fragprog_validate(struct nv40_context *nv40)
917 {
918 struct nv40_fragment_program *fp = nv40->fragprog;
919 struct pipe_buffer *constbuf =
920 nv40->constbuf[PIPE_SHADER_FRAGMENT];
921 struct pipe_screen *pscreen = nv40->pipe.screen;
922 struct nouveau_stateobj *so;
923 boolean new_consts = FALSE;
924 int i;
925
926 if (fp->translated)
927 goto update_constants;
928
929 nv40->fallback_swrast &= ~NV40_NEW_FRAGPROG;
930 nv40_fragprog_translate(nv40, fp);
931 if (!fp->translated) {
932 nv40->fallback_swrast |= NV40_NEW_FRAGPROG;
933 return FALSE;
934 }
935
936 fp->buffer = pscreen->buffer_create(pscreen, 0x100, 0, fp->insn_len * 4);
937 nv40_fragprog_upload(nv40, fp);
938
939 so = so_new(4, 1);
940 so_method(so, nv40->screen->curie, NV40TCL_FP_ADDRESS, 1);
941 so_reloc (so, nouveau_bo(fp->buffer), 0, NOUVEAU_BO_VRAM |
942 NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW |
943 NOUVEAU_BO_OR, NV40TCL_FP_ADDRESS_DMA0,
944 NV40TCL_FP_ADDRESS_DMA1);
945 so_method(so, nv40->screen->curie, NV40TCL_FP_CONTROL, 1);
946 so_data (so, fp->fp_control);
947 so_ref(so, &fp->so);
948 so_ref(NULL, &so);
949
950 update_constants:
951 if (fp->nr_consts) {
952 float *map;
953
954 map = pipe_buffer_map(pscreen, constbuf,
955 PIPE_BUFFER_USAGE_CPU_READ);
956 for (i = 0; i < fp->nr_consts; i++) {
957 struct nv40_fragment_program_data *fpd = &fp->consts[i];
958 uint32_t *p = &fp->insn[fpd->offset];
959 uint32_t *cb = (uint32_t *)&map[fpd->index * 4];
960
961 if (!memcmp(p, cb, 4 * sizeof(float)))
962 continue;
963 memcpy(p, cb, 4 * sizeof(float));
964 new_consts = TRUE;
965 }
966 pipe_buffer_unmap(pscreen, constbuf);
967
968 if (new_consts)
969 nv40_fragprog_upload(nv40, fp);
970 }
971
972 if (new_consts || fp->so != nv40->state.hw[NV40_STATE_FRAGPROG]) {
973 so_ref(fp->so, &nv40->state.hw[NV40_STATE_FRAGPROG]);
974 return TRUE;
975 }
976
977 return FALSE;
978 }
979
980 void
981 nv40_fragprog_destroy(struct nv40_context *nv40,
982 struct nv40_fragment_program *fp)
983 {
984 if (fp->insn_len)
985 FREE(fp->insn);
986 }
987
988 struct nv40_state_entry nv40_state_fragprog = {
989 .validate = nv40_fragprog_validate,
990 .dirty = {
991 .pipe = NV40_NEW_FRAGPROG,
992 .hw = NV40_STATE_FRAGPROG
993 }
994 };
995