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gallium: remove the swizzling parts of ExtSwizzle
[mesa.git] / src / gallium / drivers / nv40 / nv40_fragprog.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "pipe/p_inlines.h"
5
6 #include "pipe/p_shader_tokens.h"
7 #include "tgsi/tgsi_parse.h"
8 #include "tgsi/tgsi_util.h"
9
10 #include "nv40_context.h"
11
12 #define SWZ_X 0
13 #define SWZ_Y 1
14 #define SWZ_Z 2
15 #define SWZ_W 3
16 #define MASK_X 1
17 #define MASK_Y 2
18 #define MASK_Z 4
19 #define MASK_W 8
20 #define MASK_ALL (MASK_X|MASK_Y|MASK_Z|MASK_W)
21 #define DEF_SCALE NV40_FP_OP_DST_SCALE_1X
22 #define DEF_CTEST NV40_FP_OP_COND_TR
23 #include "nv40_shader.h"
24
25 #define swz(s,x,y,z,w) nv40_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w)
26 #define neg(s) nv40_sr_neg((s))
27 #define abs(s) nv40_sr_abs((s))
28 #define scale(s,v) nv40_sr_scale((s), NV40_FP_OP_DST_SCALE_##v)
29
30 #define MAX_CONSTS 128
31 #define MAX_IMM 32
32 struct nv40_fpc {
33 struct nv40_fragment_program *fp;
34
35 uint attrib_map[PIPE_MAX_SHADER_INPUTS];
36
37 unsigned r_temps;
38 unsigned r_temps_discard;
39 struct nv40_sreg r_result[PIPE_MAX_SHADER_OUTPUTS];
40 struct nv40_sreg *r_temp;
41
42 int num_regs;
43
44 unsigned inst_offset;
45 unsigned have_const;
46
47 struct {
48 int pipe;
49 float vals[4];
50 } consts[MAX_CONSTS];
51 int nr_consts;
52
53 struct nv40_sreg imm[MAX_IMM];
54 unsigned nr_imm;
55 };
56
57 static INLINE struct nv40_sreg
58 temp(struct nv40_fpc *fpc)
59 {
60 int idx = ffs(~fpc->r_temps) - 1;
61
62 if (idx < 0) {
63 NOUVEAU_ERR("out of temps!!\n");
64 assert(0);
65 return nv40_sr(NV40SR_TEMP, 0);
66 }
67
68 fpc->r_temps |= (1 << idx);
69 fpc->r_temps_discard |= (1 << idx);
70 return nv40_sr(NV40SR_TEMP, idx);
71 }
72
73 static INLINE void
74 release_temps(struct nv40_fpc *fpc)
75 {
76 fpc->r_temps &= ~fpc->r_temps_discard;
77 fpc->r_temps_discard = 0;
78 }
79
80 static INLINE struct nv40_sreg
81 constant(struct nv40_fpc *fpc, int pipe, float vals[4])
82 {
83 int idx;
84
85 if (fpc->nr_consts == MAX_CONSTS)
86 assert(0);
87 idx = fpc->nr_consts++;
88
89 fpc->consts[idx].pipe = pipe;
90 if (pipe == -1)
91 memcpy(fpc->consts[idx].vals, vals, 4 * sizeof(float));
92 return nv40_sr(NV40SR_CONST, idx);
93 }
94
95 #define arith(cc,s,o,d,m,s0,s1,s2) \
96 nv40_fp_arith((cc), (s), NV40_FP_OP_OPCODE_##o, \
97 (d), (m), (s0), (s1), (s2))
98 #define tex(cc,s,o,u,d,m,s0,s1,s2) \
99 nv40_fp_tex((cc), (s), NV40_FP_OP_OPCODE_##o, (u), \
100 (d), (m), (s0), none, none)
101
102 static void
103 grow_insns(struct nv40_fpc *fpc, int size)
104 {
105 struct nv40_fragment_program *fp = fpc->fp;
106
107 fp->insn_len += size;
108 fp->insn = realloc(fp->insn, sizeof(uint32_t) * fp->insn_len);
109 }
110
111 static void
112 emit_src(struct nv40_fpc *fpc, int pos, struct nv40_sreg src)
113 {
114 struct nv40_fragment_program *fp = fpc->fp;
115 uint32_t *hw = &fp->insn[fpc->inst_offset];
116 uint32_t sr = 0;
117
118 switch (src.type) {
119 case NV40SR_INPUT:
120 sr |= (NV40_FP_REG_TYPE_INPUT << NV40_FP_REG_TYPE_SHIFT);
121 hw[0] |= (src.index << NV40_FP_OP_INPUT_SRC_SHIFT);
122 break;
123 case NV40SR_OUTPUT:
124 sr |= NV40_FP_REG_SRC_HALF;
125 /* fall-through */
126 case NV40SR_TEMP:
127 sr |= (NV40_FP_REG_TYPE_TEMP << NV40_FP_REG_TYPE_SHIFT);
128 sr |= (src.index << NV40_FP_REG_SRC_SHIFT);
129 break;
130 case NV40SR_CONST:
131 if (!fpc->have_const) {
132 grow_insns(fpc, 4);
133 fpc->have_const = 1;
134 }
135
136 hw = &fp->insn[fpc->inst_offset];
137 if (fpc->consts[src.index].pipe >= 0) {
138 struct nv40_fragment_program_data *fpd;
139
140 fp->consts = realloc(fp->consts, ++fp->nr_consts *
141 sizeof(*fpd));
142 fpd = &fp->consts[fp->nr_consts - 1];
143 fpd->offset = fpc->inst_offset + 4;
144 fpd->index = fpc->consts[src.index].pipe;
145 memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4);
146 } else {
147 memcpy(&fp->insn[fpc->inst_offset + 4],
148 fpc->consts[src.index].vals,
149 sizeof(uint32_t) * 4);
150 }
151
152 sr |= (NV40_FP_REG_TYPE_CONST << NV40_FP_REG_TYPE_SHIFT);
153 break;
154 case NV40SR_NONE:
155 sr |= (NV40_FP_REG_TYPE_INPUT << NV40_FP_REG_TYPE_SHIFT);
156 break;
157 default:
158 assert(0);
159 }
160
161 if (src.negate)
162 sr |= NV40_FP_REG_NEGATE;
163
164 if (src.abs)
165 hw[1] |= (1 << (29 + pos));
166
167 sr |= ((src.swz[0] << NV40_FP_REG_SWZ_X_SHIFT) |
168 (src.swz[1] << NV40_FP_REG_SWZ_Y_SHIFT) |
169 (src.swz[2] << NV40_FP_REG_SWZ_Z_SHIFT) |
170 (src.swz[3] << NV40_FP_REG_SWZ_W_SHIFT));
171
172 hw[pos + 1] |= sr;
173 }
174
175 static void
176 emit_dst(struct nv40_fpc *fpc, struct nv40_sreg dst)
177 {
178 struct nv40_fragment_program *fp = fpc->fp;
179 uint32_t *hw = &fp->insn[fpc->inst_offset];
180
181 switch (dst.type) {
182 case NV40SR_TEMP:
183 if (fpc->num_regs < (dst.index + 1))
184 fpc->num_regs = dst.index + 1;
185 break;
186 case NV40SR_OUTPUT:
187 if (dst.index == 1) {
188 fp->fp_control |= 0xe;
189 } else {
190 hw[0] |= NV40_FP_OP_OUT_REG_HALF;
191 }
192 break;
193 case NV40SR_NONE:
194 hw[0] |= (1 << 30);
195 break;
196 default:
197 assert(0);
198 }
199
200 hw[0] |= (dst.index << NV40_FP_OP_OUT_REG_SHIFT);
201 }
202
203 static void
204 nv40_fp_arith(struct nv40_fpc *fpc, int sat, int op,
205 struct nv40_sreg dst, int mask,
206 struct nv40_sreg s0, struct nv40_sreg s1, struct nv40_sreg s2)
207 {
208 struct nv40_fragment_program *fp = fpc->fp;
209 uint32_t *hw;
210
211 fpc->inst_offset = fp->insn_len;
212 fpc->have_const = 0;
213 grow_insns(fpc, 4);
214 hw = &fp->insn[fpc->inst_offset];
215 memset(hw, 0, sizeof(uint32_t) * 4);
216
217 if (op == NV40_FP_OP_OPCODE_KIL)
218 fp->fp_control |= NV40TCL_FP_CONTROL_KIL;
219 hw[0] |= (op << NV40_FP_OP_OPCODE_SHIFT);
220 hw[0] |= (mask << NV40_FP_OP_OUTMASK_SHIFT);
221 hw[2] |= (dst.dst_scale << NV40_FP_OP_DST_SCALE_SHIFT);
222
223 if (sat)
224 hw[0] |= NV40_FP_OP_OUT_SAT;
225
226 if (dst.cc_update)
227 hw[0] |= NV40_FP_OP_COND_WRITE_ENABLE;
228 hw[1] |= (dst.cc_test << NV40_FP_OP_COND_SHIFT);
229 hw[1] |= ((dst.cc_swz[0] << NV40_FP_OP_COND_SWZ_X_SHIFT) |
230 (dst.cc_swz[1] << NV40_FP_OP_COND_SWZ_Y_SHIFT) |
231 (dst.cc_swz[2] << NV40_FP_OP_COND_SWZ_Z_SHIFT) |
232 (dst.cc_swz[3] << NV40_FP_OP_COND_SWZ_W_SHIFT));
233
234 emit_dst(fpc, dst);
235 emit_src(fpc, 0, s0);
236 emit_src(fpc, 1, s1);
237 emit_src(fpc, 2, s2);
238 }
239
240 static void
241 nv40_fp_tex(struct nv40_fpc *fpc, int sat, int op, int unit,
242 struct nv40_sreg dst, int mask,
243 struct nv40_sreg s0, struct nv40_sreg s1, struct nv40_sreg s2)
244 {
245 struct nv40_fragment_program *fp = fpc->fp;
246
247 nv40_fp_arith(fpc, sat, op, dst, mask, s0, s1, s2);
248
249 fp->insn[fpc->inst_offset] |= (unit << NV40_FP_OP_TEX_UNIT_SHIFT);
250 fp->samplers |= (1 << unit);
251 }
252
253 static INLINE struct nv40_sreg
254 tgsi_src(struct nv40_fpc *fpc, const struct tgsi_full_src_register *fsrc)
255 {
256 struct nv40_sreg src;
257
258 switch (fsrc->SrcRegister.File) {
259 case TGSI_FILE_INPUT:
260 src = nv40_sr(NV40SR_INPUT,
261 fpc->attrib_map[fsrc->SrcRegister.Index]);
262 break;
263 case TGSI_FILE_CONSTANT:
264 src = constant(fpc, fsrc->SrcRegister.Index, NULL);
265 break;
266 case TGSI_FILE_IMMEDIATE:
267 assert(fsrc->SrcRegister.Index < fpc->nr_imm);
268 src = fpc->imm[fsrc->SrcRegister.Index];
269 break;
270 case TGSI_FILE_TEMPORARY:
271 src = fpc->r_temp[fsrc->SrcRegister.Index];
272 break;
273 /* NV40 fragprog result regs are just temps, so this is simple */
274 case TGSI_FILE_OUTPUT:
275 src = fpc->r_result[fsrc->SrcRegister.Index];
276 break;
277 default:
278 NOUVEAU_ERR("bad src file\n");
279 break;
280 }
281
282 src.abs = fsrc->SrcRegisterExtMod.Absolute;
283 src.negate = fsrc->SrcRegister.Negate;
284 src.swz[0] = fsrc->SrcRegister.SwizzleX;
285 src.swz[1] = fsrc->SrcRegister.SwizzleY;
286 src.swz[2] = fsrc->SrcRegister.SwizzleZ;
287 src.swz[3] = fsrc->SrcRegister.SwizzleW;
288 return src;
289 }
290
291 static INLINE struct nv40_sreg
292 tgsi_dst(struct nv40_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
293 switch (fdst->DstRegister.File) {
294 case TGSI_FILE_OUTPUT:
295 return fpc->r_result[fdst->DstRegister.Index];
296 case TGSI_FILE_TEMPORARY:
297 return fpc->r_temp[fdst->DstRegister.Index];
298 case TGSI_FILE_NULL:
299 return nv40_sr(NV40SR_NONE, 0);
300 default:
301 NOUVEAU_ERR("bad dst file %d\n", fdst->DstRegister.File);
302 return nv40_sr(NV40SR_NONE, 0);
303 }
304 }
305
306 static INLINE int
307 tgsi_mask(uint tgsi)
308 {
309 int mask = 0;
310
311 if (tgsi & TGSI_WRITEMASK_X) mask |= MASK_X;
312 if (tgsi & TGSI_WRITEMASK_Y) mask |= MASK_Y;
313 if (tgsi & TGSI_WRITEMASK_Z) mask |= MASK_Z;
314 if (tgsi & TGSI_WRITEMASK_W) mask |= MASK_W;
315 return mask;
316 }
317
318 static boolean
319 src_native_swz(struct nv40_fpc *fpc, const struct tgsi_full_src_register *fsrc,
320 struct nv40_sreg *src)
321 {
322 const struct nv40_sreg none = nv40_sr(NV40SR_NONE, 0);
323 struct nv40_sreg tgsi = tgsi_src(fpc, fsrc);
324 uint mask = 0, zero_mask = 0, one_mask = 0, neg_mask = 0;
325 uint neg[4] = { fsrc->SrcRegisterExtSwz.NegateX,
326 fsrc->SrcRegisterExtSwz.NegateY,
327 fsrc->SrcRegisterExtSwz.NegateZ,
328 fsrc->SrcRegisterExtSwz.NegateW };
329 uint c;
330
331 for (c = 0; c < 4; c++) {
332 switch (tgsi_util_get_full_src_register_swizzle(fsrc, c)) {
333 case TGSI_SWIZZLE_X:
334 case TGSI_SWIZZLE_Y:
335 case TGSI_SWIZZLE_Z:
336 case TGSI_SWIZZLE_W:
337 mask |= (1 << c);
338 break;
339 default:
340 assert(0);
341 }
342
343 if (!tgsi.negate && neg[c])
344 neg_mask |= (1 << c);
345 }
346
347 if (mask == MASK_ALL && !neg_mask)
348 return TRUE;
349
350 *src = temp(fpc);
351
352 if (mask)
353 arith(fpc, 0, MOV, *src, mask, tgsi, none, none);
354
355 if (zero_mask)
356 arith(fpc, 0, SFL, *src, zero_mask, *src, none, none);
357
358 if (one_mask)
359 arith(fpc, 0, STR, *src, one_mask, *src, none, none);
360
361 if (neg_mask) {
362 struct nv40_sreg one = temp(fpc);
363 arith(fpc, 0, STR, one, neg_mask, one, none, none);
364 arith(fpc, 0, MUL, *src, neg_mask, *src, neg(one), none);
365 }
366
367 return FALSE;
368 }
369
370 static boolean
371 nv40_fragprog_parse_instruction(struct nv40_fpc *fpc,
372 const struct tgsi_full_instruction *finst)
373 {
374 const struct nv40_sreg none = nv40_sr(NV40SR_NONE, 0);
375 struct nv40_sreg src[3], dst, tmp;
376 int mask, sat, unit;
377 int ai = -1, ci = -1, ii = -1;
378 int i;
379
380 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
381 return TRUE;
382
383 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
384 const struct tgsi_full_src_register *fsrc;
385
386 fsrc = &finst->FullSrcRegisters[i];
387 if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
388 src[i] = tgsi_src(fpc, fsrc);
389 }
390 }
391
392 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
393 const struct tgsi_full_src_register *fsrc;
394
395 fsrc = &finst->FullSrcRegisters[i];
396
397 switch (fsrc->SrcRegister.File) {
398 case TGSI_FILE_INPUT:
399 case TGSI_FILE_CONSTANT:
400 case TGSI_FILE_TEMPORARY:
401 if (!src_native_swz(fpc, fsrc, &src[i]))
402 continue;
403 break;
404 default:
405 break;
406 }
407
408 switch (fsrc->SrcRegister.File) {
409 case TGSI_FILE_INPUT:
410 if (ai == -1 || ai == fsrc->SrcRegister.Index) {
411 ai = fsrc->SrcRegister.Index;
412 src[i] = tgsi_src(fpc, fsrc);
413 } else {
414 src[i] = temp(fpc);
415 arith(fpc, 0, MOV, src[i], MASK_ALL,
416 tgsi_src(fpc, fsrc), none, none);
417 }
418 break;
419 case TGSI_FILE_CONSTANT:
420 if ((ci == -1 && ii == -1) ||
421 ci == fsrc->SrcRegister.Index) {
422 ci = fsrc->SrcRegister.Index;
423 src[i] = tgsi_src(fpc, fsrc);
424 } else {
425 src[i] = temp(fpc);
426 arith(fpc, 0, MOV, src[i], MASK_ALL,
427 tgsi_src(fpc, fsrc), none, none);
428 }
429 break;
430 case TGSI_FILE_IMMEDIATE:
431 if ((ci == -1 && ii == -1) ||
432 ii == fsrc->SrcRegister.Index) {
433 ii = fsrc->SrcRegister.Index;
434 src[i] = tgsi_src(fpc, fsrc);
435 } else {
436 src[i] = temp(fpc);
437 arith(fpc, 0, MOV, src[i], MASK_ALL,
438 tgsi_src(fpc, fsrc), none, none);
439 }
440 break;
441 case TGSI_FILE_TEMPORARY:
442 /* handled above */
443 break;
444 case TGSI_FILE_SAMPLER:
445 unit = fsrc->SrcRegister.Index;
446 break;
447 case TGSI_FILE_OUTPUT:
448 break;
449 default:
450 NOUVEAU_ERR("bad src file\n");
451 return FALSE;
452 }
453 }
454
455 dst = tgsi_dst(fpc, &finst->FullDstRegisters[0]);
456 mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
457 sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
458
459 switch (finst->Instruction.Opcode) {
460 case TGSI_OPCODE_ABS:
461 arith(fpc, sat, MOV, dst, mask, abs(src[0]), none, none);
462 break;
463 case TGSI_OPCODE_ADD:
464 arith(fpc, sat, ADD, dst, mask, src[0], src[1], none);
465 break;
466 case TGSI_OPCODE_CMP:
467 tmp = temp(fpc);
468 arith(fpc, sat, MOV, dst, mask, src[2], none, none);
469 tmp.cc_update = 1;
470 arith(fpc, 0, MOV, tmp, 0xf, src[0], none, none);
471 dst.cc_test = NV40_VP_INST_COND_LT;
472 arith(fpc, sat, MOV, dst, mask, src[1], none, none);
473 break;
474 case TGSI_OPCODE_COS:
475 arith(fpc, sat, COS, dst, mask, src[0], none, none);
476 break;
477 case TGSI_OPCODE_DDX:
478 if (mask & (MASK_Z | MASK_W)) {
479 tmp = temp(fpc);
480 arith(fpc, sat, DDX, tmp, MASK_X | MASK_Y,
481 swz(src[0], Z, W, Z, W), none, none);
482 arith(fpc, 0, MOV, tmp, MASK_Z | MASK_W,
483 swz(tmp, X, Y, X, Y), none, none);
484 arith(fpc, sat, DDX, tmp, MASK_X | MASK_Y, src[0],
485 none, none);
486 arith(fpc, 0, MOV, dst, mask, tmp, none, none);
487 } else {
488 arith(fpc, sat, DDX, dst, mask, src[0], none, none);
489 }
490 break;
491 case TGSI_OPCODE_DDY:
492 if (mask & (MASK_Z | MASK_W)) {
493 tmp = temp(fpc);
494 arith(fpc, sat, DDY, tmp, MASK_X | MASK_Y,
495 swz(src[0], Z, W, Z, W), none, none);
496 arith(fpc, 0, MOV, tmp, MASK_Z | MASK_W,
497 swz(tmp, X, Y, X, Y), none, none);
498 arith(fpc, sat, DDY, tmp, MASK_X | MASK_Y, src[0],
499 none, none);
500 arith(fpc, 0, MOV, dst, mask, tmp, none, none);
501 } else {
502 arith(fpc, sat, DDY, dst, mask, src[0], none, none);
503 }
504 break;
505 case TGSI_OPCODE_DP3:
506 arith(fpc, sat, DP3, dst, mask, src[0], src[1], none);
507 break;
508 case TGSI_OPCODE_DP4:
509 arith(fpc, sat, DP4, dst, mask, src[0], src[1], none);
510 break;
511 case TGSI_OPCODE_DPH:
512 tmp = temp(fpc);
513 arith(fpc, 0, DP3, tmp, MASK_X, src[0], src[1], none);
514 arith(fpc, sat, ADD, dst, mask, swz(tmp, X, X, X, X),
515 swz(src[1], W, W, W, W), none);
516 break;
517 case TGSI_OPCODE_DST:
518 arith(fpc, sat, DST, dst, mask, src[0], src[1], none);
519 break;
520 case TGSI_OPCODE_EX2:
521 arith(fpc, sat, EX2, dst, mask, src[0], none, none);
522 break;
523 case TGSI_OPCODE_FLR:
524 arith(fpc, sat, FLR, dst, mask, src[0], none, none);
525 break;
526 case TGSI_OPCODE_FRC:
527 arith(fpc, sat, FRC, dst, mask, src[0], none, none);
528 break;
529 case TGSI_OPCODE_KILP:
530 arith(fpc, 0, KIL, none, 0, none, none, none);
531 break;
532 case TGSI_OPCODE_KIL:
533 dst = nv40_sr(NV40SR_NONE, 0);
534 dst.cc_update = 1;
535 arith(fpc, 0, MOV, dst, MASK_ALL, src[0], none, none);
536 dst.cc_update = 0; dst.cc_test = NV40_FP_OP_COND_LT;
537 arith(fpc, 0, KIL, dst, 0, none, none, none);
538 break;
539 case TGSI_OPCODE_LG2:
540 arith(fpc, sat, LG2, dst, mask, src[0], none, none);
541 break;
542 // case TGSI_OPCODE_LIT:
543 case TGSI_OPCODE_LRP:
544 tmp = temp(fpc);
545 arith(fpc, 0, MAD, tmp, mask, neg(src[0]), src[2], src[2]);
546 arith(fpc, sat, MAD, dst, mask, src[0], src[1], tmp);
547 break;
548 case TGSI_OPCODE_MAD:
549 arith(fpc, sat, MAD, dst, mask, src[0], src[1], src[2]);
550 break;
551 case TGSI_OPCODE_MAX:
552 arith(fpc, sat, MAX, dst, mask, src[0], src[1], none);
553 break;
554 case TGSI_OPCODE_MIN:
555 arith(fpc, sat, MIN, dst, mask, src[0], src[1], none);
556 break;
557 case TGSI_OPCODE_MOV:
558 arith(fpc, sat, MOV, dst, mask, src[0], none, none);
559 break;
560 case TGSI_OPCODE_MUL:
561 arith(fpc, sat, MUL, dst, mask, src[0], src[1], none);
562 break;
563 case TGSI_OPCODE_POW:
564 tmp = temp(fpc);
565 arith(fpc, 0, LG2, tmp, MASK_X,
566 swz(src[0], X, X, X, X), none, none);
567 arith(fpc, 0, MUL, tmp, MASK_X, swz(tmp, X, X, X, X),
568 swz(src[1], X, X, X, X), none);
569 arith(fpc, sat, EX2, dst, mask,
570 swz(tmp, X, X, X, X), none, none);
571 break;
572 case TGSI_OPCODE_RCP:
573 arith(fpc, sat, RCP, dst, mask, src[0], none, none);
574 break;
575 case TGSI_OPCODE_RET:
576 assert(0);
577 break;
578 case TGSI_OPCODE_RFL:
579 tmp = temp(fpc);
580 arith(fpc, 0, DP3, tmp, MASK_X, src[0], src[0], none);
581 arith(fpc, 0, DP3, tmp, MASK_Y, src[0], src[1], none);
582 arith(fpc, 0, DIV, scale(tmp, 2X), MASK_Z,
583 swz(tmp, Y, Y, Y, Y), swz(tmp, X, X, X, X), none);
584 arith(fpc, sat, MAD, dst, mask,
585 swz(tmp, Z, Z, Z, Z), src[0], neg(src[1]));
586 break;
587 case TGSI_OPCODE_RSQ:
588 tmp = temp(fpc);
589 arith(fpc, 0, LG2, scale(tmp, INV_2X), MASK_X,
590 abs(swz(src[0], X, X, X, X)), none, none);
591 arith(fpc, sat, EX2, dst, mask,
592 neg(swz(tmp, X, X, X, X)), none, none);
593 break;
594 case TGSI_OPCODE_SCS:
595 if (mask & MASK_X) {
596 arith(fpc, sat, COS, dst, MASK_X,
597 swz(src[0], X, X, X, X), none, none);
598 }
599 if (mask & MASK_Y) {
600 arith(fpc, sat, SIN, dst, MASK_Y,
601 swz(src[0], X, X, X, X), none, none);
602 }
603 break;
604 case TGSI_OPCODE_SEQ:
605 arith(fpc, sat, SEQ, dst, mask, src[0], src[1], none);
606 break;
607 case TGSI_OPCODE_SFL:
608 arith(fpc, sat, SFL, dst, mask, src[0], src[1], none);
609 break;
610 case TGSI_OPCODE_SGE:
611 arith(fpc, sat, SGE, dst, mask, src[0], src[1], none);
612 break;
613 case TGSI_OPCODE_SGT:
614 arith(fpc, sat, SGT, dst, mask, src[0], src[1], none);
615 break;
616 case TGSI_OPCODE_SIN:
617 arith(fpc, sat, SIN, dst, mask, src[0], none, none);
618 break;
619 case TGSI_OPCODE_SLE:
620 arith(fpc, sat, SLE, dst, mask, src[0], src[1], none);
621 break;
622 case TGSI_OPCODE_SLT:
623 arith(fpc, sat, SLT, dst, mask, src[0], src[1], none);
624 break;
625 case TGSI_OPCODE_SNE:
626 arith(fpc, sat, SNE, dst, mask, src[0], src[1], none);
627 break;
628 case TGSI_OPCODE_STR:
629 arith(fpc, sat, STR, dst, mask, src[0], src[1], none);
630 break;
631 case TGSI_OPCODE_SUB:
632 arith(fpc, sat, ADD, dst, mask, src[0], neg(src[1]), none);
633 break;
634 case TGSI_OPCODE_TEX:
635 tex(fpc, sat, TEX, unit, dst, mask, src[0], none, none);
636 break;
637 case TGSI_OPCODE_TXB:
638 tex(fpc, sat, TXB, unit, dst, mask, src[0], none, none);
639 break;
640 case TGSI_OPCODE_TXP:
641 tex(fpc, sat, TXP, unit, dst, mask, src[0], none, none);
642 break;
643 case TGSI_OPCODE_XPD:
644 tmp = temp(fpc);
645 arith(fpc, 0, MUL, tmp, mask,
646 swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
647 arith(fpc, sat, MAD, dst, (mask & ~MASK_W),
648 swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
649 neg(tmp));
650 break;
651 default:
652 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
653 return FALSE;
654 }
655
656 release_temps(fpc);
657 return TRUE;
658 }
659
660 static boolean
661 nv40_fragprog_parse_decl_attrib(struct nv40_fpc *fpc,
662 const struct tgsi_full_declaration *fdec)
663 {
664 int hw;
665
666 switch (fdec->Semantic.SemanticName) {
667 case TGSI_SEMANTIC_POSITION:
668 hw = NV40_FP_OP_INPUT_SRC_POSITION;
669 break;
670 case TGSI_SEMANTIC_COLOR:
671 if (fdec->Semantic.SemanticIndex == 0) {
672 hw = NV40_FP_OP_INPUT_SRC_COL0;
673 } else
674 if (fdec->Semantic.SemanticIndex == 1) {
675 hw = NV40_FP_OP_INPUT_SRC_COL1;
676 } else {
677 NOUVEAU_ERR("bad colour semantic index\n");
678 return FALSE;
679 }
680 break;
681 case TGSI_SEMANTIC_FOG:
682 hw = NV40_FP_OP_INPUT_SRC_FOGC;
683 break;
684 case TGSI_SEMANTIC_GENERIC:
685 if (fdec->Semantic.SemanticIndex <= 7) {
686 hw = NV40_FP_OP_INPUT_SRC_TC(fdec->Semantic.
687 SemanticIndex);
688 } else {
689 NOUVEAU_ERR("bad generic semantic index\n");
690 return FALSE;
691 }
692 break;
693 default:
694 NOUVEAU_ERR("bad input semantic\n");
695 return FALSE;
696 }
697
698 fpc->attrib_map[fdec->DeclarationRange.First] = hw;
699 return TRUE;
700 }
701
702 static boolean
703 nv40_fragprog_parse_decl_output(struct nv40_fpc *fpc,
704 const struct tgsi_full_declaration *fdec)
705 {
706 unsigned idx = fdec->DeclarationRange.First;
707 unsigned hw;
708
709 switch (fdec->Semantic.SemanticName) {
710 case TGSI_SEMANTIC_POSITION:
711 hw = 1;
712 break;
713 case TGSI_SEMANTIC_COLOR:
714 switch (fdec->Semantic.SemanticIndex) {
715 case 0: hw = 0; break;
716 case 1: hw = 2; break;
717 case 2: hw = 3; break;
718 case 3: hw = 4; break;
719 default:
720 NOUVEAU_ERR("bad rcol index\n");
721 return FALSE;
722 }
723 break;
724 default:
725 NOUVEAU_ERR("bad output semantic\n");
726 return FALSE;
727 }
728
729 fpc->r_result[idx] = nv40_sr(NV40SR_OUTPUT, hw);
730 fpc->r_temps |= (1 << hw);
731 return TRUE;
732 }
733
734 static boolean
735 nv40_fragprog_prepare(struct nv40_fpc *fpc)
736 {
737 struct tgsi_parse_context p;
738 int high_temp = -1, i;
739
740 tgsi_parse_init(&p, fpc->fp->pipe.tokens);
741 while (!tgsi_parse_end_of_tokens(&p)) {
742 const union tgsi_full_token *tok = &p.FullToken;
743
744 tgsi_parse_token(&p);
745 switch(tok->Token.Type) {
746 case TGSI_TOKEN_TYPE_DECLARATION:
747 {
748 const struct tgsi_full_declaration *fdec;
749 fdec = &p.FullToken.FullDeclaration;
750 switch (fdec->Declaration.File) {
751 case TGSI_FILE_INPUT:
752 if (!nv40_fragprog_parse_decl_attrib(fpc, fdec))
753 goto out_err;
754 break;
755 case TGSI_FILE_OUTPUT:
756 if (!nv40_fragprog_parse_decl_output(fpc, fdec))
757 goto out_err;
758 break;
759 case TGSI_FILE_TEMPORARY:
760 if (fdec->DeclarationRange.Last > high_temp) {
761 high_temp =
762 fdec->DeclarationRange.Last;
763 }
764 break;
765 default:
766 break;
767 }
768 }
769 break;
770 case TGSI_TOKEN_TYPE_IMMEDIATE:
771 {
772 struct tgsi_full_immediate *imm;
773 float vals[4];
774
775 imm = &p.FullToken.FullImmediate;
776 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
777 assert(fpc->nr_imm < MAX_IMM);
778
779 vals[0] = imm->u[0].Float;
780 vals[1] = imm->u[1].Float;
781 vals[2] = imm->u[2].Float;
782 vals[3] = imm->u[3].Float;
783 fpc->imm[fpc->nr_imm++] = constant(fpc, -1, vals);
784 }
785 break;
786 default:
787 break;
788 }
789 }
790 tgsi_parse_free(&p);
791
792 if (++high_temp) {
793 fpc->r_temp = CALLOC(high_temp, sizeof(struct nv40_sreg));
794 for (i = 0; i < high_temp; i++)
795 fpc->r_temp[i] = temp(fpc);
796 fpc->r_temps_discard = 0;
797 }
798
799 return TRUE;
800
801 out_err:
802 if (fpc->r_temp)
803 FREE(fpc->r_temp);
804 tgsi_parse_free(&p);
805 return FALSE;
806 }
807
808 static void
809 nv40_fragprog_translate(struct nv40_context *nv40,
810 struct nv40_fragment_program *fp)
811 {
812 struct tgsi_parse_context parse;
813 struct nv40_fpc *fpc = NULL;
814
815 fpc = CALLOC(1, sizeof(struct nv40_fpc));
816 if (!fpc)
817 return;
818 fpc->fp = fp;
819 fpc->num_regs = 2;
820
821 if (!nv40_fragprog_prepare(fpc)) {
822 FREE(fpc);
823 return;
824 }
825
826 tgsi_parse_init(&parse, fp->pipe.tokens);
827
828 while (!tgsi_parse_end_of_tokens(&parse)) {
829 tgsi_parse_token(&parse);
830
831 switch (parse.FullToken.Token.Type) {
832 case TGSI_TOKEN_TYPE_INSTRUCTION:
833 {
834 const struct tgsi_full_instruction *finst;
835
836 finst = &parse.FullToken.FullInstruction;
837 if (!nv40_fragprog_parse_instruction(fpc, finst))
838 goto out_err;
839 }
840 break;
841 default:
842 break;
843 }
844 }
845
846 fp->fp_control |= fpc->num_regs << NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT;
847
848 /* Terminate final instruction */
849 fp->insn[fpc->inst_offset] |= 0x00000001;
850
851 /* Append NOP + END instruction, may or may not be necessary. */
852 fpc->inst_offset = fp->insn_len;
853 grow_insns(fpc, 4);
854 fp->insn[fpc->inst_offset + 0] = 0x00000001;
855 fp->insn[fpc->inst_offset + 1] = 0x00000000;
856 fp->insn[fpc->inst_offset + 2] = 0x00000000;
857 fp->insn[fpc->inst_offset + 3] = 0x00000000;
858
859 fp->translated = TRUE;
860 out_err:
861 tgsi_parse_free(&parse);
862 if (fpc->r_temp)
863 FREE(fpc->r_temp);
864 FREE(fpc);
865 }
866
867 static void
868 nv40_fragprog_upload(struct nv40_context *nv40,
869 struct nv40_fragment_program *fp)
870 {
871 struct pipe_screen *pscreen = nv40->pipe.screen;
872 const uint32_t le = 1;
873 uint32_t *map;
874 int i;
875
876 map = pipe_buffer_map(pscreen, fp->buffer, PIPE_BUFFER_USAGE_CPU_WRITE);
877
878 #if 0
879 for (i = 0; i < fp->insn_len; i++) {
880 fflush(stdout); fflush(stderr);
881 NOUVEAU_ERR("%d 0x%08x\n", i, fp->insn[i]);
882 fflush(stdout); fflush(stderr);
883 }
884 #endif
885
886 if ((*(const uint8_t *)&le)) {
887 for (i = 0; i < fp->insn_len; i++) {
888 map[i] = fp->insn[i];
889 }
890 } else {
891 /* Weird swapping for big-endian chips */
892 for (i = 0; i < fp->insn_len; i++) {
893 map[i] = ((fp->insn[i] & 0xffff) << 16) |
894 ((fp->insn[i] >> 16) & 0xffff);
895 }
896 }
897
898 pipe_buffer_unmap(pscreen, fp->buffer);
899 }
900
901 static boolean
902 nv40_fragprog_validate(struct nv40_context *nv40)
903 {
904 struct nv40_fragment_program *fp = nv40->fragprog;
905 struct pipe_buffer *constbuf =
906 nv40->constbuf[PIPE_SHADER_FRAGMENT];
907 struct pipe_screen *pscreen = nv40->pipe.screen;
908 struct nouveau_stateobj *so;
909 boolean new_consts = FALSE;
910 int i;
911
912 if (fp->translated)
913 goto update_constants;
914
915 nv40->fallback_swrast &= ~NV40_NEW_FRAGPROG;
916 nv40_fragprog_translate(nv40, fp);
917 if (!fp->translated) {
918 nv40->fallback_swrast |= NV40_NEW_FRAGPROG;
919 return FALSE;
920 }
921
922 fp->buffer = pscreen->buffer_create(pscreen, 0x100, 0, fp->insn_len * 4);
923 nv40_fragprog_upload(nv40, fp);
924
925 so = so_new(4, 1);
926 so_method(so, nv40->screen->curie, NV40TCL_FP_ADDRESS, 1);
927 so_reloc (so, nouveau_bo(fp->buffer), 0, NOUVEAU_BO_VRAM |
928 NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW |
929 NOUVEAU_BO_OR, NV40TCL_FP_ADDRESS_DMA0,
930 NV40TCL_FP_ADDRESS_DMA1);
931 so_method(so, nv40->screen->curie, NV40TCL_FP_CONTROL, 1);
932 so_data (so, fp->fp_control);
933 so_ref(so, &fp->so);
934 so_ref(NULL, &so);
935
936 update_constants:
937 if (fp->nr_consts) {
938 float *map;
939
940 map = pipe_buffer_map(pscreen, constbuf,
941 PIPE_BUFFER_USAGE_CPU_READ);
942 for (i = 0; i < fp->nr_consts; i++) {
943 struct nv40_fragment_program_data *fpd = &fp->consts[i];
944 uint32_t *p = &fp->insn[fpd->offset];
945 uint32_t *cb = (uint32_t *)&map[fpd->index * 4];
946
947 if (!memcmp(p, cb, 4 * sizeof(float)))
948 continue;
949 memcpy(p, cb, 4 * sizeof(float));
950 new_consts = TRUE;
951 }
952 pipe_buffer_unmap(pscreen, constbuf);
953
954 if (new_consts)
955 nv40_fragprog_upload(nv40, fp);
956 }
957
958 if (new_consts || fp->so != nv40->state.hw[NV40_STATE_FRAGPROG]) {
959 so_ref(fp->so, &nv40->state.hw[NV40_STATE_FRAGPROG]);
960 return TRUE;
961 }
962
963 return FALSE;
964 }
965
966 void
967 nv40_fragprog_destroy(struct nv40_context *nv40,
968 struct nv40_fragment_program *fp)
969 {
970 if (fp->insn_len)
971 FREE(fp->insn);
972 }
973
974 struct nv40_state_entry nv40_state_fragprog = {
975 .validate = nv40_fragprog_validate,
976 .dirty = {
977 .pipe = NV40_NEW_FRAGPROG,
978 .hw = NV40_STATE_FRAGPROG
979 }
980 };
981