src/gallium/drivers/nv40/nv40_screen.c

   1 #include "pipe/p_screen.h"
   2
   3 #include "nv40_context.h"
   4 #include "nv40_screen.h"
   5
   6 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
   7 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
   8 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
   9
  10 static const char *
  11 nv40_screen_get_name(struct pipe_screen *pscreen)
  12 {
  13         struct nv40_screen *screen = nv40_screen(pscreen);
  14         struct nouveau_device *dev = screen->nvws->channel->device;
  15         static char buffer[128];
  16
  17         snprintf(buffer, sizeof(buffer), "NV%02X", dev->chipset);
  18         return buffer;
  19 }
  20
  21 static const char *
  22 nv40_screen_get_vendor(struct pipe_screen *pscreen)
  23 {
  24         return "nouveau";
  25 }
  26
  27 static int
  28 nv40_screen_get_param(struct pipe_screen *pscreen, int param)
  29 {
  30         struct nv40_screen *screen = nv40_screen(pscreen);
  31
  32         switch (param) {
  33         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  34                 return 16;
  35         case PIPE_CAP_NPOT_TEXTURES:
  36                 return 1;
  37         case PIPE_CAP_TWO_SIDED_STENCIL:
  38                 return 1;
  39         case PIPE_CAP_GLSL:
  40                 return 0;
  41         case PIPE_CAP_S3TC:
  42                 return 1;
  43         case PIPE_CAP_ANISOTROPIC_FILTER:
  44                 return 1;
  45         case PIPE_CAP_POINT_SPRITE:
  46                 return 1;
  47         case PIPE_CAP_MAX_RENDER_TARGETS:
  48                 return 4;
  49         case PIPE_CAP_OCCLUSION_QUERY:
  50                 return 1;
  51         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  52                 return 1;
  53         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  54                 return 13;
  55         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  56                 return 10;
  57         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  58                 return 13;
  59         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  60         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  61                 return 1;
  62         case NOUVEAU_CAP_HW_VTXBUF:
  63                 return 1;
  64         case NOUVEAU_CAP_HW_IDXBUF:
  65                 if (screen->curie->grclass == NV40TCL)
  66                         return 1;
  67                 return 0;
  68         default:
  69                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  70                 return 0;
  71         }
  72 }
  73
  74 static float
  75 nv40_screen_get_paramf(struct pipe_screen *pscreen, int param)
  76 {
  77         switch (param) {
  78         case PIPE_CAP_MAX_LINE_WIDTH:
  79         case PIPE_CAP_MAX_LINE_WIDTH_AA:
  80                 return 10.0;
  81         case PIPE_CAP_MAX_POINT_WIDTH:
  82         case PIPE_CAP_MAX_POINT_WIDTH_AA:
  83                 return 64.0;
  84         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
  85                 return 16.0;
  86         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
  87                 return 16.0;
  88         default:
  89                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  90                 return 0.0;
  91         }
  92 }
  93
  94 static boolean
  95 nv40_screen_surface_format_supported(struct pipe_screen *pscreen,
  96                                      enum pipe_format format,
  97                                      enum pipe_texture_target target,
  98                                      unsigned tex_usage, unsigned geom_flags)
  99 {
 100         if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
 101                 switch (format) {
 102                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 103                 case PIPE_FORMAT_R5G6B5_UNORM:
 104                 case PIPE_FORMAT_Z24S8_UNORM:
 105                 case PIPE_FORMAT_Z16_UNORM:
 106                         return TRUE;
 107                 default:
 108                         break;
 109                 }
 110         } else {
 111                 switch (format) {
 112                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 113                 case PIPE_FORMAT_A1R5G5B5_UNORM:
 114                 case PIPE_FORMAT_A4R4G4B4_UNORM:
 115                 case PIPE_FORMAT_R5G6B5_UNORM:
 116                 case PIPE_FORMAT_R16_SNORM:
 117                 case PIPE_FORMAT_L8_UNORM:
 118                 case PIPE_FORMAT_A8_UNORM:
 119                 case PIPE_FORMAT_I8_UNORM:
 120                 case PIPE_FORMAT_A8L8_UNORM:
 121                 case PIPE_FORMAT_Z16_UNORM:
 122                 case PIPE_FORMAT_Z24S8_UNORM:
 123                 case PIPE_FORMAT_DXT1_RGB:
 124                 case PIPE_FORMAT_DXT1_RGBA:
 125                 case PIPE_FORMAT_DXT3_RGBA:
 126                 case PIPE_FORMAT_DXT5_RGBA:
 127                         return TRUE;
 128                 default:
 129                         break;
 130                 }
 131         }
 132
 133         return FALSE;
 134 }
 135
 136 static void *
 137 nv40_surface_map(struct pipe_screen *screen, struct pipe_surface *surface,
 138                  unsigned flags )
 139 {
 140         struct pipe_winsys      *ws = screen->winsys;
 141         struct pipe_surface     *surface_to_map;
 142         void                    *map;
 143
 144         if (!(surface->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) {
 145                 struct nv40_miptree *mt = (struct nv40_miptree *)surface->texture;
 146
 147                 if (!mt->shadow_tex) {
 148                         unsigned old_tex_usage = surface->texture->tex_usage;
 149                         surface->texture->tex_usage = NOUVEAU_TEXTURE_USAGE_LINEAR;
 150                         mt->shadow_tex = screen->texture_create(screen, surface->texture);
 151                         surface->texture->tex_usage = old_tex_usage;
 152
 153                         assert(mt->shadow_tex->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR);
 154                         mt->shadow_surface = screen->get_tex_surface
 155                         (
 156                                 screen, mt->shadow_tex,
 157                                 surface->face, surface->level, surface->zslice,
 158                                 surface->usage
 159                         );
 160                 }
 161
 162                 surface_to_map = mt->shadow_surface;
 163         }
 164         else
 165                 surface_to_map = surface;
 166
 167         assert(surface_to_map);
 168
 169         map = ws->buffer_map(ws, surface_to_map->buffer, flags);
 170         if (!map)
 171                 return NULL;
 172
 173         return map + surface_to_map->offset;
 174 }
 175
 176 static void
 177 nv40_surface_unmap(struct pipe_screen *screen, struct pipe_surface *surface)
 178 {
 179         struct pipe_winsys      *ws = screen->winsys;
 180         struct pipe_surface     *surface_to_unmap;
 181
 182         /* TODO: Copy from shadow just before push buffer is flushed instead.
 183                  There are probably some programs that map/unmap excessively
 184                  before rendering. */
 185         if (!(surface->texture->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) {
 186                 struct nv40_miptree *mt = (struct nv40_miptree *)surface->texture;
 187
 188                 assert(mt->shadow_tex);
 189
 190                 surface_to_unmap = mt->shadow_surface;
 191         }
 192         else
 193                 surface_to_unmap = surface;
 194
 195         assert(surface_to_unmap);
 196
 197         ws->buffer_unmap(ws, surface_to_unmap->buffer);
 198
 199         if (surface_to_unmap != surface) {
 200                 struct nv40_screen *nvscreen = nv40_screen(screen);
 201
 202                 nvscreen->nvws->surface_copy(nvscreen->nvws,
 203                                              surface, 0, 0,
 204                                              surface_to_unmap, 0, 0,
 205                                              surface->width, surface->height);
 206         }
 207 }
 208
 209 static void
 210 nv40_screen_destroy(struct pipe_screen *pscreen)
 211 {
 212         struct nv40_screen *screen = nv40_screen(pscreen);
 213         struct nouveau_winsys *nvws = screen->nvws;
 214
 215         nvws->res_free(&screen->vp_exec_heap);
 216         nvws->res_free(&screen->vp_data_heap);
 217         nvws->res_free(&screen->query_heap);
 218         nvws->notifier_free(&screen->query);
 219         nvws->notifier_free(&screen->sync);
 220         nvws->grobj_free(&screen->curie);
 221
 222         FREE(pscreen);
 223 }
 224
 225 struct pipe_screen *
 226 nv40_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
 227 {
 228         struct nv40_screen *screen = CALLOC_STRUCT(nv40_screen);
 229         struct nouveau_stateobj *so;
 230         unsigned curie_class;
 231         unsigned chipset = nvws->channel->device->chipset;
 232         int ret;
 233
 234         if (!screen)
 235                 return NULL;
 236         screen->nvws = nvws;
 237
 238         /* 3D object */
 239         switch (chipset & 0xf0) {
 240         case 0x40:
 241                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (chipset & 0x0f)))
 242                         curie_class = NV40TCL;
 243                 else
 244                 if (NV4X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 245                         curie_class = NV44TCL;
 246                 break;
 247         case 0x60:
 248                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 249                         curie_class = NV44TCL;
 250                 break;
 251         default:
 252                 break;
 253         }
 254
 255         if (!curie_class) {
 256                 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", chipset);
 257                 return NULL;
 258         }
 259
 260         ret = nvws->grobj_alloc(nvws, curie_class, &screen->curie);
 261         if (ret) {
 262                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 263                 return FALSE;
 264         }
 265
 266         /* Notifier for sync purposes */
 267         ret = nvws->notifier_alloc(nvws, 1, &screen->sync);
 268         if (ret) {
 269                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 270                 nv40_screen_destroy(&screen->pipe);
 271                 return NULL;
 272         }
 273
 274         /* Query objects */
 275         ret = nvws->notifier_alloc(nvws, 32, &screen->query);
 276         if (ret) {
 277                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 278                 nv40_screen_destroy(&screen->pipe);
 279                 return NULL;
 280         }
 281
 282         ret = nvws->res_init(&screen->query_heap, 0, 32);
 283         if (ret) {
 284                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 285                 nv40_screen_destroy(&screen->pipe);
 286                 return NULL;
 287         }
 288
 289         /* Vtxprog resources */
 290         if (nvws->res_init(&screen->vp_exec_heap, 0, 512) ||
 291             nvws->res_init(&screen->vp_data_heap, 0, 256)) {
 292                 nv40_screen_destroy(&screen->pipe);
 293                 return NULL;
 294         }
 295
 296         /* Static curie initialisation */
 297         so = so_new(128, 0);
 298         so_method(so, screen->curie, NV40TCL_DMA_NOTIFY, 1);
 299         so_data  (so, screen->sync->handle);
 300         so_method(so, screen->curie, NV40TCL_DMA_TEXTURE0, 2);
 301         so_data  (so, nvws->channel->vram->handle);
 302         so_data  (so, nvws->channel->gart->handle);
 303         so_method(so, screen->curie, NV40TCL_DMA_COLOR1, 1);
 304         so_data  (so, nvws->channel->vram->handle);
 305         so_method(so, screen->curie, NV40TCL_DMA_COLOR0, 2);
 306         so_data  (so, nvws->channel->vram->handle);
 307         so_data  (so, nvws->channel->vram->handle);
 308         so_method(so, screen->curie, NV40TCL_DMA_VTXBUF0, 2);
 309         so_data  (so, nvws->channel->vram->handle);
 310         so_data  (so, nvws->channel->gart->handle);
 311         so_method(so, screen->curie, NV40TCL_DMA_FENCE, 2);
 312         so_data  (so, 0);
 313         so_data  (so, screen->query->handle);
 314         so_method(so, screen->curie, NV40TCL_DMA_UNK01AC, 2);
 315         so_data  (so, nvws->channel->vram->handle);
 316         so_data  (so, nvws->channel->vram->handle);
 317         so_method(so, screen->curie, NV40TCL_DMA_COLOR2, 2);
 318         so_data  (so, nvws->channel->vram->handle);
 319         so_data  (so, nvws->channel->vram->handle);
 320
 321         so_method(so, screen->curie, 0x1ea4, 3);
 322         so_data  (so, 0x00000010);
 323         so_data  (so, 0x01000100);
 324         so_data  (so, 0xff800006);
 325
 326         /* vtxprog output routing */
 327         so_method(so, screen->curie, 0x1fc4, 1);
 328         so_data  (so, 0x06144321);
 329         so_method(so, screen->curie, 0x1fc8, 2);
 330         so_data  (so, 0xedcba987);
 331         so_data  (so, 0x00000021);
 332         so_method(so, screen->curie, 0x1fd0, 1);
 333         so_data  (so, 0x00171615);
 334         so_method(so, screen->curie, 0x1fd4, 1);
 335         so_data  (so, 0x001b1a19);
 336
 337         so_method(so, screen->curie, 0x1ef8, 1);
 338         so_data  (so, 0x0020ffff);
 339         so_method(so, screen->curie, 0x1d64, 1);
 340         so_data  (so, 0x00d30000);
 341         so_method(so, screen->curie, 0x1e94, 1);
 342         so_data  (so, 0x00000001);
 343
 344         so_emit(nvws, so);
 345         so_ref(NULL, &so);
 346         nvws->push_flush(nvws, 0, NULL);
 347
 348         screen->pipe.winsys = ws;
 349         screen->pipe.destroy = nv40_screen_destroy;
 350
 351         screen->pipe.get_name = nv40_screen_get_name;
 352         screen->pipe.get_vendor = nv40_screen_get_vendor;
 353         screen->pipe.get_param = nv40_screen_get_param;
 354         screen->pipe.get_paramf = nv40_screen_get_paramf;
 355
 356         screen->pipe.is_format_supported = nv40_screen_surface_format_supported;
 357
 358         screen->pipe.surface_map = nv40_surface_map;
 359         screen->pipe.surface_unmap = nv40_surface_unmap;
 360
 361         nv40_screen_init_miptree_functions(&screen->pipe);
 362
 363         return &screen->pipe;
 364 }
 365