src/gallium/drivers/nv40/nv40_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_util.h"
   3
   4 #include "nv40_context.h"
   5 #include "nv40_screen.h"
   6
   7 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
   8 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
   9 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  10
  11 static const char *
  12 nv40_screen_get_name(struct pipe_screen *pscreen)
  13 {
  14         struct nv40_screen *screen = nv40_screen(pscreen);
  15         static char buffer[128];
  16
  17         snprintf(buffer, sizeof(buffer), "NV%02X", screen->chipset);
  18         return buffer;
  19 }
  20
  21 static const char *
  22 nv40_screen_get_vendor(struct pipe_screen *pscreen)
  23 {
  24         return "nouveau";
  25 }
  26
  27 static int
  28 nv40_screen_get_param(struct pipe_screen *pscreen, int param)
  29 {
  30         struct nv40_screen *screen = nv40_screen(pscreen);
  31
  32         switch (param) {
  33         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  34                 return 16;
  35         case PIPE_CAP_NPOT_TEXTURES:
  36                 return 1;
  37         case PIPE_CAP_TWO_SIDED_STENCIL:
  38                 return 1;
  39         case PIPE_CAP_GLSL:
  40                 return 0;
  41         case PIPE_CAP_S3TC:
  42                 return 1;
  43         case PIPE_CAP_ANISOTROPIC_FILTER:
  44                 return 1;
  45         case PIPE_CAP_POINT_SPRITE:
  46                 return 1;
  47         case PIPE_CAP_MAX_RENDER_TARGETS:
  48                 return 4;
  49         case PIPE_CAP_OCCLUSION_QUERY:
  50                 return 1;
  51         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  52                 return 1;
  53         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  54                 return 13;
  55         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  56                 return 10;
  57         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  58                 return 13;
  59         case NOUVEAU_CAP_HW_VTXBUF:
  60                 return 1;
  61         case NOUVEAU_CAP_HW_IDXBUF:
  62                 if (screen->curie->grclass == NV40TCL)
  63                         return 1;
  64                 return 0;
  65         default:
  66                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  67                 return 0;
  68         }
  69 }
  70
  71 static float
  72 nv40_screen_get_paramf(struct pipe_screen *pscreen, int param)
  73 {
  74         switch (param) {
  75         case PIPE_CAP_MAX_LINE_WIDTH:
  76         case PIPE_CAP_MAX_LINE_WIDTH_AA:
  77                 return 10.0;
  78         case PIPE_CAP_MAX_POINT_WIDTH:
  79         case PIPE_CAP_MAX_POINT_WIDTH_AA:
  80                 return 64.0;
  81         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
  82                 return 16.0;
  83         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
  84                 return 16.0;
  85         default:
  86                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  87                 return 0.0;
  88         }
  89 }
  90
  91 static boolean
  92 nv40_screen_surface_format_supported(struct pipe_screen *pscreen,
  93                                      enum pipe_format format, uint type)
  94 {
  95         switch (type) {
  96         case PIPE_SURFACE:
  97                 switch (format) {
  98                 case PIPE_FORMAT_A8R8G8B8_UNORM:
  99                 case PIPE_FORMAT_R5G6B5_UNORM:
 100                 case PIPE_FORMAT_Z24S8_UNORM:
 101                 case PIPE_FORMAT_Z16_UNORM:
 102                         return TRUE;
 103                 default:
 104                         break;
 105                 }
 106                 break;
 107         case PIPE_TEXTURE:
 108                 switch (format) {
 109                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 110                 case PIPE_FORMAT_A1R5G5B5_UNORM:
 111                 case PIPE_FORMAT_A4R4G4B4_UNORM:
 112                 case PIPE_FORMAT_R5G6B5_UNORM:
 113                 case PIPE_FORMAT_U_L8:
 114                 case PIPE_FORMAT_U_A8:
 115                 case PIPE_FORMAT_U_I8:
 116                 case PIPE_FORMAT_U_A8_L8:
 117                 case PIPE_FORMAT_Z16_UNORM:
 118                 case PIPE_FORMAT_Z24S8_UNORM:
 119                 case PIPE_FORMAT_DXT1_RGB:
 120                 case PIPE_FORMAT_DXT1_RGBA:
 121                 case PIPE_FORMAT_DXT3_RGBA:
 122                 case PIPE_FORMAT_DXT5_RGBA:
 123                         return TRUE;
 124                 default:
 125                         break;
 126                 }
 127                 break;
 128         default:
 129                 assert(0);
 130         };
 131
 132         return FALSE;
 133 }
 134
 135 static void
 136 nv40_screen_destroy(struct pipe_screen *pscreen)
 137 {
 138         struct nv40_screen *screen = nv40_screen(pscreen);
 139         struct nouveau_winsys *nvws = screen->nvws;
 140
 141         nvws->res_free(&screen->vp_exec_heap);
 142         nvws->res_free(&screen->vp_data_heap);
 143         nvws->res_free(&screen->query_heap);
 144         nvws->notifier_free(&screen->query);
 145         nvws->notifier_free(&screen->sync);
 146         nvws->grobj_free(&screen->curie);
 147
 148         FREE(pscreen);
 149 }
 150
 151 struct pipe_screen *
 152 nv40_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws,
 153                    unsigned chipset)
 154 {
 155         struct nv40_screen *screen = CALLOC_STRUCT(nv40_screen);
 156         struct nouveau_stateobj *so;
 157         unsigned curie_class;
 158         int ret;
 159
 160         if (!screen)
 161                 return NULL;
 162         screen->chipset = chipset;
 163         screen->nvws = nvws;
 164
 165         /* 3D object */
 166         switch (chipset & 0xf0) {
 167         case 0x40:
 168                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (chipset & 0x0f)))
 169                         curie_class = NV40TCL;
 170                 else
 171                 if (NV4X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 172                         curie_class = NV44TCL;
 173                 break;
 174         case 0x60:
 175                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 176                         curie_class = NV44TCL;
 177                 break;
 178         default:
 179                 break;
 180         }
 181
 182         if (!curie_class) {
 183                 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", chipset);
 184                 return NULL;
 185         }
 186
 187         ret = nvws->grobj_alloc(nvws, curie_class, &screen->curie);
 188         if (ret) {
 189                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 190                 return FALSE;
 191         }
 192
 193         /* Notifier for sync purposes */
 194         ret = nvws->notifier_alloc(nvws, 1, &screen->sync);
 195         if (ret) {
 196                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 197                 nv40_screen_destroy(&screen->pipe);
 198                 return NULL;
 199         }
 200
 201         /* Query objects */
 202         ret = nvws->notifier_alloc(nvws, 32, &screen->query);
 203         if (ret) {
 204                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 205                 nv40_screen_destroy(&screen->pipe);
 206                 return NULL;
 207         }
 208
 209         ret = nvws->res_init(&screen->query_heap, 0, 32);
 210         if (ret) {
 211                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 212                 nv40_screen_destroy(&screen->pipe);
 213                 return NULL;
 214         }
 215
 216         /* Vtxprog resources */
 217         if (nvws->res_init(&screen->vp_exec_heap, 0, 512) ||
 218             nvws->res_init(&screen->vp_data_heap, 0, 256)) {
 219                 nv40_screen_destroy(&screen->pipe);
 220                 return NULL;
 221         }
 222
 223         /* Static curie initialisation */
 224         so = so_new(128, 0);
 225         so_method(so, screen->curie, NV40TCL_DMA_NOTIFY, 1);
 226         so_data  (so, screen->sync->handle);
 227         so_method(so, screen->curie, NV40TCL_DMA_TEXTURE0, 2);
 228         so_data  (so, nvws->channel->vram->handle);
 229         so_data  (so, nvws->channel->gart->handle);
 230         so_method(so, screen->curie, NV40TCL_DMA_COLOR1, 1);
 231         so_data  (so, nvws->channel->vram->handle);
 232         so_method(so, screen->curie, NV40TCL_DMA_COLOR0, 2);
 233         so_data  (so, nvws->channel->vram->handle);
 234         so_data  (so, nvws->channel->vram->handle);
 235         so_method(so, screen->curie, NV40TCL_DMA_VTXBUF0, 2);
 236         so_data  (so, nvws->channel->vram->handle);
 237         so_data  (so, nvws->channel->gart->handle);
 238         so_method(so, screen->curie, NV40TCL_DMA_FENCE, 2);
 239         so_data  (so, 0);
 240         so_data  (so, screen->query->handle);
 241         so_method(so, screen->curie, NV40TCL_DMA_UNK01AC, 2);
 242         so_data  (so, nvws->channel->vram->handle);
 243         so_data  (so, nvws->channel->vram->handle);
 244         so_method(so, screen->curie, NV40TCL_DMA_COLOR2, 2);
 245         so_data  (so, nvws->channel->vram->handle);
 246         so_data  (so, nvws->channel->vram->handle);
 247
 248         so_method(so, screen->curie, 0x1ea4, 3);
 249         so_data  (so, 0x00000010);
 250         so_data  (so, 0x01000100);
 251         so_data  (so, 0xff800006);
 252
 253         /* vtxprog output routing */
 254         so_method(so, screen->curie, 0x1fc4, 1);
 255         so_data  (so, 0x06144321);
 256         so_method(so, screen->curie, 0x1fc8, 2);
 257         so_data  (so, 0xedcba987);
 258         so_data  (so, 0x00000021);
 259         so_method(so, screen->curie, 0x1fd0, 1);
 260         so_data  (so, 0x00171615);
 261         so_method(so, screen->curie, 0x1fd4, 1);
 262         so_data  (so, 0x001b1a19);
 263
 264         so_method(so, screen->curie, 0x1ef8, 1);
 265         so_data  (so, 0x0020ffff);
 266         so_method(so, screen->curie, 0x1d64, 1);
 267         so_data  (so, 0x00d30000);
 268         so_method(so, screen->curie, 0x1e94, 1);
 269         so_data  (so, 0x00000001);
 270
 271         so_emit(nvws, so);
 272         so_ref(NULL, &so);
 273         nvws->push_flush(nvws, 0, NULL);
 274
 275         screen->pipe.winsys = ws;
 276         screen->pipe.destroy = nv40_screen_destroy;
 277
 278         screen->pipe.get_name = nv40_screen_get_name;
 279         screen->pipe.get_vendor = nv40_screen_get_vendor;
 280         screen->pipe.get_param = nv40_screen_get_param;
 281         screen->pipe.get_paramf = nv40_screen_get_paramf;
 282
 283         screen->pipe.is_format_supported = nv40_screen_surface_format_supported;
 284
 285         nv40_screen_init_miptree_functions(&screen->pipe);
 286
 287         return &screen->pipe;
 288 }
 289