src/gallium/drivers/nv40/nv40_screen.c

   1 #include "pipe/p_screen.h"
   2
   3 #include "nv40_context.h"
   4 #include "nv40_screen.h"
   5
   6 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
   7 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
   8 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
   9
  10 static const char *
  11 nv40_screen_get_name(struct pipe_screen *pscreen)
  12 {
  13         struct nv40_screen *screen = nv40_screen(pscreen);
  14         struct nouveau_device *dev = screen->nvws->channel->device;
  15         static char buffer[128];
  16
  17         snprintf(buffer, sizeof(buffer), "NV%02X", dev->chipset);
  18         return buffer;
  19 }
  20
  21 static const char *
  22 nv40_screen_get_vendor(struct pipe_screen *pscreen)
  23 {
  24         return "nouveau";
  25 }
  26
  27 static int
  28 nv40_screen_get_param(struct pipe_screen *pscreen, int param)
  29 {
  30         struct nv40_screen *screen = nv40_screen(pscreen);
  31
  32         switch (param) {
  33         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  34                 return 16;
  35         case PIPE_CAP_NPOT_TEXTURES:
  36                 return 1;
  37         case PIPE_CAP_TWO_SIDED_STENCIL:
  38                 return 1;
  39         case PIPE_CAP_GLSL:
  40                 return 0;
  41         case PIPE_CAP_S3TC:
  42                 return 1;
  43         case PIPE_CAP_ANISOTROPIC_FILTER:
  44                 return 1;
  45         case PIPE_CAP_POINT_SPRITE:
  46                 return 1;
  47         case PIPE_CAP_MAX_RENDER_TARGETS:
  48                 return 4;
  49         case PIPE_CAP_OCCLUSION_QUERY:
  50                 return 1;
  51         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  52                 return 1;
  53         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  54                 return 13;
  55         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  56                 return 10;
  57         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  58                 return 13;
  59         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  60         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  61                 return 1;
  62         case NOUVEAU_CAP_HW_VTXBUF:
  63                 return 1;
  64         case NOUVEAU_CAP_HW_IDXBUF:
  65                 if (screen->curie->grclass == NV40TCL)
  66                         return 1;
  67                 return 0;
  68         default:
  69                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  70                 return 0;
  71         }
  72 }
  73
  74 static float
  75 nv40_screen_get_paramf(struct pipe_screen *pscreen, int param)
  76 {
  77         switch (param) {
  78         case PIPE_CAP_MAX_LINE_WIDTH:
  79         case PIPE_CAP_MAX_LINE_WIDTH_AA:
  80                 return 10.0;
  81         case PIPE_CAP_MAX_POINT_WIDTH:
  82         case PIPE_CAP_MAX_POINT_WIDTH_AA:
  83                 return 64.0;
  84         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
  85                 return 16.0;
  86         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
  87                 return 16.0;
  88         default:
  89                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  90                 return 0.0;
  91         }
  92 }
  93
  94 static boolean
  95 nv40_screen_surface_format_supported(struct pipe_screen *pscreen,
  96                                      enum pipe_format format,
  97                                      enum pipe_texture_target target,
  98                                      unsigned tex_usage, unsigned geom_flags)
  99 {
 100         if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
 101                 switch (format) {
 102                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 103                 case PIPE_FORMAT_R5G6B5_UNORM:
 104                 case PIPE_FORMAT_Z24S8_UNORM:
 105                 case PIPE_FORMAT_Z16_UNORM:
 106                         return TRUE;
 107                 default:
 108                         break;
 109                 }
 110         } else {
 111                 switch (format) {
 112                 case PIPE_FORMAT_A8R8G8B8_UNORM:
 113                 case PIPE_FORMAT_A1R5G5B5_UNORM:
 114                 case PIPE_FORMAT_A4R4G4B4_UNORM:
 115                 case PIPE_FORMAT_R5G6B5_UNORM:
 116                 case PIPE_FORMAT_R16_SNORM:
 117                 case PIPE_FORMAT_L8_UNORM:
 118                 case PIPE_FORMAT_A8_UNORM:
 119                 case PIPE_FORMAT_I8_UNORM:
 120                 case PIPE_FORMAT_A8L8_UNORM:
 121                 case PIPE_FORMAT_Z16_UNORM:
 122                 case PIPE_FORMAT_Z24S8_UNORM:
 123                 case PIPE_FORMAT_DXT1_RGB:
 124                 case PIPE_FORMAT_DXT1_RGBA:
 125                 case PIPE_FORMAT_DXT3_RGBA:
 126                 case PIPE_FORMAT_DXT5_RGBA:
 127                         return TRUE;
 128                 default:
 129                         break;
 130                 }
 131         }
 132
 133         return FALSE;
 134 }
 135
 136 static void *
 137 nv40_surface_map(struct pipe_screen *screen, struct pipe_surface *surface,
 138                  unsigned flags )
 139 {
 140         struct pipe_winsys *ws = screen->winsys;
 141         void *map;
 142
 143         map = ws->buffer_map(ws, surface->buffer, flags);
 144         if (!map)
 145                 return NULL;
 146
 147         return map + surface->offset;
 148 }
 149
 150 static void
 151 nv40_surface_unmap(struct pipe_screen *screen, struct pipe_surface *surface)
 152 {
 153         struct pipe_winsys *ws = screen->winsys;
 154
 155         ws->buffer_unmap(ws, surface->buffer);
 156 }
 157
 158 static void
 159 nv40_screen_destroy(struct pipe_screen *pscreen)
 160 {
 161         struct nv40_screen *screen = nv40_screen(pscreen);
 162         struct nouveau_winsys *nvws = screen->nvws;
 163
 164         nvws->res_free(&screen->vp_exec_heap);
 165         nvws->res_free(&screen->vp_data_heap);
 166         nvws->res_free(&screen->query_heap);
 167         nvws->notifier_free(&screen->query);
 168         nvws->notifier_free(&screen->sync);
 169         nvws->grobj_free(&screen->curie);
 170
 171         FREE(pscreen);
 172 }
 173
 174 struct pipe_screen *
 175 nv40_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
 176 {
 177         struct nv40_screen *screen = CALLOC_STRUCT(nv40_screen);
 178         struct nouveau_stateobj *so;
 179         unsigned curie_class;
 180         unsigned chipset = nvws->channel->device->chipset;
 181         int ret;
 182
 183         if (!screen)
 184                 return NULL;
 185         screen->nvws = nvws;
 186
 187         /* 3D object */
 188         switch (chipset & 0xf0) {
 189         case 0x40:
 190                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (chipset & 0x0f)))
 191                         curie_class = NV40TCL;
 192                 else
 193                 if (NV4X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 194                         curie_class = NV44TCL;
 195                 break;
 196         case 0x60:
 197                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (chipset & 0x0f)))
 198                         curie_class = NV44TCL;
 199                 break;
 200         default:
 201                 break;
 202         }
 203
 204         if (!curie_class) {
 205                 NOUVEAU_ERR("Unknown nv4x chipset: nv%02x\n", chipset);
 206                 return NULL;
 207         }
 208
 209         ret = nvws->grobj_alloc(nvws, curie_class, &screen->curie);
 210         if (ret) {
 211                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 212                 return FALSE;
 213         }
 214
 215         /* Notifier for sync purposes */
 216         ret = nvws->notifier_alloc(nvws, 1, &screen->sync);
 217         if (ret) {
 218                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 219                 nv40_screen_destroy(&screen->pipe);
 220                 return NULL;
 221         }
 222
 223         /* Query objects */
 224         ret = nvws->notifier_alloc(nvws, 32, &screen->query);
 225         if (ret) {
 226                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 227                 nv40_screen_destroy(&screen->pipe);
 228                 return NULL;
 229         }
 230
 231         ret = nvws->res_init(&screen->query_heap, 0, 32);
 232         if (ret) {
 233                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 234                 nv40_screen_destroy(&screen->pipe);
 235                 return NULL;
 236         }
 237
 238         /* Vtxprog resources */
 239         if (nvws->res_init(&screen->vp_exec_heap, 0, 512) ||
 240             nvws->res_init(&screen->vp_data_heap, 0, 256)) {
 241                 nv40_screen_destroy(&screen->pipe);
 242                 return NULL;
 243         }
 244
 245         /* Static curie initialisation */
 246         so = so_new(128, 0);
 247         so_method(so, screen->curie, NV40TCL_DMA_NOTIFY, 1);
 248         so_data  (so, screen->sync->handle);
 249         so_method(so, screen->curie, NV40TCL_DMA_TEXTURE0, 2);
 250         so_data  (so, nvws->channel->vram->handle);
 251         so_data  (so, nvws->channel->gart->handle);
 252         so_method(so, screen->curie, NV40TCL_DMA_COLOR1, 1);
 253         so_data  (so, nvws->channel->vram->handle);
 254         so_method(so, screen->curie, NV40TCL_DMA_COLOR0, 2);
 255         so_data  (so, nvws->channel->vram->handle);
 256         so_data  (so, nvws->channel->vram->handle);
 257         so_method(so, screen->curie, NV40TCL_DMA_VTXBUF0, 2);
 258         so_data  (so, nvws->channel->vram->handle);
 259         so_data  (so, nvws->channel->gart->handle);
 260         so_method(so, screen->curie, NV40TCL_DMA_FENCE, 2);
 261         so_data  (so, 0);
 262         so_data  (so, screen->query->handle);
 263         so_method(so, screen->curie, NV40TCL_DMA_UNK01AC, 2);
 264         so_data  (so, nvws->channel->vram->handle);
 265         so_data  (so, nvws->channel->vram->handle);
 266         so_method(so, screen->curie, NV40TCL_DMA_COLOR2, 2);
 267         so_data  (so, nvws->channel->vram->handle);
 268         so_data  (so, nvws->channel->vram->handle);
 269
 270         so_method(so, screen->curie, 0x1ea4, 3);
 271         so_data  (so, 0x00000010);
 272         so_data  (so, 0x01000100);
 273         so_data  (so, 0xff800006);
 274
 275         /* vtxprog output routing */
 276         so_method(so, screen->curie, 0x1fc4, 1);
 277         so_data  (so, 0x06144321);
 278         so_method(so, screen->curie, 0x1fc8, 2);
 279         so_data  (so, 0xedcba987);
 280         so_data  (so, 0x00000021);
 281         so_method(so, screen->curie, 0x1fd0, 1);
 282         so_data  (so, 0x00171615);
 283         so_method(so, screen->curie, 0x1fd4, 1);
 284         so_data  (so, 0x001b1a19);
 285
 286         so_method(so, screen->curie, 0x1ef8, 1);
 287         so_data  (so, 0x0020ffff);
 288         so_method(so, screen->curie, 0x1d64, 1);
 289         so_data  (so, 0x00d30000);
 290         so_method(so, screen->curie, 0x1e94, 1);
 291         so_data  (so, 0x00000001);
 292
 293         so_emit(nvws, so);
 294         so_ref(NULL, &so);
 295         nvws->push_flush(nvws, 0, NULL);
 296
 297         screen->pipe.winsys = ws;
 298         screen->pipe.destroy = nv40_screen_destroy;
 299
 300         screen->pipe.get_name = nv40_screen_get_name;
 301         screen->pipe.get_vendor = nv40_screen_get_vendor;
 302         screen->pipe.get_param = nv40_screen_get_param;
 303         screen->pipe.get_paramf = nv40_screen_get_paramf;
 304
 305         screen->pipe.is_format_supported = nv40_screen_surface_format_supported;
 306
 307         screen->pipe.surface_map = nv40_surface_map;
 308         screen->pipe.surface_unmap = nv40_surface_unmap;
 309
 310         nv40_screen_init_miptree_functions(&screen->pipe);
 311
 312         return &screen->pipe;
 313 }
 314